MAX9972ACCS+DW-T [MAXIM]
Comparator;
| 型号： | MAX9972ACCS+DW-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Comparator 放大器 |
| 文件： | 总22页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0474; Rev 9; 10/11
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
General Description
Features
o Small Footprint—Four Channels in 0.3in2
The MAX9972 four-channel, ultra-low-power, pin-elec-
tronics IC includes, for each channel, a three-level pin
driver, a window comparator, a passive load, and
force-and-sense Kelvin-switched parametric measure-
ment unit (PMU) connections. The driver features a
-2.2V to +5.2V voltage range, includes high-impedance
and active-termination (3rd-level drive) modes, and is
highly linear even at low voltage swings. The window
comparator features 500MHz equivalent input band-
width and programmable output voltage levels. The
passive load provides pullup and pulldown voltages to
the device-under-test (DUT).
o Low-Power Dissipation: 325mW/Channel (typ)
o High Speed: 300Mbps at 3VP-P
o -2.2V to +5.2V Operating Range
o Active Termination (3rd-Level Drive)
o Integrated PMU Switches
o Passive Load
o Low-Leak Mode: 20nA (max)
o Low Gain and Offset Error
Low-leakage, high-impedance, and terminate controls
are operational configurations that are programmed
through a 3-wire, low-voltage, CMOS-compatible serial
interface. High-speed PMU switching is realized through
dedicated digital control inputs.
Ordering Information
This device is available in an 80-pin, 12mm x 12mm
body, 1.0mm pitch TQFP with an exposed 6mm x 6mm
die pad on the bottom of the package for efficient heat
removal. The MAX9972 is specified to operate over the
0°C to +70°C commercial temperature range, and fea-
tures a die temperature monitor output.
TEMP
RANGE
PIN-
HEAT
PART
PACKAGE EXTRACTION
0°C to
+70°C
MAX9972ACCS+
80 TQFP-EP*
Bottom
+Denotes a lead(Pb)-free/RoHs-compliant package.
*EP = Exposed pad.
Applications
NAND Flash Testers
DRAM Probe Testers
Low-Cost Mixed-Signal/System-on-Chip (SoC)
Testers
Active Burn-In Systems
Structural Testers
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
ABSOLUTE MAXIMUM RATINGS
V
DD
V
SS
V
to GND...........................................................-0.3V to +9.4V
to GND..........................................................-6.25V to +0.3V
CHV_, CLV_ to DUT_ ..................................................V to V
SS DD
DOUT to GND...........................................................-0.3V to +5V
TEMP Short-Circuit Duration ......................................Continuous
FORCE_ Path Switch Current..............................................50mA
SENSE_ Path Switch Current .............................................1.5mA
to V ........................................................................+15.7V
DD
SS
V to GND.................................................................-0.3V to +5V
L
DHV_, DTV_, DLV_, LDV_, DUT_ to GND...................V to V
SS
DD
DATA_, RCV_ ...........................................................-0.3V to +5V
CHV_, CLV_, CMPH_, CMPL_, COMPHI,
Continuous Power Dissipation (T = +70°C)
A
80-Pin TQFP-EP (derate 35.7mW/°C above +70°C) ....2857mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
COMPLO to GND.....................................................V to V
SS
DD
DD
FORCE_, SENSE_, PMU_ to GND ..............................V to V
SS
MAX972
LD, DIN, SCLK, CS to GND......................................-0.3V to +5V
DUT_, CMPH_, CMPL_ Short-Circuit Duration...........Continuous
DHV_, DLV_, DTV_ to Each Other ..............................V to V
SS
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +8V, V
= -5V, V = +3V, V
= +1V, V
= 0V, V
= 0V, LOAD EN LOW = LOAD EN HIGH = 0,
LDV_
DD
SS
L
COMPHI
COMPLO
T = +75°C. All temperature coefficients measured at T = +50°C to +100°C, unless otherwise noted.) (Note 1)
J
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER (all specifications apply when DUT_ = DHV_, DUT_ = DTV_, or DUT_ = DLV_)
DC CHARACTERISTICS
Voltage Range
-2.2
+5.2
V
V/V
Gain
Measured at 0V and 3V
0.995
1
1.005
Gain Temperature Coefficient
Offset
50
ppm/°C
mV
V
= 2V, V
= 0V, V = 1V
DTV_
10
18
DHV_
DLV_
Offset Temperature Coefficient
250
µV/°C
V
, V independently varied over full
DD SS
Power-Supply Rejection Ratio
PSRR
mV/V
range
Maximum DC Drive Current
DC Output Resistance
I
All drive mode specs valid over this range
40
mA
_
DUT_
I
I
=
10mA (Note 2)
48.5
49.5
50.5
2.5
DUT_
DUT_
DC Output Resistance Variation
= -40mA to +40mA
_
DHV_ to DLV_ and DTV_:
V
V
= V
= +1.5V,
DTV_
5
5
5
DLV_
DHV_
= -2.2V, +5.2V
DLV_ to DHV_ and DTV_:
V
V
DC Crosstalk
Linearity Error
= V
= +1.5V,
DTV_
mV
DHV_
DLV_
= -2.2V, +5.2V
DTV_ to DHV_ and DLV_:
V
V
= V
= +1.5V,
DLV_
DHV_
DTV_
= -2.2V, +5.2V
0 to 3V (Note 3)
5
mV
mV
Full range (Note 4)
15
2
_______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
ELECTRICAL CHARACTERISTICS (continued)
(V
= +8V, V
= -5V, V = +3V, V
= +1V, V
= 0V, V
= 0V, LOAD EN LOW = LOAD EN HIGH = 0,
LDV_
DD
SS
L
COMPHI
COMPLO
T = +75°C. All temperature coefficients measured at T = +50°C to +100°C, unless otherwise noted.) (Note 1)
J
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS (Note 5)
Dynamic Output Current
(Note 1)
40
mA
mV
Drive-Mode Overshoot,
Undershoot, and Preshoot
5%
+10
200mV to 4V
swing (Note 6)
P-P
V
V
V
V
= V
= 1V, V
= 0V
= 1V
25
25
25
25
2.6
DHV_
DLV_
DLV_
DLV_
DTV_
DLV_
Term-Mode Spike
mV
= V
= 0V, V
DTV_
DHV_
= -1V, V
= 0V
DHV_
DHV_
High-Impedance-Mode Spike
mV
ns
= 0V, V
= 1V
Propagation Delay, Data to Output
1.6
4.2
Prop-Delay Temperature
Coefficient
10
30
ps/°C
ps
Prop-Delay Match, t vs. t
LH
HL
Prop-Delay Skew, Drivers Within
Package
150
ps
3V , 40MHz,
P-P
PW = 4ns to 21ns
20
90
Prop-Delay Change vs. Pulse
Width
Relative to 12.5ns
pulse
ps
1V , 40MHz,
P-P
PW = 2.5ns to 23.5ns
Prop-Delay Change vs. Common-
Mode Voltage
1V , V
= 0 to 3V, relative to delay at
P-P DLV_
80
ps
ns
V
= 1V
DLV_
Prop Delay, Data to High
Impedance
V
= +1.5V, V
= -1.5V, both
DHV_
DLV_
1.8
1.6
directions
V
= +1.5V, V
= -1.5V, V
= 0V,
DTV_
DHV_
DLV_
Prop Delay, Data to Term
Minimum Voltage Swing
ns
both directions
(Note 7)
25
0.7
0.7
2.0
mV
V
V
V
= 0.2V, V
= 0V, 20% to 80%
DLV_
DHV_
DHV_
DHV_
= 1V, V
= 3V, V
= 4V, V
= 0V, 20% to 80%
= 0V, 10% to 90%
= 0V,
DLV_
DLV_
1.5
2.5
Rise/Fall Time
ns
V
DHV_
DLV_
2.6
3.4
R = 500_, 10% to 90%
L
V
= 5V, V
= 0V,
DLV_
DHV_
R = 500_, 10% to 90%
L
Rise/Fall-Time Matching
V
= 1V to 5V
5
1.8
2.4
3.3
%
DHV_
200mV, V
= 0.2V, V
= 0V
DLV_
DHV_
Minimum Pulse Width (Note 8)
1V, V
3V, V
= 1V, V
= 0V
= 0V
ns
DHV_
DHV_
DLV_
DLV_
= 3V, V
_______________________________________________________________________________________
3
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
ELECTRICAL CHARACTERISTICS (continued)
(V
= +8V, V
= -5V, V = +3V, V
= +1V, V
= 0V, V
= 0V, LOAD EN LOW = LOAD EN HIGH = 0,
LDV_
DD
SS
L
COMPHI
COMPLO
T = +75°C. All temperature coefficients measured at T = +50°C to +100°C, unless otherwise noted.) (Note 1)
J
J
PARAMETER
COMPARATOR (Note 9)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS (driver in high-impedance mode) (V
= 0.8V, V
= 0.2V)
COMPHI
COMPLO
Input Voltage Range
-2.2
-7.4
+5.2
+7.4
V
MAX972
Differential Input Voltage
Hysteresis
V
DUT_
V
CHV_
V
DUT_
- V
, V
- V
CLV_
V
CHV_ DUT_
= V
= 1.5V
8
mV
mV
CLV_
Input Offset Voltage
= 1.5V
10
Input Offset Temperature
Coefficient
25
μV/°C
dB
Common-Mode Rejection Ratio
CMRR
PSRR
V
= 0 and 3V
= 1.5V
60
DUT_
V
5
DUT_
DUT_
Linearity Error (Note 10)
mV
V
= -2.2V, +5.2V
10
V
DUT_
= 1.5V, supplies independently
Power-Supply Rejection Ratio
AC CHARACTERISTICS (Note 11)
Equivalent Input Bandwidth
Propagation Delay
5
mV/V
varied over full range
Terminated (Note 12)
500
300
2.2
MHz
ns
High impedance (Note 13)
0.9
3.1
Prop-Delay Temperature
Coefficient
4
ps/°C
ps
Prop-Delay Match, t to t
120
200
LH
HL
Prop-Delay Skew, Comparators
Within Package
Same edges (LH and HL)
ps
Prop-Delay Dispersions vs.
Common-Mode Voltage
(Note 14)
0 to 4.9V
20
30
ps
ps
-1.9V to +4.9V
V
CHV_
V
DUT_
= V
= 0.1V to 0.9V,
CLV_
Prop-Delay Dispersions vs.
Overdrive
= 1V , t = t = 500ps, 10% to
220
P-P
R
F
90% relative to timing at 50% point
Prop-Delay Dispersions vs.
Pulse Width
2ns to 23ns pulse width, relative to 12.5ns
pulse width
60
50
ps
ps
Prop-Delay Dispersions vs.
Slew Rate
0.5V/ns to 2V/ns
4
_______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
ELECTRICAL CHARACTERISTICS (continued)
(V
= +8V, V
= -5V, V = +3V, V
= +1V, V
= 0V, V
= 0V, LOAD EN LOW = LOAD EN HIGH = 0,
LDV_
DD
SS
L
COMPHI
COMPLO
T = +75°C. All temperature coefficients measured at T = +50°C to +100°C, unless otherwise noted.) (Note 1)
J
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC OUTPUTS
Reference Voltages COMPHI and
COMPLO
(Note 15)
0
+3.6
50
V
I
= 0mA, relative to COMPHI at
OUT
Output High Voltage Offset
Output Low Voltage Offset
mV
mV
V
= 1V
COMPHI
I
= 0mA, relative to COMPLO at
OUT
50
60
V
= 0V
COMPLO
Output Resistance
Current Limit
I
= I
=
10mA
40
50
25
Ω
CHV_
CLV_
mA
20% to 80%, V
load = T-line, 50Ω, > 1ns
= 1V
,
CHV_
P-P
Rise/Fall Time
0.7
ns
PASSIVE LOAD
DC CHARACTERISTICS (R
LDV_ Voltage Range
Gain
≥ 10MΩ)
DUT_
-2.2
+5.2
1.01
V
0.99
V/V
Gain Temperature Coefficient
Offset
0.02
%/°C
mV
100
Offset Temperature Coefficient
Power-Supply Rejection Ratio
0.02
10
mV/°C
mV/V
PSRR
Output Resistance
Tolerance—High Value
I
I
=
=
0.2mA, V
0.1mA, V
= 1.5V
= 1.5V
7.125
1.90
7.5
2.0
7.875
2.10
kΩ
kΩ
%
DUT_
DUT_
LDV_
LDV_
Output Resistance
Tolerance—Low Value
0 to 3V
Full range
10
30
4
Switch Resistance Variation
Relative to 1.5V
V
V
= -2V, V
= +5V
LDV_
LDV_
DUT_
Maximum Output Current
(Note 16)
mA
mV
= +5V, V
= -2V
4
DUT_
Measured at -2.2V, +1.5V, and +5.2V
(Note 16)
Linearity Error, Full Range
AC CHARACTERISTICS
Settling Time, LDV_ to Output
25
V
= -2V to +5V step, R
= 100kΩ
DUT_
LDV_
0.5
20
µs
ns
(Note 17)
V
= +1.5V, V
= -2V to +5V square
= 50Ω
LDV_
DUT_
DUT_
Output Transient Response
wave at 1MHz, R
_______________________________________________________________________________________
5
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
ELECTRICAL CHARACTERISTICS (continued)
(V
= +8V, V
= -5V, V = +3V, V
= +1V, V
= 0V, V
= 0V, LOAD EN LOW = LOAD EN HIGH = 0,
LDV_
DD
SS
L
COMPHI
COMPLO
T = +75°C. All temperature coefficients measured at T = +50°C to +100°C, unless otherwise noted.) (Note 1)
J
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PMU SWITCHES (FORCE_, SENSE_, PMU_)
Voltage Range
-2.2
+5.2
40
V
Force Switch Resistance
V
V
= 1.5V, I
=
10mA
Ω
FORCE_
PMU_
MAX972
= 6.2V, V
set to make
PMU_
FORCE_
25
25
I
= 30mA
FORCE_
Force Switch Compliance
mA
V
= -3.2V, V
FORCE_
= -30mA
set to make
PMU_
I
FORCE_
0 to 3V
Full range
10
30
Force Switch Resistance
Variation (Note 18)
%
Ω
Sense Switch Resistance
700
1000
1300
Sense Switch Resistance
Variation
Relative to 1.3V, full range
30
%
PMU_ Capacitance
Force-and-sense switches open
5
5
pF
pF
pF
nF
nF
FORCE_ Capacitance
SENSE_ Capacitance
0.2
2
FORCE_ External Capacitance
SENSE_ External Capacitance
Allowable external capacitance
Allowable external capacitance
1
FORCE_ and SENSE_ Switching
Speed
Connect or disconnect
10
µs
FORCE EN_ = SENSE EN_ = 0,
PMU_ Leakage
0.5
5
nA
V
= V
= -2.2V to +5.2V
SENSE_
FORCE_
TOTAL FUNCTION
DUT_
Load switches open,
V
V
V
V
= +5.2V,
DUT_
CLV_
DUT_
CLV_
Leakage, High-Impedance Mode
= V
= -2.2V,
2
µA
CHV_
= -2.2V,
= V
= +5.2V, full range
CHV_
Leakage, Low-Leakage Mode
Low-Leakage Recovery Time
Full range
(Note 19)
1
10
2
20
nA
µs
Term mode
Combined Capacitance
pF
High-impedance mode
(Note 20)
5
Load Resistance
1
GΩ
Load Capacitance
(Note 20)
12
nF
6
_______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
ELECTRICAL CHARACTERISTICS (continued)
(V
= +8V, V
= -5V, V = +3V, V
= +1V, V
= 0V, V
= 0V, LOAD EN LOW = LOAD EN HIGH = 0,
LDV_
DD
SS
L
COMPHI
COMPLO
T = +75°C. All temperature coefficients measured at T = +50°C to +100°C, unless otherwise noted.) (Note 1)
J
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE REFERENCE INPUTS (DHV_, DTV_, DLV_, DATA_, RCV_, CHV_, CLV_, LDV_, COMPHI, COMPLO)
Input Bias Current
100
µA
nA/°C
µs
Input Bias Current Temperature
Coefficient
200
Settling to Output
0.1% of full-scale step
10
DIGITAL INPUTS (DATA_, RCV_, LD, DIN, SCLK, CS)
V /2 +
L
0.2
Input High Voltage
Input Low Voltage
(Note 21)
+3.6
V
V
V /2 -
L
0.2
(Note 21)
0
DATA_,
100
Input Bias Current
µA
LD, DIN,
SCLK, CS
1
SERIAL DATA OUTPUT (DOUT)
V
- 0.4
L
Output High Voltage
I
I
= -1mA
= 1mA
V
L
V
OH
OL
Output Low Voltage
0
+0.4
V
Output Rise and Fall Time
C = 10pF
L
1.1
ns
SERIAL-INTERFACE TIMING (Note 22)
SCLK Frequency
50
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to SCLK High Setup
SCLK High to CS Low Hold
CS High to SCLK High Setup
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
CS High to LOAD Low Hold
CS High Pulse Width
t
10
10
3.5
3.5
3.5
15
7.5
3.5
6
CH
t
CL
t
CSS0
CSH0
t
t
CSS1
CSH1
t
t
DS
DH
t
t
CSHLD
t
20
20
0
CSWH
LD Low Pulse Width
t
LDW
LD High to Any Activity
SCLK Low to DOUT Delay
t
C = 10pF
L
5
40
DO
V Rising to CS Low
L
Power-on delay
2
TEMP SENSOR
Nominal Voltage
T = +27°C
J
3.20
+10
500
V
mV/°C
Ω
Temperature Coefficient
Output Resistance
_______________________________________________________________________________________
7
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
ELECTRICAL CHARACTERISTICS (continued)
(V
= +8V, V
= -5V, V = +3V, V
= +1V, V
= 0V, V
= 0V, LOAD EN LOW = LOAD EN HIGH = 0,
LDV_
DD
SS
L
COMPHI
COMPLO
T = +75°C. All temperature coefficients measured at T = +50°C to +100°C, unless otherwise noted.) (Note 1)
J
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
Logic Supply Voltage
V
(Note 23)
(Note 23)
7.6
-5.25
2.3
8
8.4
-4.75
3.6
V
V
DD
V
-5
SS
MAX972
V
V
L
Positive Supply Current
Negative Supply Current
Logic Supply Current
I
f
f
= 0MHz
= 0MHz
97
99
120
120
0.30
1.5
mA
mA
mA
W
DD
OUT
I
SS
OUT
I
0.15
1.3
1.4
L
Static Power Dissipation
Operating Power Dissipation
f
f
= 0MHz
OUT
OUT
= 100Mbps (Note 24)
W
Note 1: All minimum and maximum specifications are 100% production tested except driver dynamic output current and
driver/comparator propagation delays, which are guaranteed by design. All specifications are with DUT_ and PMU_ elec-
trically isolated, unless otherwise noted.
Note 2: Nominal target value is 49.5Ω. Contact factory for alternate trim selections within the 45Ω to 55Ω range.
Note 3: Measured at 1.5V, relative to a straight line through 0 and 3V.
Note 4: Measured at end points, relative to a straight line through 0 and 3V.
Note 5: DUT_ is terminated with 50Ω to ground, V
= 3V, V
= 0, V
= 1.5V, unless otherwise specified. DATA_ and
DTV_
DHV_
DLV_
RCV_ logic levels are V
= 2V, V
= 1V.
HIGH
LOW
Note 6: Undershoot is any reflection of the signal back towards its starting voltage after it has reached 90% of its swing. Preshoot
is any aberration in the signal before it reaches 10% of its swing.
Note 7: At the minimum voltage swing, undershoot is less than 20%. DHV_ and DLV_ references are adjusted to result in the
specified swing.
Note 8: At this pulse width, the output reaches at least 90% of its nominal (DC) amplitude. The pulse width is measured at DATA_.
Note 9: With the exception of offset and gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 10: Relative to a straight line through 0 and 3V.
Note 11: Unless otherwise noted, all propagation delays are measured at 40MHz, V
= 0 to 1V, V
= V
= +0.5V, t = t
CLV_ R F
DUT_
CHV_
= 500ps, Z = 50Ω, driver in term mode with V
= +0.5V. Comparator outputs are terminated with 50Ω to GND.
S
DTV_
Measured from V
crossing calibrated CHV_/CLV_ threshold to midpoint of nominal comparator output swing.
DUT_
Note 12: Terminated is defined as driver in drive mode and set to zero volts.
Note 13: High impedance is defined as driver in high-impedance mode.
Note 14: V
= 200mV . Propagation delay is compared to a reference time at 1.5V.
P-P
DUT_
Note 15: The comparator meets all its timing specifications with the specified output conditions when the output current is less than
10mA, V > V , and V - V ≤ 1V. Higher voltage swings are valid but AC performance may
COMPHI
COMPLO
COMPHI
COMPLO
degrade. The maximum comparator output swing is (COMPHI - COMPLO) ≤ 1V when the output is terminated with a 50Ω
resistor to termination voltage V , where COMPHI ≥ V ≥ COMPLO.
TERM
TERM
Note 16: LOAD EN LOW = LOAD EN HIGH = 1.
Note 17: Waveform settles to within 5% of final value into load 100kΩ.
Note 18: I 2mA at V = -2.2V, +1.5V, and +5.2V. Percent variation relative to value calculated at V = +1.5V.
FORCE_
=
PMU_
FORCE_
Note 19: Time to return to the specified maximum leakage after a 3V, 4V/ns step at DUT_.
Note 20: Load at end of 2ns transmission line; for stability only, AC performance may be degraded.
Note 21: The driver meets all of its timing specifications over the specified digital input voltage range.
Note 22: Timing characteristics with V = 3V.
L
Note 23: Specifications are simulated and characterized over the full power-supply range. Production tests are performed with
power supplies at typical values.
Note 24: All channels driven at 3V , load = 2ns, 50Ω transmission line terminated with 3pF.
P-P
8
_______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
DRIVER SMALL-
DRIVER LARGE-
DRIVER LARGE-
SIGNAL RESPONSE
SIGNAL RESPONSE
SIGNAL RESPONSE INTO 500Ω
V
= 0
V
DLV_
= 0
V
= 0
DLV_
DLV_
R = 50Ω
L
R = 500Ω
C = 0.1pF
L
R = 50Ω
L
L
V
= 500mV
DHV_
V
= 3V
V
= 3V
= 1V
DHV_
DHV_
V
V
= 200mV
= 100mV
DHV_
DHV_
V
DHV_
V
DHV_
= 1V
0
0
0
4.5ns CABLE
t = 2.0ns/div
t = 2.0ns/div
t = 2.0ns/div
DRIVER 1V , 150Mbps
P-P
SIGNAL RESPONSE
DRIVER 1V , 400Mbps
P-P
SIGNAL RESPONSE
DRIVER 3V , 100Mbps
P-P
SIGNAL RESPONSE
V
V
= 0
= 1V
V
V
= 0
= 1V
V
V
= 0
= 3V
DLV_
DHV_
L
DLV_
DHV_
DLV_
DHV_
L
0
0
0
R = 50Ω
R = 50Ω
L
R = 50Ω
t = 2ns/div
t = 1ns/div
t = 2.5ns/div
DRIVER DC CURRENT-LIMIT
AND OVERVOLTAGE RESPONSE
DRIVER 3V TRAILING-EDGE
TIMING ERROR vs. PULSE WIDTH
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
2.5
2.0
100
80
50
0
V
= 1.5V
POSITIVE PULSE
DHV_
DUT_ = DTV_
V
V
= 1.5V
= 1.5V
DLV_
DHV_
1.5
60
-50
1.0
40
20
0.5
-100
-150
-200
-250
-300
0
0
-20
-40
-60
-80
-100
-0.5
-1.0
-1.5
-2.0
-2.5
NEGATIVE PULSE
NORMALIZED AT PW = 12.5ns,
PERIOD = 25ns, V
= 3V, V
= 0
DHV_
DLV_
-6
-3
0
3
6
9
3
4
5
6
7
8
9
10 11 12 13
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
V
(V)
DUT_
PULSE WIDTH (ns)
V
DUT_
_______________________________________________________________________________________
9
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
80
DRIVE-TO-TERM
TRANSITION
DRIVE-TO-HIGH-IMPEDANCE
TRANSITION
RISING EDGE
60
40
DHV_ TO DTV_
MAX972
DHV_ TO HIGH IMPEDANCE
FALLING EDGE
20
0
0
-20
-40
-60
DLV_ TO DTV_
t = 2ns/div
DLV_ TO HIGH IMPEDANCE
0
NORMALIZED AT V = 1.5V
CM
R = 50Ω
L
R = 50Ω
L
0
0.5
1.0
1.5
2.0
2.5
3.0
t = 2ns/div
COMMON-MODE VOLTAGE (V)
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
2.5
2.0
2.5
2.5
2.0
DUT_ = DLV_
DUT_ = DTV_
DUT_ = DHV_
2.0
1.5
V
DHV_
V
DTV_
= 1.5V
= 1.5V
V
V
= 1.5V
= 1.5V
V
V
= 1.5V
= 1.5V
DLV_
DHV_
DLV_
DTV_
1.5
1.5
1.0
0.5
1.0
1.0
0.5
0.5
0
0
0
-0.5
-0.5
-1.0
-1.5
-2.0
-2.5
-0.5
-1.0
-1.5
-2.0
-2.5
-1.0
-1.5
-2.0
-2.5
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
V
DUT_
V
V
DUT_
DUT_
CROSSTALK, DUT_ DRIVEN BY
DHV_ WITH DLV_ VARIED
CROSSTALK, DUT_ DRIVEN BY
DHV_ WITH DTV_ VARIED
CROSSTALK, DUT_ DRIVEN BY
DLV_ WITH DHV_ VARIED
100
80
100
80
100
80
V
V
= 3V
DHV_
V
V
= 1.5V
= 0
V
V
= 3V
= 1.5V
DTV_
DLV_
DHV_
DTV_
= 0
DLV_
60
40
60
40
60
40
20
20
20
0
0
0
-20
-40
-60
-20
-40
-60
-20
-40
-60
-80
-80
-80
NORMALIZED AT V = 1.5V
DTV_
NORMALIZED AT V
= 3V
NORMALIZED AT V
= 0
DHV_
DLV_
-100
-100
-100
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
V
V
V
DHV_
DLV_
DTV_
10 ______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
CROSSTALK, DUT_ DRIVEN BY
DLV_ WITH DTV_ VARIED
CROSSTALK, DUT_ DRIVEN BY
DTV_ WITH DHV_ VARIED
CROSSTALK, DUT_ DRIVEN BY
DTV_ WITH DLV_ VARIED
100
80
100
80
100
80
V
V
= 3V
= 0
V
V
= 3V
= 1.5V
V
DTV_
V
DLV_
= +1.5V
= -1.5V
DHV_
DLV_
DHV_
DTV_
60
40
60
40
60
40
20
20
20
0
0
0
-20
-40
-60
-20
-40
-60
-20
-40
-60
-80
-80
-80
NORMALIZED AT V
= 0
NORMALIZED AT V
= 3V
NORMALIZED AT V
= 1.5V
DLV_
DHV_
DTV_
-100
-100
-100
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
V
V
V
DLV_
DTV_
DHV_
COMPARATOR RESPONSE TO
0 TO 3V SIGNAL
DRIVER GAIN vs. TEMPERATURE
DRIVER OFFSET vs. TEMPERATURE
1.0008
1.0006
1.0004
1.0002
1.0000
5
V
V
= V = 1.5V, R = 50Ω
CLV_ L
CHV_
= 1V, V
= 0
4
3
COMPHI
COMPLO
2
1
0
-1
0.9998
0.9996
-2
-3
NORMALIZED AT T = +85°C
NORMALIZED AT T = +85°C
J
J
50
60
70
80
90
100
50
60
70
80
90
100
t = 2.0ns/div
TEMPERATURE (°C)
TEMPERATURE (°C)
COMPARATOR TIMING VARIATION
vs. PULSE WIDTH
COMPARATOR OFFSET
vs. COMMON-MODE VOLTAGE
COMPARATOR WAVEFORM TRACKING
50
30
400
300
200
100
0
0.20
0.15
0.10
0.05
0
V
DUT_
FALLING
10
V
RISING
DUT_
-10
-30
-50
-70
-90
-110
-130
-150
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-100
-200
-300
-400
NORMALIZED AT V = 1.5V
CM
OTHER COMPARATOR REFERENCE = -2.5V
NORMALIZED AT 50% REFERENCE
= 0 TO 1V PULSE
V
DUT_
NORMALIZED AT PW = 10ns
0
20
40
60
80
100
1
2
3
4
5
6
7
8
9
10
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
COMMON-MODE VOLTAGE (V)
REFERENCE LEVEL (%)
PULSE WIDTH (ns)
______________________________________________________________________________________ 11
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
COMPARATOR TIMING VARIATION
COMPARATOR OFFSET
vs. TEMPERATURE
COMPARATOR RESPONSE
vs. HIGH SLEW-RATE OVERDRIVE
vs. INPUT SLEW RATE
60
50
40
150
100
50
INPUT SLEW RATE = 6V/ns
TERM MODE, V
= 0 TO 1V
DTV_
MAX972
V
FALLING
V
RISING
DUT_
DUT_
30
20
0
-50
10
-100
-150
-200
-250
-300
0
-10
-20
-30
-40
-50
-60
NORMALIZED AT SR = 2V/ns
= 1V, V = 0, R = 50Ω
-350
-400
NORMALIZED AT T = +75°C
V
= 1V, V
= 0, R
= 50Ω
J
COMPHI
COMPLO
COMP_
V
COMPHI
COMPLO
L
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SLEW RATE (V/ns)
50
60
70
80
90
100
t = 2ns/div
TEMPERATURE (°C)
HIGH-IMPEDANCE LEAKAGE AT DUT_
vs. DUT_ VOLTAGE
DRIVE 1V TO LOW-LEAKAGE TRANSITION
LOW LEAKAGE TO DRIVE 1V TRANSITION
0.2
0.1
0
10μA
-0.1
-0.2
10μA
-0.3
-0.4
-0.5
-0.6
-0.7
0μA
0μA
-0.8
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
t = 2.5μs/div
t = 100ns/div
V
DUT_
(V)
LOW-LEAKAGE CURRENT
vs. DUT_VOLTAGE
I
SUPPLY CURRENT
vs.TEMPERATURE
I
SUPPLY CURRENT
SS
vs.TEMPERATURE
DD
1.8
1.7
1.6
1.5
1.4
108
107
-104
-105
-106
106
105
104
-107
-108
-109
-110
1.3
1.2
1.1
1.0
0.9
103
102
101
100
0.8
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
50
60
70
80
90
100
50
60
70
80
90
100
V
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
DUT_
12 ______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
PASSIVE LOAD OFFSET
vs. TEMPERATURE
PASSIVE LOAD HIGH RESISTOR
vs. VOLTAGE
PASSIVE LOAD LOW RESISTOR
vs. VOLTAGE
160
140
8000
7900
7800
7700
7600
7500
7400
2200
2150
2100
2050
2000
1950
1900
1850
1800
DUT_ = DLV_
= -2.2V
DUT_ = DLV_
V
= -2.2V
DLV_
120
100
80
V
DLV_
V
= +5.2V
DLV_
V
= +5.2V
DLV_
60
40
7300
7200
7100
V
= +1.5V
V
DLV_
= +1.5V
DLV_
20
0
-20
7000
50
60
70
80
90
100
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
VOLTAGE (V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
VOLTAGE (V)
TEMPERATURE (°C)
PMU_ FORCE_ SWITCH RESISTANCE
vs. FORCE_ CURRENT
PMU_ FORCE_ SWITCH RESISTANCE
vs. FORCE_ CURRENT
PMU_ FORCE_ SWITCH RESISTANCE
vs. FORCE_ CURRENT
45
42
39
36
33
30
27
24
21
18
15
45
42
39
36
33
30
27
24
21
18
15
45
42
39
36
33
30
27
24
21
18
15
V = -2.2V
PMU_
V
= 5.2V
V
= 1.5V
PMU_
PMU_
-50 -40 -30 -20 -10
0
10 20 30 40 50
-50 -40 -30 -20 -10
0
10 20 30 40 50
-50 -40 -30 -20 -10
0
10 20 30 40 50
FORCE_ CURRENT (mA)
FORCE_ CURRENT (mA)
FORCE_ CURRENT (mA)
______________________________________________________________________________________ 13
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
Pin Description
PIN
1
NAME
DATA1
RCV1
GND
FUNCTION
Channel 1 Multiplexer Control Input. Selects driver 1 input from DHV1 or DLV1 in drive mode. See
Table 1 and Figure 2.
2
Channel 1 Multiplexer Control Input. Sets channel 1 mode to drive or receive. See Table 1 and Figure 2.
3, 8, 13,
18, 51
Analog Ground
MAX972
4
5
CMPH1 Channel 1 High-Side Comparator Output
CMPL1
DATA2
RCV2
Channel 1 Low-Side Comparator Output
Channel 2 Multiplexer Control Input. Selects driver 2 input from DHV2 or DLV2 in drive mode. See
Table 1 and Figure 2.
6
7
Channel 2 Multiplexer Control Input. Sets channel 2 mode to drive or receive. See Table 1 and Figure 2.
9
CMPH2 Channel 2 High-Side Comparator Output
10
11
12
14
CMPL2
CMPL3
Channel 2 Low-Side Comparator Output
Channel 3 Low-Side Comparator Output
CMPH3 Channel 3 High-Side Comparator Output
RCV3
DATA3
CMPL4
Channel 3 Multiplexer Control Input. Sets channel 3 mode to drive or receive. See Table 1 and Figure 2.
Channel 3 Multiplexer Control Input. Selects driver 3 input from DHV3 or DLV3 in drive mode. See
Table 1 and Figure 2.
15
16
17
19
Channel 4 Low-Side Comparator Output
CMPH4 Channel 4 High-Side Comparator Output
RCV4
Channel 4 Multiplexer Control Input. Sets channel 4 mode to drive or receive. See Table 1 and Figure 2.
Channel 4 Multiplexer Control Input. Selects driver 4 input from DHV4 or DLV4 in drive mode. See
Table 1 and Figure 2.
20
DATA4
21
22
23
24
25
26
27
28
29
30
31
32
DHV4
DLV4
DTV4
CHV4
CLV4
DHV3
DLV3
DTV3
CHV3
CLV3
DGND
DOUT
Channel 4 Driver High Voltage Input
Channel 4 Driver Low Voltage Input
Channel 4 Driver Termination Voltage Input
Channel 4 Threshold Voltage Input for High-Side Comparator
Channel 4 Threshold Voltage Input for Low-Side Comparator
Channel 3 Driver High Voltage Input
Channel 3 Driver Low Voltage Input
Channel 3 Driver Termination Voltage Input
Channel 3 Threshold Voltage Input for High-Side Comparator
Channel 3 Threshold Voltage Input for Low-Side Comparator
Digital Ground Connection
Serial-Interface Data Output
Load Input. Latches data from the serial input register to the control register on rising edge.
Transparent when low.
33
LD
34
35
36
37
38
DIN
SCLK
CS
Serial-Interface Data Input
Serial Clock
Chip Select
SENSE4
Channel 4 PMU Sense Connection
FORCE4 Channel 4 PMU Force Connection
14 ______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
Pin Description (continued)
PIN
39
NAME
FUNCTION
SENSE3
Channel 3 PMU Sense Connection
40
FORCE3 Channel 3 PMU Force Connection
41
TEMP
Temperature Sensor Output
42, 47, 52,
56, 60
V
DD
Positive Power-Supply Input
43
44
DUT4
PMU4
Channel 4 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 4.
Channel 4 Parametric Measurement Connection. PMU switch I/O node for channel 4.
45, 50, 53,
57
V
Negative Power-Supply Input
SS
46
48
49
54
55
58
59
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
—
V
Logic Power-Supply Input
L
DUT3
PMU3
PMU2
DUT2
PMU1
DUT1
Channel 3 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 3.
Channel 3 Parametric Measurement Connection. PMU switch I/O node for channel 3.
Channel 2 Parametric Measurement Connection. PMU switch I/O node for channel 2.
Channel 2 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 2.
Channel 1 Parametric Measurement Connection. PMU switch I/O node for channel 1.
Channel 1 Device-Under-Test Connection. Driver, comparator, and load I/O node for channel 1.
FORCE2 Channel 2 PMU Force Connection
SENSE2 Channel 2 PMU Sense Connection
FORCE1 Channel 1 PMU Force Connection
SENSE1 Channel 1 PMU Sense Connection
COMPLO Comparator Output-Low Voltage Reference Input
COMPHI Comparator Output-High Voltage Reference Input
LDV4
LDV3
LDV2
LDV1
CLV2
CHV2
DTV2
DLV2
DHV2
CLV1
CHV1
DTV1
DLV1
DHV1
EP
Channel 4 Load Voltage Input
Channel 3 Load Voltage Input
Channel 2 Load Voltage Input
Channel 1 Load Voltage Input
Channel 2 Threshold Voltage Input for Low-Side Comparator
Channel 2 Threshold Voltage Input for High-Side Comparator
Channel 2 Driver Termination Voltage Input
Channel 2 Driver Low Voltage Input
Channel 2 Driver High Voltage Input
Channel 1 Threshold Voltage Input for Low-Side Comparator
Channel 1 Threshold Voltage Input for High-Side Comparator
Channel 1 Driver Termination Voltage Input
Channel 1 Driver Low Voltage Input
Channel 1 Driver High Voltage Input
Exposed Pad. Leave unconnected or connect to ground.
______________________________________________________________________________________ 15
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
ONE OF FOUR IDENTICAL CHANNELS SHOWN
MAX9972
DHV_
50Ω
MULTIPLEXER
BUFFER
DUT_
DTV_
DLV_
0
MAX972
LLEAK
HIGH IMPEDANCE
DATA_
RCV_
0
HIGH-IMPEDANCE
LOGIC
TERM
CHV_
CMPH_
CMPL_
SEE
TABLE 3
CLV_
LDV_
7.5kΩ
0
0
LOAD EN
HIGH
2.0kΩ
LOAD EN
LOW
30Ω
1kΩ
PMU_
TEMP
FORCE_
SENSE_
0
0
FORCE EN
SENSE EN
COMMON TO ALL FOUR CHANNELS
COMPHI
COMPLO
V
DD
TERM
CS
V
L
SCLK
LLEAK
V
SS
DIN
LD
SENSE EN
FORCE EN
LOAD EN LOW
SERIAL
INTERFACE
GND
DGND
DOUT
LOAD EN HIGH
Figure 1. Block Diagram
16 ______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
The nominal driver output resistance is 50Ω. Custom
Detailed Description
The MAX9972 is a four-channel, pin-electronics IC for
resistance values from 45Ω to 51Ω are possible; con-
sult factory for further information.
automated test equipment that includes, for each chan-
nel, a three-level pin driver, a window comparator, a
passive load, and a Kelvin instrument connection
(Figure 1). All functions feature a -2.2V to +5.2V operat-
ing range and the drivers include both high-impedance
and active-termination (3rd-level drive) modes. The
comparators feature programmable output voltages,
allowing optimization for different CMOS interface stan-
dards. The loads have selectable output resistance for
optimizing DUT current loading. The Kelvin paths allow
accurate connection of an instrument with 25mA
source/sink capability. Additionally, the MAX9972 offers
a low-leakage mode that reduces DUT_ leakage cur-
rent to less than 20nA.
Table 1. Driver Channel Control Signals
EXTERNAL
INTERNAL
DRIVER
OUTPUT
DRIVER
MODE
CONNECTIONS CONTROL BITS
RCV_ DATA_ TERM LLEAK
0
0
0
1
X
X
0
0
DUT_ = DLV_
DUT_ = DHV_
Drive
Drive
High
Impedance
1
1
X
X
X
X
0
1
X
0
0
1
Receive
DUT_ = DTV_ Receive
Low
Low Leak
Each of the four channels feature single-ended CMOS-
compatible inputs, DATA_ and RCV_, for control of the
driver signal path (Figure 2). The MAX9972 modal
operation is programmed through a 3-wire, low-voltage
CMOS-compatible serial interface.
Leakage
0
1
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs: DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_ and
RCV_, and mode-control bit TERM (Table 1). DATA_
and RCV_ are single-ended inputs with threshold levels
DLV_
0
1
50Ω
0
BUFFER
DUT_
DHV_
DTV_
LLEAK
DATA_
RCV_
equal to V /2. Each channel’s threshold levels are inde-
L
COMPARATORS
AND LOAD
pendently generated to minimize crosstalk.
DUT_ can be toggled at high speed between the buffer
output and high-impedance mode, or it can be placed
into low-leakage mode (Figure 2, Table 1). High-speed
input RCV_ and mode-control bits TERM and LLEAK
control these modes. In high-impedance mode, the
bias current at DUT_ is less than 2µA over the -2.2V to
+5.2V range, while the node maintains its ability to
track high-speed signals. In low-leakage mode, the
bias current at DUT_ is further reduced to less than
20nA, and signal tracking slows.
TERM
HIGH
IMPEDANCE
MAX9972
Figure 2. Multiplexer and Driver Channel
______________________________________________________________________________________ 17
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
Comparators
The MAX9972 provides two independent high-speed
Table 2. Comparator Logic
comparators for each channel. Each comparator has
one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (see Figure 1).
Comparator outputs are a logical result of the input
conditions, as indicated in Table 2.
DUT_ > CHV_ DUT_ > CLV_
CMPH_
CMPL_
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
The comparator output voltages are easily interfaced to a
wide variety of logic standards. Use buffered inputs
COMPHI and COMPLO to set the high and low output
voltages. For correct operation, COMPHI should be
greater than or equal to COMPLO. The comparator 50Ω
output impedance provides source termination (Figure 3).
MAX972
MAX9972
Passive Load
The MAX9972 channels each feature a passive load
consisting of a buffered input voltage, LDV_, connected
to DUT_ through two resistive paths (Figure 1). Each
path connects to DUT_ individually by a switch con-
trolled through the serial interface. Programming
options include none (load disconnected), either, or
both paths connected. The loads facilitate fast
open/short testing in conjunction with the comparator,
and pullup of open-drain DUT_ outputs.
COMPHI
CHV_
50Ω
CMPH_
DUT_
Parametric Switches
Each of the four MAX9972 channels provides force-
and-sense paths for connection of a PMU or other DC
resource to the device-under-test (Figure 1). Each
force-and-sense switch is independently controlled
though the serial interface providing maximum applica-
tion flexibility. PMU_ and DUT_ are provided on sepa-
rate pins allowing designs that do not require the
parametric switch feature to avoid the added capaci-
tance of PMU_. It also allows PMU_ to connect to DUT_
either directly or with an impedance-matching network.
50Ω
CMPL_
CLV_
COMPLO
Figure 3. Complementary 50Ω Comparator Outputs
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port places the
MAX9972 into a very-low-leakage state (see the
Electrical Characteristics table). This mode is conve-
nient for making IDDQ and PMU measurements without
the need for an output disconnect relay. LLEAK control
is independent for each channel.
Table 3. Passive Load Resistance Values
HIGH RESISTOR (kΩ)
LOW RESISTOR (kΩ)
7.5
2
Temperature Monitor
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal opera-
tion. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behav-
ior under this condition.
Each device supplies a single temperature output sig-
nal, TEMP, that asserts a nominal 3.43V output voltage
at a +70°C (343K) die temperature. The output voltage
increases proportionately with temperature at a rate of
10mV/°C. The temperature sensor output impedance is
500Ω, typical.
18 ______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
The latches contain the six mode bits for each channel
of the device. The mode bits, in conjunction with exter-
nal inputs DATA_ and RCV_, manage the features of
each channel. Transfer data asynchronously from the
input registers to the channel registers by forcing LD
low. With LD always low, data transfer on the rising
edge of CS.
Serial Interface and Device Control
A CMOS-compatible serial interface controls the
MAX9972 modes (Figure 4). Control data flow into a 12-
bit shift register (LSB first) and are latched when CS is
taken high. Data from the shift register are then loaded
to the per-channel control latches as determined by
bits D8–D11, and indicated in Figure 4 and Table 4.
SCLK
DIN
11
10
9
8
7
6
5
4
3
2
1
0
ENABLE
CS
LD
MAX9972
QUAD F/F
QUAD F/F
QUAD F/F
QUAD F/F
0–5
0–5
11
0–5
8
0–5
D
Q
D
Q
D
Q
D
Q
9
10
ENABLE
LOAD
ENABLE
LOAD
ENABLE
LOAD
ENABLE
LOAD
6
6
6
6
MODE BITS
CHANNEL 1
MODE BITS
CHANNEL 2
MODE BITS
CHANNEL 3
MODE BITS
CHANNEL 4
Figure 4. Serial Interface
Table 4. Control Register Bit Functions
BIT STATE
POWER-UP
STATE
BIT
NAME
FUNCTION
0
1
0
1
TERM
LLEAK
Term Mode Control
Assert Low-Leakage Mode
Enable Sense Switch
High Impedance
Term Mode
Disabled
Disabled
Disabled
Disabled
X
Term Mode
Low Leakage
Enabled
Enabled
Enabled
Enabled
X
0
0
0
0
0
0
0
0
1
1
1
1
2
SENSE EN
FORCE EN
LOAD EN LOW
LOAD EN HIGH
—
3
Enable Force Switch
4
Enable Low Load Resistor
Enable High Load Resistor
Unused
5
6
7
—
Unused
X
X
8
CH1
Update Channel 1 Control Register
Update Channel 2 Control Register
Update Channel 3 Control Register
Update Channel 4 Control Register
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
9
CH2
10
11
CH3
CH4
______________________________________________________________________________________ 19
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
t
CH
SCLK
t
t
CL
t
CSS1
CSSO
t
t
CSH1
9
CSHO
CS
t
CSWH
t
DH
t
DS
DIN
D0
D1
D2
D3
D4
D5
D10
D11
t
DO
D10 LAST
D11 LAST
D0
DOUT
LOAD
D0 LAST
D1 LAST
D2 LAST
D3 LAST
D4 LAST
D5 LAST
t
CSHLD
t
LDW
Figure 5. Serial-Interface Timing
Heat Removal
Chip Information
Package Information
With adequate airflow, no external heat sinking is need-
ed under most operating conditions. If excess heat must
be dissipated through the exposed pad, solder it to cir-
cuit board copper. The exposed pad must be either left
unconnected, isolated, or connected to ground.
PROCESS: BiCMOS
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Power Minimization
To minimize power consumption, activate only the
needed channels. Each channel placed in low-leakage
mode saves approximately 240mW.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
80 TQFP-EP
C80E+4
21-0115
90-0152
20 ______________________________________________________________________________________
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
MAX972
Pin Configuration
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62
61
+
DATA1
1
2
60
V
DD
RCV1
GND
59 DUT1
58 PMU1
3
CMPH1
CMPL1
DATA2
RCV2
4
57
56
V
V
SS
5
DD
6
55 DUT2
54 PMU2
7
GND
8
53
52
V
V
SS
9
CMPH2
CMPL2
CMPL3
CMPH3
DD
10
11
12
51 GND
50
MAX9972
V
SS
49 PMU3
48 DUT3
GND 13
RCV3 14
47
46
45
V
V
V
DD
L
DATA3
CMPL4
CMPH4
15
16
17
SS
44 PMU4
43 DUT4
EP
GND 18
RCV4 19
DATA4 20
V
42
41
DD
TEMP
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
TQFP
______________________________________________________________________________________ 21
Quad, Ultra-Low-Power, 300Mbps ATE
Drivers/Comparators
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/06
Initial release
—
Changed driver offset max value in Electrical Characteristics table and removed all
references to MAX9971
1
2
7/09
4/10
1–22
Added soldering temperature to Absolute Maximum Ratings, updated SCLK to DOUT
specification in Electrical Characteristics table, and replaced Figure 5
MAX972
2, 7, 20
3
4
9/10
Updated Absolute Maximum Ratings and Figure 1
Updated Electrical Characteristics table and notes
2, 16
12/10
3, 4, 7, 8
Changed maximum DC drive current in Electrical Characteristics table to reflect actual
circuit operation
5
6
7
1/11
3/11
6/11
2
Narrowed down product offerings and modified exposed die pad connection
description; added CS high pulse width to Electrical Characteristics table
1, 2, 4, 5, 7, 15,
17, 18, 20
Corrected/changed SPI timing parameters to improve yield and changed global levels
2–8
for V
and V
COMPLO
COMPHI
8
9
6/11
Restored original global levels changed in Rev 7
Correct value for Temp Sensor nominal voltage
2–8
7
10/11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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