MAX9979KCTK+TD [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFN-68;
| 型号： | MAX9979KCTK+TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFN-68 信息通信管理 转换器 |
| 文件： | 总60页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4134; Rev 6; 8/11
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
General Description
Features
The MAX9979 fully integrated, high-performance, dual-
channel pin electronics integrates multiple automatic test
equipment (ATE) functions into a single IC, including dri-
ver/comparator/load (DCL), parametric measurement unit
(PMU), and built-in (16-bit) level-setting digital-to-analog
converters (DACs). The device is ideal for memory and
SOC tester applications. Each channel includes a four-
level pin driver, window comparator, differential compara-
tor, dynamic clamps, a versatile PMU, an active load, a
high-voltage (VHH) programmable level, and 14 indepen-
dent level-setting DACs. The MAX9979 features program-
mable cable-droop compensation for the driver output
and for the comparator input, adjustable driver output
resistance that allows optimal performance over typical
data-path transmission-line variations, slew-rate adjust-
ment, and a programmable high-voltage driver output.
o High Speed: 1.1Gbps at 1V
P-P
o Extremely Low Power Dissipation: 1.2W/Channel
(Active Load Disabled)
o Wide Voltage Range: -1.5V to +6.5V and Up to 13V
VHH
o Wide Voltage Swing Range: 50mV
o Low-Leak Mode: 10nA max
to 13V
P-P
P-P
o Integrated Termination-on-the-Fly (3rd-Level
Drive)
o Integrated VHH High Voltage (4th-Level Drive)
o Integrated Voltage Clamps
o Integrated 20mA Active Load
o Integrated Per-Pin PMU
The MAX9979 driver features a wide 8V (-1.5V to +6.5V)
high-speed operating voltage range and a VHH program-
mable range of up to +13V. Operation modes include
high-impedance, active-termination (3rd-level drive) and
VHH (4th-level drive) modes. The device is highly linear
even at low voltage swings. The driver provides high-
speed differential control inputs compatible with most
high-speed logic families. The window comparators pro-
vide extremely low timing variation over changes in slew
rate, pulse width, and overdrive voltage. In high-imped-
ance mode, the MAX9979 features dynamic clamps that
dampen high-speed device-under-test (DUT) waveforms.
The 20mA active load facilitates fast contact testing when
used in conjunction with the comparators, and functions
as a pullup/pulldown for open-drain/collector DUT out-
puts. The PMU offers five current ranges from 2ꢀA to
50mA and can force and measure current or voltage.
An SPI™-compatible serial interface configures the
MAX9979.
o Integrated Level-Setting CALDACs
o Programmable Cable-Droop Compensation for
Both Driver Output and Comparator Input
o Programmable Driver Output Impedance
o Four Slew-Rate Settings for Driver Output
o Analog Measure Bus
o Very Low Timing Dispersion
o Minimal External Component Count
o SPI-Compatible Serial Control Interface
o 68-Pin Thermally Enhanced TQFN Package with
Top-Side Heat Removal
The MAX9979 is available in a small footprint, 68-pin
(10mm x 10mm x 1mm) TQFN-EP-IDP package with
exposed pad on the top for easy heat removal. Power dis-
sipation is 1.2W per channel (typ) over the full operating
voltage range with the active load disabled. The
MAX9979 operates over an internal die temperature
range of +40°C to +100°C and provides a temperature
monitor output.
Ordering Information
PART
MAX9979KCTK+
TEMP RANGE
PIN-PACKAGE
0°C to +70°C
68 TQFN-EP-IDP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP-IDP = Exposed pad, inverted die pad.
Applications
Memory ATE Testers
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
SOC ATE Testers
SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ABSOLUTE MAXIMUM RATINGS
V
V
V
V
V
to GND............................................................-0.3V to +11V
to GND............................................................-5.5V to +0.3V
TEMP to GND .................................................................0 to V
CC
CC
EE
MEAS_ to GND.................................(V - 0.3V) to (V
REF to GND..............................................-0.3V to (2.6V + V
+ 0.3V)
)
DGS
EE
CC
to V ...........................................................-0.3V to +16.5V
CC
DD
HHP
EE
to DGND ........................................................-0.3V to +5.2V
to GND..........................................................-0.3V to +19V
Current into SCLK, DIN, CS, RST, LOAD ......................... 30mA
Current into LLEAKP_, HIZMEASP_, ENVHHP_,
DGND to GND .................................................................... 0.3V
CTV_, BV_ to GND....................................................-0.3V to +5V
DATA_, NDATA_, RCV_,
DUTHI_, DUTLO_ ........................................................... 30mA
PMU-F Continuous Current............................................... 35mA
PMU-F Peak Current......................................................... 70mA
PMU-S Continuous Current ................................................ 1mA
PMU-S Peak Current......................................................... 20mA
DGS to GND ....................................................................... 0.3V
DUT_, SENSE_ Short-Circuit
NRCV_ to GND..............................(V - 0.3V) to (V
+ 0.3V)
+ 0.3V)
EE
BV_
MAX79
CH_, NCH_, CL_, NCL_ to GND..............-1.5V to (V
CTV_
Current into CH_, NCH_, CL_, NCL_................................ 35mA
DATA_ to NDATA_, RCV_ to NRCV_ ..................................... 1V
DUT_, PMU-F, PMU-S, SENSE_ to GND
Duration to V , V ................................................Continuous
CC EE
(non-VHH mode) ...........................(V - 0.3V) to (V
DUT_, PMU-F, PMU-S, SENSE_ to GND
(VHH mode).......................................................-3.5V to +13.5V
SCLK, DIN, CS, RST, LOAD to GND..........-0.3V to (V
LLEAKP_, HIZMEASP_, ENVHHP_, DUTHI_,
+ 0.3V)
Power Dissipation (T = +70°C)*
EE
A
CC
MAX9979KCTK (derate 125mW/°C above +70°C).............10W
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V)
DD
DUTLO_, to GND......................................-0.3V to (V
+ 0.3V)
DD
*Dissipation wattage values are based on still air with no heatsink. Actual maximum power dissipation is a function of heat extraction
technique and may be substantially higher.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS**
TQFN
Junction-to-Case Thermal Resistance (θ )...............8.0°C/W
JA
Junction-to-Ambient Thermal Resistance (θ )......................0.3°C/W
JC
**Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
EE
DD
= 1.4V, V
HHP
= 4V, V
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CPLV_
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER
DC CHARACTERISTICS (R ≥ 10MΩ, unless otherwise noted; includes DAC error)
L
V
V
V
V
V
V
V
= -1.5V, V
= 1.5V
-1.45 to +6.50
-1.50 to +6.45
DHV
DLV_
DHV_
DHV_
DHV_
DLV_
DTV_
DTV_
DTV_
DLV_
Output-Voltage Range
V
V
= 6.5V, V
= 6.5V, V
= 1.5V
V
DLV
DTV
DHV
= -1.5V (Note 2)
-1.50
+6.50
V
= 3V, V
= -1.5V, V
= 1.5V
= 1.5V
5
5
5
DLV_
DHV_
DTV_
Output Offset Voltage
mV
V
V
= 0V, V
= 6.5V, V
DLV
DTV
DTV_
= 1.5V, V
= 6.5V, V
= -1.5V
DHV_
DLV_
Output-Voltage Temperature
Coefficient (Notes 3, 4)
DHV_, DLV_, DTV_
75
500
ꢀV/°C
2
_______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
= -1.5V, V
= 1.5V, V
= 0V
= 0V
= 0V
DLV_
DTV_
DTV_
DLV_
DHV_
A
0.998
1
1.002
DHV_
and 4.5V
V
= 6.5V, V
= 1.5V, V
DHV_
DLV_
A
0.998
0.998
1
1
1.002
1.002
Gain
V/V
DLV
and 4.5V
V
= 6.5V, V
= -1.5V, V
DTV_
DHV_
A
DTV
and 4.5V
V
= -1.5V, V
DTV_
DLV_
= 1.5V, V
= 0V,
2
2
DHV_
0.75V, 1.5V, 2.25V, 3V
= 6.5V, V =
DTV_
0 to 3V relative to
calibration points
at 0 and 3V
V
DHV_
1.5V, V
= 0V,
DLV_
0.75V, 1.5V, 2.25V, 3V
V
= -1.5V, V
DLV_
DHV_
= 6.5V, V
= 0V,
2
DTV_
0.75V, 1.5V, 2.25V, 3V
V
= -1.5V, V
DTV_
DLV_
= 1.5V, V
and 6V
= -1V
4.5
4.5
4.5
6
DHV_
-1V to 6V relative
to calibration
V
= 6.5V, V
=
DTV_
= -1V
DHV_
Linearity Error
1.5V, V
mV
DLV_
points at 0 and 3V and 6V
V
= -1.5V, V
DLV_
DHV_
= -1V
= 6.5V, V
and 6V
DTV_
V
= -1.5V, V
DLV_
DTV_
= 1.5V, V
=
DHV_
-1.25V and 6.5V
V
= 6.5V, V
=
Full range relative
to calibration
DHV_
DTV_
1.5V, V
= -1.5V
6
DLV_
and 6.25V
points at 0 and 3V
V
= -1.5V, V
DLV_
DHV_
= 6.5V, V
and 6.5V
= -1.5V
6
DTV_
_______________________________________________________________________________________
3
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
= 0V, V
=
=
=
DLV_
DTV_
MAX79
DHV_ to DLV_
DLV_ to DHV_
1.5V, V
and 6.5V
= 0.2V
7
DHV_
V
= 5V, V
DHV_
DTV_
1.5V, V
and 4.8V
= -1.5
7
2
3
3
2
DLV_
V
0V, V
and 6.5V
= 3V, V
DHV_
DLV_
DTV_ to DLV_ and
DHV_
Crosstalk
= -1.5V
mV
DTV_
V
0V, V
and 3V
= 1.5V, V
=
=
=
DTV_
DLV_
= 1.6V
DHV_ to DTV_
DLV_ to DTV_
DHV_
V
3V, V
and 1.4V
= 1.5V, V
DTV_
DHV_
= 0
DLV_
V
3V, V
DATA_ = 0 and 1
= 1.5V, V
DTV_
DHV_
Dependence on
DATA_
Term Voltage
= 0V,
mV
dB
DLV_
DHV_
DLV_
DTV_
V
V
V
= 3V
= 0V
40
40
40
DHV_
DLV_
DTV_
DC Power-Supply Rejection
(Note 5)
= 1.5V
DATA_ = 1, V
-1.5V
=
=
DUT_
+60
+110
V
V
= 6.5V,
= -1.5V
DHV_
DLV_
DC Drive Current Limit
DC Output Resistance
mA
Ω
DATA_ = 0, V
6.5V
DUT_
-110
48
-60
52
2
(Note 6)
50
1
DATA_ = 1, V
1.5V, I
= 3V, V
= 0V, V
=
DHV_
DLV_
DTV_
= 1mA, 8mA, 15mA, 40mA
DUT_
DC Output Resistance Variation
(Note 7)
Ω
DATA_ = 0, V
1.5V, I
= 3V, V
= 0V, V
=
DHV_
DLV_
DTV_
1
2
= -1mA, -8mA, -15mA, -40mA
DUT_
Adjustable Output Resistance
Range
R
R
= 0xF vs. R = 0x8 and R = 0x0 vs.
O O
= 0x8, resolution of 0.36Ω (Note 6)
O
2.5
Ω
O
4
_______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
AC CHARACTERISTICS (R
Dynamic Drive Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
_ = 50Ω to Ground) (Note 8)
(Note 9)
DUT
130
30
mA
Cable-droop compensation off, V
= 0V,
= 0V,
= 0V,
= 0V,
DLV_
DLV_
DLV_
DLV_
V
= 0.1V
DHV_
Cable-droop compensation off, V
= 1V
40
50
50
V
DHV_
Drive-Mode Overshoot
mV
Cable-droop compensation off, V
= 3V
V
DHV_
Cable-droop compensation off, V
V
V
V
= 5V
DHV_
DLV_
DLV_
= 0V, V
= 0V, V
= 3V, CDRP_ = 0b000
= 3V, CDRP_ = 0b111
0
DHV_
DHV_
Cable-Droop Compensation
%
10
Termination-Mode Overshoot
Cable-droop compensation off (Note 10)
To within 100mV, V = 5V, V = 0V
0
mV
0.25
0.25
0.25
1
1
1
DHV_
DLV_
Settling Time (Notes 4, 11)
To within 50mV, V
To within 50mV, V
= 3V, V
= 0V
DLV_
ns
DHV_
DHV_
= 0.5V, V
= 0V
DLV_
TIMING CHARACTERISTICS (Notes 8, 12)
Data to output, V
(Note 13)
= 3V, V
= 0V
DLV_
DHV_
1
1.9
2.7
4
Drive to term, term to drive (Notes 4, 14)
1.7
3.7
Propagation Delay
ns
ps
Drive to high impedance, high impedance
to drive, V
= 1V, V
= -1V
DLV_
1.4
2.4
3.4
80
DHV_
(Notes 4, 15)
t
LH
vs. t (Note 4)
40
40
HL
Drivers within package, same edge
Drive to high impedance vs. high
impedance to drive, V
= 1V,
0.5
DHV_
V
= -1V (Note 16)
DLV_
Propagation-Delay Match
ns
ps
High impedance vs. data
Drive to term vs. term to drive, V
0.5
0.3
0.8
= 3V,
= 0V,
DHV_
V
= 0V, V
= 1.5V (Note 17)
DTV_
DLV_
Terminate vs. data
Differential mode, V
= 1V, V
DHV_
DLV_
Propagation-Delay Channel
Match
channel 1 inverted, DIFFERENTIAL0 = 1,
INVERT1 = 1
40
_______________________________________________________________________________________
5
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
= 0V (Note 4)
DLV_
MIN
TYP
MAX
UNITS
Propagation-Delay Temperature
Coefficient
V
= 3V, V
3
5
ps/°C
DHV_
MAX79
V
= 1V, V
=
DLV_
DHV_
0V, 1ns to 24ns pulse
width (Note 4)
25
35
60
60
V
= 3V, V
=
DLV_
DHV_
Change vs. pulse
width (Note 18)
0V, 1ns to 24ns pulse
width (Note 4)
Propagation-Delay Change
ps
V
= 5V, V
=
DLV_
DHV_
0V, 1.5ns to 23.5ns
pulse width
100
50
Peak-to-peak change vs. common mode,
- V = 1V, V = 0 to 6V, using
V
60
DHV_
DLV_
DHV_
a DC-blocking capacitor (Note 4)
0.2V programmed, V = 0.2V,
P-P
DHV_
275
450
650
1000
40
V
= 0V, 20% to 80%
DLV_
1V
programmed, V
= 1V,
DHV_
P-P
330
500
800
550
800
V
= 0V, 10% to 90%
DLV_
Rise-and-Fall Time
ps
3V
programmed, V
= 3V,
DHV_
P-P
V
= 0V, 10% to 90%, trim condition
DLV_
5V
programmed, V
= 5V,
DHV_
P-P
1200
V
= 0V, 10% to 90% (Note 4)
DLV_
0.2V
programmed, V
= 0.2V,
DHV_
P-P
V
= 0V, 20% to 80%
DLV_
1V
programmed, V
= 0V, 10% to 90%
= 1V,
DHV_
P-P
50
130
200
V
DLV_
Rise-and-Fall Time Matching
ps
3V
programmed, V
= 0V, 10% to 90%
= 3V,
= 5V,
P-P
DHV_
50
V
DLV_
5V
programmed, V
DHV_
= 0V, 10% to 90%
P-P
50
V
DLV_
6
_______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
SC1 = 0, SC0 = 1,
= 3V, V
MIN
TYP
MAX
UNITS
V
=
75
DHV_
DLV_
0V, 20% to 80%
SC1 = 1, SC0 = 0,
Relative to SC1 =
SC0 = 0
Slew Rate
V
DHV_
= 3V, V
= 0V,
50
25
%
DLV_
20% to 80%
SC1 = 1, SC0 = 1,
= 3V, V
V
DHV_
= 0V,
DLV_
20% to 80%
0.2V programmed,
P-P
V
V
= 0.2V,
= 0V (Note 19)
800
950
1000
1300
1100
DHV_
DLV_
1V programmed,
P-P
V
DHV_
= 1V, V
= 0V
DLV_
(Note 19)
Positive or
negative
Minimum Pulse Width
ps
3V
V
programmed,
P-P
= 3V, V
= 0V
DLV_
1250
DHV_
(Notes 4, 19)
5V
V
(Note 19)
programmed,
P-P
= 5V, V
= 0V
DLV_
DHV_
0.2V programmed,
V
P-P
= 0.2V, V
DLV_
DHV_
= 0V
1V programmed,
P-P
900
800
To 95%
(Note 20)
P-P
V
DHV_
= 1V, V
= 0V
DLV_
3V programmed,
P-P
V
DHV_
= 3V, V
= 0V
DLV_
5V programmed,
P-P
680
V
DHV_
= 5V, V
= 0V
DLV_
Data Rate
Mbps
0.2V programmed,
P-P
1200
1100
900
V
DHV_
= 0.2V, V
= 0V
DLV_
1V programmed,
P-P
V
DHV_
= 1V, V
= 0V
DLV_
To 90%
P-P
(Note 21)
3V programmed,
P-P
V
DHV_
= 3V, V
= 0V
DLV_
5V programmed,
P-P
720
V
DHV_
= 5V, V
= 0V
DLV_
_______________________________________________________________________________________
7
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
= 3V, V
MIN
TYP
MAX
UNITS
Drive to term, V
= 0V, V
DTV_
DHV_
DLV_
300
500
1000
MAX79
= 1.5V, measured 10% to 90% of waveform
Term to drive, V = 3V, V = 0V, V
DTV_
Rise-and-Fall Time
ps
DHV_
DLV_
300
-1.5
600
850
= 1.5V, measured 10% to 90% of waveform
HIGH-SPEED COMPARATORS
DC CHARACTERISTICS
Input-Voltage Range
(Notes 2, 22)
+6.5
V
V
Differential Input Voltage
Input Offset Voltage
V
V
- V
, V
- V (Note 23)
CLV_
8
5
DUT_
DUT_
CHV_ DUT_
= 1.5V
1
mV
Input-Voltage Temperature
Coefficient
(Notes 4, 24)
= -1.5V, 6.5V (Note 25)
50
175
ꢀV°C
dB
Common-Mode Rejection Ratio
CMRR
PSRR
V
50
50
55
1
DUT_
0 to 3V, V
= 0V, 1.5V, 3V
5
DUT_
Linearity Error (Note 26)
mV
dB
Full range, V
= -1.5V, 0V, 1.5V, 3V, 6.5V
1
10
DUT_
Power-Supply Rejection Ratio
V
= -1.5 and 6.5V (Notes 5, 27)
66
DUT_
HYST0
HYST1
HYST2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
2
4
Hysteresis
6
mV
8
10
12
15
AC CHARACTERISTICS (Notes 4, 28, 29, 30)
Minimum Pulse Width
(Note 31)
0.50
0.9
0.65
1.5
ns
ns
Propagation Delay
0.5
Propagation-Delay Temperature
Coefficient
1.7
10
40
25
30
ps/°C
ps
High/low vs. low/high, absolute value of
delta for each comparator
Propagation-Delay Match
25
55
40
55
Propagation-Delay Dispersion vs.
Common-Mode Input
-1.4V to +6.4V (Note 32)
ps
P-P
Propagation-Delay Dispersion vs.
Duty Cycle
0.6ns to 24.4ns pulse width, relative to 5ns
pulse width
ps
Propagation-Delay Dispersion vs.
Slew Rate
1V/ns to 6V/ns, relative to 2V/ns (Note 33)
ps
8
_______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
= 0.5V, driver terminated (Note 34)
MIN
1000
TYP
1500
700
0
MAX
UNITS
V
DTV_
Equivalent 20–80 Bandwidth
MHz
Driver high impedance
CDRP = 0b000
CDRP = 0b111
Cable-Droop Compensation,
Peaking
1V swing, rise/fall time =
500ps, DRV terminated
%
10
LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_ collector output, R = 50Ω internal pullup to CTV)
L
Termination Voltage
CTV
0
3.5
V
mA
mA
V
_
Output High Current
Output Low Current
0
16
Output-Voltage Compliance
Differential Rise Time
Differential Fall Time
Termination Resistor Value
Set by I
, R
and V
-0.5
CTV
_
OUT_ TERM_
CTV
20% to 80% (Note 4)
20% to 80% (Note 4)
200
200
400
400
52
ps
ps
Ω
CTV to CH_, NCH_, CL_, NCL_
48
_
With output resistors, R
(Note 56)
to V
CTV - CTV -
TERM
CTV
CTV
_
_
Output High Voltage
Output Low Voltage
Output-Voltage Swing
V
CTV
V
V
OH
_
0.1
0.02
With output resistors, R
(Note 56)
to V
CTV - CTV - CTV -
TERM
_
_
_
V
OL
0.55
0.4
0.35
With output resistors, 50Ω nominal trim
(Note 56)
350
400
450
mV
DYNAMIC CLAMPS
CPHV_ Functional Clamp Range
I
I
_ = -1mA, V
= -1.5V (Note 2)
= 6.5V (Note 2)
-0.3
-1.5
+6.5
+5.3
V
V
DUT
CPLV_
CPLV_ Functional Clamp Range
_ = 1mA, V
DUT
CPHV_
CPHV_ Maximum Programmable
Voltage
I
I
_ = 0mA (Note 23)
_ = 0mA (Note 23)
7.2
7.5
V
V
DUT
CPLV_ Minimum Programmable
Voltage
-2.5
-2.2
DUT
I
= -1mA, V
= 1mA, V
= 1.5V, V = -1.5V
CPLV_
10
10
DUT_
CPHV_
Offset Voltage
mV
I
= 1.5V, V
= 6.5V
DUT_
CPLV_
CPHV_
Offset-Voltage Temperature
Coefficient
V
= V
= 1.5V
CPLV_
0.5
mV/°C
CPHV_
I
= -1mA, V
= 1.5V, V
=
DUT_
CPHV_ CPLV_
40
40
-1.5V (Note 5)
Power-Supply Rejection Ratio
dB
I
= +1mA, V
= 1.5V, V
=
CPHV_
DUT_
CPLV_
6.5V (Note 5)
High Clamp Voltage Gain
Low Clamp Voltage Gain
V
V
= -0.3V, 6.5V
0.998
0.998
1.002
1.002
V/V
V/V
CPHV_
CPLV_
= -1.5V, 5.3V
Voltage-Gain Temperature
Coefficient
100
ppm/°C
_______________________________________________________________________________________
9
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
_ = -1mA, V = -0.3V, 1.5V, 3.25V,
MIN
TYP
MAX
UNITS
I
DUT
CPHV_
30
MAX79
5V, 6.5V
Linearity
mV
I
_ = 1mA, V
4V, 5.3V
= -1.5V, 0.5V, 2.25V,
DUT
CPLV_
CPLV_
CPHV_
CPLV_
30
-60
120
55
V
6.5V
= 0V, V
= 5V, V
= 0V, V
= -1.5V, R = 0Ω to
L
CPHV_
-120
60
Static Output Current
mA
V
= 6.5V, R = 0Ω to
L
CPLV_
-1.5V
V
= -1.5V, I
_ =
DUT
CPHV_
High Clamp Resistance
48
Ω
Ω
Ω
-5mA and -15mA
V
= 6.5V, V
= 0V, I _ = 5mA
DUT
CPHV_
CPLV_
Low Clamp Resistance
48
55
and 15mA
I
V
_ = -20mA and -30mA, V
DUT
= 2.5V,
CPHV_
High Clamp-Resistance Variation
5
= -1.5V (Note 35)
CPLV_
I
V
_ = 20mA and 30mA, V
= 2.5V,
CPLV_
DUT
Low Clamp-Resistance Variation
Overshoot and Undershoot
5
Ω
= 6.5V (Note 35)
CPHV_
(Note 36)
700
mV
PARAMETRIC MEASUREMENT UNIT (PMU)
DC ELECTRICAL CHARACTERISTICS
FORCE VOLTAGE (R ≥ 10MΩ, V
= 2.5V, unless otherwise noted)
L
IN_
I
I
I
I
I
I
= 0mA
-1.5
-1.5
-1.5
1.1
-1.1
-5
+6.5
+4.5
+6.1
6.5
DUT_
DUT_
DUT_
DUT_
DUT_
DUT_
= +FSR/2, range A
Force-Voltage Output Range
(Note 2)
V
= +FSR/2, ranges B–E
= -FSR/2, range A
= -FSR/2, ranges B–E
= 0mA
V
IN
+6.5
+5
Force-Voltage Offset Error
Force-Voltage PSRR
mV
(Note 5)
-5
+5
mV/V
I
= +FSR/2 to -FSR/2 using SENSE_
DUT_
Force-Voltage Load Regulation
200
50
ꢀV
input
Force-Voltage Offset
Temperature Coefficient
(Note 37)
ꢀV/°C
%
Force-Voltage Gain Error
V
V
= -1.5V to +6.5V, nominal gain = +1
= -1.5V, 0.5V, 2.5V, 4.5V, 6.5V
-0.1
+0.1
IN
IN
Force-Voltage Gain Temperature
Coefficient
10
ppm/°C
Force-Voltage Linearity Error
-0.02
+0.02
%FSR
(Notes 38, 39)
10 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
From any two adjacent ranges, C
=
DUT_
Force-Voltage Range Switching
Glitch
100pF, I
= ( 0.25 x FSR) of lower
0.3
V
DUT_
current range (Note 4)
MEASURE CURRENT (Measured at MEAS_ in FIMI mode, V
= V
= V
= 2.5V)
IN_
IIOS
DUT_
Measure-Current Offset
IMOS
(Note 38)
-1
+1
%FSR
Measure-Current PSRR
I
= 0mA (Note 5)
-0.05
+0.05 %FSR/V
DUT_
Measure-Current Offset
Temperature Coefficient
ppmFSR/
°C
20
Ranges A, B, C
Ranges D, E
Ranges B–E
Range A
-1.0
-1.1
+1.0
%
Measure-Current Gain Error
IMGE
+1.1
20
Measure-Current Gain
Temperature Coefficient
ppm/°C
+0.02
+100
Ranges B–E, I
= -FSR/2, -FSR/4, 0,
DUT_
-0.02
-0.03
-0.06
FSR/4, FSR/2 relative to end points
Measure-Current Linearity Error
(Note 38)
Range A, I = -30mA, -15mA, 0, 15mA,
DUT_
IMLER
+0.03
+0.06
%FSR
30mA, relative to end points
Range A, I = -FSR/2, -FSR/4, 0, FSR/4,
DUT_
FSR/2 relative to end points
V
V
V
V
= 2V (Note 40)
= 4V (Note 40)
= 2V (Note 40)
= 4V (Note 40)
6
8
IIOSMIN
IIOSMAX
IIOSMIN
IIOSMAX
+FSR Measure Output Voltage
-FSR Measure Output Voltage
V
V
-2
0
Rejection of Output Measure Error Due
to Common-Mode Sense Voltage
I
= 0mA, V = -1.5V to +6.5V, percent
DUT_ IN_
CMVRLER
0.003 %FSR/V
+2
FSR change at MEAS_ per volt change at DUT_
Range E, R_E = 500kΩ
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
-2
-20
-200
-2
+20
+200
+2
ꢀA
Measure-Current Range (Note 2)
Range B, R_B = 500Ω
Range A, R_A = 20Ω (Note 41)
mA
-50
+50
FORCE CURRENT (V
= V
= V
= 2.5V, unless otherwise noted)
DUT_
IN_
IIOS
V
V
V
V
= 2V
6
IIOSMIN
IIOSMAX
IIOSMIN
IIOSMAX
Input-Voltage Range For Setting
Force Current to +FSR/2
V
V
V
= 3.5V
= 2V
7.5
-2
Input-Voltage Range For Setting
Force Current to -FSR/2
= 3.5V
-0.5
Current-Sense Amplifier Offset
Voltage Input
Relative to V
2.0
2.5
3.5
DGS
______________________________________________________________________________________ 11
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
Force-Current Offset
SYMBOL
CONDITIONS
MIN
-0.1
-0.2
TYP
MAX
+0.1
+0.2
UNITS
%FSR
(Note 38)
(Note 5)
MAX79
Force-Current Offset PSRR
%FSR/V
Force-Current Offset-Temperature
Coefficient
ppmFSR/
°C
(Note 37)
20
Force-Current Gain Error
V
= -1.5V and 6.5V
-0.1
+0.1
%
IN_
Ranges B–E
Range A
20
Force-Current Gain-Temperature
Coefficient
ppm/°C
-100
Ranges B–E, V
6.5V relative to end points of I
= -1.5V, 0.5V, 2.5V, 4.5V,
IN_
-0.025
-0.03
-0.06
+0.025
+0.03
+0.06
DUT_
Force-Current Linearity Error
(Notes 38, 39)
Range A, IDUT_ 30mA, VIN_ = 0V, 1V, 1.3V,
2.5V, 3.7V, 4.9V relative to end points of I
%FSR
DUT_
Range A, V
= -1.5V, 0.5V, 2.5V, 4.5V,
IN_
6.5V relative to end points of I
DUT_
Rejection of Output Error Due to
Common-Mode DUT_ Voltage
Percent of FSR change of the force current per
volt change in DUT_, V = -1.5V to 6.5V
0.007 %FSR/V
+2
DUT_
Range E, R_E = 500kꢀ
Range D, R_D = 50kꢀ
Range C, R_C = 5kꢀ
Range B, R_B = 500ꢀ
-2
-20
-200
-2
μA
+20
+200
+2
Force-Current Range (Note 2)
mA
Range A, R_A = 20 , (Note 41)
-50
+50
MEASURE VOLTAGE (Measured at MEAS_ in FVMV mode, V
= 0, V
= V
= V
IIOS
= 2.5V)
-25
VIOS
DUT_
IN_
Measure-Voltage Offset
+25
+5
mV
Measure-Voltage PSRR
(Note 5)
-5
mV/V
Measure-Voltage Offset
Temperature Coefficient
100
10
μV/°C
%
Measure-Voltage Gain Error
V
DUT_
= -1.5V and 6.5V, nominal gain = +1
-1
+1
Measure-Voltage Gain-
Temperature Coefficient
ppm/°C
V
= -1.5V, 0.5V, 2.5V, 4.5V, 6.5V relative
IN_
Measure-Voltage Linearity Error
-0.02
+0.02
%FSR
to end points. (Note 38)
For V = 6.5V, measure voltage input
DUT_
6.5 +
range = -1.5V to 6.5V, V
range at MEAS_
offsets the
VIOS
V
VIOS
Measure Output Voltage
(Note 42)
V
V
-1.5 +
For V
= -1.5V
DUT_
V
VIOS
Voltage Sense Amp Offset
Voltage Input
V
Relative to DUT ground (Note 42)
0
1.5
IOS
12 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
FORCE OUTPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Range A, V
CLENABLE = 0
= -1.5V, V
= -1.5V, V
= 6.5V,
= 6.5V,
= -1.5V,
= -1.5V,
IN_
DUT_
DUT_
DUT_
DUT_
-100
-8
-55
-3
Range B, V
CLENABLE = 0
IN_
Short-Circuit Current Limit in
FV Mode
mA
Range A, V = 6.5V, V
CLENABLE = 0
IN_
55
3
100
8
Range B, V = 6.5V, V
CLENABLE = 0
IN_
Force-to-Sense Resistor
RFS
(Note 4)
10
k
SENSE INPUT
All modes except V
driver mode
-1.5
-1.5
+6.5
HHP
Input-Voltage Range
V
VHH_ driver-mode compliance, SENSE
open (Note 43)
+13.0
V
= -1.5V and 6.5V, sense input
SENSE_
Input Bias Current
-5
+5
nA
enabled
COMPARATOR INPUTS (V
= V
IIOS
= 2.5V, HYSTEN = 0, unless otherwise noted)
IN_
Maximum at V
= 3.4V, MI mode
= 2V, MI mode
+7.4
-2.2
IIOS
Input-Voltage Range
V
Minimum at V
IIOS
FIMV Offset Voltage
FVMI Offset Current
V
= 2.5V (Note 44)
-5
+5
mV
DUT_
IVMAX_ = IVMIN_ = 2.5V (Note 44)
-0.1
+0.1
%FSR
HYSTEN = 1, functionally tested in
MV mode
Hysteresis
25
50
mV
VOLTAGE CLAMPS (FI mode, CLENABLE_ = 1)
Clamp Voltage Range
(Note 45)
-1.5
+6.5
V
V
FI loop not influenced when V
from voltage clamps
0.5V
V
V
DUT_
CLAMPLO_
+ 0.5
CLAMPHI_
- 0.5
Linear FI DUT_ Range
V
= V
= -1.5V, 0V, 1.5V,
CLAMPHI_
CLAMPLO_
Clamp Voltage Accuracy
-20
+20
mV
2.5V, 4V, 5V, 6.5V
CURRENT CLAMPS (FV mode, CLENABLE_ = 1)
Clamp current = I
=
V
+
-
CLAMPHI_
IIOS
1.3V
V
CLAMPHI_MAX
(V
- V
)/R (sourcing)
RANGE
CLAMPHI_
IIOS
Input Control Voltage Range
V
Clamp current = I
(V
=
V
IIOS
CLAMPLOI_
VCLAMPLO_MIN
- V
)/ R (sinking)
RANGE
1.3V
CLAMPLO_
IIOS
______________________________________________________________________________________ 13
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
Range E, R_E = 500kΩ
MIN
-2.2
-22
TYP
MAX
+2.2
+22
UNITS
MAX79
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
Range A, R_A = 20Ω
ꢀA
-220
-2.2
-55
+220
+2.2
+55
Clamp Current Range (Note 45)
mA
A
FV loop not influenced when I
FSR from current clamps
≥ 10%
I
I
CLAMPHI_
- 10%FSR
DUT_
CLAMPLO_
+ 10%FSR
Linear FV I
Range
DUT_
|I
| = |I
= 0, (0.25 x FSR),
CLAMPHI_
CLAMPLO_
(0.50 x FSR) and (0.55 x FSR), calibrated at 0
and (0.50 x FSR)
Clamp Current Accuracy
-0.5
+0.5
%FSR
COMPARATOR OUTPUTS (Note 46)
Output High Voltage
V
0.2
-
DD
R
R
= 1kΩ to V
= 1kΩ to V
V
V
PULLUP
PULLUP
DD
DD
Output Low Voltage
0.4
High-Impedance State Leakage
Current
1
6
ꢀA
High-Impedance State Output
Capacitance
pF
AC ELECTRICAL CHARACTERISTICS (V
= 0V, V
= 2.5V, C
= C
= 100pF, R
= 4 x R
to 2.5V,
VIOS
IIOS
DUT_
MEAS_
DUT_
RANGE
unless otherwise noted; setting times are to 0.1%FSR)
FORCE VOLTAGE
Range E, R_E = 500kΩ
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
140
30
V
= -1.5V, 6.5V
IN_
20
30
Settling Time
ꢀs
20
Range A, R_A = 20Ω ,
V
= -1V to
IN_
R
DUT_
= 200Ω to 2.5V
20
+6.5V
(Note 41)
Maximum Stable Load
Capacitance
2500
pF
FORCE VOLTAGE/MEASURE CURRENT
Range E, R_E = 500kΩ
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
300
40
20
35
Settling Time
ꢀs
20
Range A, R_A = 20Ω , R
2.5V (Note 41)
= 200Ω to
DUT_
20
14 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
In addition to force-voltage and measure-
current settling times, range A to range B
(Note 47)
Range-Change Switching
20
ꢀs
FORCE CURRENT (Measured at MEAS_ in FIMI Mode)
Range E, R_E = 500kΩ
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
500
100
25
V
= -1.5V,
IN_
+6.5V
35
Settling Time
20
ꢀs
Range A, R_A = 20Ω
V
= -1.1V to
IN_
+4.1V
R
= 200Ω to 2.5V
20
DUT_
(Note 41)
FORCE CURRENT/MEASURE VOLTAGE (Note 48)
Range E, R_E = 500kΩ
1900
200
30
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
40
Settling Time
ꢀs
20
Range A, R_A = 20Ω, R
2.5V (Note 41)
= 200Ω to
DUT_
20
20
In addition to force-current/measure-voltage
settling times, range A to range B. (Note 47)
Range-Change Switching
ꢀs
ꢀs
SENSE INPUT TO MEASURE OUTPUT PATH (Note 49)
Measured at 90% of output, SENSE input
slew rate ≤ 2V/ꢀs
Propagation Delay
0.07
80
MEASURE OUTPUT
High-Impedance Leakage Current
V
= -1.5V, 2.5V, 6.5V
-10
+10
nA
ns
MEAS_
R
= 5kΩ to GND, V
= 2.5V,
= 2.5V,
MEAS_
SENSE
HIZMEASP_ True to High-
Impedance Time
measured from the 50% point of
HIZMEASP_ to 90% of output
R
= 5kΩ to GND, V
SENSE
MEAS_
measured from the 50% point of
HIZMEASP_ False to Active Time
40
ns
HIZMEASP_ to 10% of output
Maximum Stable Load
Capacitance
1000
pF
FORCE OUTPUT
V
= 1V, R
= R
to GND, FVMI
RANGE_
IN_
DUT_
mode, measured from the 50% point of
LLEAKP_ True to Low-Leak Time
0.3
ꢀs
LLEAKP_ to 90% of output
______________________________________________________________________________________ 15
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
= R to GND, FVMI
RANGE_
MIN
TYP
MAX
UNITS
V
= 1V, R
IN
_
DUT_
MAX79
mode, measured from the 50% point of
LLEAKP_ False to Active Time
0.3
ꢀs
LLEAKP_ to 10% of output
COMPARATORS (C
_
= 20PF, R
= 1kΩ to V )
DD
CMP
PULLUP
Rise Time
Fall Time
20% to 80%
80% to 20%
35
1.5
ns
ns
Measured from the 50% point of CS (or
LOAD) to 10% of the output
Disable True to High Impedance
25
20
ns
ns
Measured from the 50% point of CS (or
LOAD) to 90% of the output
Disable False to Active
ACTIVE LOAD
DC CHARACTERISTICS (V
VCOM_ Voltage Range
VCOM_ Offset Voltage
= 2.5V, V
= V
= 6V, unless otherwise noted)
VCOM_
DHV_
DLV_
VCOM_
-1.5
-8
+6.5
5
V
mV
V
I
= 0mA
DUT_
Differential Voltage Range
V
V
V
- V
+8
DUT_
VCOM_
Offset Voltage-Temperature
Coefficient
100
1
ꢀV/°C
V/V
VCOM_ Voltage Gain
_
= 0, 4.5V
0.998
1.002
15
VCOM
VCOM_ Voltage-Gain
Temperature Coefficient
-10
ppm/°C
_
= -1.5V, 0V, 1.5V, 3V, 4.5V, 6.5V
VCOM
VCOM_ Linearity Error
3
mV
dB
relative to end points
VCOM_ Output-Voltage Power-
Supply Rejection Ratio
(Note 5)
40
30
I
= I
= I
=
=
SOURCE
SINK
V
V
V
V
_ = 3V, 6.5V with
DUT
VCOM
20mA
_
= -1.5V or
= -1.5V, 2V with
Sink or Source Output Resistance
Linear Region Output Resistance
Dead-Band
kΩ
Ω
_
DUT
I
SOURCE
SINK
250
_
= 6.5V
VCOM
1mA
I
I
_
=
10mA
12
18
DUT
= I
SINK_
= 10mA, 80%
SOURCE
commutation
_
400
mV
95% I
to 95% I
, I
=
SOURCE_
= 20mA
SINK_ SOURCE
700
900
I
SINK
16 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
= -1V, V = 6V, V
CONDITIONS
MIN
TYP
MAX
UNITS
SOURCE CURRENT (V
= 0V, V = 6V, unless otherwise noted)
DUT_
VCOM_
VLDL_
VLDH_
Source Current Output Range
V
= 0 to 6V (Note 2)
= 300mV (1mA)
0
20
mA
ꢀA
VLDH_
VLDH_
Source Current Offset
V
-20
+20
Source Current Programming
Gain
V
= 0.3V, 5.4V (1mA, 18mA)
3.326
3.333
-10
3.340
mA/V
ꢀA/oC
ꢀA/V
ꢀA
VLDH_
Source Current Temperature
Coefficient
Source Current Power-Supply
Rejection Ratio
(Note 5)
60
80
V
= 0V, 0.1V, 0.3V, 1.5V, 3V, 5.4V, 6V,
VLDH_
Source Current Linearity
relative to 0.3V and 5.4V
= -1V, V = 6V, V = 0V, unless otherwise noted)
VCOM_ VLDL_
SINK CURRENT (V
= 6V, V
DUT_
VLDH_
Sink Current Output Range
V
V
V
= 0 to 6V (Note 2)
0
20
mA
ꢀA
VLDL_
VLDL_
VLDL_
Sink Current Offset
= 300mV (1mA)
-20
+20
Sink Current Programming Gain
= 0.3V, 5.4V (1mA, 18mA)
3.326
3.333
10
3.340
mA/V
Sink Current Temperature
Coefficient
ꢀA/°C
ꢀA/V
ꢀA
Sink Current Power-Supply
Rejection Ratio
PSRR
(Note 5)
60
80
V
= 0V, 0.1V, 0.3V, 1.5V, 3V, 5.4V, 6V,
VLDL_
Sink Current Linearity
relative to 0.3V and 5.4V
AC CHARACTERISTICS (Z = 50Ω to GND, V
= V = 6V, TMSEL_ = LDDIS_ = LDCAL_ = 0)
L
VLDH_
VLDL_
Measured from 50% crossing of RCV/NRVC
Transition Time to/from Inhibit via
RCV/NRCV
t
to 10% level of output waveform; V =
VCOM_
2
ns
EN
-1.5V and 1.5V
Spike During Enable/Disable
Transition
V
= 0V (Note 4)
200
300
mV
VCOM_
TEMPERATURE MONITOR
Nominal Voltage
T = +70°C, R ≥ 10MΩ
3.43
10
V
J
L
Temperature Coefficient
Output Resistance
DIGITAL I/O
mV/°C
kΩ
15
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_)
Input High Voltage
-1.6
-2.0
0.15
+3.5
+3.1
1.0
V
V
V
Input Low Voltage
Differential Input Voltage
______________________________________________________________________________________ 17
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Between RCV and NRCV, DATA, and
Differential Termination
Resistance
MAX79
NDATA, tested at I
(Note 50)
=
4mA
96
104
Ω
RCV_/NRCV_
SINGLE-ENDED CONTROL INPUTS (CS, SCLK, DIN, RST, LOAD, ENVHHP_, LLEAKP_, HIZMEASP_)
2/3 x
Input High
V
V
DD
V
DD
1/3 x
Input Low
-0.1
-25
V
V
DD
Input Bias Current
+25
ꢀA
SINGLE-ENDED OUTPUT (DOUT)
V
0.15
-
DD
Output High
I
I
= 25ꢀA
V
V
OH
OL
DGND
+ 0.15
Output Low
= -25ꢀA
SERIAL PORT TIMING
SCLK Frequency
f
50
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to SCLK High Setup
SCLK High to CS Low Hold
CS High to SCLK High Setup
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
CS High Pulse Width
t
8
CH
t
8
CL
t
3.5
3.5
3.5
3.5
3.5
3.5
40
20
20
20
CSS0
CSH0
t
t
CSS1
t
CSH1
t
DS
t
DH
t
CSWH
LOAD Low Pulse Width
RST Low Pulse Width
t
LDW
t
RST
CS High to LOAD Low Hold Time
SCLK to DOUT Delay
t
CSHLD
t
40
DO
COMMON FUNCTIONS
Operating Voltage Range
(Note 2)
-1.5
-2
+13.0
+2
V
V
V
V
_ = 0V, 1.5V, 3V
DUT
DUT_ High-Impedance Leakage
_ = V
_ = 6.5V, V _ = -1.5V
DUT
-5
+5
ꢀA
CLV
CLV
CHV
CHV
_ = V
_ = -1.5V, V _ = 6.5V
DUT
-5
+5
18 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
_ = 0V, 1.5V, 3V, T < +90°C
MIN
-10
TYP
MAX
+10
UNITS
V
V
DUT
J
_ = V _ = 6.5V, V _ = -1.5V,
CHV DUT
CLV
-10
-10
+10
T < +90°C
DUT_ Low-Leak Mode Leakage
J
nA
V
J
_ = V _ = -1.5V, V _ = 6.5V,
CHV DUT
CLV
+10
4.3
T < +90°C
Driver in terminate mode (Note 4)
3.4
8
DUT_ Combined Capacitance
pF
Driver in high impedance, PMU in high
impedance
Low-Leakage Enable Time
Low-Leakage Disable Time
POWER SUPPLY
LLEAKP_ low to DUT_ = low leak
LLEAKP_ high to normal operation
20
20
ꢀs
ꢀs
Positive Supply Voltage
Negative Supply Voltage
Logic Supply Voltage
V
9.5
-5.2
2.7
17
9.75
-4.75
3.3
10.5
-4.5
5.0
18
V
V
CC
V
EE
V
V
DD
V
Supply Voltage
V
17.5
120
245
4.5
V
HHP
HHP
Positive Supply Current
Negative Supply Current
Logic Supply Current
I
(Note 51)
135
260
7
mA
mA
mA
CC
I
(Note 51)
EE
I
(Note 51)
DD
(Note 51)
1.5
2.0
50
V
Supply Current
I
mA
W
HHP
H
VHH mode, no load
45
Includes CTV power at V
1.4V (Note 51)
= V
=
CTV1
CTV2
Power Dissipation per Channel
1.2
1.35
ANALOG INPUTS
DUT GROUND SENSE
Input Range
V
Relative to AGND (Note 52)
V = 0V
DGS
-150
-10
+150
+10
mV
ꢀA
DGS
Input Bias Current
DHV_, DLV_, DTV_, CPHV_, CPLV_, VHH_
All other levels and MEAS_ output
0.985
0.995
0.990
1.000
1.005
1.005
Gain
V/V
2.5V REFERENCE
Nominal Voltage
Input Bias Current
V
(Notes 53, 54)
2.5
V
REF
-2
+2
ꢀA
ANALOG BUS (V
= -1.5V to +6.5V, PMU-F = PMU-S = -1.5V to +6.5V, unless otherwise noted)
I
=
2.5mA, V
= -1.25V, 2.50V,
SWITCH
DUT_
PMU-F Switch
100
2.5
Ω
6.25V
I
=
100ꢀA, V
= -1.25V, 2.50V,
SWITCH
DUT_
PMU-S Switch
kΩ
6.25V
______________________________________________________________________________________ 19
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
=
10ꢀA, V
= 6.5V to 13V,
DUT_
SWITCH
MAX79
PMU-S Switch
V
= V
= 6.5V to 13V for V
HH
5
kΩ
PMU-F
PMU-S
level calibration
PMU-F Path Current
30
+10
+10
mA
nA
nA
F and S Independent, other channel
switches off
PMU-F, PMU-S On-Leakage
-10
-10
5
1
PMU-F, PMU-S Off-Leakage
DIFFERENTIAL COMPARATOR (DIFFERENTIAL_ = 1)
DC CHARACTERISTICS (V
= V
= 0V, unless otherwise noted)
CLV_
CHV_
V
V
,
DUT0
Input-Voltage Range
(Notes 22, 55)
-1.5
-1
+6.5
+1
V
V
DUT1
Differential Threshold Voltage
Range
Levels may be safely programmed beyond
this range
CLV, CHV
Differential Input Voltage
Offset Error
(Notes 22, 23)
-8
-5
+8
+5
V
V
V
= 0V
mV
V/V
DUT_
DUTn
Gain
= 0V, V
= -1V, 1V
0.998
1
1.002
DUTm
DUTm
Linearity Error Relative to Straight
Line from -1V to +1V
V
= 0V, V
= -1V, -0.5V, 0, 0.5V,
DUTn
-5
+5
mV
mV
1V
HYST0
HYST1
HYST2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
2
1
0
4
Hysteresis
1
6
0
8
1
10
12
15
0
1
Offset Temperature Coefficient
DC Power-Supply Rejection Ratio
V
V
= 0V and V
= -1V, 1V (Note 4)
-150
50
+150
ꢀV/°C
dB
DUTn
DUT_
DUTm
= 1.5V (Note 27)
66
55
V
= -1.5V and 6.5V, V
= V
=
CHV_
DUT_
CLV_
Common-Mode Rejection Ratio
CMRR
50
dB
0V (Note 25)
AC CHARACTERISTICS (V
Minimum Pulse Width
Propagation Delay
= V
= 0V, driver terminated, unless otherwise noted) (Note 4)
CHV_
CLV_
(Note 31)
0.5
1
0.65
1.5
ns
ns
0.5
Propagation-Delay Match H/L vs.
L/H, Individual Comparator
-25
+25
ps
20 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Change in Propagation Delay vs.
Duty Cycle
500mV swing, 250mV overdrive, 2ns to
23ns pulse width, relative to PW = 12.5ns
-45
+45
ps
V
= 200mV, 100mV overdrive,
SWING
Propagation Delay vs. Common-
Mode Voltage
common-mode voltage = -1.4V to +6.4V
(Note 32)
70
50
ps
P-P
Propagation-Delay Temperature
Coefficient
3
ps/°C
ps
Propagation Delay vs. Slew Rate
1V/ns to 6V/ns, relative to 2V/ns
CDRP = 0b000
CDRP = 0b111
0
1V swing, rise/fall time =
500ps
Cable-Droop Compensation
%
10
DRIVER VHH
DC CHARACTERISTICS
Output-Voltage Range
VHH
0
13
V
VHH_ = 13V, I
= 10mA, V
> 12.25V
< 0.75V
+10
DUT_
DUT_
DC Output Current
Current Limit
mA
VHH_ = 0V, I
= -10mA, V
-10
25
DUT_
DUT_
VHH_ = 13V, V
= 0V and VHH_ = 0V,
DUT_
11
mA
V
= 13V
DUT_
Offset Voltage
VHH_ = 8V
VHH_ = 8V, 12V
30
1.002
10
mV
V/V
mV
mV
Ω
Gain
0.998
1
Linearity Relative to 8V, 12V
Linearity Relative to 2V, 12V
Output Resistance
VHH_ = 7V, 8V, 10V, 12V, 13V
VHH_ = 0, 2V, 4V, 8V 12V, 13V
30
I
=
2mA, VHH_ = 1V
VHH_ = 7V to 13V (Note 4)
= 100pF)
DUT_
75
DUT_
Output-Voltage Temperature
Coefficient
75
500
ꢀV/°C
AC CHARACTERISTICS (R ≥ 10MΩ, C
L
VHH Rise/Fall Times
V
V
= 3V, VHH_ = 13V, 10% to 90%
= 3V to VHH_ = 13V rise
170
150
200
ns
DHV_
DHV_
VHH Overshoot (Note 4)
mV
VHH_ = 13V to V
= 3V fall
DHV_
LEVEL DACs
Settling Time
Full-scale transition to within 5mV
(VLDH_), I (VLDL_)
20
ꢀs
ꢀA
mV
mV
I
3.5
2
SOURCE
SINK
Differential Nonlinearity
VHH_, IIOS
All other levels
1
______________________________________________________________________________________ 21
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
Note 1: Unless otherwise specified, all minimum and maximum specifications are production tested. All other specification test
limits are guaranteed by design. All tests are performed at nominal supply voltages and after gain and offset calibration,
unless otherwise specified.
MAX79
Note 2: Guaranteed by the associated linearity test.
Note 3: Change in offset at any voltage over the operating range. Specification includes both gain and offset temperature effects.
Limits have been simulated over the entire operating range and verified at worst-case conditions (V
- V
>
DHV_
DLV_
200mV).
Note 4: Guaranteed by design and characterization.
Note 5:
Note 6: DATA_ = 1V, V
V
and V independently varied over their full range.
CC E
E
= 3V, V
= 0V, V
= 1.5V, I
= 30mA. Different values within the range of 48Ω to 52Ω are
OUT
DHV_
DLV_
DTV_
available by custom trimming (contact factory).
Note 7: Resistance measurements are made using 2.5mA current changes in the loading instrument about the noted value.
Absolute value of the difference in measured resistance at the specified points, tested separately for each current polarity.
Note 8: Rise time, unless otherwise specified for the differential inputs DATA_ and RCV_, is 250ps (10% to 90%) at 40MHz. (These
conditions are for bench characterization. Final test conditions may differ from bench.)
Note 9:
8V step into AC-coupled 10Ω load. Current supplied for a minimum of 10ns. Guaranteed by design to be greater than or
equal to DC drive current.
Note 10: V
= 1.5V, R = 50Ω. External signal driven into a transmission line to produce a 0 to 3V edge at the comparator input
DTV_
S
with a 600ps rise time (10% to 90%). Measurement point is at the comparator input.
Note 11: Measured between the 90% point of the driver output (relative to its final value) and the waveform settling to within the
specified limit.
Note 12: Propagation delays are measured from the crossing point of the differential input signals to the 50% point of expected out-
put swing.
Note 13: Average of two measurements for propagation-delay match, t vs. t
.
HL
LH
Note 14: Four measurements are made: DHV_ to high impedance, DLV_ to high impedance, high impedance to DHV_, and high
impedance to DLV_. The worst of the four measurements is reported.
Note 15: Average of four measurements of propagation-delay match, drive to high impedance vs. high impedance to drive.
Measured from the crossing point of RCV/NRCV to the 50% point of the output waveform.
Note 16: Average of four measurements for propagation-delay match, drive to term vs. term to drive. Measured from the crossing
point of RCV/NRCV to the 50% point of the output waveform.
Note 17: Four measurements are made: DHV_ to DTV_, DLV_ to DTV_, DTV_ to DHV_, and DTV_ to DLV_. The worst-case differ-
ence is reported.
Note 18: Propagation-delay change is reported with respect to a 5ns pulse width.
Note 19: At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The pulse width is measured at DATA_
and NDATA_.
Note 20: Maximum data rate in transitions/second. A waveform that reaches at least 95% of its programmed amplitude may be gen-
erated at half of this frequency.
Note 21: Maximum data rate in transitions/second. A waveform that reaches at least 90% of its programmed amplitude may be gen-
erated at half of this frequency.
Note 22: The comparators tolerate the V
produced by the driver; however, the specifications only apply to the -1.5V to +6.5V
HH
input range.
Note 23: This specification is implicitly tested, by meeting the high-impedance leakage specification.
Note 24: Change in offset at any voltage over operating range. Includes both gain (CMRR) and offset temperature effects.
Note 25: Change in offset voltage over the input range.
Note 26: Relative to straight line between 0 and 3V.
Note 27: Change in offset voltage with power supplies independently varied over their full range. Both high and low comparators
are tested.
Note 28: All propagation delays measured from V
crossing calibrated CHV_/CLV_ threshold to crossing point of differential
DUT_
outputs.
22 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0V, V
= 7.2V,
= 2.5V,
CC
CPLV_
EE
DD
= 1.4V, V
HHP
DHV_
DLV_
DTV_
CPHV_
= 1V, V
IVMIN_ COM_
= -2.2V, V
= 4V, V
= V
= 0V, V
= V
= 2V, V
= V
DGS
GND
CTV_
BV_
CHV_
IVMAX_
CLV_
V
= 0V, V
= 0V, V
= 2.5V, V
= 0V, V
= 2.5V, V
= 5V, V
= 0V, V
= 10V, CDRP = 0b001, RO
LDHV_
LDLV_
IN_
VIOS
J
IIOS
CLAMPHI_
CLAMPLO_
HH_
= 0b1000, HYST = 0b000, Z
measured at T = +40°C to +100°C, unless otherwise noted.) (Note 1)
= 50Ω, T = +70°C to an accuracy of 15°C, unless otherwise noted. All temperature coefficients are
LOAD
J
Note 29: All delay specifications are measured with DUT_ (comparator input) as the reference.
Note 30: 40MHz, 0 to 1V input to comparator, reference = 0.5V, 50% duty cycle, 250ps rise/fall time, Z = 50Ω, driver in term mode
S
with V
= 0V, and hysteresis disabled, unless otherwise specified.
DTV_
Note 31: At this pulse width, the output reaches at least 90% of its nominal peak-to-peak swing. The pulse width is measured at the
crossing points of the differential outputs. 250ps rise/fall time at DUT_. Timing dispersion specifications are not guaran-
teed.
Note 32: V
= 200mV
, rise/fall time = 150ps, overdrive = 100mV, V
= V . Valid for common-mode ranges where the
DUT_
DTV_ CM
P-P
signal does not exceed the operating range. Specification is worst case (slowest–fastest) over the specified range.
Note 33: For any input slew rate up to 6V/ns, no unusual behavior should be exhibited (i.e., glitching, changing polarity, etc.).
2
Note 34: Input to comparator is 40MHz at 0 to 1V, 50% duty cycle, 250ps 10% to 90% rise time. EQ bandwidth = 0.22/(t
^ +
TCMP
2
t ^ )^(1/2) where t
TINPUT
and t
are the 20% to 80% transition time of the comparator input and reconstructed
TINPUT
TCMP
output.
Note 35: Resistance measurements are made using 2.5mA current changes in the loading instrument. Value reported is the absolute
value of the difference in measured resistance over the specified range, tested separately for each current polarity.
Note 36: Stimulus is 0 to 3V, 2.5V/ns square wave from far end of 3ns transmission line with R = 25Ω, clamps set to 0 and 3V.
S
Note 37: Change in offset over the entire operating range. Includes both gain and offset temperature effects.
Note 38: Interpretation of errors are expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point-to-
end-point range (i.e., for the 2mA range, the full-scale range = 4mA and a 1% error = 40ꢀA).
Note 39: With clamps enabled, the linear DUT_ current range for force voltage is defined by the clamp-current-range specification,
and the linear DUT_ voltage range for force current is defined by the linear FI V
range specification.
DUT_
Note 40: For currents greater than +FSR/2, V
is greater than V
+ 4V and for currents less than -FSR/2, V
is less than
MEAS
IIOS
MEAS
V
IIOS
- 4V.
Note 41: This current is supplied by the driver.
Note 42: V
may be programmed to greater than 1.5V to a maximum value of 2.5V; however, the maximum valid V
value
VIOS
DUT_
must be reduced below 6.5V, as the maximum MEAS output is limited to 8V. Because V
= V
+ V
, then
VIOS
MEAS_
DUT_
V
= 8V - V
when V
> 1.5V.
DUT_MAX
VIOS
VIOS
Note 43: Guaranteed by driver VHH_ and DLV_ linearity tests.
Note 44: IVMAX and IVMIN do not have separate calibration registers for MI and MV modes. Specifications apply with calibration
for each mode.
Note 45: Guaranteed by the associated accuracy test.
Note 46: The digital interface is compatible with 2.7V ≤ V
≤ 5V CMOS logic.
DD
Note 47: See the Typical Operating Characteristics section.
Note 48: FIMV settling times are a function of C and R
. Increased DUT_ capacitance will increase settling time.
RANGE
DUT_
Note 49: The propagation delay time is guaranteed only over the force-voltage output range. Propagation delay is measured by
holding V steady and transitioning IVMAX_ or IVMIN_.
SENSE_
Note 50: Default configuration has internal 100Ω resistors between DATA and NDATA, RCV and NRCV. Resistor terminations from
DATA, NDATA, RCV, and NRCV to a separate pin are available by special request.
Note 51: At nominal supply voltages. Total current for dual device. R ≥ 10MΩ.
L
Note 52: Increasing DGS beyond 0V requires a proportional increase in the minimum supply levels. Specified ranges for all DAC
output levels are defined with respect to DGS.
Note 53: The error of the external 2.5V reference impacts the accuracy of the DAC levels; a 1% error in the 2.5V reference will trans-
late to a 1% error in the DAC level gain. Use a precision voltage reference, such as the MAX6225.
Note 54: Generate the 2.5V external reference with respect to DGS (DUT ground sense).
Note 55: Guaranteed by associated CMRR_ test.
Note 56: The comparator outputs are normally source side-terminated with 50Ω on-die to CTV_ and at the receive side of the trans-
mission path. The comparator outputs are tested with the 50Ω on-die source resistors only with limits relative to CTV_ twice
the values indicated.
______________________________________________________________________________________ 23
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Typical Operating Characteristics
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T
L
J
measured at T = +40°C to +100°C.)
J
DRIVER TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH
DRIVER SMALL-SIGNAL RESPONSE
DRIVER LARGE-SIGNAL RESPONSE
30
20
V
= 0V
V
= 0V
DLV_
DLV_
9
R = 50Ω TO GND
L
R = 50Ω TO GND
L
POSITIVE PULSE
V
= 0.5V
V
= 5V
DHV_
DHV_
10
0
V
= 0.2V
V
= 3V
DHV_
DHV_
-10
-20
-30
-40
NEGATIVE PULSE
V
= 0.1V
V
= 1V
DHV_
DHV_
0
NORMALIZED TO PW = 5ns,
0
PERIOD = 25ns, V
= 3V, V
= 0V
DHV_
DLV_
20
2ns/div
0
5
10
15
25
2ns/div
PULSE WIDTH (ns)
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
DRIVER TO HIGH-IMPEDANCE TRANSITION
DRIVER-TO-TERM TRANSITION
25
20
15
10
5
R = 50Ω TO GND,
DHV_
DLV_
R = 50Ω TO GND,
L
V
V
L
NORMALIZED AT V = 1.5V
CM
= 1V,
= -1V
V
V
V
= 3V,
= 1.5V,
= 0V
DHV_
DTV_
DLV_
DHV
DLV
DHV
DLV
RISING EDGE
0
0
-5
-10
0
FALLING EDGE
0
1
2
3
4
5
6
2ns/div
2ns/div
COMMON-MODE VOLTAGE (V)
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
DUT_ = DLV_
DUT_ = DHV_
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
DUT_
V
DUT_
24 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Typical Operating Characteristics (continued)
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T
L
J
measured at T = +40°C to +100°C.)
J
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
CROSSTALK TO DUT_
FROM DLV_ WITH DUT_ = DHV_
CROSSTALK TO DUT_
FROM DHV_ WITH DUT_ = DLV_
3.0
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
DUT_ = DTV_
NORMALIZED AT V
= 5V,
DHV_
NORMALIZED AT V
= 0V,
= 1.5V
DLV_
2.5
V
= 0V, V
= 1.5V
DLV_
DTV_
V
= 5V, V
DHV_
DTV_
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-0.5
-0.5
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
0
1
2
3
4
5
6
7
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
(V)
V
(V)
V
(V)
DHV_
V
DUT_
DLV_
CROSSTALK TO DUT_
FROM DTV_ WITH DUT_ = DHV_
CROSSTALK TO DUT_
FROM DTV_ WITH DUT_ = DLV_
CROSSTALK TO DUT_
FROM DLV_ WITH DUT_ = DTV_
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
NORMALIZED AT V
= 1.5V,
NORMALIZED AT V
= 1.5V,
NORMALIZED AT V
= 0V,
= 3V
DTV_
= 3V
DTV_
= 3V
DLV_
V
= 0V, V
V
= 0V, V
V
= 1.5V, V
DLV_
DHV_
DLV_
DHV_
DTV_
DHV_
-0.5
-1.0
-1.5
-0.5
-0.5
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
V
V
V
(V)
DLV_
DTV_
DTV_
CROSSTALK TO DUT_
FROM DHV_ WITH DUT_ = DTV_
DRIVER GAIN ERROR
vs. TEMPERATURE
2.0
1.5
1.0
0.5
0
0.4
0.3
0.2
0.1
0
NORMALIZED AT V
= 3V,
DHV_
V
= 0V, V
= 1.5V
DLV_
DTV_
DHV
DLV
DTV
-0.1
-0.2
NORMALIZED AT T = +85°C
J
-0.5
40
50
60
70
80
90
100
1.5
2.5
3.5
4.5
(V)
5.5
6.5
V
TEMPERATURE (°C)
DHV_
______________________________________________________________________________________ 25
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Typical Operating Characteristics (continued)
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T
L
J
measured at T = +40°C to +100°C.)
J
DRIVER OFFSET
vs. TEMPERATURE
COMPARATOR OFFSET
vs. COMMON-MODE VOLTAGE
COMPARATOR RISING-EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
1.5
0.2
0
8
6
4
2
NORMALIZED AT V = 1.5V
CM
DLV
1.0
MAX79
CHV
-0.2
-0.4
-0.6
0.5
CHV
DHV
0
-0.5
-1.0
-1.5
CLV
0
-2
-4
-6
-0.8
-1.0
-1.2
-1.4
CLV
DTV
NORMALIZED AT T = +85°C
J
NORMALIZED AT V = 1.5V
CM
V
= 3.0V, V
= 1.5V, V
= 0V
DHV_
DTV_
DLV_
40
50
60
70
80
90
100
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
COMPARATOR FALLING-EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
COMPARATOR TRAILING-EDGE TIMING
VARIATION vs. PULSE WIDTH
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE
40
35
30
25
20
15
10
5
30
25
20
15
10
5
40
30
20
10
NORMALIZED AT V = 1.5V
CM
NORMALIZED AT PW = 5ns,
PERIOD = 25ns
V
RISING
DUT_
LOW
PULSE
V
FALLING
DUT_
HIGH
PULSE
0
-10
-20
-30
-40
CHV
0
-5
0
CLV
-10
-15
-5
NORMALIZED AT 2V/ns
-10
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
0
5
10
15
20
25
1
2
3
4
5
6
PULSE WIDTH (ns)
SLEW RATE (V/ns)
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE
COMPARATOR RESPONSE
TO HIGH SLEW-RATE INPUT
HIGH-IMPEDANCE MODE, INPUT = 6V/ns
INPUT
OUTPUT
0
R = 50Ω
L
1ns/div
3ns/div
26 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Typical Operating Characteristics (continued)
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T
L
J
measured at T = +40°C to +100°C.)
J
COMPARATOR OFFSET
vs. TEMPERATURE
ACTIVE LOAD
CURRENT vs. VOLTAGE
CLAMP RESPONSE AT SOURCE
2.0
25
20
15
10
5
R
V
= 25Ω, V
SOURCE
= 3.1V, V
= 0 to 3V SQUARE WAVE
= -0.1V,
CPLV_
V
= V
= 6V
VLDL_
S
CPHV_
VLDH_
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
0
-5
-10
-15
-20
0
NORMALIZED AT T = +70°C
J
-2.0
-25
40
50
60
70
80
90
100
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
3ns/div
TEMPERATURE (°C)
V
DUT_
ACTIVE LOAD LINEARITY ERROR
HIGH-IMPEDANCE LEAKAGE CURRENT
vs. DUT_ VOLTAGE
ACTIVE-LOAD LINEARITY ERROR
vs. V
I
vs. V
I
DUT_
LDL_
DUT_
LDH_
50
40
1.0
0.8
0.6
0.4
0.2
0
50
40
CALIBRATION POINTS AT
CALIBRATION POINTS AT
V
V
= 300mV AND 5.4V,
V
V
= 300mV AND 5.4V, V
= 6V,
LDL_
LDH_
LDL_
COM_
= -1V, V
= 0V, V
= 6V
DUT_
= 0V, V
= -1.0V
COM_
LDH_
DUT_
30
30
20
20
10
10
0
0
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
-0.2
-0.4
-0.6
-0.8
-1.0
0.1
1
10
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
0.1
1.0
10.0
V
(V)
V
(V)
DUT_
V
(V)
LDL_
LDH_
LOW-LEAKAGE CURRENT
vs. DUT_ VOLTAGE
HIGH-IMPEDANCE CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
V
= 5V, V
= 6.5V
CPLV_
CPHV_
-10
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
DUT_
DUT_
______________________________________________________________________________________ 27
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Typical Operating Characteristics (continued)
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T
L
J
measured at T = +40°C to +100°C.)
J
HIGH-IMPEDANCE CLAMP CURRENT
HIGH IMPEDANCE TO LOW-LEAK
TRANSITION
DRIVE TO LOW-LEAK
TRANSITION
vs. DIFFERENCE VOLTAGE
10
R
= 50Ω TO GND
R
= 50Ω TO GND
LOAD
LOAD
0
-10
-20
-30
-40
MAX79
LOW-LEAK TO HIGH IMPEDANCE
LOW-LEAK TO DRIVE
DRIVE TO LOW-LEAK
-50
-60
-70
0
0
V
= -1.5V, V
= 0V
-80
-90
CPLV_
CPHV_
HIGH IMPEDANCE TO LOW-LEAK
10ns/div
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
10ns/div
V
DUT_
SUPPLY CURRENT
(I vs. V
SUPPLY CURRENT
SUPPLY CURRENT
(I vs. TEMPERATURE)
CC
)
(I vs. V
)
CC
DRIVER TERM MODE, V
CC
EE
EE
140
0
140
120
100
80
= 1.5V, NO LOAD
DTV_
T = +70°C
J
120
100
80
-50
-100
-150
-200
-250
-300
LOW-LEAK MODE
60
40
20
0
60
40
20
0
LOW-LEAK MODE
DRIVER TERM MODE, V
= 1.5V, NO LOAD
DTV_
DRIVER TERM MODE, V
= 1.5V, NO LOAD
T = +70°C
J
DTV_
9.5
9.7
9.9
V
10.1
(V)
10.3
10.5
-5.2 -5.1 -5.0 -4.9 -4.8 -4.7 -4.6 -4.5
(V)
40
50
60
70
80
90
100
V
EE
TEMPERATURE (°C)
CC
SUPPLY CURRENT
(I vs. TEMPERATURE)
TRANSIENT RESPONSE
FVMI RANGE A
EE
DRIVER TERM MODE, V
0
= 1.5V, NO LOAD
DTV_
V
RISING
DUT_
-50
-100
-150
-200
-250
-300
V
RISING
MEAS_
V
FALLING
FALLING
MEAS_
0
V
DUT_
V
= -1V TO +6.5V AND +6.5V TO -1V
R = 200Ω TO 2.5V
IN_
L
40
50
60
70
80
90
100
5μs/div
TEMPERATURE (°C)
28 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Typical Operating Characteristics (continued)
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T
L
J
measured at T = +40°C to +100°C.)
J
TRANSIENT RESPONSE
FVMI RANGE B
TRANSIENT RESPONSE
FVMI RANGE C
TRANSIENT RESPONSE
FVMI RANGE D
V
= -1.5V TO +6.5V AND +6.5V TO -1.5V
V
RISING
V
RISING
MEAS_
IN_
L
MEAS_
R = 2000Ω TO 2.5V
V
RISING AND V
RISING
DUT_
MEAS_
V
RISING
V
RISING
DUT_
DUT_
V
= -1.5V TO +6.5V AND
IN_
+6.5V TO -1.5V
R = 200kΩ TO 2.5V
L
V
= -1.5V TO +6.5V AND +6.5V TO -1.5V
IN_
L
R = 20kΩ TO 2.5V
V
FALLING
0
DUT_
0
0
V
FALLING
DUT_
V
FALLING
MEAS_
V
FALLING AND V
FALLING
V
FALLING
DUT_
MEAS_
MEAS_
5μs/div
5μs/div
5μs/div
TRANSIENT RESPONSE
FVMI RANGE E
TRANSIENT RESPONSE
FIMI RANGE A
TRANSIENT RESPONSE
FIMI RANGE B
V
RISING
MEAS_
V
RISING AND V
RISING
V
RISING
MEAS_
DUT_
DUT_
V
RISING
DUT_
V
RISING
MEAS_
V
= -1.5V TO +6.5V AND +6.5V TO -1.5V
V
= -1.5V TO +6.5V AND
IN_
L
IN_
R = 2MΩ TO 2.5V
V
= 1.1V TO 4.1V AND 4.1V TO 1.1V
IN_
+6.5V TO -1.5V
R = 2kΩ TO 2.5V, C
R = 200Ω TO 2.5V, C
= 100pF
= 100pF
L
LOAD
L
LOAD
0
V
FALLING
DUT_
V
FALLING
MEAS_
0
0
V
FALLING
MEAS_
V
FALLING
DUT_
V
FALLING AND V
FALLING
MEAS_
DUT_
50μs/div
5μs/div
5μs/div
TRANSIENT RESPONSE
FIMI RANGE C
TRANSIENT RESPONSE
FIMI RANGE D
V
RISING
V
RISING
MEAS_
MEAS_
V
RISING
V
RISING
DUT_
DUT_
V
= -1.5V TO +6.5V AND
V
= -1.5V TO +6.5V AND
IN_
IN_
+6.5V TO -1.5V
+6.5V TO -1.5V
R = 20kΩ TO 2.5V, C
= 100pF
R = 200kΩ TO 2.5V,
LOAD
L
LOAD
L
C
= 100pF
0
0
V
FALLING
DUT_
V
FALLING
DUT_
V
FALLING
V
FALLING
MEAS_
MEAS_
5μs/div
12.5μs/div
______________________________________________________________________________________ 29
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Typical Operating Characteristics (continued)
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T
L
J
measured at T = +40°C to +100°C.)
J
TRANSIENT RESPONSE
FIMI RANGE E
TRANSIENT RESPONSE
FIMV RANGE C
TRANSIENT RESPONSE
VHH
V
= -1.5V TO +6.5V AND +6.5V TO -1.5V
IN_
L
V
RISING AND V
RISING
MAX79
R = 2MΩ TO 2.5V, C
= 100pF
DUT_
MEAS_
LOAD
V
RISING
MEAS_
V
= -1.5V TO +6.5V AND
V
RISING
IN_
DUT_
+6.5V TO -1.5V
R = 20kΩ TO 2.5V, C
= 100pF
L
LOAD
V
FALLING
DUT_
0
0
0
V
FALLING
V
FALLING AND V
FALLING
MEAS_
DUT_
MEAS_
5μs/div
0.1μs/div
50μs/div
DRIVER
DRIVER
1.2Gbps TOGGLE RATE, 1V
DRIVER
900Mbps TOGGLE RATE, 3V
CABLE-DROOP COMPENSATION
R
= 50Ω TO GND
LOAD
R
= 50Ω TO GND,
LOAD
3V SWING,
CDRP = 0b001,
0b100, 0b111
0
0
R
= 50Ω TO GND
LOAD
0
2.5ns/div
0.5ns/div
0.5ns/div
PMU
RANGE CHANGE A TO B
PMU
RANGE CHANGE B TO A
C
= 100pF, R
= -2mA, -1mA, 0, 1mA, AND 2mA
= 2kΩ TO 2.5V
C
= 100pF, R
= -2mA, -1mA, 0, 1mA, AND 2mA
= 2kΩ TO 2.5V
LOAD
LOAD
LOAD
LOAD
I
I
LOAD
LOAD
0
0
5μs/div
5μs/div
30 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Typical Operating Characteristics (continued)
(V
= 9.75V, V = -4.75V, V
= 3.3V, V
= 17.5V, V
= 3V, V
= 0V, V
= 1.5V, SC1 = SC0 = 0, V
= 7.2V,
CC
EE
DD
HHP
DHV_
DLV_
DTV_
CPHV_
V
= -2.2V, R = 50Ω || 1pF, C = 100pF, CTV_ = 1.4V, T = +70°C, unless otherwise specified. All temperature coefficients are
CPLV_
T L J
measured at T = +40°C to +100°C.)
J
PMU
FV LINEARITY
PMU
MV LINEARITY
PMU
MI LINEARITY
4
0.020
0.016
0.012
0.008
0.004
0
0.020
0.016
0.012
0.008
0.004
0
FVMI MODE, RANGE C,
= 2.5V, V = 2.5V
SENSE_ INPUT, RANGE B,
V
3
2
I
= -2mA, 0, AND 2mA
VIOS_
DUT_
LOAD
1
0
-0.004
-0.008
-0.012
-0.016
-0.020
-0.004
-0.008
-0.012
-0.016
-0.020
-1
-2
-3
-4
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
_ (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
V
MEAS_
IN_
DUT
PMU MI
COMMON-MODE RESPONSE
PMU
VOLTAGE CLAMP ACCURACY
PMU
CURRENT CLAMP ACCURACY
4
3
20
15
10
5
0.4
0.3
0.2
0.1
0
FVMI MODE, RANGE B,
FIMV MODE
FVMI MODE, RANGE B, V = 2.5V
IIOS
V
= 2.5V, V
= V
,
IIOS
DUT_
IN_
NORMALIZED AT V = 2.5V,
IN_
CLAMPHI_
2
I
= -2mA, 0, AND 2mA
LOAD
1
CLAMPHI_
0
0
CLAMPLO_
CLAMPLO_
-1
-2
-3
-4
-5
-0.1
-0.2
-0.3
-0.4
-10
-15
-20
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
V
V
(V)
CLAMP_
IN_
CLAMP_
______________________________________________________________________________________ 31
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Pin Description
PIN
1
NAME
MEAS0
DUTHI0
DUTLO0
REF
DESCRIPTION
Channel 0 Measure Output
Channel 0 PMU High Comparator Output
Channel 0 PMU Low Comparator Output
DAC Reference Input
2
3
4
5
DGS
DUT Ground Sense Input
Analog Ground
MAX79
6, 35, 51
GND
7
DOUT
DGND
CS
Data Output. Serial-interface data output.
Digital Ground
8
9
Chip-Select Input
10
11
12
13
14
15
16
17
SCLK
DIN
Serial-Clock Input
Data Input. Serial-interface data input.
Digital Power Supply
V
DD
LOAD
RST
Load Input. Serial-interface asynchronous load control.
Reset Input. Serial-interface reset.
DUTLO1
DUTHI1
MEAS1
Channel 1 PMU Low Comparator Output
Channel 1 PMU High Comparator Output
Channel 1 Measure Output
18, 37, 40,
46, 49, 68
V
Positive Power Supply
Negative Power Supply
CC
19, 36, 39,
47, 50, 67
V
EE
20
21
HIZMEASP1 Channel 1 High-Impedance Enable Input for PMU Measure Output
LLEAKP1
NRCV1
RCV1
Channel 1 Low-Leak Enable Input
22
Channel 1 Negative Receive Multiplexer Control Input
Channel 1 Positive Receive Multiplexer Control Input
Channel 1 Bias Voltage Input
23
24
BV1
25
NDATA1
DATA1
ENVHHP1
NCL1
Channel 1 Negative Data Multiplexer Control Input
Channel 1 Positive Data Multiplexer Control Input
Channel 1 High-Voltage Mode Enable Input
Channel 1 Negative Low Comparator Output
Channel 1 Positive Low Comparator Output
Channel 1 Comparator Termination Voltage
Channel 1 Negative High Comparator Output
Channel 1 Positive High Comparator Output
Channel 1 PMU Sense Input
26
27
28
29
CL1
30
CTV1
31
NCH1
CH1
32
33
SENSE1
N.C.
34, 42, 52
38
No Connection. Not internally connected.
Channel 1 DUT Connection
DUT1
32 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Pin Description (continued)
PIN
41
43
44
45
48
53
54
55
56
57
58
59
60
61
62
63
64
65
66
NAME
TEMP
DESCRIPTION
Temperature Output
V
High-Voltage Power Supply
HHP
PMU-F
PMU-S
DUT0
PMU External Force Connection
PMU External Sense Connection
Channel 0 DUT Connection
SENSE0
CH0
Channel 0 PMU Sense Input
Channel 0 Positive High Comparator Output
NCH0
Channel 0 Negative High Comparator Output
Channel 0 Comparator Termination Voltage
Channel 0 Positive Low Comparator Output
Channel 0 Negative Low Comparator Output
Channel 0 High-Voltage Mode Enable Input
Channel 0 Positive Data Multiplexer Control Input
Channel 0 Negative Data Multiplexer Control Input
Channel 0 Bias Voltage Input
CTV0
CL0
NCL0
ENVHHP0
DATA0
NDATA0
BV0
RCV0
Channel 0 Positive Receive Multiplexer Control Input
Channel 0 Negative Receive Multiplexer Control Input
Channel 0 Low-Leak Enable Input
NRCV0
LLEAKP0
HIZMEASP0 Channel 0 High-Impedance Enable Input For PMU Measure Output
Exposed Pad. Internally connected to ground. Connect to a large open copper PCB plane or heatsink
to maximize thermal performance. Not intended as an electrical connection point.
—
EP
comparators provide extremely low timing variation over
changes in slew rate, pulse width, or overdrive voltage,
Detailed Description
The MAX9979 dual-channel pin electronics DCL/PMU
integrates multiple pin-electronics functions into a sin-
gle IC. Each channel includes a four-level pin driver, a
window comparator, a differential comparator, dynamic
clamps, a versatile PMU, an active load, and 14 inde-
pendent 16-bit level-setting DACs. Additionally, each
channel of the MAX9979 features programmable cable-
droop compensation for the driver output and for the
comparator input, adjustable driver output resistance,
and driver slew-rate adjustment.
and have 50Ω source outputs internally terminated to an
applied voltage at CTV_. When high-impedance mode is
selected, the programmable dynamic clamps provide
damping of high-speed DUT waveforms. The 20mA
active load facilitates fast contact testing when used in
conjunction with the comparators, and functions as a
pullup for open-drain/collector DUT outputs. The PMU
offers five current ranges from 2ꢀA to 50mA and can
force and measure current or voltage. Placing the
MAX9979 DUT_ output into its very low-leakage state
disables the DCL functions and the PMU force function.
This feature is convenient for making IDDQ measure-
ments without the need for an output disconnect relay.
Low-leakage control is independent for each channel.
An SPI-compatible serial interface and external inputs
configure the MAX9979.
The MAX9979 driver features a wide -1.5V to +6.5V high-
speed operating range, high-impedance and active-ter-
mination (3rd-level drive) modes, and is highly linear
even at low voltage swings. The MAX9979 also features
a built-in super voltage (VHH) level up to 13V. The driver
provides high-speed differential control inputs compati-
ble with most high-speed logic families. The window
______________________________________________________________________________________ 33
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
HYSTERESIS
CONTROL
INPUT
SELECT
MAX9979
CHV*
CH_
NCH_
DUT FROM
OTHER CHANNEL
CTV_
COMPARATORS
CL_
MAX79
NCL_
CLV*
CS
SCLK
DIN
LOAD CONTROL
DROOP
COMPENSATION
SERIAL
INTERFACE
LOAD
RST
VLDH
VLDL
ACTIVE
LOAD
VCOM
SLEW
CONTROL
DROOP
LLEAKP_
COMPENSATION
R
CONTROL
OUT
DHV
DTV
20Ω
DUT_
DLV
25Ω 2.5
MUX/DRIVER
VHH*
CPHV
DATA_
NDATA_
RCV_
TO OTHER
CHANNEL
CLAMPS
CPLV
RANGE CONTROL
PMU-F
PMU-S
NRCV_
REF
VIN
BV_
V
V
CC
DD
V
EE
CLAMPHI*
CLAMPLO
V
HHP
10kΩ
GND
4x
1x
PMU
DGND
ENVHHP_
TEMP_
IIOS
MEAS_
DGS
IVMAX*
IVMIN*
VIOS
DUTHI_
DUTLO_
SENSE_
HIZMEASP_
HIGH-IMPEDANCE CONTROL
*SHARED LEVELS.
KEY:
DAC
SERIAL BITS
Figure 1. Simplified Block Diagram. Only one of two channels is shown. The PMU is shown in high range. The single serial interface
controls both channels.
34 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
The integration of DCL and PMU functions in the
MAX9979 requires defined states to manage the inter-
action of these resources. The PMU controls supersede
those of the DCL, as described below and shown in
Table 1. Important details to keep in mind are:
tion modes. While in a calibration mode, the DCL
states are still selected by the controls normally
associated with those functions. When in a calibra-
tion mode, the PMU range A is not available. The
PMU range defaults to range B if the serial-interface
bit RS2_ = 1.
• Normal high-speed DCL operation is intended only
when the PMU is in the FNMN state and the DCL is
available, as indicated by Note B in Table 1.
Driver
The driver uses a high-speed multiplexer to select one
of three DAC voltages (DHV_, DLV_, and DTV_), or to
select high-impedance mode. Multiplexer switching is
controlled by high-speed differential inputs
DATA_/NDATA_ and RCV_/NRCV_ and mode-control
bit TMSEL_ (see Table 2). The multiplexer output is
buffered to drive DUT_. A programmable slew-rate cir-
cuit controls the slew rate of the buffer input.
• Forcing LLEAKP_ = 0 immediately places the DCL
into low-leak mode, and the PMU into its high-
impedance state independent of any other pro-
grammed control bit or external control inputs.
Forcing LLEAKP_ = 1 is required to allow any other
mode of operation.
• Forcing HIZFORCE_ = 1 enables the PMU and
simultaneously forces the DCL into low-leak mode.
In high-impedance mode, the clamps and comparators
remain connected to DUT_, the DUT_ bias current is
less than 2ꢀA, and the node continues to track high-
speed signals. In low-leakage mode, the bias current at
DUT_ is further reduced to less than 10nA, yet signal
tracking slows.
• Additional PMU settings such as the force and mea-
sure modes, current range, the measure output,
comparators, and the clamp features are controlled
as described later in this document.
• The MAX9979 provides calibration modes under
which both the DCL and the PMU are simultaneously
active. Forcing HIZFORCE_ = 0 ordinarily disables
the PMU, however, when LLEAKS_ is not asserted,
the FMODE_ and MMODE_ bits select these calibra-
The nominal driver output resistance is 50Ω and fea-
tures an adjustment range of 2.5Ω through the serial
interface in 360mΩ increments. Contact the factory for
different output resistance values.
Table 1. MAX9979 Mode Selection
MODES
DRIVER
Low leak
Low leak
Low leak
Low leak
Low leak
Available
Available
Available
Low leak
Low leak
COMPARATOR
Low leak
Low leak
Low leak
Low leak
Available
Available
Available
Available
Low leak
Low leak
LOAD
PMU
FVMI
FVMV
FIMI
FMODE_
MMODE_
LLEAKP_
HIZFORCE_
NOTE
—
—
—
—
A
Low leak
Low leak
Low leak
Low leak
Available
Available
Available
Available
Low leak
Low leak
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
X
X
PMU
FIMV
FVMI
FIMV
FNMN
FNMV
FNMN
FNMV
A
DCL
B
A
—
—
FNMx
A = Calibration modes.
B = Normal high-speed DCL operation mode.
______________________________________________________________________________________ 35
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Table 2. Driver Control
SERIAL-INTERFACE BITS
DIGITAL INPUTS
DRIVER OUTPUT
Drive to DLV
LLEAKS_
ENVHHS_
TMSEL_
LLEAKP_
ENVHHP_
RCV_
DATA_
0
0
0
0
0
0
X
1
X*
X*
0
X
X
0
1
X
X
X
X
1
1
1
1
1
1
0
X
1
1
1
1
X
0
X
X
0
0
1
1
1
X
X
X
0
1
X
X
X
X
X
X
Drive to DHV
High-impedance receive
Drive to DTV
0
MAX79
1
Drive to VHH**
Drive to VHH**
Low leak
0
X
X
Low leak
*Specified DHV, DLV transition times are not altered by the state of ENVHHS_.
**PMU and active load must be disabled to drive to VHH_ (HIZFORCE_ = 0, FMODE_ = 1, MMODE_ = 0, LDDIS_ = 1).
Table 3. Driver Slew Control
TRANSMISSION
LOSS
TYPICAL
DRIVER
SC1_
SC0_
DRIVER SLEW RATE (%)
DUT
0
0
1
1
0
1
0
1
100*
75
50
25
*The power-on-reset and RST default value.
MAX9979
Driver Slew Control
TRANSMISSION
LOSS
BUFFER
A slew-rate circuit controls the slew rate of the buffer
input. Select one of four possible slew rates according
to Table 3. The speed of the internal multiplexer sets
the 100% driver slew rate (see the Driver Large-Signal
Response graph in the Typical Operating
Characteristics section). SC1 and SC0 are set to 0 at
power-up or when RST is forced low.
WAVEFORM
SHAPING
MUX
DUT
CDRP_
VHH Function
VHH allows DUT_ to drive voltages up to 13V. The
VHH_ DAC, which doubles as the PMU’s CLAMPHI_ DAC,
adjusts from 0 to +13V. Table 2 indicates the control
settings required to set DUT_ to VHH_. Table 23 shows
the transfer function for the VHH_ DAC.
Figure 2. Cable-Droop Compensation
form to the nominal output waveform (pre-emphasis).
Figure 2 depicts a comparison between a typical driver
and the MAX9979, and shows how droop compensa-
tion counters signal degradation. Control bits CDRP0,
CDRP1, and CDRP2 vary the amplitude of the compen-
sation signal. Table 4 shows the percent compensation
as a function of control bit settings. The power-on-reset
and RST values for CDRP0, CDRP1, and CDRP2 are 0.
The specified default value is CDRP0 = 1 for Electrical
Characteristics table data.
Driver Cable-Droop Compensation
The driver incorporates active cable-droop compensa-
tion. At high frequencies, transmission-line effects from
the DUT_ output, across the tester signal delivery path
to the device under test, can degrade the output wave-
form fidelity, resulting in a highly degraded or unusable
signal. The compensation circuit counters this degrada-
tion by adding a double time-constant decaying wave-
36 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Table 4. Cable-Droop Compensation Control
SERIAL-INTERFACE BITS
DROOP COMPENSATION (%)
CDRP2_
CDRP1_
CDRP0_
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0*
1.5**
3
4.5
6
7.5
9
10.5
*The power-on-reset and RST default value.
**Specified default value for Electrical Characteristics table data.
Adjustable Driver Output Impedance (ΔR )
value. Table 5 presents the output resistance control
O
The MAX9979’s nominal 50Ω driver output resistance is
adjustable by 2.5Ω with a 360mΩ resolution. The RO
bits in the DCL calibration register set the resistance
logic. The output resistance is set to R + 0.0Ω
O
(0b1000) at power-up or when RST is forced low.
Table 5. Output Resistance Control
SERIAL-INTERFACE BITS
DRIVER OUTPUT RESISTANCE (Ω)
RO3_
RO2_
RO1_
RO0_
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R
R
- 2.88
- 2.52
-2.16
- 1.80
- 1.44
- 1.08
- 0.72
- 0.36
+ 0*
O
O
R
O
O
O
O
O
O
R
R
R
R
R
R
O
R
+ 0.36
+ 0.72
+ 1.08
+ 1.44
+ 1.80
+ 2.16
+ 2.52
O
R
R
R
R
R
R
O
O
O
O
O
O
*Power-on-reset and RST default value.
______________________________________________________________________________________ 37
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Driver DATA Invert Mode
The DATA_/NDATA_ signals for a driver channel are
internally inverted when the INVERT_ bit in the DCL reg-
ister is asserted. The INVERT_ bit is set to 0 at power-
up or when RST is forced low.
voltages at least 0.7V outside the expected DUT_ volt-
age range when not using the clamps. Overvoltage
protection then remains active without loading DUT_.
Driver clamps are always and only enabled in driver
high-impedance mode.
Driver Differential Data Mode
The MAX9979 allows the drivers to be configured for
control of both channels from the channel 0
DATA0/NDATA0 inputs. This feature allows the two
channels to drive DUT nodes in parallel, providing a
25Ω driver at twice the nominal drive current. Enable
this feature by setting the DIFFERENTIAL0 bit in the
DCL register. The DIFFERENTIAL0 bit is set to 0 at
power-up or when RST is forced low.
High-Speed Comparators
The MAX9979 provides two independent high-speed
comparators for each channel. Each comparator has
one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (Figure 4).
Cable-droop compensation is present on both chan-
nels. Comparator outputs are a logical result of the
input conditions.
MAX79
This configuration switches a 16mA current source
between the two outputs, and each output has an internal
termination resistor connected to CTV_. These resistors
are typically 50Ω. Use alternate configurations to termi-
nate different path impedance provided that the absolute
maximum ratings are not exceeded. Note that the resistor
value also sets the voltage swing. The output provides a
Driver Invert + Differential Data Mode
Combining the differential and the invert modes allows
the two channels to produce complementary outputs at
DUT0 and DUT1 from a single digital data stream at
DATA0/NDATA0. The driver block diagram (Figure 3)
shows the logic of the differential and inverted modes.
nominal 400mV
swing with a 50Ω load termination,
P-P
and a 50Ω source termination. See the Electrical
Bias Voltage Input (BV_)
Characteristics section titled High-Speed Comparators,
Logic Outputs for definition of the V
Apply a voltage to BV_ that is ≥ the V voltage used for
IH
voltage.
the DATA_ and RCV_ inputs (V (DATA_, RCV_)) <
OH
IH
V
BV
< 3.5V, because there are ESD-protection diodes
Single-Ended Window Comparator
Set the DIFFERENTIAL1 bit = 0 in the channel 1 DCL
register to enable the high-speed window comparator.
DAC voltages CHV_ and CLV_ control the comparator
thresholds. Table 6 shows the truth table for the com-
parators. Figure 4 shows the comparator block dia-
gram.
between BV_ and the high-speed inputs. Failure to do
this turns on the protection diodes, degrading the
DATA_ and RCV_ signals. Input bias current for BV_ is
less than 1ꢀA.
Driver Voltage Clamps
The voltage clamps (high and low) limit the voltage at
DUT_ and suppress reflections when the channel is
configured as a high-impedance receiver. The clamps
behave as diodes connected to the outputs of high-
current buffers (Figure 1). Internal circuitry compen-
sates for the diode drop at 1mA clamp current. Set the
clamp voltages using the level-setting DACs (CPHV_
and CPLV_). The clamps are enabled only when the
driver is in the high-impedance mode. For transient
suppression, set the clamp voltages to approximately
the minimum and maximum expected DUT_ voltage
range. The optimal clamp voltages are application-spe-
cific and must be empirically determined. Set the clamp
Table 6. Single-Ended Window
Comparator Truth Table
CONDITION
CH_
CL_
0
V
V
V
V
< V
< V
> V
> V
V
V
V
V
< V
> V
< V
> V
0
0
1
1
DUT_
DUT_
DUT_
DUT_
CHV_
CHV_
CHV_
CHV_
DUT_
DUT_
DUT_
DUT_
CLV_
CLV_
CLV_
CLV_
1
0
1
38 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
LLEAKS0
LLEAKP0
TMSEL0
SLEW
DROOP
CONTROL
CONTROL
VHH0
SC0
CDRP0
CPLV0
CPHV0
DLV0
DTV0
DHV0
20Ω
CABLE
COMPENSATION
OUTPUT
BUFFER
MUX
DUT0
25Ω 2.5
NRCV0
BV0*
RO0
VHH
ENABLE
100Ω
ENVHHS0
RCV0
ENVHHP0
NDATA0
MAX9979
INVERT0
100Ω
100Ω
0
1
DATA0
DATA1
0
DGS
0
1
NDATA1
INVERT1
DIFFERENTIAL0
ENVHHP1
RCV1
BV1*
ENVHHS1
VHH
ENABLE
100Ω
RO1
NRCV1
CPHV1
CPLV1
DHV1
DTV1
DLV1
20Ω
CABLE
COMPENSATION
OUTPUT
BUFFER
MUX
SC1
DUT1
25Ω 2.5
CDRP1
VHH1
SLEW
DROOP
CONTROL
CONTROL
TMSEL1
LLEAKP1
LLEAKS1
*SEE THE BIAS VOLTAGE INPUT (BV_) SECTION.
Figure 3. Driver Block Diagram
______________________________________________________________________________________ 39
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
CHV0
0
CH0
NCH0
1
CHANNEL ZERO
CABLE-DROOP
MAX79
DUT0
COMPARATORS
COMPENSATION
CTV0
CDRP0
0
1
CL0
NCL0
CLV0
LLEAKP0
50Ω x 4
LLEAKS0
HYST0
MAX9979
DIFFERENTIAL
COMPARATORS
DIFFERENTIAL1
DGS
50Ω x 4
1
0
1
CH1
CHV1
NCH1
CTV1
CHANNEL ONE
COMPARATORS
CABLE-DROOP
COMPENSATION
DUT1
1
0
1
CL1
CDRP1
CLV1
NCL1
HYST1
LLEAKP1
LLEAKS1
Figure 4. High-Speed Comparators Block Diagram
40 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Table 7. Differential Window Comparator Truth Table
CONDITION
CH0
CL0
0
V
V
V
V
- V
- V
- V
- V
< V
< V
> V
> V
- V
- V
- V
- V
V
V
V
V
- V
- V
- V
- V
< V
> V
< V
> V
- V
- V
- V
- V
0
0
1
1
DUT0
DUT0
DUT0
DUT0
DUT1
DUT1
DUT1
DUT1
CHV1
CHV1
CHV1
CHV1
DGS
DGS
DGS
DGS
DUT0
DUT0
DUT0
DUT0
DUT1
DUT1
DUT1
DUT1
CLV1
CLV1
CLV1
CLV1
DGS
DGS
DGS
DGS
1
0
1
Differential Window Comparator
select one of eight values (0, 2mV, 4mV, 6mV, 8mV,
10mV, 12mV, or 15mV). Hysteresis control affects both
single-ended and differential comparators. The HYST
bits are set to 0b000 at power-up or when RST is forced
low. Table 8 shows the HYST bit functions.
Set the DIFFERENTIAL1 bit = 1 in the channel 1 DCL
register to enable the high-speed differential window
comparator. CHV1 and CLV1 control the differential
comparator thresholds. CHV0 and CLV0 are not used
when differential comparison is active. The valid volt-
age range for CHV1 and CLV1 in differential compari-
son mode is 1V. Setting levels outside 1V does not
damage the device, but performance is not guaran-
teed. Differential comparator outputs are multiplexed to
the channel 0 comparator outputs. The channel 1 com-
parator outputs are both forced to a high state. Figure 4
shows the operation of the comparators. Table 7 shows
the truth table for the differential comparator. Figure 4
shows the comparator block diagram.
Table 8. Hysteresis Logic
SERIAL-INTERFACE BITS
COMPARATOR
HYSTERESIS (mV)
HYST1_
HYST1_
HYST0_
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
2
4
6
8
Comparator Hysteresis
The DCL calibration register controls the high-speed
comparator hysteresis. The HYST bits of that register
10
12
15
VLDH_
MAX9979
DUT_
VCOM_
LDCAL_
0
LLDIS_
TMSEL_
RCV_
VLDL_
TRM
100Ω
DGS
NRCV_
LLEAK_
LLEAKP_
Figure 5. Active Load Block Diagram (One Channel Shown)
______________________________________________________________________________________ 41
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Comparator Cable-Droop Compensation
Control comparator cable-droop compensation using
the same serial bits used for the driver droop compen-
sation, CDRP_. Cable-droop compensation is active for
both the single-ended and the differential comparators.
Load Calibration Enable (LDCAL_)
LDCAL_ allows the load and driver to be simultaneously
enabled for diagnostic purposes. LDDIS_ overrides
LDCAL_.
Parametric Measurement Unit (PMU)
The MAX9979 PMU forces and measures voltages from
-1.5V to 6.5V, and currents up to 50mA. The lowest
full-scale current range is 2ꢀA. Available PMU modes
are force-voltage/measure voltage (FVMV), force-volt-
age/measure current (FVMI), force-current/measure
current (FIMI), force-current/measure voltage (FIMV),
force-nothing/measure voltage (FNMV), and force-noth-
ing/measure nothing (FNMN). Figure 6 presents a block
diagram on the PMU.
Active Load
The active load is a linearly programmable current
source and sink, a commutation buffer, and a diode
bridge (Figure 5). Level-setting DACs VLDH_ and
VLDL_ set the sink and source currents from 0 to 20mA.
Level-setting DAC VCOM_ sets the commutation buffer
output voltage. The source and sink naming convention
is referenced to the MAX9979, so current out of the
MAX9979 constitutes source current and current into
the MAX9979 constitutes sink current.
MAX79
PMU Current-Range Selection
Three bits from the control word (RS0, RS1, and RS2)
control the full-scale current range for both force-
current (FI) and measure-current (MI) modes. The PMU
ranges are independent of the programmed PMU
mode, except range A, which is not allowed in any cali-
bration mode. In these modes range A defaults to
range B (see Table 1). Table 10 presents the PMU cur-
rent-range control logic.
The programmed source current loads the device
under test when V
_ < V
_. The programmed
COM
DUT
sink current loads the device under test when V
_ >
DUT
V
_. The high-speed differential inputs
COM
(RCV_/NRCV_) and three bits of the control word
(LLDIS_, LDCAL_, and TMSEL_) control the load.
LLEAKP_ and LLEAK_ place the load into low-leakage
mode. The low-leakage controls override other controls.
Table 9 details load control logic.
Table 9. Load Control Logic
RCV_
TMSEL_
LDDIS_
LDCAL_
LLEAKS_
LLEAKP_
LOAD STATE
X
X
0
X
1
1
X
X
X
X
X
1
0
X
X
X
0
1
0
0
0
X
X
0
X
0
0
1
1
X
0
0
0
0
0
X
0
1
1
1
1
1
Low leak
Low leak
Off
Off
Off
On
On
Table 10. PMU Current-Range Control
DIGITAL INPUT
SERIAL-INTERFACE BITS
RANGE
LLEAKP_
HIZFORCE_
RS2_
RS1_
RS0_
X
X
X
X
X
0
1
X
X
X
X
0
1
1
0
0
0
0
1
1
1
0
0
1
1
X
X
X
0
1
0
1
X
X
X
E
D
C
B
B*
B*
A
*Range A operation is not allowed for PMU high-impedance modes—PMU defaults to range B.
42 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
TO OTHER CHANNEL
PMU-F_
100Ω
PMU-F
PMU-S
HIZFORCE_
VIN_
RANGE-SETTING
RESISTORS
1
1
LLEAKP_
2.5kΩ
PMU-S_
25Ω
DUT_
1
0
1
10kΩ
REF
FMODE_
CLAMPLO_
CLAMPHI_
CLENABLE_
1
0
CLAMP
CONTROL
MEASI
TO OTHER
CHANNEL
4x
1x
HIZMEASS_
IIOS
DGS
HIZMEASP_
MEAS_
0
0
1
DISABLE_
SENSE_
1
MMODE_
IVMAX_
VIOS
TO OTHER
CHANNEL
DUTHI_
DUTLO_
MEASV
PMUSENSE_
0
1
IVMIN_
MAX9979
HYSTEN_
Figure 6. PMU Block Diagram (One Channel Shown)
______________________________________________________________________________________ 43
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
PMU Comparators
Two comparators, configured as a window comparator,
monitor the MEASV_ and MEASI_ signals (Figure 6).
Level-setting DACs IVMAX_ and IVMIN_ set the high
and low thresholds that determine the window (DAC
IVMAX_ shares duties with VHH_). Both PMU window
comparator outputs are open-drain and share a single
serial disable bit (DISABLE_) that puts the outputs in a
high-impedance, low-leakage state. MEAS_ includes the
influence of VIOS, while the comparator outputs do not.
Table 11 presents the PMU comparator output logic.
IIOS Reference Level for PMU Measure Current
MEAS_ Output
In MI mode, adjust the MEAS_ output around the I
DUT_
= 0 center reference using the IIOS level-setting DAC.
IIOS is programmable from 0 to 5V, but levels outside
of the 2V to 4V range are invalid. The single IIOS DAC
is shared by both channels. IIOS allows level shifting
the 4V MI output range to fully above ground at the
MEAS_ output, useful when MEAS_ is read by a unipo-
lar ADC. The nominal 0x0000 to 0xFFFF code range for
IIOS equates to 0 to 5V. The power-on-reset and RST
state of IIOS is 0x4000, or 1.25V. For normal operation,
the level of IIOS is 2.5V for a -1.5V to +6.5V MI MEAS_
output. The IIOS DAC range is programmable outside
the valid operational range of the IIOS signal, but doing
so will not harm the device. Table 23 presents the IIOS
DAC transfer function.
MAX79
PMU Measure Output (MEAS_)
The MEAS_ output presents a voltage proportional to
the measured voltage or current. Force logic input
HIZMEASP_ or bit HIZMEASS_ low to place MEAS_ in a
low-leakage, high-impedance state.
The MI MEAS_ output is a buffered version of an inter-
nal node that is used to close the force-current loop.
The sourcing range of forced current is limited for IIOS
VIOS Offset Level for PMU Measure Voltage
MEAS_ Output
In MV mode, use the VIOS level-setting DAC to offset
the MEAS_ output voltage. The valid range of VIOS is 0
to 1.5V, but the VIOS DAC is programmable from
-1.25V to +3.75V. The single VIOS DAC is shared by
both channels. VIOS allows level shifting the MEAS_
output, useful when MEAS_ is read by a unipolar ADC.
The nominal 0x0000 to 0xFFFF code range for VIOS
equates to -1.25V to +3.75V. The power-on-reset and
RST state of VIOS is 0x4000, or 0V, the level for normal
operation. The MEAS_ output tracks DGS. The VIOS
DAC range is programmable outside the valid opera-
tional range of the VIOS signal, but doing so will not
harm the device. Table 23 presents the VIOS DAC
transfer function.
levels above 3.5V by the V upper limit of approxi-
IN
mately 7.5V.
PMU Sense
Control bit PMUSENSE_ determines which of two inputs
reaches the PMU sense amplifier (Figure 6). One input
is from DUT_ through an internal 10kΩ resistor, the
other input is from external input SENSE_. Not shown in
Figure 6 is a third input to the sense amplifier (GND),
which is used in VHH and FNMN modes to isolate and
protect the amplifier from potential overvoltage and
glitches. GND is connected automatically based on
mode setting and no discrete control is required. Table
12 presents the PMU sense control logic.
Table 11. PMU Comparator Output Logic
COMPARATOR OUTPUTS
DISABLE_ BIT
CONDITION
DUTHI_
DUTLO_
0
X
High impedance
High impedance
1
V
> V
and V
0
1
1
0
1
1
0
0
MEASURE
IVMAX
IVMIN
> V
MEASURE IVMIN
1
V
> V
IVMAX
1
V
and V
> V
MEASURE
IVMAX
IVMIN
MEASURE
1
V
> V
> V
*
IVMAX
IVMIN
*Normal operation is with V
operation of the comparators.
> V
. This condition has V
IVMIN
> V
. This does not cause any problems with the
IVMAX
IVMAX
IVMIN
44 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Table 12. PMU Sense Control Logic
DIGITAL INPUT
SERIAL-INTERFACE BITS
PMU MODE
SENSE PATH
LLEAKP_
HIZFORCE_
FMODE_
MMODE_
PMUSENSE_
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
X
X
X
X
X
0
0
1
1
1
X
X
X
X
X
X
X
0
1
1
0
1
1
0
1
0
1
X
0
1
X
0
1
FyMy*
Internal
External
Internal
External
GND
FyMy*
FVMy* (calibration)
FVMy* (calibration)
FNMN
FNMV (calibration)
FNMV (calibration)
FNMN
Internal
External
GND
FNMV (calibration)
FNMV (calibration)
Internal
External
*y = V or I.
PMU Analog Signal Polarities
source drives DUT_ beyond a voltage clamp level, the
PMU will current limit safely. When a PMU voltage
clamp is active and at its limit, the MV and MI functions
remain valid. Do not let external voltage levels at DUT_
exceed the absolute maximum rating limits.
In FV mode, DUT_ voltage is proportional to level-
setting DAC voltage V . In FI mode, the current flow-
IN_
ing out of DUT_ is equal to:
V
− V
IIOS
(
)
IN
PMU Current Clamps
Current clamps are available on the PMU output only in
the FV mode. Program the clamps with level-setting
DACs CLAMPLO_ and CLAMPHI_. The PMU current
clamps handle the full current range ( 50mA for range
A, 2mA for range B, etc.). If the clamp currents are
exceeded, the PMU enters a constant-voltage mode.
The current clamp circuits override the PMU only, and
do not limit external sources. When a PMU current
clamp is active, the MV and MI functions are still valid.
4 ×R
RANGE
Positive current is defined as flowing out of the PMU. In
FN mode, the PMU output is high impedance. Table 13
presents the range resistor values. Table 23 presents
the DAC transfer functions.
PMU Voltage Clamps
Voltage clamps are available on the PMU output only in
the FI mode. Program the clamps with level-setting
DACs CLAMPLO_ and CLAMPHI_. The PMU voltage
clamps handle the full 50mA and are triggered by the
voltage at DUT_ independent of the voltage at SENSE_.
The voltage clamps override the PMU only, and do not
limit the voltage of external sources. If an external
PMU Clamp Enable
The CLENABLE_ bit in the PMU register enable the volt-
age and current clamps. Table 14 presents the clamp
enable control logic.
Table 13. Range Resistor Values
Table 14. Clamp Enable Control Logic
RANGE
RESISTOR VALUE (Ω)
CLENABLE_ BIT
MODE
1
0
Clamps enabled
Clamps disabled
A
B
C
D
E
20
500
5k
50k
500k
______________________________________________________________________________________ 45
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
PMU Voltage/Current-Limit Flags
Table 15. Measure Output High-Impedance
Control Logic
The PMU features two comparators, arranged as a win-
dow comparator, to flag current or voltage levels, allow-
ing fast go/no-go testing. The comparators monitor the
load current or voltage, and compare it to level-setting
DACs IVMAX and IVMIN. The MMODE_ bit selects
whether the window comparator monitors MEASV_ or
MEASI_ (Figure 6). If MMODE_ selects MEASV_ then
the PMUSENSE_ bit selects either the SENSE_ input or
DUT_ (Figure 6).
HIZMEASS_
HIZMEASP_
MEAS_ STATE
BIT
INPUT
1
1
0
0
1
0
1
0
Measure output enabled
High impedance
High impedance
MAX79
High impedance
Independent Control of PMU Feedback Switch
and Measure Switch
the PMU in a low-leakage state. Table 1 presents the
low-leakage logic for the PMU output.
Two single-pole/double-throw (SPDT) switches deter-
mine the mode of operation of the PMU. One switch
determines whether the sensed DUT_ current or DUT_
voltage is fed back to the input, and thus determines
which of these parameters is forced. The other switch
determines whether the sensed DUT_ current or DUT_
voltage is presented at MEAS_. Independent control of
these switches and the force high-impedance state
allow for flexible modes of operation beyond the tradi-
tional force-voltage/measure-current (FVMI) and force-
current/measure-voltage (FIMV) modes. The modes
supported are:
PMU DUT Ground Sense (DGS)
All the DAC and MEAS_ outputs track with respect to
the DUT ground sense input (DGS). Connect DGS to
the ground of the device under test.
PMU DUT_ Node Force and Sense Switches
The MAX9979 features additional PMU force (PMU-F)
and PMU sense (PMU-S) connections, through serial-
controlled switches, that are shared between channels
(Figure 6) and can be used to connect an external
PMU. The force switch is maximum 100Ω, and the
sense switch is maximum 2.5kΩ.
• FVMI: Force-voltage/measure-current mode
• FIMV: Force-current/measure-voltage mode
• FVMV: Force-voltage/measure-voltage mode
• FIMI: Force-current/measure-current mode
• FNMV: Force-nothing/measure-voltage mode
• FNMN: Force-nothing/measure-nothing mode
PMU DUT_ Voltage Swing vs. DUT_ Current
and Power-Supply Voltages
Two issues limit the DUT_ voltage that the PMU delivers.
The first issue is the headroom required by the ampli-
fiers and other on-chip circuitry at zero output current.
The second issue is the headroom required with sense
resistor and additional circuit voltage drops at full-scale
current. When the PMU is sourcing or sinking DUT_ cur-
rent, the voltage range is reduced linearly. This compli-
ance curve applies to both FV and FI modes and is
PMU Measure Output High-Impedance Control
The MEAS_ output features a low-leakage, high-imped-
ance state. To activate this state, either place the
HIZMEASS_ bit low or force the HIZMEASP_ logic input
low. The two controls are logically ANDed together
(Figure 6). The HIZMEASP_ input allows multiplexing
between PMU measure outputs without the use of the ser-
ial interface. At power-up, HIZMEASS_ defaults low, plac-
ing MEAS_ in a high-impedance state. Table 15 presents
the high-impedance control logic for the MEAS_ output.
independent of V
. Because the forced DUT_ voltage
DGS
in FV mode is = DGS + V , V
is further limited by
IN DUT_
the V
and the -2.5V to +7.5V V range. Force out-
DGS
IN
put capabilities of the PMU are presented in Figure 7.
These limitations are based on the guaranteed perfor-
mance of the MAX9979. Operating the DUT node outside
these limits will not harm the MAX9979, as long as the
absolute maximum rating limits are observed. With the
above considerations, it is possible to extend the range of
the DUT swing beyond the limits of Figure 7. However,
some specifications, such as linearity, will begin to
degrade. Performance while operating outside the limits
shown in Figure 7 is not guaranteed.
PMU Low-Leakage Mode
The PMU output features a low-leakage, high-imped-
ance state. To activate this state, either place the
HIZFORCE_ bit low or force the LLEAKP_ logic input
low. The two controls are logically ANDed together
(Figure 6). At power-up, HIZFORCE_ defaults low, placing
46 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
clock speeds up to 50MHz and includes the signals CS,
V
DUT
SCLK, DIN, RST, LOAD, and DOUT. Serial-interface tim-
ing is shown in Figure 9 and timing specifications are
detailed in the Electrical Characteristics section.
6.5V
4.5V (A)
6.1V (B–E)
Loading Data into the MAX9979
Load data into the 24-bit shift register from DIN on the
rising edge of SCLK, while CS is low (Figure 8). The
MAX9979 is updated when the control and level-setting
data are latched into the control and level-setting regis-
ters. The control and level-setting registers are separated
from the shift register by the input and channel-select
registers. Two methods allow data to transfer from the
shift register to the control and level-setting registers,
depending on the state of external digital input LOAD.
I
DUT_
1.1V (A)
-1.1V (B–E)
-1.5V
Holding LOAD high during the rising edge of CS allows
the shift register data to transfer only into the input and
channel-select registers. Force LOAD low to transfer
the data into the control and level-setting registers.
Changes update on the falling edge of LOAD, which
allows preloading of data and facilitates synchronizing
updates across multiple devices.
-FSR/2
+FSR/2
Figure 7. Output-Voltage Range
Serial Interface
An SPI-compatible serial interface and the logic-con-
trolled inputs shown in Table 1 control the MAX9979.
The serial interface, detailed in Figure 8, operates with
MAX9979
SCLK
DIN
SHIFT REGISTER
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7
DOUT
LOAD
CS
16
8
RST
CHANNEL-SELECT
REGISTER
INPUT REGISTERS
PMU CONTROL
REGISTER
DCL CONTROL
REGISTER
LEVEL-SETTING DACs
AND DAC CALIBRATION REGISTERS
Figure 8. Serial-Interface Block Diagram
______________________________________________________________________________________ 47
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
t
CH
SCLK
t
t
CL
t
CSS1
CSSO
MAX79
t
t
CSH1
CSHO
CS
t
CSWH
t
DH
t
DS
DIN
A7
A6
A5
A4
A3
A2
D1
D0
t
RST
RST
t
CSHLD
t
CLL
LOAD
t
DO
D1 LAST
D0 LAST
A7
DOUT
A7 LAST
A6 LAST
A5 LAST
A4 LAST
A3 LAST
A2 LAST
Figure 9. Serial-Interface Timing
verify that data were properly shifted in during the pre-
vious communication.
Holding LOAD low during the rising edge of CS forces
the input and channel-select registers to become trans-
parent and all data transfers through these registers
directly to the control and level-setting registers.
Changes update on the rising edge of CS. Figures 10
and 11 show how LOAD and CS function, and also the
data configuration of SCLK, DIN, and DOUT.
Controlling the MAX9979
Control and level-setting registers are selected to
receive data based on the channel and mode-select
bits (A0–A7). Table 16 presents the control register bits
and their functions. Level-setting DAC data and control-
register data are contained in the 16 data bits D0–D16.
Tables 15, 16, and 17 detail the bit functions. Clock in
bit A7 first, and bit D0 last, as shown in Figure 8.
The calibration registers change on the rising edge of
CS, regardless of the state of LOAD.
DOUT
DOUT is a buffered version of the last bit in the serial-
interface shift register. The complete contents of the
shift register can be read at DOUT during the next write
cycle. To shift data out without modifying any registers,
perform a write with address bits A4 and A5 set to 0.
Use DOUT to daisy chain multiple devices, and/or to
Bit A6 allows access to the DAC calibration registers.
Use the calibration registers to adjust the gain and off-
set of each DAC. Set bit A6 to write to the calibration
registers (Table 18). See the Level-Setting DACs sec-
tion for more information.
48 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
CS
INPUT AND
CHANNEL
REGISTERS
UPDATED
SCLK
0
1
2
3
4
5
6
7
8
9
20
21
22
23
DIN
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D3
D2
D1
D0
DOUT
A7'
A6'
A5'
A4'
A3'
A2'
A1'
A0'
D15' D14'
D3'
D2'
D1'
D0'
A7
FIRST BIT
FROM
LAST BIT
FROM
PREVIOUS
WRITE
PREVIOUS
WRITE
LOAD
RST
LEVEL-SETTING AND
CONTROL REGISTERS
UPDATED
Figure 10. Using LOAD to Update the Level-Setting and Control Registers
CS
INPUT, CHANNEL,
LEVEL-SETTING AND
CONTROL
REGISTERS ALL
UPDATED
SCLK
0
1
2
3
4
5
6
7
8
9
20
21
D2
D2'
22
D1
D1'
23
DIN
A7
A7'
A6
A6'
A5
A5'
A4
A4'
A3
A3'
A2
A2'
A1
A1'
A0
D15
D14
D3
D0
D0'
DOUT
A0' D15' D14'
D3'
A7
FIRST BIT
FROM
LAST BIT
FROM
PREVIOUS
WRITE
PREVIOUS
WRITE
LOAD = 0
RST
Figure 11. Using CS to Update the Level-Setting and Control Registers (LOAD Held Low)
______________________________________________________________________________________ 49
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Table 16. MAX9979 Control and Calibration Register Bits
REGISTER
CDRP_
FUNCTION
Driver and comparator cable-droop compensation
CLENABLE_
DIFFERENTIAL0
DIFFERENTIAL1
DISABLE_
ENVHHS_
FMODE_
GCAL_
PMU clamp enable
Select DATA1/NDATA1 as data control for both channels 1 and 2 (Figure 3)
Enable differential comparator outputs (Figure 4)
PMU comparator output disable
VHH_ mode enable
MAX79
PMU force-mode control
DAC gain calibration
HIZFORCE_
HIZMEASS_
HYST_
PMU DUT_ high-impedance control
PMU measure output high-impedance control
High-speed comparator hysteresis select
PMU comparator hysteresis enable
DATA_/NDATA_ polarity control
Load calibration enable
HYSTEN_
INVERT_
LDCAL_
LDDIS_
Load disable
LLEAKS_
MMODE_
OCAL_
DCL low-leak enable
PMU measure-mode control
DAC offset calibration
PMU-F_
Force switch enable (Figure 6)
Sense switch enable (Figure 6)
PMU MEASV input control
PMU-S_
PMUSENSE_
RO_
Driver output resistance select
PMU current range select
RS_
SC_
Driver slew-rate control
TMSEL_
Driver terminate select control
Factory use only. Program to 0.
TMUX_
Table 17. Serial-Input Data Overview
BIT
FUNCTION
A7
A6
Not used. Write 0 or 1
Calibration register write enable
Channel 1 write enable
A5
A4
Channel 0 write enable
A3–A0
D15–D0
Register address (see Table 18)
Register data (see Table 19)
50 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Table 18. Register Address Bits
BITS
REGISTER
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A6 = 0
DCL control
A6 = 1
DCL calibration
DHV calibration
DLV calibration
DTV calibration
CHV calibration
CLV calibration
CPHV calibration
CPLV calibration
—
DHV level
DLV level
DTV level
CHV level/PMU IVMAX
CLV level/PMU IVMIN
CPHV level
CPLV level
PMU control
VIN level
VIN calibration
VCOM calibration
VLDH calibration
VLDL calibration
VIOS/IIOS* calibration
VCOM level
VLDH level
VLDL level
VIOS/IIOS* level
CLAMPHI/VHH level
CLAMPLO level
CLAMPHI/VHH calibration
CLAMPLO calibration
*Channel 0 register programs the VIOS level; channel 1 register programs the IIOS level. Select channels with bits A4 and A5.
Table 19. Data Bit Assignments*
DAC GAIN AND OFFSET
CALIBRATION REGISTERS
DCL
CALIBRATION
REGISTER**
BIT
DCL CONTROL
REGISTER**
PMU CONTROL
REGISTER**
LEVEL-SETTER
REGISTER
VIN
ALL OTHERS
OCAL0
OCAL1
OCAL2
OCAL3
OCAL4
OCAL5
OCAL6
OCAL7
GCAL0
GCAL1
GCAL2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
SC0
SC1
RO0
RO1
FMODE_
MMODE_
RS0_
Bit 0 (LSB)
Bit 1
OCAL0
OCAL1
OCAL2
OCAL3
OCAL4
OCAL5
OCAL6
OCAL7
GCAL0
GCAL1
GCAL2
LLEAKS
TMSEL
RO2
Bit 2
RO3
RS1_
Bit 3
LDDIS
HYST0
HYST1
HYST2
CDRP0
CDRP1
CDRP2
—
RS2_
Bit 4
INVERT
CLENABLE_
HIZFORCE_
HIZMEASS_
DISABLE_
PMUSENSE_
HYSTEN_
Bit 5
DIFFERENTIAL
LDCAL
Bit 6
Bit 7
ENVHHS
TMUX0 = 0
TMUX1 = 0
Bit 8
Bit 9
Bit 10
*The data bits enter the shift register in the order, MSB to LSB.
**The DCL control, DCL calibration, and PMU control registers default to 0x0004, 0x0008, and 0x0003 respectively at power-up.
______________________________________________________________________________________ 51
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Table 19. Data Bit Assignments* (continued)
FUNCTION
DAC GAIN AND OFFSET
CALIBRATION REGISTERS
DCL
CALIBRATION
REGISTER**
BIT
DCL CONTROL
REGISTER**
PMU CONTROL
REGISTER**
LEVEL-SETTER
REGISTER
VIN
ALL OTHERS
GCAL3
GCAL4
GCAL5
—
D11
D12
D13
D14
D15
TMUX2 = 0
—
—
—
—
—
PMU-F
PMU-S
—
Bit 11
Bit 12
GCAL3
GCAL4
GCAL5
GCAL6
—
TMUX3 = 0
MAX79
—
—
—
Bit 13
—
Bit 14
—
Bit 15 (MSB)
—
*The data bits enter the shift register in the order, MSB to LSB.
**The DCL control, DCL calibration, and PMU control registers default to 0x0004, 0x0008, and 0x0003 respectively at power-up.
Level-Setting DACs
The MAX9979 includes 28 level-setting DACs that pro-
vide the DC voltage levels for the various control and
MAX9979
CLAMPHI1
CHV1
CLAMPHI1
VHH1
monitor circuits of the 2-channel MAX9979. Some of the
DACs are shared between the MAX9979 channels, and
some perform dual functions within a channel (Figure
12). Important details about the operation of shared
DACs are:
CHV1
CHANNEL 1
IVMAX1
CLV1
CLV1
• VIOS share a common DAC level for both channels.
VIOS DAC simultaneously updates the VIOS1 and
VIOS2 levels.
IVMIN1
IIOS
IIOS
VIOS
• IIOS share a common DAC level for both channels.
The IIOS DAC simultaneously updates the IIOS1 and
IIOS2 levels.
VIOS
VIOS
IIOS
IVMIN2
CLV2
• CLAMPHI_ and VHH_ share a common DAC level.
The CLAMPHI_/VHH_ DAC simultaneously updates
the CLAMPHI_ and VHH_ levels. Note that the VHH_
output is 0 to +13V. If CLAMPHI_ is set to a negative
value and the VHH_ mode is selected, the VHH_ out-
put limits close to 0V.
CHANNEL 2
CLV2
CHV2
IVMAX2
CHV2
VHH2
CLAMPHI2
CLAMPHI2
• CHV_ and IVMAX_ share a common DAC level. The
CHV_/IVMAX_ DAC simultaneously updates the
CHV_ and IVMAX_ levels.
Figure 12. Arrangement of Shared DACs
Calibrating DAC Gain and Offset
• CLV_ and IVMIN_ share a common DAC level. The
CLV_/IVMIN_ DAC simultaneously updates the CLV_
and IVMIN_ levels.
DAC calibration registers adjust the gain and offset of
each DAC. Each DAC has at least one calibration regis-
ter. All DAC calibration registers are programmed with a
14-bit code, except VIN_, which uses a 15-bit code
(Table 19). The codes are divided into two fields, one field
each for gain (GCAL_) and offset (OCAL_). VIN_ has a 7-
bit field for gain and an 8-bit field for offset. All other DACs
have a 6-bit field for gain and an 8-bit field for offset.
A 16-bit code that varies between 0x0000 and 0xFFFF
sets all DAC levels. Table 20 presents a list of the DACs
and their default values.
52 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
The VCH_, VCL_, and VIN_ DACs have duplicate calibra-
tion registers that are selected and addressed as a func-
tion of the selected DCL/PMU modes. The VCH_ and
VCL_ registers each have three separate calibration
registers that are used by the window comparator, the
differential comparator, and the PMU comparator,
respectively. The VIN_ register features six duplicate cali-
bration registers that are selected as a function of the
PMU force mode. These registers are individually
addressed by first selecting the appropriate mode, then
performing the register write. After the calibration regis-
ters are programmed, the appropriate register is automat-
ically switched in as a function of the operating mode.
Table 20 presents a list of the DAC registers and their
default values. Calibration registers are programmed to
default values only during a power-on reset. Asserting
RST does not force the calibration registers to their
default values. Table 21 summarizes the DAC register
addresses. Figure 13 shows how the calibration regis-
ters affect the DAC outputs.
Table 20. DAC Power-Up and Reset Default Values
LEVEL-SETTING REGISTER
POWER-UP AND RST VALUE
CALIBRATION REGISTER
POWER-UP VALUE*
DAC
DESCRIPTION
DHV_
DLV_
Driver high
Driver low
Driver term
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x2080
0x2080
0x2080
0x2080
0x2080
0x2080
0x2080
0x4080
0x2080
0x2080
0x2080
0x2080
0x2080
0x2080
0x2080
DTV_
CHV_/IVMAX_
CLV_/IVMIN_
CPHV_
High comparator/PMU high comparator
Low comparator/PMU low comparator
High high-impedance clamp
Low high-impedance clamp
PMU force value
CPLV_
VIN_
VCOM_
Load commutation voltage
Load source current
VLDH_
VLDL_
Load sink current
VIOS
PMU measure voltage offset
PMU force/measure current offset
PMU high clamp/driver super voltage
PMU low clamp
IIOS
CLAMPHI_/VHH_
CLAMPLO_
*Calibration registers not affected by RST.
______________________________________________________________________________________ 53
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Table 21. DAC Level-Setting and Calibration Register Addresses
LEVEL-SETTING
CALIBRATION
REGISTER ADDRESS
REGISTER ADDRESS
DAC
DESCRIPTION
NOTES
Ch 0
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x1D
—
Ch 1
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x29
0x2A
0x2B
0x2C
—
Both
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x39
0x3A
0x3B
0x3C
—
Ch 0
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x59
0x5A
0x5B
0x5C
0x5D
—
Ch 1
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x69
0x6A
0x6B
0x6C
-
Both
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x79
0x7A
0x7B
0x7C
—
DHV_
DLV_
Driver high
Driver low
Driver term
—
—
—
1, 3
2, 3
—
—
3
DTV_
MAX79
CHV_/IVMAX_
CLV_/IVMIN_
CPHV_
High comparator/PMU high comparator
Low comparator/PMU low comparator
High high-impedance clamp
Low high-impedance clamp
PMU force value
CPLV_
VIN_
VCOM_
Load commutation voltage
Load source current
—
—
—
4
VLDH_
VLDL_
Load sink current
VIOS
PMU measure voltage offset
PMU force/measure current offset
PMU high clamp/driver super voltage
PMU low clamp
IIOS
0x2D
0x2E
0x2F
—
0x6D
0x6E
0x6F
—
5
CLAMPHI_/VHH_
CLAMPLO_
0x1E
0x1F
0x3E
0x3F
0x5E
0x5F
0x7E
0x7F
3, 6
—
Note 1: A common DAC is used for both the CHV_ and IVMAX_ levels.
Note 2: A common DAC is used for both the CLV_ and IVMIN_ levels.
Note 3: The CHV_ and CLV_ levels each have a pair of calibration registers. One is active when using the window comparator; the
other is active when using the differential comparator. The VIN_ level has six calibration registers corresponding to the force
voltage and the five ranges of force current modes of the PMU. The CLAMPHI_, VHH_, IVMAX_, and IVMIN_ levels each
have their own dedicated calibration register. Addressing any of these calibration registers requires device mode settings
(Table 22) as well as the register’s address.
Note 4: The VIOS level is common to both channels. A channel 0 DAC is used to generate VIOS.
Note 5: The IIOS level is common to both channels. A channel 1 DAC is used to generate IIOS.
Note 6: A common DAC is used for both the CLAMPHI_ and VHH_ levels.
54 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
14-BIT GAIN AND OFFSET
ONE OF FOUR IDENTICAL
WINDOW COMPARATOR
CALIBRATION REGISTER
CIRCUITS SHOWN, FOR
DACs CHV_/IVMAX_ AND
CLV_/IVMIN_
14-BIT GAIN AND OFFSET
CALIBRATION REGISTER
DIFFERENTIAL COMPARATOR
16-BIT DAC
OFFSET AND GAIN
CALIBRATION CIRCUIT
CHV_
OFFSET AND GAIN
CALIBRATION CIRCUIT
IVMAX_
14-BIT GAIN AND OFFSET
CALIBRATION REGISTER
ONE OF 22 IDENTICAL
CIRCUITS SHOWN, FOR DACs
DHV_, DLV_, DTV_, VCOM_,
VLDH_, VLDL_, CPHV_, CPLV_,
CLAMPLO_, VIOS, AND IIOS
14-BIT GAIN AND OFFSET
CALIBRATION REGISTER
OFFSET AND GAIN
CALIBRATION CIRCUIT
DHV_
16-BIT DAC
14-BIT GAIN AND OFFSET
CALIBRATION REGISTER
VHH_AND CLAMPHI_
DACs
OFFSET AND GAIN
CALIBRATION CIRCUIT
CLAMPHI_
VHH_
16-BIT DAC
OFFSET AND GAIN
CALIBRATION CIRCUIT
14-BIT GAIN AND OFFSET
CALIBRATION REGISTER
VIN_ DACs
15-BIT GAIN AND OFFSET
CALIBRATION REGISTER
A
B
15-BIT GAIN AND OFFSET
CALIBRATION REGISTER
FV
FI
15-BIT GAIN AND OFFSET
CALIBRATION REGISTER
C
D
15-BIT GAIN AND OFFSET
CALIBRATION REGISTER
15-BIT GAIN AND OFFSET
CALIBRATION REGISTER
E
15-BIT GAIN AND OFFSET
CALIBRATION REGISTER
OFFSET AND GAIN
CALIBRATION CIRCUIT
16-BIT DAC
VIN_
Figure 13. DAC Calibration Registers
______________________________________________________________________________________ 55
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
An example calibration sequence follows:
3) Offset calibration (must be done after the gain cali-
bration).
1) Power up the MAX9979. This sets the level-setting
DACs to their default 0V values, and the gain and
offset calibration registers to their default midscale
values (Table 20).
a. Set the level of the DAC to the desired offset
calibration point (e.g., midscale).
b. Measure V
ed output.
and compare it to the expect-
OUT_
2) Gain calibration (gain must be calibrated before
calibrating offset).
c. Adjust the offset calibration register until
is as close as possible to the expected
a. Program a level-setting DAC to its minimum
value and measure the output voltage
V
OUT_
MAX79
voltage. Record the value of the offset calibra-
tion register for later use.
(V
). Then, reprogram the DAC to its
OUT_MIN
maximum value and again measure the output
voltage (V ). Calculate the gain using
4) Repeat the above procedure for all DACs that need
calibration, recording each of the gain and offset
calibration register settings for later use.
OUT_MAX
the following equation:
V
− V
OUT_MIN
OUT_MAX
The prior procedure only needs to be done once. Each
time the power is cycled, simply reprogram the gain
and offset registers using the recorded values.
GAIN =
V
− V
SET_MIN
SET_MAX
where V
and V
are the desired gain
SET_MIN
SET_MAX
calibration points.
Table 22 presents the mode settings required to access
the calibration registers of the shared DACs. In some
cases there is more than one way to access the register.
b. Set the DACs gain calibration register until the
gain is as close to 1 as possible. This cali-
brates the gain for the DAC. Record the gain
calibration register value for later use.
Table 22. Mode-Control Settings to Access Calibration Registers of Shared DACs
CALIBRATION REGISTER
SERIAL-INTERFACE BITS
RS_ BIT
DAC
MODE
HIZFORCE_
DIFFERENTIAL1 FMODE_ MMODE_
2
X
X
X
X
X
1
X
X
X
X
X
0
X
X
X
X
X
Window
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
1
X
1
X
1
X
1
X
CLV_, CHV_
Differential
X
X
X
X
0
X
X
1
1
X
1
X
1
X
1
X
IVMAX_, IVMIN_
CLAMPHI_
VHH_
—
—
—
FV*
X
X
X
FI Range A
1
1
X
X
X
X
FI Range B*
0
0
0
0
1
1
0
0
1
0
1
0
VIN_
FI Range C*
FI Range D*
FI Range E*
*Any of these conditions allow access to the calibration register.
56 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
DAC Output Level Transfer Functions
Each of the MAX9979 analog DAC levels is set with a
transfer function that includes the 16-bit DAC code set-
ting, the gain code setting, and the offset code setting.
A separate DAC (VIN_) is used for the PMU force value.
This DAC has a finer gain adjustment resolution and fol-
lows the equation:
⎛
⎜
⎞
⎟
⎟
The V
and V
expressions below present the
VINDAC
⎛
⎜
⎞
DAC
DAC
CODE
−1 × V
− V
DGS
(
)
⎟
REF
basic DAC transfer functions. Each DAC has a voltage
output range of -2.5V to +7.5V (typ). Thirteen of these
DACs are identical and generate a potential according
to the following equation:
16384
V
= ⎝
⎜
⎠
VINDAC
⎜
⎟
⎠
+ OFFSET
× 0.001 − 0.128
(
)
⎝
CODE
⎛
⎞
⎟
⎠
⎛
⎞
GAIN
CODE
× 0.98+ 0.02 ×
+ V
DGS
⎜
⎜
⎝
⎟
⎠
⎛
⎜
⎞
⎟
⎟
⎛
⎜
⎞
64
DAC
⎝
CODE
−1 × V
− V
DGS
+
⎟
(
)
REF
16384
V
= ⎝
⎜
⎠
DAC
For all DACs, the offset code is an integer value between
0 and 255. The VIN_DAC gain code is an integer value
between 0 and 127, and for all other DACs the gain code
is an integer value between 0 and 63. Offset and gain
codes are based on the calibration register settings.
⎜
⎟
⎠
OFFSET
(
× 0.001 − 0.128
)
⎝
CODE
⎛
⎞
⎟
⎠
⎛
⎞
GAIN
CODE
× 0.98+ 0.02×
+ V
⎜
⎜
⎝
⎟
⎠
DGS
32
⎝
Table 23. DAC Transfer Functions
LEVEL
LEVEL TRANSFER FUNCTION
DHV_
DLV_
V
V
V
V
V
V
V
V
V
V
x DHV_ gain + DHV_ offset
x DLV_ gain + DLV_ offset
x DTV_ gain + DTV_ offset
x CHV_ gain + CHV_ offset
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
VINDAC
DTV_
CHV_
IVMAX_
x IVMAX_ gain + IVMAX_ offset
x CLV_ gain + CLV_ offset
CLV_
IVMIN_
x IVMIN_ gain + IVMIN_ offset
x CPHV_ gain + CPHV_ offset
x CPLV_ gain + CPLV_ offset
CPHV_
CPLV_
VIN_ (FVMI)
VIN_ (FIMV 50mA)
VIN_ (FIMV 2mA)
VIN_ (FIMV 200_A)
VIN_ (FIMV 20_A)
VIN_ (FIMV 2_A)
VCOM_
x PMU_FV_ gain + PMU_FV_ offset
(V
(V
(V
(V
(V
- V
- V
- V
- V
- V
) x (50mA/4V) x PMU_FI_ gain + PMU_FI_ offset
) x (2mA/4V) x PMU_FI_ gain + PMU_FI_ offset
) x (200_A/4V) x PMU_FI_ gain + PMU_FI_ offset
) x (20_A/4V) x PMU_FI_ gain + PMU_FI_ offset
) x (2_A/4V) x PMU_FI_ gain + PMU_FI offset
VINDAC
VINDAC
VINDAC
VINDAC
VINDAC
IIOS
IIOS
IIOS
IIOS
IIOS
V
x VCOM_ gain + VCOM_ offset
DAC
VLDH_
(V
DAC
(V
DAC
- DGS) x (20mA/6V) x VLDH_ gain + VLDH_ offset
- DGS) x (20mA/6V) x VLDL_ gain + VLDL_ offset
VLDL_
VIOS
((V
((V
+ DGS)/2) x VIOS gain + VIOS offset
+ REF)/2) x IIOS gain + IIOS offset
DAC
DAC
DAC
IIOS
VHH_
(V
- DGS) x 2 x VHH_ gain + VHH_ offset + DGS
CLAMPHI_ (Voltage)
CLAMPHI_ (Current)
CLAMPLO_ (Voltage)
CLAMPLO_ (Current)
V
x CLAMPHI_ gain + CLAMPHI_ offset
DAC
(V
- V
) x FSR/2V x CLAMPHI_ gain + CLAMPHI_ offset
DAC
DAC
IIOS
V
x CLAMPLO_ gain + CLAMPLO_ offset
- V ) x FSR/2V x CLAMP_LO_ gain + CLAMPLO_ offset
(V
DAC
IIOS
•
•
Values for PMU_FI_ gain and PMU_FI_ offset are different
for each PMU current range.
VLDH_ and VLDL_ levels less than zero are truncated.
•
Full-scale range is dependent upon the PMU current range.
Values are 100mA, 4mA, 400ꢀA, 40ꢀA, and 4ꢀA for ranges
A–E, respectively.
•
Values for CLAMPHI_ gain, CLAMPLO_ gain, CLAMPHI_ off-
set, and CLAMPLO_ offset vary with PMU force mode and
current range.
______________________________________________________________________________________ 57
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
The V
voltages are then utilized for the various sig-
0x0004, 0x0008, and 0x0003, respectively. For initial
power-up values for the level-setting registers, see Table
20. Power supplies may be powered on in any sequence.
DAC
nal paths within the MAX9979 (i.e., driver level DHV_).
Each of these signal paths have inherent gain and offset
errors, denoted as _gain and _offset terms in the Level
Transfer Function column in Table 23. These error terms
are presented to convey the non-ideal gain and offset of
the signal paths—they do not have a specified value.
Power-Supply Considerations
Bypass each supply input to GND and REF to DGS with
0.1ꢀF capacitors (Figure 13). Additionally, use bulk
bypassing of at least 10ꢀF where the power-supply
connections meet the circuit board.
The GAIN
and OFFSET
features of each
CODE
CODE
DAC are designed to correct for these errors to make
the level transfer function expressions, and therefore,
the final signal path outputs (e.g., DHV_) more ideal.
MAX79
Exposed Pad
The exposed pad is internally connected to ground.
Connect to a open copper PCB ground plane or
heatsink to maximize thermal performance. Not intend-
ed as an electrical connection point.
Applications Information
Device Power-Up State
Upon power-up, the DCL enters low-leak mode and the
PMU enters high-impedance mode. The DCL control,
DCL calibration, and PMU control registers default to
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
+
MEAS0
DUTHI0
DUTLO0
REF
1
2
3
4
5
6
7
8
9
51 GND
50
49
V
V
EE
CC
48 DUT0
DGS
47
46
V
V
EE
GND
CC
DOUT
DGND
CS
45 PMU-S
44 PMU-F
MAX9979
43
V
HHP
SCLK 10
DIN 11
42 N.C.
41 TEMP
V
12
40
39
V
V
DD
CC
EE
LOAD 13
RST 14
38 DUT1
DUTLO1 15
DUTHI1 16
MEAS1 17
37
36
V
V
CC
EE
*EP
35 GND
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
TQFN-EP-IDP
*EP = EXPOSED PAD.
58 ______________________________________________________________________________________
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
MAX79
Typical Operating Circuit
+9.75V
-4.75V
+1.4V
+17.5V
+3.3V
TO OTHER
MAX9979s
4 X 50Ω
MAX6225
2.2μF
2.2μF
+3.5V
0.1μF
0.1μF
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
+
1
2
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
MEAS0
GND
2 x 1000Ω
V
DUTHI0
DUTLO0
REF
EE
3
0.1μF
0.1μF
V
CC
4
DUT0
0.1μF
5
TO DUT
GROUND
V
DGS
EE
6
V
GND
CC
7
DOUT
DGND
CS
PMU-S
PMU-F
MAX9979
8
0.1μF
9
V
HHP
10
11
12
13
14
15
16
17
SCLK
DIN
N.C.
TEMP
0.1μF
V
CC
V
DD
0.1μF
0.1μF
V
LOAD
EE
RST
DUT1
V
DUTLO1
DUTHI1
MEAS1
CC
V
EE
2 x 1000Ω
GND
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
+3.5V
0.1μF
0.1μF
4 X 50Ω
+1.4V
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
21-0192
90-0090
68 TQFN-EP-IDP T6800RN+6
______________________________________________________________________________________ 59
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
6/08
Initial release
—
10/08
Corrected error in Table 2 and formula on page 57
36, 57
37, 38, 41, 42, 44,
45, 46, 48, 50–54,
56, 57, 58
2
12/08
Added new Tables 6 and 7 and renumbered subsequent tables
MAX79
3
4
5
6
4/09
6/09
1/11
8/11
Made spec changes and clarifications
5–8, 20, 57
59
Corrected Typical Operating Circuit
Updated Pin Description, Exposed Pad section, and Package Information
Clarified use of exposed die attach pad
33, 58, 59
33, 58
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
60 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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