MAXQ612 [MAXIM]
16-Bit Microcontrollers with Infrared Module and Optional USB; 16位微控制器具有红外模块和USB（可选）
| 型号： | MAXQ612 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit Microcontrollers with Infrared Module and Optional USB |
| 文件： | 总30页 (文件大小：1178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5117; Rev 0; 2/10
16-Bit Microcontrollers with
Infrared Module and Optional USB
S 1.70V to 3.6V Operating Voltage
General Description
S Can Be Powered from Battery (V ) or USB (V
S 33 Total Instructions for Simplified Programming
)
DD DDB
M
The MAXQ612/MAXQ622 are low-power, 16-bit MAXQ
microcontrollers designed for low-power applications
including universal remote controls, consumer elec-
tronics, and white goods. Both devices use a low-
power, high-throughput, 16-bit RISC microcontroller.
Serial peripherals include two universal synchronous/
asynchronous receiver-transmitters (USARTs), two SPIK
master/slave communications ports, and an inter-inte-
S Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
S Dedicated Pointer for Direct Read from Code Space
S 16-Bit Instruction Word, 16-Bit Data Bus
S 16 x 16-Bit General-Purpose Working Registers
S Secure MMU for Application Partitioning and IP
Protection
S Memory Features
2
grated circuit (I C) bus. The devices also incorporate
an IR module with carrier frequency generation and
flexible port I/O capable of multiplexed keypad control.
The MAXQ622 adds a universal serial bus (USB) with
integrated physical interface (PHY).
128KB Flash Memory
512-Byte Sectors
20,000 Erase/Write Cycles per Sector
6KB Data SRAM
The MAXQ612/MAXQ622 include 128KB of flash memory
and 6KB of data SRAM. Intellectual property (IP) protection is
provided by a secure memory management unit (MMU) that
supports multiple application privilege levels and protects
code against copying and reverse engineering. Privilege
levels enable vendors to provide libraries and applications to
execute on the MAXQ612/MAXQ622, while limiting access
to only data and code allowed by their privilege level.
S USB Features (MAXQ622 Only)
USB 2.0 Full-Speed Compatible
Hardware Receive and Transmit Buffers for High
Throughput
Integrated Full-Speed Transceiver
On-Chip Termination and Pullup Resistors
S Additional Peripherals
Power-Fail Warning
For the ultimate in low-power battery-operated perfor-
mance, the devices include an ultra-low-power stop mode
(0.3FA typical). In this mode, the minimum amount of
circuitry is powered. Wake-up sources include external
interrupts, the power-fail interrupt, and a timer interrupt.
The microcontroller runs from a wide operating voltage of
1.70V to 3.6V, and can also be powered from the USB.
Power-On Reset (POR)/Brownout Reset
Automatic IR Carrier Frequency Generation and
Modulation
Two 16-Bit Programmable Timers/Counters with
Prescaler and Capture/Compare
Two SPI Communication Ports
Two USART Communication Ports
2
Applications
Consumer Electronics
Home Appliances
White Goods
I C Port
Programmable Watchdog Timer
Remote Controls
Battery-Powered
Portable Equipment
8kHz Nanopower Ring Oscillator Wake-Up Timer
Up to 56 General-Purpose I/O
S Low Power Consumption
0.3µA (typ), 3µA (max) in Stop Mode
Features
T
A
= +25NC, Power-Fail Monitor Disabled
S High-Performance, Low-Power, 16-Bit RISC Core
S DC to 12MHz Operation Across Entire Operating Range
4.8mA (typ) at 12MHz, 520µA (typ) at 1MHz in
Active Mode
Ordering Information/Selector Guide
OPERATING
VOLTAGE (V) MEMORY (KB) MEMORY (KB)
PROGRAM
DATA
USB FULL
SPEED
PART
TEMP RANGE
PIN-PACKAGE
MAXQ612J-0000+
MAXQ612G-0000+
MAXQ622G-0000+
0NC to +70NC
0NC to +70NC
0NC to +70NC
1.7 to 3.6
1.7 to 3.6
1.7 to 3.6
128 Flash
128 Flash
128 Flash
6
6
6
No
No
44 TQFN-EP*
64 LQFP
Yes
64 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Note: Bare die versions for most of these devices are available. Contact the factory for availability at https://support.maxim-ic.com/micro.
MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit Microcontrollers with
Infrared Module and Optional USB
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
I C Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
I C Bus Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
IR Transmit—Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
IR Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Carrier Burst-Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16-Bit Timers/Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2
I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
USB Controller (MAXQ622 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ROM Loader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Loading Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
In-Circuit Debug and JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-Supply Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-Fail Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2
______________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
TABLE OF CONTENTS (continued)
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LIST OF FIGURES
Figure 1. Series Resistors (R ) for Protecting Against High-Voltage Spikes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
S
2
Figure 2. I C Bus Controller Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIST OF TABLES
Table 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. Power-Fail Warning Level Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . 28
_______________________________________________________________________________________
3
16-Bit Microcontrollers with
Infrared Module and Optional USB
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
with Respect to GND .....-0.3V to +3.6V
Voltage Range on DP, DM with
DD
Voltage Range on Any Lead with
Respect to GND Except V .............. -0.3V to (V
Respect to GND...................................-0.3V to (V
+ 0.3V)
BUS
+ 0.5V)
DD
Operating Temperature Range............................. 0NC to +70NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature .........................Refer to the IPC/JEDEC
J-STD-020 Specification.
BUS
Voltage Range on V
with Respect to GND....-0.3V to +6.0V
BUS
Continuous Output Current
Any Single I/O Pin...........................................................25mA
All I/O Pins Combined.....................................................25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(V
DD
= V to 3.6V, T = 0NC to +70NC.) (Note 1)
RST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
3.6
UNITS
Supply Voltage
V
DD
V
V
V
RST
1.8V Internal Regulator
V
1.62
1.8
1.8
1.98
REG18
Power-Fail Warning Voltage for
Supply
Monitors V
DD
(Notes 2, 3, 4)
V
1.75
1.85
V
PFW
Power-Fail Reset Voltage
POR Voltage
V
Monitors V
Monitors V
(Note 6)
(Note 5)
1.64
1.0
1.67
1.70
1.42
V
V
V
RST
DD
V
V
POR
DD
RAM Data-Retention Voltage
1.0
DRV
I
Sysclk = 12MHz
4.8
0.52
0.3
2.8
24
5.5
0.8
3
DD_1
DD_2
Active Current
mA
I
Sysclk = 1MHz (Note 6)
T
T
T
T
= +25NC
= +70NC
= +25NC
= +70NC
Power-Fail Off
(Note 7)
A
A
A
A
I
I
S1
S2
13
30
40
Stop-Mode Current
FA
Power-Fail On
(Notes 6, 8, 9)
(Note 10)
30
[(3 x I
+ ((PCI -
)
S2
Current Consumption During
Power Fail
I
3) x (I
+
))]/
FA
PFR
S1
I
NANO
PCI
Current Consumption During
POR
I
100
nA
POR
375 +
8192
Stop-Mode Resume Time
t
Fs
ON
t
HFXIN
Power-Fail Monitor Startup
Time
t
(Note 6)
150
Fs
Fs
V
PFM_ON
Power-Fail Warning Detection
Time
t
(Notes 6, 11)
10
PFW
Input Low Voltage for IRTX,
IRRX, RESET, and All Port Pins
V
IL
V
0.3 x V
DD
GND
Input High Voltage for IRTX,
IRRX, RESET, and All Port Pins
V
0.7 x V
V
DD
V
IH
DD
4
______________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
RECOMMENDED OPERATING CONDITIONS (continued)
(V
DD
= V to 3.6V, T = 0NC to +70NC.) (Note 1)
RST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Hysteresis (Schmitt)
V
IHYS
300
mV
External driven clock and not
feedback connected crystal
oscillator
Input Low Voltage for HFXIN
V
V
0.3 x V
DD
V
V
IL_HFXIN
IH_HFXIN
GND
External driven clock and not
feedback connected crystal
oscillator
Input High Voltage for HFXIN
V
0.7 x V
V
DD
DD
IRRX Input Filter Pulse-Width
Reject
t
t
50
ns
ns
IRRX_R
IRRX_A
IRRX Input Filter Pulse-Width
Accept
300
V
V
V
V
V
V
= 3.6V, I = 25mA (Note 6)
1.0
1.0
1.0
0.5
0.5
0.5
DD
DD
DD
DD
DD
DD
OL
Output Low Voltage for IRTX
V
= 2.35V, I = 10mA (Note 6)
V
OL_IRTX
OL
= 1.85V, I = 4.5mA
OL
= 3.6V, I = 11mA (Note 6)
0.4
0.4
0.4
OL
Output Low Voltage for RESET
and All Port Pins (Note 12)
V
OL
= 2.35V, I = 8mA (Note 6)
V
V
OL
= 1.85V, I = 4.5mA
OL
Output High Voltage for IRTX
and All Port Pins
V
DDIO
0.5
-
V
I
= -2mA
V
OH
OH
DDIO
Input/Output Pin Capacitance
for All Port Pins Except DP, DM
C
I
(Note 6)
15
pF
nA
IO
Input Leakage Current
Internal pullup disabled
-100
16
+100
39
L
V
DD
V
DD
V
DD
V
DD
= 3V, V = V /2 (Note 6)
25
27
28
30
OL
DD
= 2V, V = V /2
17
41
Input Pullup Resistor for
RESET, IRTX, IRRX, P0 to P6
OL
DD
R
PU
kW
= 3.0V, V = 0.4V (Note 6)
16
39
OL
= 2.0V, V = 0.4V (Note 6)
17
41
OL
V
current is the sum of V
DDIO
DDIOH
GPIO Supply Output High
Voltage
V
current and I
20mA
of all GPIO, I
=
V
DD
- 0.4
V
DD
V
DDIOH
OH
OH
EXTERNAL CRYSTAL/RESONATOR
Crystal/Resonator
f
t
(Note 13)
1
12
MHz
ns
HFXIN
HFXIN
Crystal/Resonator Period
1/f
HFXIN
Crystal/Resonator Warmup
Time
8192 x
t
From initial oscillation
ms
XTAL_RDY
t
HFXIN
Oscillator Feedback Resistor
Crystal ESR
R
(Note 6)
(Note 6)
0.5
1.0
1.5
60
OSCF
MW
W
EXTERNAL CLOCK INPUT
External Clock Frequency
External Clock Period
External Clock Duty Cycle
f
t
(Note 13)
DC
45
12
55
MHz
ns
XCLK
1/f
XCLK
XCLK
t
%
XCLK_DUTY
f
HFXIN
System Clock Frequency
f
MHz
CK
HFXOUT = GND
f
XCLK
_______________________________________________________________________________________
5
16-Bit Microcontrollers with
Infrared Module and Optional USB
RECOMMENDED OPERATING CONDITIONS (continued)
(V
DD
= V to 3.6V, T = 0NC to +70NC.) (Note 1)
RST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1/f
MAX
UNITS
System Clock Period
t
ns
CK
CK
NANOPOWER RING
T
T
= +25NC
3
13
20
A
A
Nanopower Ring Frequency
f
kHz
NANO
= +25NC, V
= POR voltage
DD
1.7
40
2.4
(Note 6)
Nanopower Ring Duty Cycle
Nanopower Ring Current
WAKE-UP TIMER
t
I
(Note 6)
60
%
NANO
NANO
Typical at V
+25°C (Note 6)
= 1.64V, T =
A
DD
40
400
nA
65,535/
Wake-Up Timer Interval
FLASH MEMORY
t
1/f
NANO
s
WAKEUP
f
NANO
System Clock During Flash
Programming/Erase
f
1
MHz
ms
FPSYSCLK
t
Mass erase
Page erase
20
20
40
40
ME
Flash Erase Time
t
ERASE
Flash Programming Time per
Word
t
(Note 14)
20
100
Fs
PROG
Write/Erase Cycles
Data Retention
USB
20,000
100
Cycles
Years
T
= +25NC
A
USB Supply Voltage
V
(Note 15)
Transmitting on DP and DM at
4.5
5.0
5.5
V
BUS
12Mbps, C = 50pF on DP and DM
L
13.5
mA
to GND, FRCVDD = 0
V
BUS
Supply Current (Note 16)
I
VBUS
Transmitting on DP and DM at
12Mbps, C = 50pF on DP and DM
L
to GND, FRCVDD = 1
3.5
6
mA
mA
DP = high, DM = low, FRCVDD = 0
(Note 6)
V
Supply Current During
BUS
I
VBUSID
Idle (Note 16)
Suspend Supply Current
DP = high, DM = low, FRCVDD = 1
0.2
mA
V
BUS
I
500
FA
VBUSSUS
Single-Ended Input High
Voltage DP, DM
V
2.0
V
V
IHD
Single-Ended Input Low
Voltage DP, DM
V
0.8
0.3
ILD
Output Low Voltage DP, DM
Output High Voltage DP, DM
V
OLD
R = 1.5kI from DP to 3.6V
V
V
L
V
OHD
R = 15kIfrom DP and DM to GND
L
2.8
0.2
0.8
Differential Input Sensitivity
DP, DM
V
DP to DM
V
V
DI
Common-Mode Voltage Range
V
Includes V range
2.5
CM
DI
6
______________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
RECOMMENDED OPERATING CONDITIONS (continued)
(V
DD
= V to 3.6V, T = 0NC to +70NC.) (Note 1)
RST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Single-Ended Receiver
Threshold
V
SE
0.8
2.0
V
Single-Ended Receiver
Hysteresis
V
SEH
V
CRS
200
mV
V
Differential Output Signal
Cross-Point Voltage
C = 50pF (Note 6)
L
1.3
2.0
DP, DM Off-State Input
Impedance
R
300
LZ
kW
W
Driver Output Impedance
R
Steady-state drive
Idle
28
0.9
44
DRV
1.575
3.090
DP Pullup Resistor
R
PU
kW
Receiving
1.425
USB TIMING
DP, DM Rise Time (Transmit)
DP, DM Fall Time (Transmit)
t
C = 50pF
4
4
20
20
ns
ns
R
L
t
C = 50pF
L
F
Rise/Fall Time Matching
(Transmit)
t /t
R F
C = 50pF (Note 6)
L
90
110
%
IR
Carrier Frequency
SPI (Note 6)
f
f /2
CK
Hz
IR
SPI Master Operating
Frequency
1/t
f
f
/2
/4
MHz
MCK
CK
SPI Slave Operating
Frequency
1/t
MHz
ns
SCK
CK
C = 15pF, pullup = 560W
L
SPI I/O Rise/Fall Time
t
8
24
SPI_RF
SCLK_ Output Pulse-Width
High/Low
t
t
t
/2 -
MCK
t
, t
ns
MCH MCL
t
SPI_RF
MOSI_ Output Hold Time After
SCLK_ Sample Edge
/2 -
MCK
t
ns
ns
ns
ns
ns
ns
ns
MOH
t
SPI_RF
MOSI_ Output Valid to Sample
Edge
/2 -
MCK
t
MOV
t
SPI_RF
MISO_ Input Valid to SCLK_
Sample Edge Rise/Fall Setup
t
25
0
MIS
MIH
MISO_ Input to SCLK_ Sample
Edge Rise/Fall Hold
t
SCLK_ Inactive to MOSI_
Inactive
t
/2 -
MCK
t
MLH
t
SPI_RF
SCLK_ Input Pulse-Width
High/Low
t
, t
t
/2
SCK
SCH SCL
SSEL_ Active to First Shift
Edge
t
t
SSE
SPI_RF
_______________________________________________________________________________________
7
16-Bit Microcontrollers with
Infrared Module and Optional USB
RECOMMENDED OPERATING CONDITIONS (continued)
(V
DD
= V to 3.6V, T = 0NC to +70NC.) (Note 1)
RST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MOSI_ Input to SCLK_ Sample
Edge Rise/Fall Setup
t
t
t
ns
SIS
SPI_RF
MOSI_ Input from SCLK_
Sample Edge Transition Hold
t
ns
ns
ns
ns
ns
SIH
SPI_RF
MISO_ Output Valid After
SCLK_ Shift Edge Transition
t
50
SOV
t
+
CK
t
SSEL_ Inactive
SSH
t
t
SPI_RF
SCLK_ Inactive to SSEL_
Rising
t
SD
SPI_RF
MISO_ Output Disabled After
SSEL_ Edge Rise
2t
+
CK
2t
SPI_RF
t
SLH
2
I C ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 3.6V, T = 0NC to +70NC.) (Note 1, Figure 1)
A
STANDARD MODE
FAST MODE
MIN MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 18)
(Note 18)
UNITS
MIN
MAX
Input Low Voltage
Input High Voltage
V
-0.5
0.3 x V
-0.5
0.3 x V
DD
V
V
V
V
IL_I2C
DD
V
0.5V
+
DD
V
0.7 x V
0.7 x V
IH_I2C
DD
DD
0.05 x
Input Hysteresis (Schmitt)
V
V
V
> 2V
IHYS_I2C
DD
V
DD
Output Logic-Low (Open
Drain or Open Collector)
> 2V, 3mA sink cur-
DD
V
0
0.4
0
0.4
OL_I2C
rent
Output Fall Time from
V
to V
with
20 +
IH_MIN
IL_MAX
t
(Notes 19, 20)
250
250
ns
ns
OF_I2C
Bus Capacitance from
10pF to 400pF
0.1C
B
Pulse Width of Spike
Filtering That Must Be
Suppressed by Input
Filter
t
0
50
SP_I2C
Input voltage from
Input Current on I/O
I/O Capacitance
I
-10
+10
10
-10
+10
10
FA
IN_I2C
0.1 x V
to 0.9 x V
DD
DD
C
pF
IO_I2C
8
______________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
I C BUS CONTROLLER TIMING
2
(Notes 6, 21) (Figure 2)
STANDARD MODE
FAST MODE
PARAMETER
SYMBOL
UNITS
MIN
0
MAX
MIN
MAX
2
I C Bus Operating Frequency
f
100
0
400
kHz
MHz
Hz
Fs
I2C
System Frequency
f
0.90
3.60
SYS
2
I C Bit Rate
f
f
/8
SYS
f
/8
I2C
SYS
Hold Time After (Repeated) START
Clock Low Period
t
4.0
4.7
4.0
4.7
0
0.6
1.3
HD:STA
t
Fs
LOW_I2C
Clock High Period
t
0.6
Fs
HIGH_I2C
Setup Time for Repeated START
Hold Time for Data (Notes 22, 23)
Setup Time for Data (Note 24)
SDA/SCL Fall Time (Note 20)
SDA/SCL Rise Time (Note 20)
Setup Time for STOP
t
0.6
Fs
SU:STA
t
3.45
0
0.9
Fs
HD:DAT
t
250
100
ns
SU:DAT
t
300
20 + 0.1C
20 + 0.1C
0.6
300
300
ns
F_I2C
R_I2C
B
t
1000
ns
B
t
4.0
4.7
Fs
SU:STO
Bus Free Time Between STOP and
START
t
1.3
Fs
BUF
Capacitive Load for Each Bus Line
C
B
400
400
pF
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
V
0.1 x V
0.2 x V
0.1 x V
0.2 x V
V
V
nL_I2C
DD
DD
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
V
nH_I2C
DD
DD
Note 1: Specifications to 0NC are guaranteed by design and are not production tested.
Note 2: V can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V Q3%. The values
PFW
listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal.
Note 3: It is not recommended to write to flash when the supply voltage drops below the power-fail warning levels, as there is
uncertainty in the duration of continuous power supply. The user application should check the status of the power-fail
warning flag before writing to flash to ensure complete write operations.
Note 4: The power-fail warning monitor and the power-fail reset monitor are designed to track each other with a minimum delta
between the two of 0.11V.
Note 5: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals
is active at all times when V
achieved.
< V , ensuring the device maintains the reset state until minimum operating voltage is
RST
DD
Note 6: Guaranteed by design and not production tested.
Note 7: I is measured with the USB data RAM powered down.
S1
Note 8: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles.
Note 9: Measured on the V
pin and the device not in reset. All inputs are connected to GND or V . Outputs do not source/
DD
DD
sink any current. The device is executing code from flash memory.
Note 10: Current consumption during POR when powering up while V is less than the POR release voltage.
DD
Note 11: The minimum amount of time that V
must be below V
before a power-fail event is detected.
DD
PFW
Note 12: The maximum total current, I
and I , for all listed outputs combined should not exceed 25mA to satisfy the
OL(MAX)
OH(MAX)
maximum specified voltage drop. This does not include the IRTX output.
Note 13: External clock frequency must be 12MHz to support USB functionality. Full-speed USB(12Mbps)-required bit-rate accu-
racy is Q2500ppm or Q0.25%. This is inclusive of all potential error sources: frequency tolerance, temperature, aging,
crystal capacitive loading, board layout, etc.
Note 14: Programming time does not include overhead associated with utility ROM interface.
_______________________________________________________________________________________
9
16-Bit Microcontrollers with
Infrared Module and Optional USB
Note 15: For USB operation, both V
and V
must be connected.
DD
BUS
Note 16: FRCVDD is the force V
power-supply bit (PWCN.10). When FRCVDD = 1, V power switching is disabled, and V
DDB DD
DD
is always used as the core 3V power supply.
Note 17: The ESD protection scheme is in production on existing parts. The 1FF capacitor on V
is intended to protect that
BUS
pin from ESD damage (rather than DP or DM) since it is externally exposed. The ESD test uses 150pF charged to 15kV
applied to the 1FF capacitor creating a delta V of approximately 2.25V and limiting the voltage on V
Note 18: Devices that use nonstandard supply voltages that do not conform to the intended I C bus system levels must relate their
.
BUS
2
input levels to the voltage to which the pullup resistors R are connected.
P
Note 19: The maximum fall time, t
of 300ns for the SDA and SCL bus lines is longer than the specificed maximum t
of
F_I2C
OF_I2C
250ns for the output stages. This allows series protection resistors (R ) to be connected between the SDA/SCL pins and
S
2
the SDA/SCL bus lines as shown in I C Bus Controller Timing without exceeding the maximum specified fall time.
Note 20: C = Capacitance of one bus line in pF.
B
Note 21: All values referred to V
and V
.
IH_I2C(MIN)
IL_I2C (MAX)
Note 22: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
of the SCL
IH_I2C(MIN)
signal) to bridge the undefined region of the falling edge of SCL.
Note 23: The maximum t
need only be met if the device does not stretch the low period (t
) of the SCL signal.
LOW_I2C
HD:DAT
2
2
Note 24: A fast-mode I C bus device can be used in a standard-mode I C bus system, but the requirement t
R 250ns must
SU:DAT
be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
1000 + 250 = 1250ns (according to the standard-mode I C specification) before the SCL line is released.
+ t
=
R_I2C(MAX)
SU:DAT
2
Note 25: AC electrical specifications are guaranteed by design and are not production tested.
V
DD
2
I C
2
I C
DEVICE
DEVICE
R
R
P
MAXQ612
MAXQ622
P
R
S
R
R
R
S
S
S
SDA
SCL
P0.3
P0.4
Figure 1. Series Resistors (R ) for Protecting Against High-Voltage Spikes
S
S
SR
P
S
SDA
t
BUF
t
t
R_I2C
F_I2C
t
t
t
SU:STA
LOW_I2C
SU:DAT
SCL
t
t
HIGH_I2C
HD:STA
t
t
SU:STO
HD:DAT
NOTE: TIMING REFERENCED TO V
AND V
IL_I2C(MAX).
IH_I2C(MIN)
2
Figure 2. I C Bus Controller Timing Diagram
10 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
Pin Configurations
TOP VIEW
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
GND
P3.4/INT12
P3.3/INT11
P3.2/INT10
P3.1/INT9
P3.0/INT8
HFXOUT
HFXIN
MAXQ612
GND
IRTX
REG18
*EP
IRRX
V
DD
+
P0.0/IRTXM
RESET
TQFN
*EXPOSED PAD.
______________________________________________________________________________________ 11
16-Bit Microcontrollers with
Infrared Module and Optional USB
Pin Configurations (continued)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
32
31
30
P1.2/INT2
P1.3/INT3
P3.5/INT13
P3.4/INT12
P3.3/INT11
P1.4/INT4 51
P1.5/INT5 52
29 P3.2/INT10
28
53
54
55
P1.6/INT6
P1.7/INT7
P4.0
P3.1/INT9
27
P3.0/INT8
26
25
24
23
22
21
20
19
HFXOUT
HFXIN
GND
P4.1 56
P4.2 57
P4.3 58
P4.4 59
P4.5 60
P4.6 61
MAXQ612
REG18
V
DD
N.C.
N.C.
N.C.
62
P4.7
GND 63
IRTX 64
18 N.C.
17 N.C.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
LQFP
12 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
Pin Configurations (continued)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
32
31
30
P1.2/INT2
P1.3/INT3
P3.5/INT13
P3.4/INT12
P3.3/INT11
P1.4/INT4 51
P1.5/INT5 52
29 P3.2/INT10
28
53
54
55
P1.6/INT6
P1.7/INT7
P4.0
P3.1/INT9
27
P3.0/INT8
26
25
24
23
22
21
20
19
HFXOUT
HFXIN
GND
P4.1 56
P4.2 57
P4.3 58
P4.4 59
P4.5 60
MAXQ622
REG18
V
V
V
V
DD
DDIO
DDB
BUS
61
62
P4.6
P4.7
GND 63
IRTX 64
18 DM
17 GND
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
LQFP
Pin Description
PIN
NAME
FUNCTION
MAXQ612
TQFN-EP
MAXQ612
LQFP
MAXQ622
LQFP
POWER PINS
13
22
22
V
DD
Supply Voltage
8, 24, 35,
63
8, 17, 24,
35, 63
15, 28, 41
GND
Ground
Regulator Capacitor. This pin must be connected to ground through a
1.0FF external ceramic-chip capacitor. The capacitor must be placed as
close to this pin as possible. No external devices other than the capaci-
tor should be connected to this pin.
14
—
23
—
23
—
REG18
EP
Exposed Pad (TQFN Only). Connect EP to the ground plane.
______________________________________________________________________________________ 13
16-Bit Microcontrollers with
Infrared Module and Optional USB
Pin Description (continued)
PIN
NAME
FUNCTION
MAXQ612
TQFN-EP
MAXQ612
LQFP
MAXQ622
LQFP
RESET PINS
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this
pin is low and begins executing from the reset vector when released. The
pin includes pullup current source and should be driven by an open-drain,
external source capable of sinking in excess of 4mA. This pin is driven low
as an output when an internal reset condition occurs.
12
15
15
RESET
CLOCK PINS
High-Frequency Crystal Input. Connect an external crystal or resona-
tor between HFXIN and HFXOUT as the high-frequency system clock.
Alternatively, HFXIN is the input for an external, high-frequency clock
source when HFXOUT is shorted to ground during POR.
16
17
25
26
25
26
HFXIN
HFXOUT
USB FUNCTION PINS
USB V
Supply Voltage. Connect V
to a positive 5.0V power sup-
BUS
BUS
—
—
—
—
—
—
19
16
18
V
ply. Bypass V
to ground with a 1.0FF ceramic capacitor as close to
BUS
BUS
the V
pin as possible.
BUS
USB D+ Signal. This bidirectional pin carries the positive differential
data or single-ended data. Connect this pin to a USB “B” connector.
This pin is weakly pulled high internally when the USB is disabled.
DP
USB D- Signal. This bidirectional pin carries the negative differential
data or single-ended data. Connect this pin to a USB “B” connector.
This pin is weakly pulled high internally when the USB is disabled.
DM
USB Transceiver Supply Voltage. This is the power output of the internal
voltage regulator that is used for the USB transceiver (3.3V) block. This
pin is bypassed to ground with a 1.0FF capacitor as close as possible
to the package. No external circuitry should be powered from this pin.
—
—
—
—
20
21
V
DDB
Switched 3V Power Supply. This is the power output after selection
between V
and V . Must be connected to an external ceramic
DD
BUS
V
chip capacitor. The capacitor must be placed as close to this pin as
possible. No external devices other than the capacitor should be con-
nected to this pin.
DDIO
IR FUNCTION PINS
IR Transmit Output. Active-low IR transmit pin capable of sinking 25mA.
This pin defaults to three-state input with the weak pullup disabled dur-
ing all forms of reset. Software must configure this pin after release from
reset to remove the three-state input condition.
42
43
64
1
64
1
IRTX
IRRX
IR Receive Input
14 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
Pin Description (continued)
PIN
NAME
FUNCTION
MAXQ612
TQFN-EP
MAXQ612
LQFP
MAXQ622
LQFP
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS
General-Purpose, Digital, I/O, Type C Port. These port pins function as
bidirectional I/O pins. All port pins default to three-state mode after a
reset. All alternate functions must be enabled from software.
P0.0–P0.7;
IRTXM,
MAXQ612
TQFN-EP
MAXQ612 MAXQ622
SPECIAL
FUNCTION
PORT
LQFP
LQFP
RX0, TX0,
RX1, TX1,
SDA, SCL,
TBA0,
TBA1,
TBB0, TBB1
44
1
2
3
2
3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
IRTXM
RX0
44, 1–7
2–7, 9, 10
2–7, 9, 10
2
4
4
TX0
3
5
5
RX1/SDA
TX1/SCL
TBA0/TBA1
TBB0
4
6
6
5
7
7
6
9
9
7
10
10
TBB1
General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable
Interrupt. These port pins function as bidirectional I/O pins or as inter-
rupts. All port pins default to three-state mode after a reset. All interrupt
functions must be enabled from software.
MAXQ612
TQFN-EP
MAXQ612 MAXQ622
SPECIAL
FUNCTION
PORT
LQFP
LQFP
33
34
35
36
37
38
39
40
45
45
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
P1.0–P1.7;
INT0–INT7
33–40
45, 48–54
45, 48–54
48
48
49
49
50
50
51
51
52
52
53
53
54
54
______________________________________________________________________________________ 15
16-Bit Microcontrollers with
Infrared Module and Optional USB
Pin Description (continued)
PIN
NAME
FUNCTION
MAXQ612
TQFN-EP
MAXQ612
LQFP
MAXQ622
LQFP
General-Purpose, Digital, I/O, Type C Port. These port pins function as
bidirectional I/O pins. P2.0 to P2.3 default to three-state mode after a
reset. All alternate functions must be enabled from software. Enabling
the pin’s special function disables the general-purpose I/O on the pin.
The JTAG pins (P2.4 to P2.7) default to their JTAG function with weak
pullups enabled after a reset. The JTAG function can be disabled using
the TAP bit in the SC register.
P2.7 functions as the JTAG test-data output on reset and defaults to
an input with a weak pullup. The output function of the test data is only
enabled during the TAP’s shift_IR or shift_DR states.
P2.0–P2.7;
MOSI0,
MISO0,
SCLK0,
SSEL0,
11–14,
41–44
11–14,
41–44
8–11, 29–32
MAXQ612
TQFN-EP
MAXQ612 MAXQ622
SPECIAL
FUNCTION
PORT
LQFP
LQFP
TCK, TDI,
TMS, TDO
8
11
11
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
MOSI0
MISO0
SCLK0
9
12
12
10
11
29
30
31
32
13
13
14
14
SSEL0
TCK
TDI
41
41
42
42
43
43
TMS
TDO
44
44
General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable
Interrupt. These port pins function as bidirectional I/O pins or as inter-
rupts. All port pins default to three-state mode after a reset. All interrupt
functions must be enabled from software.
MAXQ612
TQFN
MAXQ612 MAXQ622
SPECIAL
FUNCTION
PORT
LQFP
LQFP
18
19
20
21
22
23
24
25
27
27
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
INT8
INT9
P3.0–P3.7;
INT8–INT15
18–25
27–34
27–34
28
28
29
29
INT10
INT11
INT12
INT13
INT14
INT15
30
30
31
31
32
32
33
33
34
34
16 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
Pin Description (continued)
PIN
NAME
FUNCTION
MAXQ612
TQFN-EP
MAXQ612
LQFP
MAXQ622
LQFP
General-Purpose, Digital, I/O, Type C Port. These port pins function as
bidirectional I/O pins. All port pins default to three-state mode after a
reset.
MAXQ612
TQFN-EP
MAXQ612 MAXQ622
SPECIAL
FUNCTION
PORT
LQFP
LQFP
—
—
—
—
—
—
—
—
55
55
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
—
—
—
—
—
—
—
—
—
55-62
55–62
P4.0–P4.7
56
56
57
57
58
58
59
59
60
60
61
61
62
62
General-Purpose, Digital, I/O, Type C Port. These port pins function as
bidirectional I/O pins. All port pins default to three-state mode after a
reset. All alternate functions must be enabled from software. Enabling
the pin’s special function disables the general-purpose I/O on the pin.
P5.0–P5.3;
MOSI1,
MISO1,
SCLK1,
SSEL1
MAXQ612
TQFN-EP
MAXQ612
LQFP
MAXQ622
LQFP
SPECIAL
FUNCTION
—
37–40
37–40
PORT
—
—
—
—
37
38
39
40
37
38
39
40
P5.0
P5.1
P5.2
P5.3
MOSI1
MISO1
SCLK1
SSEL1
NO CONNECTION PINS
16–21, 36,
46, 47
26, 27
36, 46, 47
N.C.
No Connection. Reserved for future use. Leave these pins unconnected.
for generating IR carrier frequencies and modulation. A
Detailed Description
high-current, 25mA, IR drive pin and output pins capable
of sinking up to 5mA support IR applications. It also
includes a USB slave interface compatible with existing
The MAXQ612/MAXQ622 provide integrated, low-cost
solutions that simplify the design of IR communications
equipment such as universal remote controls. Standard
features include the highly optimized, single-cycle,
MAXQ, 16-bit RISC core; 128KB of flash memory; 6KB
data RAM; soft stack; 16 general-purpose registers; and
three data pointers. The MAXQ core has the industry’s
best MIPS/mA rating, allowing developers to achieve
the same performance as competing microcontrollers at
substantially lower clock rates. Lower active-mode cur-
rent combined with the even lower MAXQ612/MAXQ622
stop-mode current results in increased battery life. IR
application-specific peripherals include flexible timers
2
host HID device drivers, I C, dual SPI, dual USARTs, up
to 56 general-purpose I/O pins ideal for keypad matrix
input, and a power-fail-detection circuit to notify.
Operating from DC to 12MHz, almost all instructions execute
in a single clock cycle (83.3ns at 12MHz), enabling nearly
12MIPS true-code operation. When active device opera-
tion is not required, an ultra-low-power stop mode can be
invoked from software, resulting in quiescent current con-
sumption of less than 300nA typical and 3FA maximum. The
combination of high-performance instructions and ultra-low
______________________________________________________________________________________ 17
16-Bit Microcontrollers with
Infrared Module and Optional USB
stop-mode current increases battery life over competing
microcontrollers. An integrated POR circuit with brownout
support resets the device to a known condition following a
power-up cycle or brownout condition. Additionally, a power-
fail warning flag is set, and a power-fail interrupt can be
generated when the system voltage falls below the power-
Memory is accessed through specific data-pointer regis-
ters with autoincrement/decrement support.
Memory
The microcontroller incorporates several memory types:
• 128KB program flash memory
• 6KB SRAM data memory
• 6KB utility ROM
fail warning voltage, V . The power-fail warning feature
PFW
allows the application to notify the user that the system sup-
ply is low and appropriate action should be taken.
• Soft stack
Microprocessor
Memory Protection
The optional memory-protection feature separates code
memory into three areas: system, user loader, and user
application. Code in the system area can be kept con-
fidential. Code in the user areas can be prevented from
reading and writing system code. The user loader can
also be protected from user application code.
The MAXQ612/MAXQ622 are based on Maxim’s MAXQ20
core, which is a low-power implementation of the new
16-bit MAXQ family of RISC cores. The core supports
the Harvard memory architecture with separate internal
16-bit program and data address buses. A fixed 16-bit
instruction word is standard, but data can be arranged
in 8 or 16 bits. The MAXQ core is a pipelined proces-
sor with performance approaching 1MIPS per MHz.
The 16-bit data path is implemented around register
modules, and each register module contributes specific
functions to the core. The accumulator module consists
of sixteen 16-bit registers and is tightly coupled with the
arithmetic logic unit (ALU). Program flow is supported by
a configurable soft stack.
Memory protection is implemented using privilege levels
for code. Each area has an associated privilege level.
RAM/ROM are assigned privilege levels as well. Refer to
the MAXQ622 User’s Guide for a more thorough expla-
nation of the topic.
Stack Memory
A 16-bit-wide internal stack provides storage for pro-
gram return addresses and can also be used for general-
purpose data storage. The stack is used automatically
by the processor when the CALL, RET, and RETI instruc-
tions are executed and when an interrupt is serviced. An
application can also store values in the stack explicitly
by using the PUSH, POP, and POPI instructions.
Execution of instructions is triggered by data transfer
between functional register modules or between a func-
tional register module and memory. Because data move-
ment involves only source and destination modules,
circuit switching activities are limited to active modules
only. For power-conscious applications, this approach
localizes power dissipation and minimizes switching
noise. The modular architecture also provides a maxi-
mum of flexibility and reusability that are important for a
microprocessor used in embedded applications.
On reset, the stack pointer, SP, initializes to the top of the
stack (BF0h). The CALL, PUSH, and interrupt-vectoring
operations decrement SP, then store a value at the loca-
tion pointed to by SP. The RET, RETI, POP, and POPI
operations retrieve the value at SP and then increment SP.
The MAXQ instruction set is highly orthogonal. All arith-
metical and logical operations can use any register
in conjunction with the accumulator. Data movement
is supported from any register to any other register.
Utility ROM
The utility ROM is a 6KB block of internal ROM memory
that defaults to a starting address of 8000h. The utility
Table 1. Memory Areas and Associated Maximum Privilege Levels
AREA
System
PAGE ADDRESS
0 to ULDR-1
ULDR to UAPP-1
UAPP to top
N/A
MAXIMUM PRIVILEGE LEVEL
High
Medium
Low
User Loader
User Application
Utility ROM
Other (RAM)
High
N/A
Low
18 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
ROM consists of subroutines that can be called from
application software. These include the following:
Watchdog Timer
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the applica-
tion software. If software is operating correctly, the coun-
ter is periodically reset and never reaches its maximum
count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
• In-system programming (bootstrap loader) using
JTAG interface
• In-circuit debug routines
• Test routines (internal memory tests, memory loader,
etc.)
• User-callable routines for in-application flash memory
programming and fast table lookup
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of system code, or to one of the special rou-
tines mentioned. Routines within the utility ROM are user
accessible and can be called as subroutines by the
application software. More information on the utility ROM
functions is contained in the MAXQ622 User’s Guide.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
15
24
Some applications require protection against unau-
thorized viewing of program code memory. For these
applications, access to in-system programming, in-
application programming, or in-circuit debugging func-
tions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses 0010h to 001Fh.
2
to 2 system clock cycles. An interrupt is gener-
ated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the pro-
grammed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires.
Three password locks protect three different program
memory segments. When the PWL is set to one (power-
on reset default) and the contents of the memory at
addresses 0010h to 001Fh are any value other than FFh
or 00h, the password is required to access the utility
ROM, including in-circuit debug and in-system program-
ming routines that allow reading or writing of internal
memory. When PWL is cleared to zero, these utilities are
fully accessible without password. The PWLS bit uses a
password that is at ULDR + 0010 to ULDR + 001F, and
the PWLL uses a password at UAPP + 0010 to UAPP +
001F. The password is automatically set to all ones fol-
lowing a mass erase.
IR Carrier Generation
and Modulation Timer
The dedicated IR timer/counter module simplifies low-
speed infrared (IR) communication. The IR timer imple-
ments two pins (IRTX and IRRX) for supporting IR
transmit and receive, respectively. The IRTX pin has no
corresponding port pin designation, so the standard
PD, PO, and PI port control status bits are not present.
However, the IRTX pin output can be manipulated high
or low using the PWCN.IRTXOUT and PWCN.IRTXOE
bits when the IR timer is not enabled (i.e., IREN = 0).
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (µs)
WD[1:0]
WATCHDOG CLOCK
WATCHDOG INTERRUPT TIMEOUT
15
00
01
10
11
Sysclk/2
2.7ms
21.9ms
174.7ms
1.4s
42.7
42.7
42.7
42.7
18
Sysclk/2
21
Sysclk/2
24
Sysclk/2
______________________________________________________________________________________ 19
16-Bit Microcontrollers with
Infrared Module and Optional USB
The IR timer is composed of a carrier generator and a
carrier modulator. The carrier generation module uses
the 16-bit IR carrier register (IRCA) to define the high
and low time of the carrier through the IR carrier high
byte (IRCAH) and IR carrier low byte (IRCAL). The carrier
modulator uses the IR data bit (IRDATA) and IR modula-
tor time register (IRMT) to determine whether the carrier
or the idle condition is present on IRTX.
condition, as defined by IRTXPOL, is output on the IRTX
pin during the next IRMT cycles.
The IR timer acts as a down counter in transmit mode. An
IR transmission starts when the IREN bit is set to 1 when
IRMODE = 1; when the IRMODE bit is set to 1 when IREN
= 1; or when IREN and IRMODE are both set to 1 in the
same instruction. The IRMT and IRCA registers, along
with the IRDATA and IRTXPOL bits, are sampled at the
beginning of the transmit process and every time the IR
timer value reload its value. When the IRV reaches 0000h
value, on the next carrier clock, it does the following:
Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of
the number of IR input clocks, whereas the IRCAL byte
defines the carrier low time.
1) Reloads IRV with IRMT.
IRDIV[1:0]
• IR Input Clock (f
) = f
/2
2) Samples IRCA, IRDATA, and IRTXPOL.
3) Generates IRTX accordingly.
4) Sets IRIF to 1.
IRCLK
SYS
• Carrier Frequency (f
) = f
/(IRCAH +
IRCLK
CARRIER
IRCAL + 2)
• Carrier High Time = IRCAH + 1
• Carrier Low Time = IRCAL + 1
5) Generates an interrupt to the CPU if enabled (IRIE = 1).
IR Transmit—Independent External Carrier
and Modulator Outputs
• Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for
each IRV downcount interval, and is sampled along with
the IRTXPOL and IRDATA bits at the beginning of each
new IRV downcount interval so that duty-cycle variation
and frequency shifting is possible from one interval to the
next. The starting/idle state and the carrier polarity of the
IRTX pin can be configured when the IR timer is enabled.
The normal transmit mode modulates the carrier based
upon the IRDATA bit. However, the user has the option
to input the modulator (envelope) on an external pin if
desired. The IRDATA bit is output directly to the IRTXM
pin (if IRTXPOL = 0) on each IRV downcount interval
boundary just as if it were being used to internally modu-
late the carrier frequency. If IRTXPOL = 1, the inverse
of the IRDATA bit is output to the IRTXM pin on the IRV
interval downcount boundaries. When the envelope
mode is enabled, it is possible to output either the modu-
lated (IRENV[1:0] = 01b) or unmodulated (INENV[1:0] =
10b) carrier to the IRTX pin.
IR Transmission
During IR transmission (IRMODE = 1), the carrier gen-
erator creates the appropriate carrier waveform, while
the carrier modulator performs the modulation. The car-
rier modulation can be performed as a function of carrier
cycles or IRCLK cycles dependent on the setting of the
IRCFME bit. When IRCFME = 0, the IRV down counter is
clocked by the carrier frequency and thus the modula-
tion is a function of carrier cycles. When IRCFME = 1, the
IRV down counter is clocked by IRCLK, allowing carrier
modulation timing with IRCLK resolution.
IR Receive
When configured in receive mode (IRMODE = 0), the
IR hardware supports the IRRX capture function. The
IRRXSEL[1:0] bits define which edge(s) of the IRRX pin
should trigger the IR timer capture function. Once started,
the IR timer (IRV) starts up counting from 0000h when a
qualified capture event as defined by IRRXSEL happens.
The IRV register is, by default, counting carrier cycles
as defined by the IRCA register. However, the IR carrier
frequency detect (IRCFME) allows clocking of the IRV
register directly with the IRCLK for finer resolution. When
IRCFME = 0, the IRCA defined carrier is counted by IRV.
When IRCFME = 1, the IRCLK clocks the IRV register.
The IRTXPOL bit defines the starting/idle state as well as
the carrier polarity for the IRTX pin. If IRTXPOL = 1, the
IRTX pin is set to a logic-high when the IR timer module is
enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low
when the IR timer is enabled.
A separate register bit, IR data (IRDATA), is used to
determine whether the carrier generator output is output
to the IRTX pin for the next IRMT carrier cycles. When
IRDATA = 1, the carrier waveform (or inversion of this
waveform if IRTXPOL = 1) is output on the IRTX pin dur-
ing the next IRMT cycles. When IRDATA = 0, the idle
On the next qualified event, it does the following:
1) Captures the IRRX pin state and transfers its value
to IRDATA. If a falling edge occurs, IRDATA = 0. If a
rising edge occurs, IRDATA = 1.
20 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
2) Transfers its current IRV value to the IRMT.
• 16-bit timer with capture
3) Resets IRV content to 0000h (if IRXRL = 1).
• 16-bit timer with compare
4) Continues counting again until the next qualified event.
• Input/output enhancements for pulse-width modulation
• Set/reset/toggle output state on comparator match
• Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
If the IR timer value rolls over from 0FFFFh to 0000h
before a qualified event happens, the IR timer overflow
(IROV) flag is set to 1 and an interrupt is generated, if
enabled. The IR module continues to operate in receive
mode until it is stopped by switching into transmit mode
or clearing IREN = 0.
General-Purpose I/O
The microcontroller provides port pins for general-pur-
pose I/O that have the following features:
Carrier Burst-Count Mode
A special mode reduces the CPU processing burden
when performing IR learning functions. Typically, when
operating in an IR learning capacity, some number of
carrier cycles are examined for frequency determination.
Once the frequency has been determined, the IR receive
function can be reduced to counting the number of car-
rier pulses in the burst and the duration of the combined
mark-space time within the burst. To simplify this pro-
cess, the receive burst-count mode can be used. When
RXBCNT = 0, the standard IR receive capture function-
ality is in place. When RXBCNT = 1, the IRV capture
operation is disabled and the interrupt flag associated
with the capture no longer denotes a capture. In the
carrier burst-count mode, the IRMT register only counts
qualified edges. The IRIF interrupt flag now sets if two
IRCA cycles elapse without getting a qualified edge. The
IRIF interrupt flag thus denotes absence of the carrier
and the beginning of a space in the receive signal. The
IRCFME bit is still used to define whether the IRV register
is counting system IRCLK clocks or IRCA-defined carrier
cycles. The IRXRL bit defines whether the IRV register
is reloaded with 0000h on detection of a qualified edge
(per the IRXSEL[1:0] bits).
• CMOS output drivers
• Schmitt trigger inputs
• Optional weak pullup to V
when operating in input
DD
mode
While the microcontroller is in a reset state, all port pins
become three-state with both weak pullups and input
buffers disabled, unless otherwise noted.
From a software perspective, each port appears as a
group of peripheral registers with unique addresses.
Special function pins can also be used as general-pur-
pose I/O pins when the special functions are disabled.
For a detailed description of the special functions avail-
able for each pin, refer to the IC-specific user’s guide,
e.g., the MAXQ622 User’s Guide describes all special
functions available on the MAXQ612/MAXQ622.
Serial Peripherals
The microcontroller supports two independent USARTs,
two SPI master/slave communications ports, and an I C
bus.
2
USART
The USART units are implemented with the following
characteristics:
16-Bit Timers/Counters
The microcontroller provides two general-purpose tim-
ers/counters that support the following functions:
• 2-wire interface
• Full-duplex operation for asynchronous data transfers
• Half-duplex operation for synchronous data transfers
• Programmable interrupt for receive and transmit
• Independent baud-rate generator
• 16-bit timer/counter
• 16-bit up/down autoreload
• Counter function of external pulse
Table 3. USART Mode Details
MODE
Mode 0
Mode 1
Mode 2
Mode 3
TYPE
START BITS
DATA BITS
STOP BITS
Synchronous
Asynchronous
Asynchronous
Asynchronous
N/A
1
8
N/A
1
8
1
8 + 1
8 + 1
1
1
1
______________________________________________________________________________________ 21
16-Bit Microcontrollers with
Infrared Module and Optional USB
• Programmable 9th bit parity support
by a USB host as a peripheral, characterized by the fol-
lowing endpoints:
• Start/stop bit support
• EP0: Bidirectional CONTROL endpoint with a 64-byte
Serial Peripheral Interface (SPI)
data storage.
The dual-integrated SPI interfaces provide independent
serial communication channels that communicate syn-
chronously with peripheral devices in a multiple master
or multiple slave system. The interface allows access to
a 4-wire, full-duplex serial bus, and can be operated in
either master mode or slave mode. Collision detection
is provided when two or more masters attempt a data
transfer at the same time.
• EP1-OUT: BULK (or INT) OUT endpoint. Double-
buffered 64 bytes data storage.
• EP2-IN: BULK (or INT) IN endpoint. Double-buffered
64 bytes data storage.
• EP3-IN: BULK (or INT) IN endpoint. Single-buffered 64
bytes data storage.
The choice to use EP1, EP2, and EP3 as BULK or
INTERRUPT endpoints is strictly a function of the end-
point descriptors that the USB controller returns to the
USB host during enumeration.
The maximum SPI master transfer rate is Sysclk/2. When
operating as an SPI slave, the MAXQ612/MAXQ622 can
support up to Sysclk/4 SPI transfer rate. Data is trans-
ferred as an 8-bit or 16-bit value, MSB first. In addition,
the SPI module supports configuration of an active SSEL
state through the slave active select. Separate pins and
registers are used to differentiate between the two SPI ports.
The USB controller communicates to a total of 384
bytes of endpoint data memory (2 x 64 bytes for each
data moving endpoint EP1 and EP2), 64 bytes for the
CONTROL endpoint, and 64 bytes for endpoint EP3.
2
I C Bus
Double-buffering EP1 and EP2 improves throughput by
allowing the CPU to read or load the next packet while
the USB controller is moving the current packet over
USB. EP3-IN is intended to serve as a large interrupt
endpoint for various USB class specifications such as
the Still Image Capture Device. It can also be used as a
second BULK IN endpoint.
2
The microcontroller integrates an internal I C bus mas-
ter/slave for communication with a wide variety of other
2
2
I C–enabled peripherals. The I C bus is a 2-wire, bidi-
rectional bus using two bus lines—the serial data line
(SDA) and the serial clock line (SCL)—and a ground line.
Both the SDA and SDL lines must be driven as open-
collector/drain outputs. External resistors are required as
shown in Figure 1 to pull the lines to a logic-high state.
On-Chip Oscillator
An external quartz crystal or a ceramic resonator can be
connected between HFXIN and HFXOUT, as illustrated
in Figure 3.
The device supports both the master and slave proto-
cols. In the master mode, the device has ownership of
2
the I C bus, drives the clock, and generates the START
and STOP signals. This allows it to send data to a slave
or receive data from a slave as required. In slave mode,
the device relies on an externally generated clock to
drive SCL and responds to data and commands only
To operate the core from an external clock, connect the
clock source to the HFXIN pin and connect the HFXOUT
2
when requested by the I C master device.
V
DD
USB Controller (MAXQ622 Only)
HFXIN
CLOCK CIRCUIT
STOP
The integrated USB controller is compliant with the USB
2.0 specification, providing full-speed operation with the
newest generation of USB peripherals. The USB con-
troller functions as a full-speed USB peripheral device.
Integrating the USB physical interface (PHY) allows
direct connection to the USB cable, reducing board
space and overall system cost. A system interrupt can
be enabled to signal that the USB needs to be serviced.
The CPU communicates to the USB controller module
through the SFR interface. The microcontroller is seen
R
F
HFXOUT
R = 1MI Q50%
C1 = C2 = 12pF
F
C1
C2
Figure 3. On-Chip Oscillator
22 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
pin to GND. The clock source should be driven through
a CMOS driver. If the clock driver is a TTL gate, its output
must be connected to V through a pullup resistor to
ensure a satisfactory logic level for active clock pulses.
To minimize system noise on the clock circuitry, the
external clock source must meet the maximum rise and
fall times and the minimum high and low times specified
for the clock source. The external noise can affect the
clock generation circuit if these parameters do not meet
the specification.
In-Application Flash Programming
From user-application code, flash memory can be pro-
grammed using the ROM utility functions from either C
or assembly language. The function declarations below
show examples of some of the ROM utility functions
provided for in-application flash memory programming:
DD
/* Write one 16-bit word to code address ‘dest’.
* Dest must be aligned to 16 bits.
* Returns 0 = failure, 1 = OK.
*/
Noise at HFXIN and HFXOUT can adversely affect on-
chip clock timing. It is good design practice to place
the crystal and capacitors as near the oscillator circuitry
as possible with a direct short trace. The typical values
of external capacitors vary with the type of crystal to be
used.
int flash_write (uint16_t dest, uint16_t data);
To erase, the following function would be used:
/* Erase the given Flash page
* addr: Flash offset (anywhere within page)
*/
ROM Loader
The ROM loader loads program memory and config-
ures loader-specific configuration features. To increase
the security of the system, the loader denies access to
the system, user loader, or user-application memories
unless an area-specific password is provided.
int flash_erasepage(uint16_t addr);
The in-application flash memory programming must call
ROM utility functions to erase and program any of the
flash memory. Memory protection is enforced by the
ROM utility functions.
Loading Flash Memory
In-Circuit Debug and JTAG
Interface
An internal bootstrap loader allows reloading over a
simple JTAG interface. As a result, software can be
upgraded in-system, eliminating the need for a costly
hardware retrofit when updates are required. Remote
software uploads are possible that enable physically
inaccessible applications to be frequently updated. The
interface hardware can be a JTAG connection to another
microcontroller, or a connection to a PC serial port using
a USB-to-JTAG converter such as the MAXQUSBJTAG-
KIT#, available from Maxim. If in-system programmabil-
ity is not required, a commercial gang programmer can
be used for mass programming. Activating the JTAG
interface and loading the test access port (TAP) with the
system programming instruction invokes the bootstrap
loader. Setting the SPE bit to one during reset through
the JTAG interface executes the bootstrap-loader mode
program that resides in the utility ROM. When program-
ming is complete, the bootstrap loader can clear the SPE
bit and reset the device, allowing the device to bypass
the utility ROM and begin execution of the application
software.
Embedded debug hardware and software are devel-
oped and integrated to provide full in-circuit debugging
capability in a user-application environment. These hard-
ware and software features include the following:
• Debug engine
• Set of registers providing the ability to set breakpoints
on register, code, or data using debug service rou-
tines stored in ROM
Collectively, these hardware and software features sup-
port two modes of in-circuit debug functionality:
• Background mode:
CPU is executing the normal user program
Allows the host to configure and set up the in-circuit
debugger
• Debug mode:
Debugger takes over the control of the CPU
Read/write accesses to internal registers and memory
Single-step of the CPU for trace operation
In addition, the ROM loader also enforces the memory-
protection policies. Passwords that are 16 words are
required to access the ROM loader interface.
The interface to the debug engine is the TAP control-
ler. The interface allows for communication with a bus
______________________________________________________________________________________ 23
16-Bit Microcontrollers with
Infrared Module and Optional USB
then (V
= V
)
DDIO
DDB
else (V
= V )
DD
DDIO
This means that if there is a power-fail event on V
and
DD
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
the device is not powered from V
, it causes a power-
BUS
MAXQ612
MAXQ622
fail interrupt (PFI) if enabled. If the device is powered by
and there is a supply on V , then no power-fail
V
BUS
DD
event is triggered. If the device is powered by V
BUS
and there is no supply on V
and V
fails, the chip
DD
BUS
CPU
attempts to switch to V , detects a power-fail event,
and a PFI occurs. Some specific examples are given
below:
DD
DEBUG
ENGINE
TMS
TCK
TDI
CONTROL
BREAKPOINT
ADDRESS
DATA
TAP
CONTROLLER
• Case 1: The device is powered from V
and
DD
the batteries are removed. Power decays until the
power-fail-reset trip point is hit, then the part goes into
low-power mode.
TDO
• Case 2: The device is set to be powered from V
DD
Figure 4. In-Circuit Debugger
only, it is connected to USB, and the batteries are
removed. Response is identical to Case 1.
master that can either be automatic test equipment or a
component that interfaces to a higher level test bus as
part of a complete system. The communication operates
across a 4-wire serial interface from a dedicated TAP
that is compatible with the JTAG IEEE Standard 1149.
The TAP provides an independent serial channel to com-
municate synchronously with the host system.
• Case 3: The device is set to be powered from either
V
DD
or V
, it is connected to USB, and the bat-
BUS
teries are removed. Because the part is already
powered from V , nothing changes. If the USB
BUS
port is subsequently disconnected, power switches
over to V , the supply decays to the power-fail-reset
DD
trip point, and the part goes into low-power mode. As
long as there is sufficient charge on the V
capacitor, it supports the part in power-fail. The hold-
up time is similar to the MAXQ610 since the USB
bypass
DD
To prevent unauthorized access of the protected memo-
ry regions through the JTAG interface, the debug engine
prevents modification of the privilege registers and
disallows all access to system memory, unless memory
protection is disabled. In addition, all services (such as
register display or modification) are denied when code
is executing inside the system area.
port is powered only by V
. Note that if the part is
BUS
powered from V
for a long time (V
and no battery has been present
= 0), then upon USB port discon-
BUS
DD
nection, the power collapses to ground in less than a
second.
Operating Modes
Power-Supply Selection
Stop Mode
The lowest power mode of operation is stop mode. In this
mode, CPU state and memories are preserved, but the
CPU is not actively running. Wake-up sources include
external I/O interrupts, the power-fail warning interrupt,
wake-up timer, or a power-fail reset. Any time the micro-
controller is in a state where code does not need to be
executed, the user software can put the microcontroller
into stop mode. The nanopower ring oscillator is an inter-
nal ultra-low-power (400nA) 8kHz ring oscillator that can
be used to drive a wake-up timer that exits stop mode.
The wake-up timer is programmable by software in steps
of 125Fs up to approximately 8s.
For maximum flexibility the microcontroller can be pow-
ered by either the USB (V
) or V . When a USB
BUS
DD
connection is made to a valid V
power source, an
BUS
internal voltage regulator generates a 3.3V supply volt-
age. When the internal voltage is at an adequate level, it
automatically powers itself from the USB supply. This is
especially beneficial in systems where the V
supply is
DD
from a battery. In either case, the chip is fully functional
when operating from either the battery or the V
.
BUS
The power monitor is attached to the switched supply,
V
V
. This supply is equivalent to the higher of V
or
DDIO
DD
DDB
The power-fail monitor is always on during normal opera-
tion. However, it can be selectively disabled during stop
. This can be expressed as follows:
If (V
> 3.0V or V
> V )
DD
DDB
DDB
24 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
Power-Fail Warning
The power-fail monitor can assert an interrupt if the volt-
age falls below a configurable threshold between the
operating voltage and the reset voltage. This, if enabled,
can allow the firmware to perform housekeeping tasks if
the voltage level decays below the warning threshold.
The power-fail threshold value should only be changed
when the power-fail warning interrupt is disabled (CKCN.
PFIE = 0) to prevent unintended triggering of the power-
fail warning condition.
Table 4. Power-Fail Warning Level Selection
PFW THRESHOLD
PWCN.PFWARNCN[1:0]
(V)
00
01
10
11
1.8
1.9
2.55
2.75
mode to minimize power consumption. This feature is
enabled using the power-fail monitor disable (PFD) bit
in the PWCN register. The reset default state for the PFD
bit is 1, which disables the power-fail monitor function
during stop mode. If power-fail monitoring is disabled
(PFD = 1) during stop mode, the circuitry responsible
for generating a power-fail warning or reset is shut down
The power-fail warning threshold is reset to 1.8V by a
POR and is not affected by other resets. See Table 4.
Power-Fail Detection
Figures 5, 6, and 7 show the power-fail detection and
response during normal and stop-mode operation.
If a reset is caused by a power-fail, the power-fail monitor
can be set to one of the following intervals:
and neither condition is detected. Thus, the V
< V
DD
RST
condition does not invoke a reset state. However, in the
event that V falls below the POR level, a POR is gen-
• Always on—continuous monitoring
DD
11
erated. The power-fail monitor is enabled prior to stop
mode exit and before code execution begins. If a power-
• 2 nanopower ring oscillator clocks (~256ms)
12
• 2 nanopower ring oscillator clocks (~512ms)
fail warning condition (V
< V ) is then detected,
PFW
DD
13
• 2 nanopower ring oscillator clocks (~1.024s)
the power-fail interrupt flag is set on stop mode exit. If a
power-fail reset condition is detected (V
CPU goes into reset.
< V
), the
RST
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
DD
V
DD
t < t
PFW
t ≥ t
t ≥ t
t ≥ t
PFW
PFW
PFW
C
V
PFW
G
V
RST
E
H
F
B
D
V
POR
I
A
INTERNAL RESET
(ACTIVE HIGH)
Figure 5. Power-Fail Detection During Normal Operation
______________________________________________________________________________________ 25
16-Bit Microcontrollers with
Infrared Module and Optional USB
Table 5. Power-Fail Detection States During Normal Operation
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
A
On
Off
On
Off
On
—
—
V
V
< V
.
DD
POR
< V
< V
.
POR
DD
RST
B
On
Crystal warmup time, t
CPU held in reset.
.
XTAL_RDY
V
> V
.
DD
RST
C
D
On
On
On
On
On
On
—
—
CPU normal operation.
Power drop too short.
Power-fail not detected.
V
RST
< V
< V
.
DD
PFW
PFI is set when V
< V
< V
and
RST
DD
PFW
maintains this state for at least t
which time a power-fail interrupt is gener-
ated (if enabled).
, at
PFW
E
On
On
On
—
CPU continues normal operation.
V
POR
< V
< V
.
DD
RST
On
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
F
Off
On
Off
On
Yes
—
(Periodically)
V
DD
> V
.
RST
Crystal warmup time, t
CPU resumes normal operation from
8000h.
.
XTAL_RDY
G
On
V
POR
< V
< V
.
DD
RST
On
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
H
I
Off
Off
Off
Off
Yes
—
(Periodically)
V
DD
< V
.
POR
Off
Device held in reset. No operation allowed.
nanopower ring-oscillator cycles. If V
> V
during
RST
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the CPU
exits the reset state in less than 20 crystal cycles after
the reset source is removed.
DD
detection, V
is monitored for an additional nanopower
DD
ring-oscillator period. If V
remains above V
for
DD
RST
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
26 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
V
DD
t < t
PFW
t ≥ t
t ≥ t
PFW
PFW
A
V
PFW
D
V
RST
B
C
E
V
POR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
Figure 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
Application enters stop mode.
A
B
On
On
Off
Off
Off
Off
Yes
Yes
V
> V
.
DD
RST
CPU in stop mode.
Power drop too short.
Power-fail not detected.
V
RST
< V
< V
.
DD
PFW
Power-fail warning detected.
Turn on regulator and crystal.
C
D
On
On
On
Off
On
Off
Yes
Yes
Crystal warmup time, t
Exit stop mode.
.
XTAL_RDY
Application enters stop mode.
> V
V
DD
.
RST
CPU in stop mode.
< V < V .
RST
V
POR
DD
On
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
E
F
Off
Off
Off
Off
Yes
—
(Periodically)
V
DD
< V
.
POR
Off
Device held in reset. No operation allowed.
______________________________________________________________________________________ 27
16-Bit Microcontrollers with
Infrared Module and Optional USB
V
DD
A
D
V
PFW
B
V
RST
C
E
V
POR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
INTERRUPT
Figure 7. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
Application enters stop mode.
A
Off
Off
Off
Off
Off
Yes
Yes
V
> V
.
DD
RST
CPU in stop mode.
V
DD
< V .
PFW
B
C
Off
On
Power-fail not detected because power-fail
monitor is disabled.
V
RST
< V
< V
.
DD
PFW
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail warning, and sets the power-fail
interrupt flag.
On
On
Yes
Turn on regulator and crystal.
Crystal warmup time, t
.
XTAL_RDY
On stop mode exit, CPU vectors to the
higher priority of power-fail and the inter-
rupt that causes stop mode exit.
28 _____________________________________________________________________________________
16-Bit Microcontrollers with
Infrared Module and Optional USB
Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
(continued)
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
Application enters stop mode.
D
Off
Off
Off
Yes
V
DD
> V
.
RST
CPU in stop mode.
< V < V .
RST
V
POR
DD
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail, and puts CPU in reset.
Power-fail monitor is turned on periodically.
On
E
F
Off
Off
Off
Off
Yes
—
(Periodically)
V
DD
< V
.
POR
Off
Device held in reset. No operation allowed.
purpose I/O pins. Negative voltage spikes on power pins
are especially problematic as they directly couple to the
internal power buses. Devices such as keypads can
conduct electrostatic discharges directly into the micro-
controller and seriously damage the device. System
designers must protect components against these tran-
sients that can corrupt system memory.
Applications Information
The low-power, high-performance RISC architecture of
this device makes it an excellent fit for many portable
or battery-powered applications. It is ideally suited for
applications such as universal remote controls that
require the cost-effective integration of IR transmit/
receive capability.
Additional Documentation
Grounds and Bypassing
Careful PCB layout significantly minimizes system-level
digital noise that could interact with the microcontroller
or peripheral components. The use of multilayer boards
is essential to allow the use of dedicated power planes.
The area under any digital components should be a con-
tinuous ground plane if possible. Keep bypass capacitor
leads short for best noise rejection and place the capaci-
tors as close to the leads of the devices as possible.
Designers must have the following documents to fully
use all the features of this device. This data sheet
contains pin descriptions, feature overviews, and elec-
trical specifications. Errata sheets contain deviations
from published specifications. The user’s guides offer
detailed information about device features and opera-
tion. The following documents can be downloaded from
www.maxim-ic.com/microcontrollers.
CMOS design guidelines for any semiconductor require
• This MAXQ612/MAXQ622 data sheet, which contains
that no pin be taken above V
or below GND. Violation
DD
electrical/timing specifications and pin descriptions.
of this guideline can result in a hard failure (damage to
the silicon inside the device) or a soft failure (uninten-
tional modification of memory contents). Voltage spikes
above or below the device’s absolute maximum ratings
can potentially cause a devastating IC latchup.
• TheMAXQ612/MAXQ622revision-specificerratasheet
(www.maxim-ic.com/errata).
• The MAXQ622 User’s Guide, which contains detailed
information on features and operation, including pro-
gramming.
Microcontrollers commonly experience negative volt-
age spikes through either their power pins or general-
______________________________________________________________________________________ 29
16-Bit Microcontrollers with
Infrared Module and Optional USB
Block Diagram
MAXQ612/MAXQ622
16-BIT MAXQ
RISC CPU
IR DRIVER
IR TIMER
2x SPI
REGULATOR
VOLTAGE
MONITOR
6KB ROM
SECURE MMU
128KB FLASH
6KB SRAM
CLOCK
GPIO
WATCHDOG
2x USART
USB SIE*
TXCVR
2x
8kHz NANO
RING
2
I C
16-BIT TIMER
*MAXQ622 ONLY.
Development and
Technical Support
Maxim and third-party suppliers provide a variety of
highly versatile, affordably priced development tools for
this microcontroller, including the following:
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
• Compilers
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
• In-circuit emulators
64 LQFP
C64+5
21-0083
21-0144
44 TQFN-EP
T4477+2
• Integrated Development Environments (IDEs)
• JTAG-to-serial converters for programming and
debugging
A partial list of development tool vendors can be found
at www.maxim-ic.com/MAXQ_tools.
For technical support, go to https://support.maxim-ic.
com/micro.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
30
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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