MCP3428-EMF_技术文档

MCP3426/7/8

16-Bit, Multi-Channel ΔΣ Analog-to-Digital Converter with

I²C™ Interface and On-Board Reference

Features

Description

• 16-bit ΔΣ ADC with Differential Inputs:

- 2 channels: MCP3426 and MCP3427

- 4 channels: MCP3428

The MCP3426, MCP3427 and MCP3428 devices

(MCP3426/7/8) are the low noise and high accuracy

16 Bit Delta-Sigma Analog-to-Digital (ΔΣ A/D) Con-

verter family members of the MCP342X series from

Microchip Technology Inc. These devices can convert

analog inputs to digital codes with up to 16 bits of reso-

lution.

• Differential Input Full Scale Range: -V_REFto

+V_REF

• Self Calibration of Internal Offset and Gain per

Each Conversion

The MCP3426 and MCP3427 devices have two

differential input channels and the MCP3428 has four

differential input channels. All electrical properties of

these three devices are the same except the

differences in the number of input channels and I²C

address bit selection options.

• On-Board Voltage Reference (V_REF):

- Accuracy: 2.048V ± 0.05%

- Drift: 15 ppm/°C

• On-Board Programmable Gain Amplifier (PGA):

- Gains of 1,2, 4 or 8

These devices can output analog-to-digital conversion

results at rates of 15 (16-bit mode), 60 (14-bit mode), or

240 (12-bit mode) samples per second depending on

the user controllable configuration bit settings using the

two-wire I²C serial interface. During each conversion,

the device calibrates offset and gain errors

automatically. This provides accurate conversion

results from conversion to conversion over variations in

temperature and power supply fluctuation.

• INL: 10 ppm of Full Scale Range

• Programmable Data Rate Options:

- 15 SPS (16 bits)

- 60 SPS (14 bits)

- 240 SPS (12 bits)

• One-Shot or Continuous Conversion Options

• Low Current Consumption (V_DD= 3V):

- Continuous Conversion: 135 µA typical

The device has an on-board 2.048V reference voltage,

which enables an input range of ± 2.048V differentially

(full scale range = 4.096/PGA).

- One-Shot Conversion with 1 SPS:

- 9 µA typical for 16 bit mode

- 2.25 µA typical for 14 bit mode

- 0.56 µA typical for 12 bit mode

The user can select the gain of the on-board

programmable gain amplifier (PGA) using the

configuration register bits (gain of x1, x2, x4, or x8).

This allows the MCP3426/7/8 devices to convert a very

weak input signal with high resolution.

• On-Board Oscillator

• I²C^™Interface:

- Standard, Fast and High Speed Modes

- User configurable two external address

selection pins for MCP3427 and MCP3428

The MCP3426/7/8 devices have two conversion

modes: (a) One-Shot Conversion mode and

(b) Continuous Conversion mode. In the One-Shot

conversion mode, the device performs a single

• Single Supply Operation: 2.7V to 5.5V

• Extended Temperature Range: -40°C to +125°C

conversion and enters

a

low current standby

Typical Applications

(shutdown) mode automatically until it receives another

conversion command. This reduces current

consumption greatly during idle periods. In continuous

conversion mode, the conversion takes place

continuously at the configured conversion speed. The

device updates its output buffer with the most recent

conversion data.

• Portable Instrumentation and Consumer Goods

• Temperature Sensing with RTD, Thermistor, and

Thermocouple

• Bridge Sensing for Pressure, Strain, and Force

• Weigh Scales and Battery Fuel Gauges

• Factory Automation Equipment

The devices operate from a single 2.7V to 5.5V power

supply and have a two-wire I²C compatible serial

interface for a standard (100 kHz), fast (400 kHz), or

high-speed (3.4 MHz) mode.

DS22226A-page 1

MCP3426/7/8

The I²C address bits for the MCP3427 and MCP3428

are selected by using two external I²C address

selection pins (Adr0 and Adr1). The user can configure

the device to one of eight available addresses by

The MCP3426 is available in 8-pin SOIC, DFN, and

MSOP packages. The MCP3427 is available in 10-pin

DFN, and MSOP packages. The MCP3428 is available

in 14-pin SOIC and TSSOP packages.

connecting these two address selection pins to V_DD

V

,

_SSor float. The I²C address bits of the MCP3426 are

programmed at the factory during production.

Package Types

MSOP, SOIC

MSOP

SOIC, TSSOP

14

CH1+

CH1-

1

2

3

4

5

6

7

CH1+

CH4-

10

9

Adr1

1

2

3

4

5

CH1+

CH1-

8

CH2-

1

CH1-

13

12

Adr0

SCL

SDA

CH4+

CH3-

7

6

5

CH2+

2

3

4

8

V

SS

CH2+

CH2-

V

DD

SS

CH2+

CH2-

7

6

SCL

11

10

SDA

CH3+

Adr1

V

DD

V

SS

9

8

V

Adr0

SCL

DD

SDA

MCP3426

2x3 DFN *

MCP3427

3x3 DFN *

CH1+

CH1-

CH2-

CH1+

CH1-

Adr1

1

2

8

7

1

10

9

CH2+

Adr0

2

EP

9

EP

11

V_DD

V_SS

V

SCL

SDA

V_DD

3

4

6

5

3

4

5

8

7

6

SS

SDA

SCL

CH2+

CH2-

* Includes Exposed Thermal Pad (EP); see Table 3-1.

MCP3426 Functional Block Diagram

V_DD

V_SS

Voltage Reference

(2.048V)

MCP3426

V_REF

CH1+

SCL

SDA

I²C

Interface

ΔΣ ADC

Converter

CH1-

CH2+

CH2-

PGA

Gain = 1, 2, 4, or 8

Clock

Oscillator

DS22226A-page 2

MCP3426/7/8

MCP3427 Functional Block Diagram

V_DD

V_SS

MCP3427

Adr1

Adr0

Voltage Reference

(2.048V)

V_REF

CH1+

SCL

I²C

ΔΣ ADC

Converter

CH1-

PGA

Interface

SDA

CH2+

CH2-

Gain = 1, 2, 4, or 8

Clock

Oscillator

MCP3428 Functional Block Diagram

V_DD

V_SS

MCP3428

CH1+

Adr1

Adr0

Voltage Reference

(2.048V)

CH1-

V_REF

CH2+

SCL

SDA

I²C

CH2-

ΔΣ ADC

Converter

PGA

Interface

CH3+

CH3-

Gain = 1, 2, 4, or 8

Clock

Oscillator

CH4+

CH4-

DS22226A-page 3

MCP3426/7/8

NOTES:

DS22226A-page 4

MCP3426/7/8

†Notice: Stresses above those listed under “Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings†

V_DD...................................................................................7.0V

All inputs and outputs ............. ..........V_SS–0.4V to V_DD+0.4V

Differential Input Voltage ...................................... |V_DD- V_SS

|

Output Short Circuit Current ................................Continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±10 mA

Storage Temperature ....................................-65°C to +150°C

Ambient Temp. with power applied ...............-55°C to +125°C

ESD protection on all pins ................ ≥ 6 kV HBM, ≥ 400V MM

Maximum Junction Temperature (T_J)..........................+150°C

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, all parameters apply for T_A= -40°C to +85°C, V_DD= +5.0V, V_SS= 0V,

CHn+ = CHn- = V_REF/2, V_INCOM= V_REF/2. All ppm units use 2*V_REFas differential full scale range.

Parameters

Analog Inputs

Sym

Min

Typ

Max

Units

Conditions

Differential Full Scale Input

Voltage Range

FSR

—

±2.048/PGA

—

V

V_IN= [CHn+ - CHn-]

Maximum Input Voltage Range

Differential Input Impedance

V_SS-0.3

—

V_DD+0.3

—

V

(Note 1)

Z_IND(f)

Z_INC(f)

2.25/PGA

MΩ

During normal mode operation

(Note 2)

Common Mode input

Impedance

—

25

—

MΩ

PGA = 1, 2, 4, 8

System Performance

Resolution and No Missing

Codes

(Effective Number of Bits)

(Note 3)

12

14

16

—

Bits

DR = 240 SPS

DR = 60 SPS

DR = 15 SPS

Data Rate

(Note 4)

DR

176

44

11

240

60

328

82

SPS

12 bits mode

14 bits mode

16 bits mode

15

20.5

—

Output Noise

—

2.5

µV_RMST_A= +25°C, DR =15 SPS,

PGA = 1, V_IN+ = V_IN- = GND

Integral Non-Linearity

INL

—

10

—

ppm of DR = 15 SPS

FSR

(Note 5)

Internal Reference Voltage

Gain Error (Note 6)

V_REF

—

2.048

0.1

—

V

%

PGA = 1, DR = 15 SPS

PGA Gain Error Match (Note 6)

Gain Error Drift (Note 6)

0.1

%

Between any 2 PGA settings

15

ppm/°C PGA=1, DR=15 SPS

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

This parameter is ensured by characterization and not 100% tested.

2: This input impedance is due to 3.2 pF internal input sampling capacitor.

3: This parameter is ensured by design and not 100% tested.

4: The total conversion speed includes auto-calibration of offset and gain.

5: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

6: Includes all errors from on-board PGA and V_REF

.

7: This parameter is ensured by characterization and not 100% tested.

8: MCP3427 and MCP3428 only.

9: Addr_Float voltage is applied at address pin.

10: No voltage is applied at address pin (left “floating”).

DS22226A-page 5

MCP3426/7/8

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for T_A= -40°C to +85°C, V_DD= +5.0V, V_SS= 0V,

CHn+ = CHn- = V_REF/2, V_INCOM= V_REF/2. All ppm units use 2*V_REFas differential full scale range.

Parameters

Offset Error

Sym

Min

Typ

Max

Units

Conditions

V_OS

—

30

—

µV

PGA = 1

DR = 15 SPS

Offset Drift vs. Temperature

Common-Mode Rejection

—

50

105

110

5

—

nV/°C

dB

at DC and PGA =1,

dB

at DC and PGA =8, T_A= +25°C

Gain vs. V_DD

ppm/V T_A= +25°C, V_DD= 2.7V to 5.5V,

PGA = 1

Power Supply Rejection at DC

Input

—

100

—

dB

T_A= +25°C, V_DD= 2.7V to 5.5V,

PGA = 1

Power Requirements

Voltage Range

V_DD

I_DDA

2.7

—

5.5

180

—

V

Supply Current during

Conversion

145

135

0.3

µA

V_DD= 5.0V

V_DD= 3.0V

V_DD= 5.0V

Supply Current during Standby

Mode

I_DDS

1

I²C Digital Inputs and Digital Outputs

High level input voltage

Low level input voltage

Low level output voltage

V_IH

0.7V_DD

—

V_DD

0.3V_DD

0.4

V

at SDA and SCL pins

I_OL= 3 mA

V_IL

V_OL

—

Hysteresis of Schmidt Trigger

V_HYST

0.05V_DD

—

f_SCL= 100 kHz

for inputs (Note 7)

Supply Current when I²C bus

line is active

I_DDB

—

10

µA

Device is in standby mode while

I²C bus is active

Input Leakage Current

I_ILH

I_ILL

Logic Status of I²C Address Pins (Note 8)

—

-1

—

1

µA

V_IH= 5.5V

V_IL= GND

—

Adr0 and Adr1 Pins

Addr_Low

V_SS

—

0.2V_DD

V_DD

V

The device reads logic low.

The device reads logic high.

Addr_High 0.75V_DD

Addr_Float 0.35V_DD

0.6V_DD

Read pin voltage if voltage is

applied to the address pin.

(Note 9)

—

V

_DD/2

—

Device outputs float output

voltage (V_DD/2) on the address

pin, if left “floating”. (Note 10)

Pin Capacitance and I²C Bus Capacitance

Pin capacitance

I²C Bus Capacitance

C_PIN

C_b

—

4

10

pF

—

400

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

This parameter is ensured by characterization and not 100% tested.

2: This input impedance is due to 3.2 pF internal input sampling capacitor.

3: This parameter is ensured by design and not 100% tested.

4: The total conversion speed includes auto-calibration of offset and gain.

5: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

6: Includes all errors from on-board PGA and V_REF

.

7: This parameter is ensured by characterization and not 100% tested.

8: MCP3427 and MCP3428 only.

9: Addr_Float voltage is applied at address pin.

10: No voltage is applied at address pin (left “floating”).

DS22226A-page 6

MCP3426/7/8

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T_A= -40°C to +125°C, V_DD= +5.0V, V_SS= 0V.

Parameters

Temperature Ranges

Sym

Min

Typ

Max

Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+85

+125

+150

°C

Thermal Package Resistances

Thermal Resistance, 8L-DFN (2x3)

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 10L-DFN (3x3)

Thermal Resistance, 10L-MSOP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

θ_JA

—

84.5

211

—

°C/W

149.5

57

202

120

100

DS22226A-page 7

MCP3426/7/8

NOTES:

DS22226A-page 8

MCP3426/7/8

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= -40°C to +85°C, V_DD= +5.0V, V_SS= 0V, CHn+ = CHn- = V_REF/2,

V_INCOM= V_REF/2.

0.005

0.004

0.003

0.002

0.001

0

12

10

8

PGA = 1

PGA = 2

6

PGA = 4

PGA = 8

4

PGA = 4

2

PGA = 2

3.5

PGA = 8

0

2.5

3

4

4.5

5

5.5

-100 -75 -50 -25

0

25

50

75 100

Input Signal (% of FSR)

V

_DD(V)

FIGURE 2-1:

(V ).

INL vs. Supply Voltage

FIGURE 2-4:

Voltage.

Output Noise vs. Input

DD

0.005

2

1.5

1

T_A= +25°C

PGA = 1

PGA = 8

0.004

0.003

0.002

0.001

0

0.5

0

2.7V

PGA = 4

-0.5

-1

PGA = 2

-1.5

-2

5V

-60 -40 -20

0

20 40 60 80 100 120 140

-100 -75 -50 -25

0

25

50

75 100

Temperature (^oC)

Input Voltage (% of Full-Scale)

FIGURE 2-2:

INL vs. Temperature.

FIGURE 2-5:

Total Error vs. Input Voltage.

0.2

0.1

20

15

10

5

V_DD= 5V

PGA = 8

PGA = 4

PGA = 8

0

PGA = 1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

0

-5

-10

-15

PGA = 2

PGA = 1

-20

-25

PGA = 4

-40 -20

0

20 40 60 80 100 120 140

Temperature (^oC)

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

FIGURE 2-3:

Offset Error vs.

FIGURE 2-6:

Gain Error vs. Temperature.

Temperature.

DS22226A-page 9

MCP3426/7/8

Note: Unless otherwise indicated, T_A= -40°C to +85°C, V_DD= +5.0V, V_SS= 0V, CHn+ = CHn- = V_REF/2,

V_INCOM= V_REF/2.

5

4

200

180

160

140

120

100

80

V_DD= 5.5V

3

2

V_DD= 2.7V

1

V_DD= 5.0V

0

V_DD= 5.0V

60

-1

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

FIGURE 2-7:

I

vs. Temperature.

FIGURE 2-10:

Oscillator Drift vs.

DDA

Temperature.

0

-10

-20

-30

-40

-50

-60

-70

-80

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Data Rate = 15 SPS

V_DD= 5.5V

V_DD= 5.0V

-90

-100

-110

-120

V_DD= 2.7V

1k

1000

10k

10000

0.1

1

10

100

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

Input Signal Frequency (Hz)

FIGURE 2-8:

I

vs. Temperature.

FIGURE 2-11:

Frequency Response.

DDS

14

V_DD= 5.5V

12

10

8

V_DD= 5.0V

V_DD= 4.5V

6

4

V_DD= 2.7V

2

0

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

FIGURE 2-9:

I

vs. Temperature.

DDB

DS22226A-page 10

MCP3426/7/8

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

MCP3426

PIN FUNCTION TABLE

MCP3427 MCP3428

Sym

Function

MSOP,

SOIC

SOIC,

TSSOP

DFN

MSOP

1

2

1

2

1

2

1

2

1

2

CH1+

CH1-

CH2+

CH2-

V_SS

Positive Differential Analog Input Pin of Channel 1

Negative Differential Analog Input Pin of Channel 1

Positive Differential Analog Input Pin of Channel 2

Negative Differential Analog Input Pin of Channel 2

Ground Pin

7

4

3

8

5

4

6

3

5

3

6

V_DD

Positive Supply Voltage Pin

4

7

SDA

SCL

Bidirectional Serial Data Pin of the I²C Interface

Serial Clock Pin of the I²C Interface

5

8

—

9

—

9

Adr0

Adr1

CH3+

CH3-

CH4+

CH4-

EP

I²C Address Selection Pin. See Section 5.3.2.

Positive Differential Analog Input Pin of Channel 3

Negative Differential Analog Input Pin of Channel 3

Positive Differential Analog Input Pin of Channel 4

Negative Differential Analog Input Pin of Channel 4

10

—

11

10

—

10

11

12

13

14

—

Exposed Thermal Pad (EP); must be connected to

V_SS

3.1

Analog Inputs (CHn+, CHn-)

3.2

Supply Voltage (V_DD, V_SS)

CHn+ and CHn- are differential input pins for

channel n. The user can also connect CHn- pin to V_SS

for a single-ended operation. See Figure 6-4 for

differential and single-ended connection examples.

V_DDis the power supply pin for the device. This pin

requires an appropriate bypass ceramic capacitor of

about 0.1 µF to ground to attenuate high frequency

noise presented in application circuit board. An

additional 10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate current spike

noises. The supply voltage (V_DD) must be maintained

in the 2.7V to 5.5V range for specified operation.

The maximum voltage range on each differential input

pin is from V_SS-0.3V to V_DD+0.3V. Any voltage below or

above this range will cause leakage currents through

the Electrostatic Discharge (ESD) diodes at the input

pins.

V_SSis the ground pin and the current return path of the

device. The user must connect the V_SSpin to a ground

plane through a low impedance connection. If an

analog ground path is available in the application PCB

(printed circuit board), it is highly recommended that

the V_SSpin be tied to the analog ground path or

isolated within an analog ground plane of the circuit

board.

This ESD current can cause unexpected performance

of the device. The input voltage at the input pins should

be within the specified operating range defined in

Section 1.0 “Electrical Characteristics” and

Section 4.0 “Description of Device Operation”.

See Section 4.5 “Input Voltage Range” for more

details of the input voltage range.

Figure 3-1 shows the input structure of the device. The

device uses a switched capacitor input stage at the

front end. C_PINis the package pin capacitance and

typically about 4 pF. D₁and D₂are the ESD diodes.

C_SAMPLEis the differential input sampling capacitor.

DS22226A-page 11

MCP3426/7/8

V_DD

D₁

Sampling

Switch

V_T= 0.6V

R_S

SS

CHn

R_SS

I_LEAKAGE

(~ ±1 nA)

C_PIN

4 pF

C_SAMPLE

(3.2 pF)

V

D₂

V_SS

LEGEND

V

R_ss

CHn

C_PIN

V_T

=

Signal Source

I_LEAKAGE

=

Leakage Current at Analog Pin

Sampling Switch

Source Impedance

Analog Input Pin

SS

R_s

C_SAMPLE

D1, D2

Sampling Switch Resistor

Sample Capacitance

Input Pin Capacitance

Threshold Voltage

=

ESD Protection Diode

FIGURE 3-1:

Equivalent Analog Input Circuit.

3.3

Serial Clock Pin (SCL)

3.4

Serial Data Pin (SDA)

SCL is the serial clock pin of the I²C interface. The

device acts only as a slave and the SCL pin accepts

only external serial clocks. The input data from the

Master device is shifted into the SDA pin on the rising

edges of the SCL clock and output from the slave

device occurs at the falling edges of the SCL clock. The

SCL pin is an open-drain N-channel driver. Therefore,

it needs a pull-up resistor from the V_DDline to the SCL

SDA is the serial data pin of the I²C interface. The SDA

pin is used for input and output data. In read mode, the

conversion result is read from the SDA pin (output). In

write mode, the device configuration bits are written

(input) though the SDA pin. The SDA pin is an

open-drain N-channel driver. Therefore, it needs a

pull-up resistor from the V_DDline to the SDA pin.

Except for start and stop conditions, the data on the

SDA pin must be stable during the high period of the

clock. The high or low state of the SDA pin can only

change when the clock signal on the SCL pin is low.

Refer to Section 5.3 “I²C Serial Communications”

for more details on I²C Serial Interface communication.

pin.

Refer

to

Section 5.3

“I²C

Serial

Communications” for more details on I²C Serial

Interface communication.

The typical range of the pull-up resistor value for SCL

and SDA is from 5 kΩ to 10 kΩ for standard (100 kHz)

and fast (400 kHz) modes, and less than 1 kΩ for high

speed mode (3.4 MHz).

3.5

Exposed Thermal Pad (EP)

There is an internal electrical connection between the

Exposed Thermal Pad (EP) and the V_SSpin; they must

be connected to the same potential on the Printed

Circuit Board (PCB).

DS22226A-page 12

MCP3426/7/8

The threshold voltage is set at 2.2V with a tolerance of

approximately ±5%. If the supply voltage falls below

this threshold, the device will be held in a reset

condition. The typical hysteresis value is approximately

200 mV.

4.0

DESCRIPTION OF DEVICE

OPERATION

4.1

General Overview

The

MCP3426/7/8

devices

are

differential

The POR circuit is shut down during the low-power

standby mode. Once a power-up event has occurred,

multi-channel low-power, 16-Bit Delta-Sigma A/D

converters with an I²C serial interface. The devices

contain an input channel selection multiplexer (mux), a

programmable gain amplifier (PGA), an on-board

voltage reference (2.048V), and an internal oscillator.

the

device

requires

additional

delay

time

(approximately 300 µs) before a conversion takes

place. During this time, all internal analog circuitries are

settled before the first conversion occurs. Figure 4-1

illustrates the conditions for power-up and power-down

events under typical start-up conditions.

When the device powers up (POR is set), it

automatically resets the configuration bits to default

settings.

V_DD

4.1.1

DEVICE DEFAULT SETTINGS ARE:

2.2V

2.0V

300 µS

• Conversion bit resolution: 12 bits (240 sps)

• Input channel: Channel 1

• PGA gain setting: x1

• Continuous conversion

Time

Once the device is powered-up, the user can

reprogram the configuration bits using I²C serial

interface any time. The configuration bits are stored in

the volatile memory.

Reset Start-up

Normal Operation

Reset

FIGURE 4-1:

POR Operation.

4.3

Internal Voltage Reference

4.1.2

USER SELECTABLE OPTIONS ARE:

The device contains an on-board 2.048V voltage

reference. This reference voltage is for internal use

only and not directly measurable. The specification of

the reference voltage is part of the device’s gain and

drift specifications. Therefore, there is no separate

specification for the on-board reference.

• Conversion bit resolution: 12, 14, or 16 bits

• Input channel selection: CH1, CH2, CH3, or CH4.

• PGA Gain selection: x1, x2, x4, or x8

• Continuous or one-shot conversion

In the Continuous Conversion mode, the device

converts the inputs continuously. While in the One-Shot

Conversion mode, the device converts the input one

time and stays in the low-power standby mode until it

receives another command for a new conversion.

During the standby mode, the device consumes less

than 1 µA maximum.

4.4

Analog Input Channels

The user can select the input channel using the

configuration register bits. Each channel can be used

for differential or single-ended input.

Each input channel has a switched capacitor input

structure. The internal sampling capacitor (3.2 pF for

PGA = 1) is charged and discharged to process a

conversion. The charging and discharging of the input

sampling capacitor creates dynamic input currents at

each input pin. The current is a function of the

differential input voltages, and inversely proportional to

the internal sampling capacitance, sampling frequency,

and PGA setting.

4.2

Power-On-Reset (POR)

The device contains an internal Power-On-Reset

(POR) circuit that monitors power supply voltage (V_DD

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

)

The device resets all configuration register bits to

default settings as soon as the POR is set.

The POR has built-in hysteresis and a timer to give a

high degree of immunity to potential ripples and noises

on the power supply. A 0.1 µF decoupling capacitor

should be mounted as close as possible to the V_DDpin

for additional transient immunity.

DS22226A-page 13

MCP3426/7/8

Care must be taken in setting the input voltage ranges

so that the input voltage does not exceed the absolute

maximum input voltage range.

4.5

Input Voltage Range

The differential (V_IN) and common mode voltage

(V_INCOM) at the input pins without considering PGA

setting are defined by:

4.6

Input Impedance

The device uses a switched-capacitor input stage using

a 3.2 pF sampling capacitor. This capacitor is switched

(charged and discharged) at a rate of the sampling

frequency that is generated by on-board clock. The

differential input impedance varies with the PGA

settings. The typical differential input impedance during

a normal mode operation is given by:

V_IN= (CHn+) – (CHn-)

(CHn+) + (CHn-)

V_INCOM= -----------------------------------------------

2

Where:

n

=

nth input channel (n=1, 2, 3, or 4)

The input signal levels are amplified by the internal

programmable gain amplifier (PGA) at the front end of

the ΔΣ modulator.

Z_IN(f) = 2.25 MΩ /PGA

Since the sampling capacitor is only switching to the

input pins during a conversion process, the above input

impedance is only valid during conversion periods. In a

low power standby mode, the above impedance is not

presented at the input pins. Therefore, only a leakage

current due to ESD diode is presented at the input pins.

The user needs to consider two conditions for the input

voltage range: (a) Differential input voltage range and

(b) Absolute maximum input voltage range.

4.5.1

DIFFERENTIAL INPUT VOLTAGE

RANGE

The conversion accuracy can be affected by the input

signal source impedance when any external circuit is

connected to the input pins. The source impedance

adds to the internal impedance and directly affects the

time required to charge the internal sampling capacitor.

Therefore, a large input source impedance connected

to the input pins can degrade the system performance,

such as offset, gain, and Integral Non-Linearity (INL)

errors. Ideally, the input source impedance should be

zero. This can be achievable by using an operational

amplifier with a closed-loop output impedance of tens

of ohms.

The device performs conversions using its internal

reference voltage (V_REF= 2.048V). Therefore, the

absolute value of the differential input voltage (V_IN),

with PGA setting is included, needs to be less than the

internal reference voltage. The device will output

saturated output codes (all 0s or all 1s except sign bit)

if the absolute value of the input voltage (V_IN), with

PGA setting is included, is greater than the internal

reference voltage (V_REF= 2.048V). The input full scale

voltage range is given by:

EQUATION 4-1:

4.7

Aliasing and Anti-aliasing Filter

–V_REF≤ (V_IN• PGA) ≤ (V_REF– 1LSB)

Aliasing occurs when the input signal contains

time-varying signal components with frequency greater

than half the sample rate. In the aliasing conditions, the

device can output unexpected output codes. For

applications that are operating in electrical noise

environments, the time-varying signal noise or high

frequency interference components can be easily

added to the input signals and cause aliasing. Although

the device has an internal first order sinc filter, the filter

response (Figure 2-11) may not give enough

attenuation to all aliasing signal components. To avoid

the aliasing, an external anti-aliasing filter, which can

be accomplished with a simple RC low-pass filter, is

typically used at the input pins. The low-pass filter cuts

off the high frequency noise components and provides

a band-limited input signal to the input pins.

Where:

V_IN

=

CHn+ - CHn-

2.048V

V_REF

If the input voltage level is greater than the above limit,

the user can use a voltage divider and bring down the

input level within the full scale range. See Figure 6-7 for

more details of the input voltage divider circuit.

4.5.2

ABSOLUTE MAXIMUM INPUT

VOLTAGE RANGE

The input voltage at each input pin must be less than

the following absolute maximum input voltage limits:

• Input voltage < V_DD+0.3V

• Input voltage > V_SS-0.3V

4.8

Self-Calibration

Any input voltage outside this range can turn on the

input ESD protection diodes, and result in input

leakage current, causing conversion errors, or

permanently damage the device.

The device performs a self-calibration of offset and

gain for each conversion. This provides reliable

conversion results from conversion-to-conversion over

variations in temperature as well as power supply

fluctuations.

DS22226A-page 14

MCP3426/7/8

Table 4-1 shows the LSB size of each conversion rate

setting. The measured unknown input voltage is

obtained by multiplying the output codes with LSB. See

the following section for the input voltage calculation

using the output codes.

4.9

Digital Output Codes and

Conversion to Real Values

4.9.1

DIGITAL OUTPUT CODE FROM

DEVICE

The digital output code is proportional to the input

voltage and PGA settings. The output data format is a

binary two’s complement. With this code scheme, the

MSB can be considered a sign indicator. When the

MSB is a logic ‘0’, the input is positive. When the MSB

is a logic ‘1’, the input is negative. The following is an

example of the output code:

TABLE 4-1:

RESOLUTION SETTINGS VS.

LSB

Resolution Setting

12 bits

LSB

1 mV

14 bits

16 bits

250 µV

62.5 µV

(a) for a negative full scale input voltage: 100...000

Example: (CHn+ - CHn-) •PGA = -2.048V

(b) for a zero differential input voltage: 000...000

Example: (CHn+ - CHn-) = 0

TABLE 4-2: EXAMPLE OF OUTPUT CODE

FOR 16 BITS (NOTE 1, NOTE 2)

Input Voltage:

Digital Output Code

[CHn+ - CHn-] • PGA

(c) for a positive full scale input voltage: 011...111

Example: (CHn+ - CHn-) • PGA = 2.048V

≥ V_REF

_REF- 1 LSB

2 LSB

0111111111111111

0000000000000010

0000000000000001

0000000000000000

1111111111111111

1111111111111110

1000000000000000

The MSB (sign bit) is always transmitted first through

the I²C serial data line. The resolution for each

conversion is 16, 14, or 12 bits depending on the

conversion rate selection bit settings by the user.

V

1 LSB

0

The output codes will not roll-over even if the input

voltage exceeds the maximum input range. In this

case, the code will be locked at 0111...11 for all

voltages greater than (V_REF- 1 LSB)/PGA and

1000...00 for voltages less than -V_REF/PGA.

Table 4-2 shows an example of output codes of various

input levels for 16-bit conversion mode. Table 4-3

shows an example of minimum and maximum output

codes for each conversion rate option.

-1 LSB

-2 LSB

- V_REF

< -V_REF

Note 1: MSB is a sign indicator:

0: Positive input (CHn+ > CHn-)

1: Negative input (CHn+ < CHn-)

2: Output data format is binary two’s

The number of output code is given by:

complement.

EQUATION 4-2:

TABLE 4-3:

MINIMUM AND MAXIMUM

OUTPUT CODES (NOTE)

Number of Output Code =

(CHn+ – CHn-)

----------------------------------------

= (Maximum Code + 1) × PGA ×

2.048V

Resolution

Setting

Minimum Maximum

Data Rate

Where:

Code

See Table 4-3 for Maximum Code

12

14

16

240 SPS

60 SPS

15 SPS

-2048

-8192

2047

8191

The LSB of the data conversion is given by:

-32768

32767

Note:

Maximum n-bit code = 2^N-1- 1

EQUATION 4-3:

Minimum n-bit code = -1 x 2^N-1

2 × V_REF

LSB = --------------------- = --------------------------

2 × 2.048V

2^N2^N

Where:

N

=

Resolution, which is programmed in

the Configuration Register: 12, 14,

or 16.

DS22226A-page 15

MCP3426/7/8

4.9.2

CONVERTING THE DEVICE

OUTPUT CODE TO INPUT SIGNAL

VOLTAGE

EQUATION 4-4:

CONVERTING OUTPUT

CODES TO INPUT

VOLTAGE

When the user gets the digital output codes from the

device as described in Section 4.9.1 “Digital output

code from device”, the next step is converting the

digital output codes to a measured input voltage.

Equation 4-4 shows an example of converting the

output codes to its corresponding input voltage.

If MSB = 0 (Positive Output Code):

Input Voltage = (Output Code) •

LSB

PGA

-----------

If MSB = 1 (Negative Output Code):

LSB

PGA

(2′s complement of Output Code)

-----------

•

Input Voltage =

If the sign indicator bit (MSB) is ‘0’, the input voltage

is obtained by multiplying the output code with the LSB

and divided by the PGA setting.

Where:

LSB

2’s complement

=

See Table 4-1

1’s complement + 1

If the sign indicator bit (MSB) is ‘1’, the output code

needs to be converted to two’s complement before

multiplied by LSB and divided by the PGA setting.

Table 4-4 shows an example of converting the device

output codes to input voltage.

TABLE 4-4:

EXAMPLE OF CONVERTING OUTPUT CODE TO VOLTAGE (WITH 16 BIT SETTING)

Input Voltage

[CHn+ - CHn-] • PGA]

Digital Output Code

MSB

Example of Converting Output Codes to Input Voltage

≥ V_REF

0111111111111111

(2¹⁴+2¹³+2¹²+2¹¹+2¹⁰+2⁹+2⁸+2⁷+2⁶+2⁵+2⁴+2³+2²+2¹+2⁰)x

LSB(62.5μV)/PGA = 2.048 (V) for PGA = 1

0

V_REF- 1 LSB

2 LSB

0111111111111111

0000000000000010

0000000000000001

0000000000000000

1111111111111111

1111111111111110

1000000000000000

(2¹⁴+2¹³+2¹²+2¹¹+2¹⁰+2⁹+2⁸+2⁷+2⁶+2⁵+2⁴+2³+2²+2¹+2⁰)x

LSB(62.5μV)/PGA = 2.048 (V) for PGA = 1

(0+0+0+0+0+0+0+0+0+0+0+0+0+2¹+0)x LSB(62.5μV)/PGA

= 125 (μV) for PGA = 1

(0+0+0+0+0+0+0+0+0+0+0+0+0+0+2⁰)x LSB(62.5μV)/PGA

= 62.5 (μV)for PGA = 1

0

1

1 LSB

0

(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0)x LSB(62.5μV)/PGA

= 0 V (V) for PGA = 1

-(0+0+0+0+0+0+0+0+0+0+0+0+0+0+2⁰)x LSB(62.5μV)/

PGA = - 62.5 (μV)for PGA = 1

-(0+0+0+0+0+0+0+0+0+0+0+0+0+2¹+0)x LSB(62.5μV)/

PGA = - 125 (μV)for PGA = 1

-(2¹⁵+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x LSB(62.5μV)/

PGA = - 2.048 (V) for PGA = 1

-(2¹⁵+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x LSB(62.5μV)/

-1 LSB

-2 LSB

- V_REF

≤ -V_REF

PGA = - 2.048 (V) for PGA = 1

Note:

MSB = sign bit (1: “-”, 0: “+”)

DS22226A-page 16

MCP3426/7/8

5.1.2

ONE-SHOT CONVERSION MODE

(O/C BIT = 0)

5.0

5.1

USING THE DEVICES

Operating Modes

Once the One-Shot Conversion (single conversion)

Mode is selected, the device performs only one

conversion, updates the output data register, clears the

data ready flag (RDY = 0), and then enters a low power

standby mode. A new One-Shot Conversion is started

again when the device receives a new write command

with RDY = 1.

The user operates the device by setting up the device

configuration register using a write command (see

Figure 5-3) and reads the conversion data using a read

command (see Figure 5-4 ). The device operates in two

modes: (a) Continuous Conversion Mode or

(b) One-Shot Conversion Mode (single conversion).

This mode selection is made by setting the O/C bit in

the Configuration Register. Refer to Section 5.2

“Configuration Register” for more information.

• When writing configuration register:

- The RDY bit needs to be set to begin a new

conversion in one-shot mode.

• When reading conversion data:

5.1.1

CONTINUOUS CONVERSION

MODE (O/C BIT = 1)

- RDY bit = 0means the latest conversion

result is ready.

The device performs a Continuous Conversion if the

O/C bit is set to logic “high”. Once the conversion is

completed, RDY bit is toggled to ‘0’and the result is

placed at the output data register. The device

immediately begins another conversion and overwrites

the output data register with the most recent result.

The device clears the data ready flag (RDY bit = 0)

when the conversion is completed. The device sets the

ready flag bit (RDY bit = 1), if the latest conversion

result has been read by the Master.

- RDY bit = 1means the conversion result is

not updated since the last reading. A new

conversion is under processing and the RDY

bit will be cleared when the new conversion is

done.

This One-Shot Conversion Mode is highly

recommended for low power operating applications

where the conversion result is needed by request on

demand. During the low current standby mode, the

device consumes less than 1 µA maximum (or 300 nA

typical). For example, if the user collects 16-bit

• When writing configuration register:

- Setting RDY bit in continuous mode does not

affect anything.

conversion data once

a

second in One-Shot

Conversion mode, the device draws only about one-

fifteenth of the operating currents for the continuous

conversion mode. In this example, the device

• When reading conversion data:

- RDY bit = 0 means the latest conversion

result is ready.

consumes

approximately

9 µA

(135 µA

/

15 SPS = 9 µA), when the device performs only one

conversion per second (1 SPS) in 16-bit conversion

mode with 3V power supply.

- RDY bit = 1 means the conversion result is

not updated since the last reading. A new

conversion is under processing and the RDY

bit will be cleared when the new conversion

result is ready.

DS22226A-page 17

MCP3426/7/8

The user can rewrite the configuration byte any time

during the device operation. Register 5-1 shows the

configuration register bits.

5.2

Configuration Register

The device has an 8-bit wide configuration register to

select for: input channel, conversion mode, conversion

rate, and PGA gain. This register allows the user to

change the operating condition of the device and check

the status of the device operation.

REGISTER 5-1:

CONFIGURATION REGISTER

R/W-1

RDY

R/W-0

C1

R/W-0

C0

R/W-1

O/C

1 *

R/W-0

S1

R/W-0

S0

R/W-0

G1

R/W-0

G0

1 *

0 *

bit 7

bit 0

* Default Configuration after Power-On Reset

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

RDY: Ready Bit

This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated

with a latest conversion result. In One-Shot Conversion mode, writing this bit to “1” initiates a new

conversion.

Reading RDY bit with the read command:

1= Output register has not been updated.

0= Output register has been updated with the latest conversion result.

Writing RDY bit with the write command:

Continuous Conversion mode: No effect

One-Shot Conversion mode:

1= Initiate a new conversion.

0= No effect.

bit 6-5

C1-C0: Channel Selection Bits

00 = Select Channel 1 (Default)

01 = Select Channel 2

10 = Select Channel 3 (MCP3428 only, treated as “00” by the MCP3426/MCP3427)

11 = Select Channel 4 (MCP3428 only, treated as “01” by the MCP3426/MCP3427)

bit 4

O/C: Conversion Mode Bit

1= Continuous Conversion Mode (Default). The device performs data conversions continuously.

0= One-Shot Conversion Mode. The device performs a single conversion and enters a low power

standby mode until it receives another write or read command.

bit 3-2

bit 1-0

S1-S0: Sample Rate Selection Bit

00 = 240 SPS (12 bits) (Default)

01 = 60 SPS (14 bits)

10 = 15 SPS (16 bits)

G1-G0: PGA Gain Selection Bits

00 = x1 (Default)

01 = x2

10 = x4

11 = x8

DS22226A-page 18

MCP3426/7/8

I²C Serial Communications

If the configuration byte is read repeatedly by clocking

continuously after reading the data bytes (i.e., after the

4th byte in the 16-bit conversion mode), the state of the

RDY bit indicates whether the device is ready with new

conversion result. When the Master finds the RDY bit is

cleared, it can send a not-acknowledge (NAK) bit and

a stop bit to exit the current read operation and send a

new read command for the latest conversion data.

Once the conversion data has been read, the ready bit

toggles to ‘1’ until the next new conversion data is

ready. The conversion data in the output register is

overwritten every time a new conversion is completed.

5.3

The device communicates with the Master

(microcontroller) through a serial I²C (Inter-Integrated

Circuit) interface and support standard (100 kbits/sec),

fast (400 kbits/sec) and high-speed (3.4 Mbits/sec)

modes. The serial I²C is a bidirectional 2-wire data bus

communication protocol using open-drain SCL and

SDA lines.

The device can only be addressed as a slave. Once

addressed, it can receive configuration bits with a write

command or transmit the latest conversion results with

a read command. The serial clock pin (SCL) is an input

only and the serial data pin (SDA) is bidirectional. The

Master starts communication by sending a START bit

and terminates the communication by sending a STOP

bit. In read mode, the device releases the SDA line

after receiving NAK and STOP bits.

Figure 5-3 shows an example of writing configuration

register, and Figure 5-4 shows an example of reading

conversion data. The user can rewrite the configuration

byte any time for a new setting. Table 5-1 and Table 5-

2 show the examples of the configuration bit operation.

TABLE 5-1:

WRITE CONFIGURATION BITS

Operation

An example of a hardware connection diagram is

shown in Figure 6-1. More details of the I²C bus

characteristic is described in Section 5.6 “I²C Bus

Characteristics”.

R/W O/C RDY

0

No effect if all other bits remain

the same - operation continues

with the previous settings.

2

5.3.1

I C DEVICE ADDRESSING

0

1

0

1

Initiate One-Shot Conversion.

Initiate Continuous Conversion.

The first byte after the START bit is always the address

byte of the device, which includes the device code (4

bits), address bits (3 bits), and R/W bit. The device

code for the devices is 1101, which is programmed at

the factory. The I²C address bits (A2, A1, A0 bits) are

as follows:

TABLE 5-2:

READ CONFIGURATION BITS

Operation

• MCP3426: Programmed at factory

R/W O/C RDY

• MCP3427 and MCP3428: Progammed by the

user. It is determined by the logic status of the two

external address selection pins on the user’s

application board (Adr0 and Adr1 pins). The

Master must know the Adr0 and Adr1 pin

conditions before sending read or write command.

See Section 5.3.2 “Device Address Bits (A2,

A1, A0) and Address Selection Pins (MCP3427

and MCP3428)” for more details

1

0

1

0

1

0

1

New conversion result in One-

Shot conversion mode has just

been read. The RDY bit remains

low until set by a new write

command.

One-Shot Conversion is in prog-

ress. The conversion result is not

updated yet. The RDY bit stays

high until the current conversion

is completed.

Figure 5-1 shows the details of the address byte.

The three I²C address bits allow up to eight devices on

the same I²C bus line. The (R/W) bit determines if the

Master device wants to read the conversion data or

write to the Configuration register. If the (R/W) bit is set

(read mode), the device outputs the conversion data in

the following clocks. If the (R/W) bit is cleared (write

mode), the device expects a configuration byte in the

following clocks. When the device receives the correct

address byte, it outputs an acknowledge bit after the

R/W bit.

New conversion result in

Continuous Conversion mode

has just been read. The RDY bit

changes to high after reading the

conversion data.

The conversion result in

Continuous Conversion mode

was already read. The next new

conversion data is not ready. The

RDY bit stays high until a new

conversion is completed.

DS22226A-page 19

MCP3426/7/8

It is recommended to issue a General Call Reset or

General Call Latch command once after the device

has powered up. This will ensure that the device reads

the address pins in a stable condition, and avoid

latching the address bits while the power supply is

ramping up. This might cause inaccurate address pin

detection.

Acknowledge bit

Read/Write bit

Start bit

Address

R/W ACK

Address Byte

When the address pin is left “floating”:

Address Byte:

When the address pin is left “floating”, the address pin

momentarily outputs a short pulse with an amplitude of

about V_DD/2 during the latch event. The device also

latches this pin voltage at the same time.

Device Code

Address Bits ^{(Note 1)}

1

0

A2 A1

A0

If the “floating” pin is connected to a large parasitic

capacitance (> 20 pF) or to a long PCB trace, this short

floating voltage output can be altered. As a result, the

device may not latch the pin correctly.

Note 1: MCP3427 and MCP3428: Configured by

the user. See Table 5-4 for address bit

configurations.

2: MCP3426: Programmed at the factory

during production.

It is strongly recommended to keep the “floating” pin

pad as short as possible in the customer application

PCB and minimize the parasitic capacitance to the pin

as small as possible (< 20 pF).

FIGURE 5-1:

5.3.2

Address Byte.

Figure 5-2 shows an example of the Latch voltage

output at the address pin when the address pin is left

“floating”. The waveform at the Adr0 pin is captured by

using an oscilloscope probe with 15 pF of capacitance.

The device latches the floating condition immediately

after the General Call Latch command.

DEVICE ADDRESS BITS (A2, A1, A0)

AND ADDRESS SELECTION PINS

(MCP3427 AND MCP3428)

The MCP3427 and MCP3428 have two external

device address pins (Adr1, Adr0). These pins can be

set to a logic high (or tied to V_DD), low (or tied to V_SS),

or left floating (not connected to anything, or tied to

V_DD/2), These combinations of logic level using the

two pins allow eight possible addresses. Table 5-3

shows the device address depending on the logic

status of the address selection pins.

Float waveform (output)

a

t address pin

The device samples the logic status of the Adr0 and

Adr1 pins in the following events:

SCL

SDA

(a) Device power-up.

(b) General Call Reset

(See Section 5.4 “General Call”).

(c) General Call Latch

(See Section 5.4 “General Call”).

FIGURE 5-2:

Command and Voltage Output at Address Pin

Left “Floating” (MCP3427 and MCP3428).

General Call Latch

The device samples the logic status (address pins)

during the above events, and latches the values until a

new latch event occurs. During normal operation (after

the address pins are latched), the address pins are

internally disabled from the rest of the internal circuit.

DS22226A-page 20

MCP3426/7/8

TABLE 5-3:

ADDRESS BITS VS. ADDRESS

SELECTION PINS FOR

(MCP3427 AND MCP3428

ONLY) (NOTE 1, 2, 3)

5.3.3

WRITING A CONFIGURATION BYTE

TO THE DEVICE

When the Master sends an address byte with the R/W

bit low (R/W = 0), the device expects one configuration

byte following the address. Any byte sent after this

second byte will be ignored. The user can change the

operating mode of the device by writing the

configuration register bits.

I²C Device

Address Bits

Logic Status of Address

Selection Pins

A2

A1

A0

Adr0 Pin

Adr1 Pin

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0 (Addr_Low)

Float

If the device receives a write command with a new

configuration setting, the device immediately begins a

new conversion and updates the conversion data.

1 (Addr_High)

1 (Addr_High) 0 (Addr_Low)

1 (Addr_High) Float

1 (Addr_High) 1 (Addr_High)

Float

0 (Addr_Low)

1 (Addr_High)

Float

Note 1: Float: (a) Leave pin without connecting to

anything (left floating), or (b) apply

Addr_Float voltage.

2: The user can tie the pins to V_SSor V_DD

:

- Tie to V_SSfor Addr_Low

- Tie to V_DDfor Addr_High

3: See Addr_Low, Addr_High, and

Addr_Float parameters in Electrical

Characteristics Table.

1

9

SCL

SDA

1

A2 A1 A0

R/W

C1 C0

S1 S0 G1 G0

0

Start Bit by

Master

ACK by

MCP3426/7/8

Stop Bit by

Master

ACK by

MCP3426/7/8

O/C

RDY

(a) One-Shot Mode: 1

(b) Continuous Mode: not effected

1st Byte:

Address Byte

with Write command

2nd Byte:

Configuration Byte

Note:

– Stop bit can be issued any time during writing.

– MCP3426/7/8 device code is 1101(programmed at the factory).

– See Figure 5-1 for details in Address Byte.

FIGURE 5-3:

Timing Diagram For Writing To The MCP3426/7/8.

DS22226A-page 21

MCP3426/7/8

The configuration byte follows the output data bytes.

The device repeatedly outputs the configuration byte

only if the Master sends clocks repeatedly after the

data bytes.

5.3.4

READING OUTPUT CODES AND

CONFIGURATION BYTE FROM THE

DEVICE

When the Master sends a read command (R/W = 1),

the device outputs both the conversion data and

configuration bytes. Each byte consists of 8 bits with

one acknowledge (ACK) bit. The ACK bit after the

address byte is issued by the device and the ACK bits

after each conversion data bytes are issued by the

Master.

The device terminates the current outputs when it

receives a Not-Acknowledge (NAK) with a repeated

start or a stop bit at the end of each output byte. It is not

required to read the configuration byte. However, the

Master may read the configuration byte to check the

RDY bit condition.The Master may continuously send

clock (SCL) to repeatedly read the configuration byte

(to check the RDY bit status).

When the device receives a read command, it outputs

two data bytes followed by a configuration register. In

16-bit conversion mode, the MSB (= sign bit) of the first

data byte is D15. In 14-bit conversion mode, the first

two bits in the first data byte are repeated MSB bits and

can be ignored, and the 3rd bit (D13) is the MSB (=sign

bit) of the conversion data. In 12-bit conversion mode,

the first four bits are repeated MSB bits and can be

ignored. The 5th bit (D11) of the byte represents the

MSB (= sign bit) of the conversion data. Table 5-4

summarizes the conversion data output of each

conversion mode.

Figure 5-4 shows the timing diagram for reading the

ADC conversion data.

TABLE 5-4:

OUTPUT CODES OF EACH RESOLUTION OPTION

Digital Output Codes

Conversion

Option

16-bits

14-bits

12-bits

D15 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 1)

MMD13D ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 2)

MMMMD11 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 3)

Note 1: D15 is MSB (= sign bit).

2: D13 is MSB (= sign bit), M is repeated MSB of the data byte.

3: D11 is MSB (= sign bit), M is repeated MSB of the data byte.

DS22226A-page 22

MCP3426/7/8

FIGURE 5-4:

Timing Diagram For Reading From The MCP3426/7/8 With 12-Bit to 16-Bit Modes.

DS22226A-page 23

MCP3426/7/8

5.4

General Call

5.5

High-Speed (HS) Mode

The device acknowledges the general call address

(0x00 in the first byte). The meaning of the general call

address is always specified in the second byte. Refer

to Figure 5-5. The device supports the following three

general calls.

For more information on the general call, or other I²C

modes, refer to the Phillips I²C specification.

The I²C specification requires that a high-speed mode

device must be ‘activated’ to operate in high-speed

mode. This is done by sending a special address byte

of “00001XXX” following the START bit. The “XXX”bits

are unique to the High-Speed (HS) mode Master. This

byte is referred to as the High-Speed (HS) Master

Mode Code (HSMMC). The MCP3426/7/8 devices do

not acknowledge this byte. However, upon receiving

this code, the device switches on its HS mode filters

and communicates up to 3.4 MHz on SDA and SCL

bus lines. The device will switch out of the HS mode on

the next STOP condition.

5.4.1

GENERAL CALL RESET

The general call reset occurs if the second byte is

‘00000110’ (06h). At the acknowledgement of this

byte, the device will abort current conversion and

perform the following tasks:

For more information on the HS mode, or other I²C

modes, refer to the Philips I²C specification.

(a) Internal reset similar to a Power-On-Reset (POR).

All configuration and data register bits are reset to

default values.

5.6

I²C Bus Characteristics

The I²C specification defines the following bus

protocol:

(b) Latch the logic status of external address selection

pins (Adr0 and Adr1 pins).

• Data transfer may be initiated only when the bus

is not busy

5.4.2

GENERAL CALL LATCH (MCP3427

AND MCP3428)

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition

The general call latch occurs if the second byte is

‘00000100’(04h). The device will latch the logic sta-

tus of the external address selection pins (Adr0 and

Adr1 pins), but will not perform a reset.

Accordingly, the following bus conditions have been

defined using Figure 5-6.

5.4.3

GENERAL CALL CONVERSION

5.6.1

BUS NOT BUSY (A)

The general call conversion occurs if the second byte

is ‘00001000’(08h). All devices on the bus initiate a

conversion simultaneously. When the device receives

this command, the configuration will be set to the

One-Shot Conversion mode and a single conversion

will be performed. The PGA and data rate settings are

unchanged with this general call.

Both data and clock lines remain HIGH.

5.6.2

START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

START

LSB STOP

5.6.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations can be ended with a STOP condition.

S

0 0 0 0 0 0 0 0

A

X X X X X X X X A S

5.6.4

DATA VALID (D)

ACK

First Byte

(General Call Address)

Second Byte

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

Note:

The I²C specification does not allow

‘00000000’ (00h) in the second byte.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

FIGURE 5-5:

General Call Address

Format.

Each data transfer is initiated with a START condition

and terminated with a STOP condition.

DS22226A-page 24

MCP3426/7/8

During reads, the Master (microcontroller) can

terminate the current read operation by not providing

an acknowledge bit (not Acknowledge (NAK)) on the

last byte. In this case, the MCP3426/7/8 devices

release the SDA line to allow the Master

(microcontroller) to generate a STOP or repeated

START condition.

5.6.5

ACKNOWLEDGE AND

NON-ACKNOWLEDGE

The Master (microcontroller) and the slave (MCP3426/

7/8) use an acknowledge pulse (ACK) as a hand shake

of communication for each byte. The ninth clock pulse

of each byte is used for the acknowledgement. The

clock pulse is always provided by the Master

(microcontroller) and the acknowledgement is issued

by the receiving device of the byte (Note: The

transmitting device must release the SDA line during

the acknowledge pulse.). The acknowledgement is

achieved by pulling-down the SDA line “LOW” during

the 9th clock pulse by the receiving device.

The non-acknowledgement (NAK) is issued by

providing the SDA line to “HIGH” during the 9th clock

pulse.

(A)

(B)

(D)

(C) (A)

SCL

SDA

START

STOP

ADDRESS OR

DATA

CONDITION

ACKNOWLEDGE ALLOWED

VALID TO CHANGE

2

FIGURE 5-6:

Data Transfer Sequence on I C Serial Bus.

DS22226A-page 25

MCP3426/7/8

2

TABLE 5-5:

I C SERIAL TIMING SPECIFICATIONS

Electrical Specifications: Unless otherwise specified, all limits are specified for T_A= -40 to +85°C, V_DD= +2.7V to +5.0V,

V

_SS= 0V, CHn+ = CHn- = V_REF/2.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Standard Mode (100 kHz)

Clock frequency

f_SCL

0

—

100

—

kHz

ns

Clock high time

T

4000

4700

—

HIGH

Clock low time

T

—

ns

LOW

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

T

1000

300

—

ns

From V_ILto V_IH(Note 1)

From V_IHto V_IL(Note 1)

R

T

—

ns

F

T

4000

ns

After this period, the first clock

pulse is generated.

HD:STA

Repeated START condition

setup time

4700

—

ns

Only relevant for repeated Start

condition

SU:STA

Data hold time

T

0

—

3450

—

ns

(Note 3)

HD:DAT

SU:DAT

SU:STO

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time

250

4000

0

T

—

T

3750

—

(Note 2, Note 3)

AA

T

4700

Time between START and STOP

conditions.

BUF

Fast Mode (400 kHz)

Clock frequency

T

0

—

400

—

kHz

ns

SCL

Clock high time

T

600

HIGH

Clock low time

T

1300

—

ns

LOW

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

T

20 + 0.1C_b

600

300

—

ns

From V_ILto V_IH(Note 1)

From V_IHto V_IL(Note 1)

R

T

ns

F

T

ns

After this period, the first clock

pulse is generated

HD:STA

Repeated START condition

setup time

600

—

ns

Only relevant for repeated Start

condition

SU:STA

Data hold time

T

0

100

600

0

—

900

—

ns

(Note 4)

HD:DAT

SU:DAT

SU:STO

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time

T

—

T

1200

—

(Note 2, Note 3)

AA

T

1300

Time between START and STOP

conditions.

BUF

Input filter spike suppression

T

0

—

50

ns

SDA and SCL pins (Note 5)

SP

Note 1: This parameter is ensured by characterization and not 100% tested.

2: This specification is not a part of the I²C specification. This specification is equivalent to the Data Hold Time (T

)

HD:DAT

plus SDA Fall (or rise) time: T_AA= T_HD:DAT+ T_F(OR T_R).

3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this

parameter is too long, Clock Low time (T_LOW) can be affected.

4: For Data Input: This parameter must be longer than t_SP. If this parameter is too long, the Data Input Setup (T_SU:DAT) or

Clock Low time (T_LOW) can be affected.

For Data Output: This parameter is characterized, and tested indirectly by testing T_AAparameter.

5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.

DS22226A-page 26

MCP3426/7/8

2

TABLE 5-5:

I C SERIAL TIMING SPECIFICATIONS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all limits are specified for T_A= -40 to +85°C, V_DD= +2.7V to +5.0V,

V

_SS= 0V, CHn+ = CHn- = V_REF/2.

Parameters

Sym

Min

Typ

Max

Units

Conditions

High Speed Mode (3.4 MHz)

Clock frequency

f_SCL

0

—

3.4

1.7

—

MHz

ns

C_b= 100 pF

C_b= 400 pF

0

Clock high time

Clock low time

T

60

C_b= 100 pF, f_SCL= 3.4 MHz

C_b= 400 pF, f_SCL= 1.7 MHz

C_b= 100 pF, f_SCL= 3.4 MHz

C_b= 400 pF, f_SCL= 1.7 MHz

HIGH

120

160

320

—

ns

T

—

ns

LOW

—

ns

SCL rise time

(Note 1)

T

40

ns

From V_ILto V_IH

C_b= 100 pF, f_SCL= 3.4 MHz

From V_ILto V_IH

,

R

—

80

40

ns

,

C_b= 400 pF, f_SCL= 1.7 MHz

SCL fall time

(Note 1)

T

From V_IHto V_IL,

C_b= 100 pF, f_SCL= 3.4 MHz

F

80

From V_IHto V_IL,

C_b= 400 pF, f_SCL= 1.7 MHz

SDA rise time

(Note 1)

T

80

From V_ILto V_IH

C_b= 100 pF, f_SCL= 3.4 MHz

From V_ILto V_IH

,

R: DAT

160

80

,

C_b= 400 pF, f_SCL= 1.7 MHz

SDA fall time

(Note 1)

T

From V_IHto V_IL,

C_b= 100 pF, f_SCL= 3.4 MHz

F: DATA

160

From V_IHto V_IL,

C_b= 400 pF, f_SCL= 1.7 MHz

Data hold time

(Note 4)

0

—

70

150

310

—

ns

C_b= 100 pF, f_SCL= 3.4 MHz

C_b= 400 pF, f_SCL= 1.7 MHz

C_b= 100 pF, f_SCL= 3.4 MHz

C_b= 400 pF, f_SCL= 1.7 MHz

HD:DAT

Output valid from clock

(Notes 2 and 3)

T

—

160

AA

START condition hold time

T

After this period, the first clock

pulse is generated

HD:STA

Repeated START condition

setup time

T_SU:STA

160

—

ns

Only relevant for repeated Start

condition

Data input setup time

T

10

160

0

—

10

ns

SU:DAT

T

SU:STO

STOP condition setup time

Input filter spike suppression

T

SDA and SCL pins (Note 5)

SP

Note 1: This parameter is ensured by characterization and not 100% tested.

2: This specification is not a part of the I²C specification. This specification is equivalent to the Data Hold Time (T

)

HD:DAT

plus SDA Fall (or rise) time: T_AA= T_HD:DAT+ T_F(OR T_R).

3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this

parameter is too long, Clock Low time (T_LOW) can be affected.

4: For Data Input: This parameter must be longer than t_SP. If this parameter is too long, the Data Input Setup (T_SU:DAT) or

Clock Low time (T_LOW) can be affected.

For Data Output: This parameter is characterized, and tested indirectly by testing T_AAparameter.

5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.

DS22226A-page 27

MCP3426/7/8

T_F

T_R

T_HIGH

T_SU:STA

SCL

T_SU:STO

T_BUF

T_SU:DAT

T_LOW

T_HD:STA

T_HD:DAT

SDA

0.7V_DD

0.3V_DD

T_SP

T_AA

2

FIGURE 5-7:

I C Bus Timing Data.

DS22226A-page 28

MCP3426/7/8

2

6.1.3

I C ADDRESS SELECTION PINS

(MCP3427 AND MCP3428)

6.0

BASIC APPLICATION

CONFIGURATION

The user can tie the Adr0 and Adr1 pins to V_SS, V_DD

,

The MCP3426/7/8 devices can be used for various

precision analog-to-digital converter applications.

These devices operate with very simple connections to

the application circuit. The following sections discuss

the examples of the device connections and

applications.

or left floating. See more details in Section 5.3.2

“Device Address Bits (A2, A1, A0) and Address

Selection Pins (MCP3427 and MCP3428)”.

MCP3428

Input

Signal 1

1

2

3

4

5

6

7

CH1+

CH1-

CH4- 14

Signal 4

6.1

Connecting to the Application

Circuits

13

12

CH4+

CH3-

Input

CH2+

CH2-

Signal 3

Signal 2

11

CH3+

2

6.1.1

BYPASS CAPACITORS ON V PIN

V

I C Address

Selection

Pins

Adr1 10

SS

DD

V

9

DD

Adr0

For an accurate measurement, the application circuit

needs a clean supply voltage and must block any noise

signal to the MCP3426/7/8 devices. Figure 6-1 shows

an example of using two bypass capacitors (a 10 µF

tantalum capacitor and a 0.1 µF ceramic capacitor) on

the V_DDline of the MCP3428. These capacitors are

helpful to filter out any high frequency noises on the

V_DDline and also provide the momentary bursts of

extra currents when the device needs from the supply.

These capacitors should be placed as close to the V_DD

pin as possible (within one inch). If the application

circuit has separate digital and analog power supplies,

the V_DDand V_SSof the MCP3426/7/8 devices should

reside on the analog plane.

C

1

SDA

8

SCL

C

2

TO MCU

(MASTER)

R_P

V

DD

Rp is the pull-up resistor:

5 kΩ - 10 kΩ for f_SCL= 100 kHz to 400 kHz

~700Ω for f_SCL= 3.45 MHz

C₁: 0.1 µF, Ceramic capacitor

2

6.1.2

CONNECTING TO I C BUS USING

PULL-UP RESISTORS

C₂: 10 µF, Tantalum capacitor

FIGURE 6-1:

Typical Connection.

The SCL and SDA pins of the MCP3426/7/8 are

open-drain configurations. These pins require a pull-up

resistor as shown in Figure 6-1. The value of these

pull-up resistors depends on the operating speed

(standard, fast, and high speed) and loading

capacitance of the I²C bus line. Higher value of pull-up

resistor consumes less power, but increases the signal

transition time (higher RC time constant) on the bus.

Therefore, it can limit the bus operating speed. The

lower value of resistor, on the other hand, consumes

higher power, but allows higher operating speed. If the

bus line has higher capacitance due to long bus line or

high number of devices connected to the bus, a smaller

pull-up resistor is needed to compensate the long RC

time constant. The pull-up resistor is typically chosen

between 5 kΩ and 10 kΩ ranges for standard and fast

modes, and less than 1 kΩ for high speed mode

depending on the presence of bus loading capacitance.

Figure 6-2 shows an example of multiple device

connections. The I²C bus loading capacitance

increases as the number of device connected to the I²C

bus line increases. The bus loading capacitance affects

on the bus operating speed. For example, the highest

bus operating speed for the 400 pF bus capacitance is

1.7 MHz, and 3.4 MHz for 100 pF. Therefore, the user

needs to consider the relationship between the

maximum operation speed versus. the number of I²C

devices that are connected to the I²C bus line.

SDA SCL

Microcontroller

(PIC16F876)

MCP3426

MCP3427

MCP3428

MCP4725

FIGURE 6-2:

Connection on I C Bus.

Example of Multiple Device

2

DS22226A-page 29

MCP3426/7/8

6.1.4

DEVICE CONNECTION TEST

6.1.5

DIFFERENTIAL AND

SINGLE-ENDED CONFIGURATION

The user can test the presence of the MCP3426/7/8 on

the I²C bus line without performing an input data

conversion. This test can be achieved by checking an

acknowledge response from the MCP3426/7/8 after

sending a read or write command. Here is an example

using Figure 6-3:

Figure 6-4 shows typical connection examples for

differential and single-ended inputs. Differential input

signals can be connected to the CHn+ and CHn- input

pins, where n = the channel number (1, 2, 3, or 4). For

the single-ended input, the input signal is applied to one

of the input pins (typically connected to the CHn+ pin)

while the other input pin (typically CHn- pin) is

grounded. All device characteristics hold for the

single-ended configuration, but this configuration loses

one bit resolution because the input can only stand in

positive half scale. Refer to Section 1.0 “Electrical

a. Set the R/W bit “HIGH” in the address byte.

b. Check the ACK pulse after sending the address

byte.

If the device acknowledges (ACK = 0), then the

device is connected, otherwise it is not

connected.

Characteristics”

.

c. Send STOP or START bit.

(a) Differential Input Signal Connection:

Excitation

Address Byte

Sensor

1

2

1

3

0

4

5

6

7

8

1

9

SCL

SDA

CHn+

Input Signal

1 A2 A1 A0

CHn-

MCP342X

Start

Bit

Stop

Bit

Address bits

Device bits

R/W

(b) Single-ended Input Signal Connection:

MCP342X

Response

Excitation

R₁

2

FIGURE 6-3:

I C Bus Connection Test.

CHn+

Input Signal

Sensor

R₂

CHn-

MCP342X

FIGURE 6-4:

Differential and

Single-Ended Input Connections.

DS22226A-page 30

MCP3426/7/8

Therefore, the current measurement often prefers to

use a current sensor with smaller resistance value,

which, in turn, requires high resolution ADC device.

6.2

Application Examples

The MCP3426/7/8 devices can be used for broad

ranges of sensor and data acquisition applications.

The device can measure the input voltage as low as

7.8 µV range (or current in ~ µA range) with 16 bit

resolution and PGA = 8 settings.

Figure 6-5 shows a circuit example measuring both the

battery voltage and current using the MCP3426 device.

Channels 1 and 2 are measuring the voltage and the

current, respectively.

The MSB (= sign bit) of the output code determines the

direction of the current, which identifies the charging or

the discharging current.

When the input voltage is greater than the internal

reference voltage (V_REF= 2.048V), it needs a voltage

divider circuit to prevent the output code from being

saturated. In the example, R₁and R₂form a voltage

divider. The R₁and R₂are set to yield V_INto be less

than the internal reference voltage (V_REF= 2.048V).

For the current measurement, the device measure the

voltage across the current sensor, and converts it by

dividing the measured voltage by a known resistance

value. The voltage drops across the sensor is waste.

Discharging Current

To Load

Current Sensor

Charging

Current

To Battery

R₁

Battery

V_BAT

MCP3426

V_IN

(Rechargeable)

8

1

2

CH2-

CH1+

CH1-

V_DD

SDA

7

6

5

CH2+

V_SS

3

4

0.1 µF

SCL

R₂

SCL

10 µF

TO MCU

(MASTER)

SDA

R₂

------------------

V_IN

=

× V_BAT

5 kΩ

R₁+ R₂

5 kΩ

R₁and R₂= Voltage Divider

V_DD

FIGURE 6-5:

Battery Voltage and Charging/Discharging Current Measurement.

DS22226A-page 31

MCP3426/7/8

Figure 6-6, shows an example of using the MCP3428

for

four-channel

thermocouple

temperature

measurement applications.

Thermocouple Sensor

Isothermal Block

MCP9800

MCP3428

MCP9800

1

2

CH1+

CH1-

14

13

12

11

CH4-

SDA

SCL

SDA

CH4+

CH3-

SCL

3 CH2+

CH2-

4

CH3+

Adr1

Adr0

SCL

5 V_SS

10

9

8

V_DD

0.1 µF

10 µF

V_DD

6

7

SDA

MCP9800

SDA

Heat

SCL

SDA

SCL

TO MCU

SDA

(MASTER)

5 kΩ

V_DD

FIGURE 6-6:

Four-Channel Thermocouple Applications.

With Type

K

thermocouple, it can measure

EQUATION 6-1:

temperature from 0°C to +1250°C degrees. The full

scale output range of the Type K thermocouple is

about 50 mV. This provides 40 µV/°C (= 50 mV/

1250°C) of measurement resolution. Equation 6-1

shows the measurement budget for sensor signal using

the MCP3426/7/8 device with 16 bits and PGA = 8

settings. With this configuration, the MCP3428 can

detect the input signal level as low as approximately

7.8 µV. By setting the internal PGA option to x8, the

40 µV/°C input from the thermocouple is amplified

internally to 320 µV/°C before the conversion takes

place. This results in about 5 LSB output codes per

1°C of change in temperature, with 16-bit conversion

mode.

Detectable Input Signal Level = 62.5μV/PGA

= 7.8125μV for PGA = 8

Input Signal Level after gain of 8:

= (40μV/°C) • 8 = 320μV/°C

320μV/°C

No. of LSB/°C = ------------------------ = 5.12 Codes/°C

62.5μV

Where:

1 LSB

=

62.5 µV with 16 bit configuration

DS22226A-page 32

MCP3426/7/8

Equation 6-2 shows an example of calculating the

expected number of output code with various PGA gain

settings for Type K thermocouple output.

EQUATION 6-2:

EXPECTED NUMBER OF

OUTPUT CODE FOR TYPE

K THERMOCOUPLE

Expected

Number of Output Code =

⎛

⎜

⎝

⎞

⎟

⎠

50 mV

-----------------

log₂

62.5μV

-----------------

PGA

ln(800 • PGA)

⎛

⎝

⎞

⎠

=

-------------------------------------

ln(2)

= 9.6 bits for PGA = 1

= 10.6 bits for PGA = 2

= 11.6 bits for PGA = 4

= 12.6 bits for PGA = 8

Where:

1 LSB

=

62.5 µV with 16 Bit configuration.

V_DD

Pressure Sensor

(NPP301)

Pressure Sensor

(NPP301)

MCP3428

1

2

CH1+

CH1-

14

CH4-

13

12

CH4+

CH3-

V_IN

V_DD

3 CH2+

V_IN

CH2-

V_SS

V_DD

SDA

11

10

4

5

6

V_DD

CH3+

Adr1

V_DD

R₁

9

8

Adr0

SCL

0.1 µF

7

R₁

R₂

Thermistor

10 µF

TO MCU

(MASTER)

Thermistor

5 kΩ

V_DD

R₂

------------------

R₁+ R₂

V_IN

=

× V_DD

R₁and R₂= Voltage Divider

FIGURE 6-7:

Example of Pressure and Temperature Measurement.

DS22226A-page 33

MCP3426/7/8

Figure 6-7 shows an example of measuring both

pressure and temperature. The pressure is measured

by using NPP 301 (manufactured by GE NovaSensor),

and temperature is measured by a thermistor. The

pressure sensor output is 20 mV/V. This gives 100 mV

of full scale output for VDD of 5V (sensor excitation

voltage). Equation 6-3 shows an example of calculating

the number of output code for the full scale output of the

NPP301.

EQUATION 6-3:

EXPECTED NUMBER OF

OUTPUT CODE FOR

NPP301 PRESSURE

SENSOR

⎛

⎜

⎝

⎞

⎟

⎠

Expected

Number of Output Code =

100 mV

--------------------

log₂

62.5μV

-----------------

PGA

ln(1600 • PGA)

⎛

⎝

⎞

⎠

=

----------------------------------------

ln(2)

= 10.6 bits for PGA = 1

= 11.6 bits for PGA = 2

= 12.6 bits for PGA = 4

= 13.6 bits for PGA = 8

Where:

1 LSB

=

62.5 µV with 16 Bit configuration.

The thermistor temperature sensor can measure the

temperature range from -100°C to +300°C. The

resistance of the thermistor sensor decreases as

temperature

increases

(negative

temperature

coefficient). As shown in Figure 6-7, the thermistor (R₂)

forms a voltage divider with R₁.

The thermistor sensor is simple to use and widely used

for the temperature measurement applications. It has

both linear and non-linear responses over temperature

range. R₁is used to adjust the linear region of interest

for measurement.

DS22226A-page 34

MCP3426/7/8

7.0

7.1

PACKAGING INFORMATION

Package Marking Information

Example:

8-Lead DFN (2x3) (MCP3426)

XXX

YWW

NN

ABX

945

25

Example:

8-Lead MSOP (MCP3426)

XXXXXX

3426A0

945256

YWWNNN

8-Lead SOIC (300 mil) (MCP3426)

Example:

3426A0E

XXXXXXXX

XXXXYYWW

e

3

SN^^0945

256

NNN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22226A-page 35

MCP3426/7/8

Package Marking Information (Continued)

10-Lead DFN (3x3) (MCP3427)

Example:

1

2

3

4

5

10

9

1

10

9

XXXX

YYWW

NNN

3427

0945

256

2

3

4

5

8

7

6

Example:

10-Lead MSOP (MCP3427)

3427E

945256

XXXXXX

YWWNNN

14-Lead SOIC (150 mil) (MCP3428)

Example:

MCP3428

E/SL^^

XXXXXXXXXXX

e

3

YYWWNNN

0945256

14-Lead TSSOP (4.4 mm) (MCP3428)

Example:

XXXXXXXX

YYWW

MCP3428E

0945

NNN

256

DS22226A-page 36

MCP3426/7/8

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/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

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DS22226A-page 37

MCP3426/7/8

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DS22226A-page 38

MCP3426/7/8

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢖꢋꢌ(ꢒꢆ)"ꢄꢈꢈꢆ*ꢎꢊꢈꢋ+ꢃꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖ)ꢘꢆ%ꢖ)*ꢇ&

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DS22226A-page 39

MCP3426/7/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22226A-page 40

MCP3426/7/8

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,

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7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

0ꢎꢇ&$ꢉꢊꢅAꢌꢑ%ꢃꢌꢄꢇꢈB

2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ

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2ꢌꢌ%ꢑꢊꢃꢄ%

2ꢌꢌ%ꢅꢔꢄꢐꢈꢉ

5ꢉꢇ"ꢅꢗꢎꢃꢍ*ꢄꢉ

5ꢉꢇ"ꢅ;ꢃ"%ꢎ

ꢖꢌꢈ"ꢅꢓꢊꢇ$%ꢅꢔꢄꢐꢈꢉꢅꢗꢌꢑ

ꢖꢌꢈ"ꢅꢓꢊꢇ$%ꢅꢔꢄꢐꢈꢉꢅ/ꢌ%%ꢌ&

5ꢀ

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ꢀꢁꢚꢒꢅꢘ,2

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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢟꢅꢕꢃꢐꢄꢃ$ꢃꢍꢇꢄ%ꢅ0ꢎꢇꢊꢇꢍ%ꢉꢊꢃ %ꢃꢍꢁ

+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢝꢚ.ꢜ/

DS22226A-page 41

MCP3426/7/8

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ)"ꢄꢈꢈꢆ*ꢎꢊꢈꢋ+ꢃꢆꢕ)ꢑꢘꢆMꢆꢑꢄ((ꢒ,ꢐꢆꢛ !ꢜꢆ""ꢆ#ꢒꢅ$ꢆ%)*-ꢗ&

ꢑꢒꢊꢃ' 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

DS22226A-page 42

MCP3426/7/8

.ꢜꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢘꢆMꢆꢛꢚꢛꢚꢜ !ꢆ""ꢆ#ꢒꢅ$ꢆ%ꢍꢏꢑ&

ꢑꢒꢊꢃ' 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

e

b

N

L

K

E

E2

EXPOSED

PAD

NOTE 1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

A1

A3

NOTE 2

4ꢄꢃ%

ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢖꢙ6

67ꢖ

ꢀꢚ

ꢚꢁ.ꢚꢅ/ꢕ0

ꢚꢁꢛꢚ

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

7ꢆꢉꢊꢇꢈꢈꢅ:ꢉꢃꢐꢎ%

ꢕ%ꢇꢄ"ꢌ$$ꢅ

0ꢌꢄ%ꢇꢍ%ꢅꢗꢎꢃꢍ*ꢄꢉ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ5ꢉꢄꢐ%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ;ꢃ"%ꢎ

6

ꢉ

ꢔ

ꢔꢀ

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ꢀꢁꢚꢚ

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ꢏꢁ+.

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ꢀꢁ.9

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ꢚꢁꢒꢚ

M

ꢏꢁꢏꢚ

ꢏꢁꢒ9

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ;ꢃ"%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ;ꢃ"%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ5ꢉꢄꢐ%ꢎ

0ꢌꢄ%ꢇꢍ%ꢝ%ꢌꢝ,#ꢑꢌ ꢉ"ꢅꢂꢇ"

,ꢏ

(

5

ꢀꢁꢒꢚ

ꢚꢁꢀ9

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M

=

ꢑꢒꢊꢃꢉ'

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢂꢇꢍ*ꢇꢐꢉꢅ&ꢇꢋꢅꢎꢇꢆꢉꢅꢌꢄꢉꢅꢌꢊꢅ&ꢌꢊꢉꢅꢉ#ꢑꢌ ꢉ"ꢅ%ꢃꢉꢅ(ꢇꢊ ꢅꢇ%ꢅꢉꢄ" ꢁ

+ꢁ ꢂꢇꢍ*ꢇꢐꢉꢅꢃ ꢅ ꢇ)ꢅ ꢃꢄꢐ!ꢈꢇ%ꢉ"ꢁ

ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢝꢚ>+/

DS22226A-page 43

MCP3426/7/8

.ꢜꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢘꢆMꢆꢛꢚꢛꢚꢜ !ꢆ""ꢆ#ꢒꢅ$ꢆ%ꢍꢏꢑ&

ꢑꢒꢊꢃ' 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

DS22226A-page 44

MCP3426/7/8

.ꢜꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢖꢋꢌ(ꢒꢆ)"ꢄꢈꢈꢆ*ꢎꢊꢈꢋ+ꢃꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕ/ꢑꢘꢆ%ꢖ)*ꢇ&

ꢑꢒꢊꢃ' 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

N

E

E1

NOTE 1

1

2

b

e

c

A

A2

φ

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ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

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ꢂꢃ%ꢍꢎ

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ꢚꢁ.ꢚꢅ/ꢕ0

7ꢆꢉꢊꢇꢈꢈꢅ:ꢉꢃꢐꢎ%

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ꢕ%ꢇꢄ"ꢌ$$ꢅ

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7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ

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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢝꢚꢏꢀ/

DS22226A-page 45

MCP3426/7/8

.0ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ)"ꢄꢈꢈꢆ*ꢎꢊꢈꢋ+ꢃꢆꢕ)ꢂꢘꢆMꢆꢑꢄ((ꢒ,ꢐꢆꢛ !ꢜꢆ""ꢆ#ꢒꢅ$ꢆ%)*-ꢗ&

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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

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ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢝꢚ>./

DS22226A-page 46

MCP3426/7/8

ꢑꢒꢊꢃ' 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

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DS22226A-page 47

MCP3426/7/8

.0ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ12ꢋ+ꢆ)2(ꢋ+ꢓꢆ)"ꢄꢈꢈꢆ*ꢎꢊꢈꢋ+ꢃꢆꢕ)1ꢘꢆMꢆ0 0ꢆ""ꢆ#ꢒꢅ$ꢆ%1))*ꢇ&

ꢑꢒꢊꢃ' 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

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ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

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7ꢆꢉꢊꢇꢈꢈꢅ:ꢉꢃꢐꢎ%

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ꢕ%ꢇꢄ"ꢌ$$ꢅ

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2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ

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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

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+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢝꢚ9ꢜ/

DS22226A-page 48

MCP3426/7/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22226A-page 49

MCP3426/7/8

NOTES:

DS22226A-page 50

MCP3426/7/8

APPENDIX A: REVISION HISTORY

Revision A (December 2009)

• Original Release of this Document.

DS22226A-page 51

MCP3426/7/8

NOTES:

DS22226A-page 52

MCP3426/7/8

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

-X

/XX

a)

MCP3426A0-E/MC: 2-Channel ADC,

Temperature Package

Range

8LD DFN package.

MCP3426A0T-E/MC: Tape and Reel,

2-Channel ADC,

b)

8LD DFN package.

Device:

MCP3426: 2-Channel 16-Bit ADC

MCP3426T: 2-Channel 16-Bit ADC

(Tape and Reel)

MCP3427: 2-Channel 16-Bit ADC

MCP3427T: 2-Channel 16-Bit ADC

(Tape and Reel)

MCP3428: 4-Channel 16-Bit ADC

MCP3428T: 4-Channel 16-Bit ADC

(Tape and Reel)

c)

d)

MCP3426A0-E/MS: 2-Channel ADC,

8LD MSOP package.

MCP3426A0T-E/MS: Tape and Reel,

2-Channel ADC,

8LD MSOP package.

e)

f)

MCP3426A0-E/SN: 2-Channel ADC,

8LD SOIC package.

MCP3426A0T-E/SN: Tape and Reel,

2-Channel ADC,

Temperature Range:

Package:

E

=

-40°C to +125°C

8LD SOIC package.

a)

b)

MCP3427-E/MF:

MCP3427T-E/MF:

2-Channel ADC,

10LD DFN package.

Tape and Reel,

2-Channel ADC,

10LD DFN package.

2-Channel ADC,

MC

MS

SN

MF

UN

SL

=

Plastic Dual Flat, No Lead (2x3 DFN), 8-lead

Plastic Micro Small Outline (MSOP), 8-lead

Plastic Small Outline SOIC, 8-lead

Plastic Dual Flat, No Lead (3x3 DFN) 10-lead

Plastic Micro Small Outline (MSOP), 10-lead

Plastic Small Outline SOIC (150 mil Body), 14-lead

Plastic TSSOP (4.4mm Body), 14-lead

ST

c)

d)

MCP3427-E/UN:

MCP3427T-E/UN:

10LD MSOP package.

Tape and Reel,

2-Channel ADC,

10LD MSOP package.

a)

b)

MCP3428-E/SL:

MCP3428T-E/SL:

4-Channel ADC,

14LD SOIC package.

Tape and Reel,

4-Channel ADC,

14LD SOIC package.

4-Channel ADC,

14LD TSSOP package.

Tape and Reel,

c)

d)

MCP3428-E/ST:

MCP3428T-E/ST:

4-Channel ADC,

14LD TSSOP package.

DS22226A-page 53

MCP3426/7/8

NOTES:

DS22226A-page 54

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, PIC³²logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, UniWinDriver, WiperLock and ZENA

are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22226A-page 55

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS22226A-page 56


型号：	MCP3428-EMF
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	16-Bit, Multi-Channel Analog-to-Digital Converter with I2C Interface and On-Board Reference 16位，多通道模拟数字转换器，带有I2C接口，并板载参考转换器
文件：	总56页 (文件大小：944K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP3428-EMF [MAXIM]

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