MX7534TD [MAXIM]
Microprocessor-Compatible, 14-Bit DACs; 微处理器兼容， 14位DAC
| 型号： | MX7534TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Microprocessor-Compatible, 14-Bit DACs |
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1116; Rev 1; 11/96
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 14-Bit Monotonic Over Full Temperature Range
♦ Full 4-Quadrant Multiplication
The MX7534/MX7535 are high-performance, CMOS,
monolithic, 14-bit digital-to-analog converters (DACs).
Wafer-level, laser-trimmed, thin-film resistors and tempera-
ture-compensated NMOS switches assure operation over
the full operating temperature range with exceptional lin-
ear and gain stability.
♦ µP-Compatible, Double-Buffered Inputs
♦ Exceptionally Low Gain Tempco (2.5ppm/°C)
♦ Low Output Leakage (<20nA) Over Temp.
♦ Low Power Consumption
The MX7534 accepts right-justified data in two bytes from
an 8-bit bus, while the MX7535 operates with a 14-bit data
bus with separate MS-byte and LS-byte select controls. In
addition, all digital inputs are compatible with both TTL and
5V CMOS-logic levels. The MX7534/MX7535 are intended
for unipolar operation, but may be operated as bipolar
DACs with additional external components. Both devices
are protected against CMOS latchup, and neither requires
the use of external Schottky protection diodes.
♦ TTL and CMOS Compatible
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE PIN-PACKAGE INL (LSBs)
MX7534KN
MX7534JN
MX7534KCWP
MX7534JCWP
MX7534KP
MX7534JP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
20 Plastic DIP
20 Plastic DIP
20 SO
±1
±2
±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
±1
±2
±1
±2
20 SO
The MX7534 is available in 20-pin narrow (0.3") DIP, wide
SO, or PLCC packages. The MX7535 is available in
28-pin, 600 mil wide DIP, wide SO, or PLCC packages.
20 PLCC
20 PLCC
MX7534J/D
MX7534BQ
MX7534AQ
MX7534BD
MX7534AD
Dice*
20 CERDIP
20 CERDIP
20 Ceramic SB
20 Ceramic SB
20 SO
________________________Ap p lic a t io n s
Machine and Motion Control Systems
Automatic Test Equipment
Digital Audio
MX7534KEWP -40°C to +85°C
MX7534JEWP -40°C to +85°C
20 SO
µP-Controlled Calibration Circuitry
Programmable-Gain Amplifiers
Digitally Controlled Filters
MX7534TQ
MX7534SQ
MX7534TD
MX7534SD
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
20 CERDIP
20 CERDIP
20 Ceramic SB
20 Ceramic SB
Programmable Power Supplies
Ordering Information continued at end of data sheet.
*Dice are tested at +25°C, DC parameters only.
_________________P in Co n fig u ra t io n s
_______________Fu n c t io n a l Dia g ra m s
TOP VIEW
REF
RFB
1
2
3
4
5
6
7
8
9
20
19
V
SS
V
DD
19
MX7534
V
DD
2
3
RFB
IOUT
1
IOUT
AGNDS
AGNDF
DGND
D7
18 CS
14-BIT DAC
REF
4
5
17 WR
AGNDS
AGNOF
14
MX7534
DAC REGISTER
A0
A1
D0
D1
16
15
14
13
8
6
MS
15
16
18
17
LS
A1
CONTROL
LOGIC
INPUT
INPUT
A0
CS
REGISTER
REGISTER
D6
D5
12 D2
11 D3
WR
D4 10
6
20
SS
7–14
D7–D0
DGND
V
DIP/SO/PLCC/Ceramic SB
Functional diagrams continued at end of data sheet.
MX7535 at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
ABSOLUTE MAXIMUM RATINGS
DD
V
to DGND ............................................................-0.3V, +17V
to AGND .............................................................-15V, +0.3V
28-Pin PLCC (derate 10.53mW/°C above +70°C) .........842mW
20-Pin CERDIP (derate 11.11mW/°C above +70°C)......889mW
28-Pin CERDIP (derate 16.67mW/°C above +70°C)........1.33W
20-Pin Ceramic SB
(derate 11.76mW/°C above +70°C).............................941mW
28-Pin Ceramic SB
V
SS
REF to AGND (MX7534) ......................................................±25V
REFS to AGND (MX7535) ....................................................±25V
REFF to AGND (MX7535) ....................................................±25V
RFB to AGND.......................................................................±25V
Digital Input Voltage to DGND.........................-0.3V, V + 0.3V
(derate 20.00mW/°C above +70°C)................................1.6W
Operating Temperature Ranges
DD
IOUT to DGND.................................................-0.3V, V + 0.3V
DD
AGND to DGND...............................................-0.3V, V + 0.3V
MX753_J/K............................................................0°C to +70°C
MX753_A/B ........................................................-25°C to +85°C
MX753_EW_.......................................................-40°C to +85°C
MX753_S/T.......................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
Continuous Power Dissipation (T = +70°C)
A
20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW
28-Pin Plastic DIP (derate 14.29mW/°C above +70°C)......1.14W
20-Pin SO (derate 10.00mW/°C above +70°C)..............800mW
28-Pin SO (derate 12.50mW/°C above +70°C).....................1W
20-Pin PLCC (derate 10.00mW/°C above +70°C) .........800mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
4/MX735
ELECTRICAL CHARACTERISTICS
(V = +11.4V to +15.75V (Note 1), V
= 10V, V
= V
= V = 0V, T = T
to T , unless otherwise noted.)
MAX
DD
REF
IOUT
AGNDS
SS
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
14
Bits
LSB
LSB
MX753_K/B/T
MX753_J/A/S
±1
±2
±1
Relative Accuracy
INL
Differential Nonlinearity
Guaranteed Monotonic
Measured with internal R
includes effects of leakage
current and gain TC
,
FB MX753_K/B/T
±4
±8
Full-Scale Error
LSB
MX753_J/A/S
MX753_K/B/T
MX753_J/A/S
±0.5
±0.5
±2.5
±5
Gain Temperature Coefficient
(Note 2)
ppm/°C
All digital
inputs at 0V
T
A
= +25°C
±5
Output Leakage Current
I
nA
OUT
All digital
inputs at 0V,
MX753_J/K/A/B
MX753_S/T
±25
T
to T
= T
A
MIN
MAX
±150
V
SS
= 0V
REFERENCE INPUT
Reference Voltage Input
Resistance (Note 3)
R
3.5
2.4
6
10
kΩ
REF
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
V
V
V
INH
V
0.8
±1
±10
7
INL
T
= +25°C
A
Digital inputs
at 0V or V
Input Leakage Current
µA
pF
DD
T
A
= T
to T
MIN MAX
Input Capacitance (Note 2)
C
IN
2
_______________________________________________________________________________________
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
ELECTRICAL CHARACTERISTICS (continued)
(V = +11.4V to +15.75V (Note 1), V
= 10V, V
= V
= V = 0V, T = T
to T , unless otherwise noted.)
MAX
DD
REF
IOUT
AGNDS
SS
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Positive Supply-Voltage Range
Negative Supply-Voltage Range
V
For specific performance
For specific performance
11.4
-200
15.75
-500
3
V
DD
V
SS
mV
MX7534
MX7535
Digital inputs at
Positive Supply Current
Negative Supply Current
I
DD
mA
µA
V
INH
or V
INL
4
I
SS
Digital inputs at 0V or V
500
DD
Note 1: Specifications are guaranteed for V of +11.4V to +15.75V. At V = +5V, device is still functional with degraded specifications.
DD
DD
Note 2: Guaranteed by design, not tested.
Note 3: Resistors have a typical -300ppm/°C tempco.
AC PERFORMANCE CHARACTERISTICS (Note 4)
(V = +11.4V to +15.75V, V
= 10V, V
= V
(V
for MX7535) = V = 0V, output amplifier is AD544*,
DD
REF
IOUT
AGND AGNDS SS
T
A
= T
to T , unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
= +25°C, to 0.003% of full-scale range,
MIN
TYP
MAX
UNITS
T
A
Output Current Setting Time
IOUT load = 100Ω 13pF, DAC register
alternately loaded with all 1s and all 0s
0.8
1.5
µs
II
Measured with V
= 0V,
REF
Digital-to-Analog Glitch Impulse
IOUT loads = 100Ω 13pF, DAC register
alternately loaded with all 1s and all 0s
50
nV-sec
mVp-p
II
V
REF
= ±10V, 10kHz
T
A
= +25°C
3
5
Multiplying Feedthrough Error
(Note 5)
sine wave, DAC register
loaded with all 0s
T
A
= T
to T
MIN
MAX
MAX
T
= +25°C
±0.01
±0.02
260
A
Power-Supply Rejection
∆V = ±5%
DD
%/%
pF
T
A
= T
to T
MIN
DAC register loaded with all 1s
DAC register loaded with all 0s
Output Capacitance (IOUT Pin)
C
OUT
130
Output Noise Voltage Density
(10Hz–100kHz)
Measured between R and I
15
nV/Hz
FB
OUT
Note 4: These characteristics are included for design guidance only, and are not subject to test.
Note 5: Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
* AD544 is an Analog Devices part.
_______________________________________________________________________________________
3
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
TIMING CHARACTERISTICS (MX7534)
(V = +11.4V to +15.75V, V
= 10V, V
= V
= V = 0V, T = T
to T , unless otherwise noted. See Figure 1a for
MAX
DD
REF
IOUT
AGND
SS
A
MIN
timing diagram.)
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
Address Valid to Write Setup Time
Address Valid to Write Hold Time
t
1
2
t
0
ns
T
= +25°C
60
70
80
20
20
30
0
A
Data Setup Time
Data Hold Time
t
T
A
= -25°C to +85°C
= -55°C to +125°C
= +25°C
ns
ns
3
4
T
A
T
A
t
T
A
= -25°C to +85°C
= -55°C to +125°C
T
A
Chip-Select to Write-Setup Time
Chip-Select to Write-Hold Time
t
t
ns
ns
5
7
0
6
T
= +25°C
170
200
240
A
Write Pulse Width
t
7
T
A
= -25°C to +85°C
= -55°C to +125°C
ns
T
A
TIMING CHARACTERISTICS (MX7535)
(V = +11.4V to +15.75V, V
= 10V, V
= V
= V = 0V, T = T
to T , unless otherwise noted. See Figure 1b for
MAX
DD
REF
IOUT
AGNDS
SS
A
MIN
timing diagram.)
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
t
1
CSMSB or CSLSB to WR Setup Time
CSMSB or CSLSB to WR Hold Time
t
2
0
ns
T
= +25°C
170
200
240
170
200
240
140
160
180
20
A
t
T
A
= -25°C to +85°C
= -55°C to +125°C
= +25°C
ns
ns
ns
ns
LDAC Pulse Width
Write Pulse Width
Data-Setup Time
Data-Hold Time
3
T
A
T
A
t
4
t
5
t
6
T
A
= -25°C to +85°C
= -55°C to +125°C
= +25°C
T
A
T
A
T
A
= -25°C to +85°C
= -55°C to +125°C
= +25°C
T
A
T
A
T
= -25°C to +85°C
= -55°C to +125°C
20
A
T
A
30
4
_______________________________________________________________________________________
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
__________P in De s c rip t io n (MX7 5 3 4 )
__________P in De s c rip t io n (MX7 5 3 5 )
PIN
1
NAME
REFS
REFF
FUNCTION
Reference Voltage Sense
Reference Voltage Force
PIN
NAME
FUNCTION
REF
Reference Input to DAC
1
2
Feedback Resistor. Used to close the
loop around an external op amp.
2
3
RFB
Feedback Resistor. Used to close the
loop around an external op amp.
3
4
RFB
IOUT
Current Output
IOUT
Current Output
Analog Ground Sense. Reference
point for external circuitry. AGNDS
should carry minimum current.
4
AGNDS
Analog Ground Sense. Reference
point for external circuitry. This pin
should carry minimum current.
5
AGNDS
Analog Ground Force. Carries current
from internal analog ground connec-
tions. AGNDS and AGNDF are tied
together internally.
Analog Ground Force. Carries current
from internal analog ground
connections. AGNDS and AGNDF
are tied together internally.
5
AGNDF
6
AGNDF
6
DGND
D7
Digital Ground
7
Data Bit 7
7
DGND
D13
D12
D11
D10
D9
Digital Ground
Data Bit 13 (MSB)
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
8
D6
Data Bit 6
8
9
D5
Data Bit 5 or Data Bit 13 (MSB)
Data Bit 4 or Data Bit 12
Data Bit 3 or Data Bit 11
Data Bit 2 or Data Bit 10
Data Bit 1 or Data Bit 9
Data Bit 0 (LSB) or Data Bit 8
Address Input 1
9
10
11
12
13
14
15
16
17
18
19
D4
10
11
12
13
14
15
16
17
18
19
20
21
D3
D2
D1
D8
Data Bit 8
D0
D7
Data Bit 7
A1
D6
Data Bit 6
A0
Address Input 0
D5
Data Bit 5
Write Input. Active low.
Chip-Select Input. Active low.
+12V to +15V Supply-Voltage Input
WR
CS
D4
Data Bit 4
D3
Data Bit 3
V
DD
D2
Data Bit 2
D1
Data Bit 1
Bias pin for high-temperature,
low-leakage configuration
20
V
SS
D0
Data Bit 0 (LSB)
Chip-Select Most Significant Byte.
Active low.
22
23
24
CSMSB
LDAC
Asynchronous Load DAC Input.
Active low.
Chip-Select Least Significant Byte.
Active low.
CSLSB
WR
25
26
Write Input. Active low.
V
DD
+12V to +15V Supply-Voltage Input
Bias pin for high-temperature,
low-leakage configuration
27
28
V
SS
N.C.
No Connection. Not internally connected.
_______________________________________________________________________________________
5
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
t
1
t
2
t
1
t
2
5V
0V
CSMSB
CSLSB
LDAC
t
1
A0,A1
t
2
t
3
t
4
5V
0V
5V
0V
t
3
5V
0V
DATA
CS
t
5
t
6
5V
0V
t
4
t
4
5V
0V
WR
t
7
5V
0V
t
6
t
6
t
5
t
5
WR
5V
0V
DATA
NOTES:
1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90%
OF +5V. t = t = 20ns.
4/MX735
NOTES:
1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90%
OF +5V. t = t = 20ns.
R
F
V + V
IH
IL
2) TIMING MEASUREMENT REFERENCE LEVEL IS
R
F
2
V + V
IH
IL
2) TIMING MEASUREMENT REFERENCE LEVEL IS
3) IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR, THEN IT MUST
STAY LOW FOR t OR LONGER AFTER WR GOES HIGH.
3
2
Figure 1a. MX7534 Timing Diagram
Figure 1b. MX7535 Timing Diagram
g(V ,N) is the Thevenin equivalent voltage generator
REF
_______________De t a ile d De s c rip t io n
due to the reference input voltage, V , and the trans-
REF
Dig it a l-t o -An a lo g S e c t io n
fer function of the R-2R ladder, N.
The basic MX7534/MX7535 digital-to-analog converter
(DAC) circuit consists of a laser-trimmed, thin-film,
11-bit R-2R resistor array, a 3-bit segmented resistor
array, and NMOS current switches, as shown in Figure
2. The three MSBs are decoded to drive switches A–G
of the segmented array, and the remaining bits drive
switches S0–S10 of the R-2R array.
Dig it a l S e c t io n
All digital inputs are both TTL and 5V CMOS logic compat-
ible. The digital inputs are protected from electrostatic dis-
charge (ESD) with typical input currents of less than 1nA.
To minimize power-supply currents, keep digital input volt-
ages as close to 0V and 5V logic levels as possible.
Binary weighted currents are switched to either AGNDF
__________Ap p lic a t io n s In fo rm a t io n
or I , depending on the status of each input bit. The
OUT
Un ip o la r Op e ra t io n (2 -Qu a d ra n t
Mu lt ip lic a t io n )
Figures 4a and 4b show the circuit diagram for unipolar
binary operation. With an AC input, the circuit performs
2-quadrant multiplication. The code table for Figure 4 is
given in Table 2.
R-2R ladder current is one-eighth of the total reference
input current. The remaining seven-eighths of the cur-
rent flows in the segmented resistors, dividing equally
among these seven resistors. The input resistance at
REF is constant; therefore, it can be driven by a voltage
or current source of positive or negative polarity.
The MX7534/MX7535 are optimized for unipolar output
Capacitor C1 provides phase compensation and helps
prevent overshoot and ringing when high-speed op
amps are used. Note that the output polarity is the
inverse of the reference input.
operation (analog output from 0V to -V
), although
REF
bipolar operation (analog output from +V
to -V ) is
REF
REF
possible with some added external components.
Figure 3 shows the equivalent circuit for the two DACs.
C
varies from about 90pF to 180pF, depending on
OUT
the digital code. R denotes the DAC’S equivalent out-
0
p ut re s is ta nc e , whic h va rie s with the inp ut c od e .
6
_______________________________________________________________________________________
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
R
R
R
REFS*
REFF*
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
R/4
G
F
E
D
C
B
A
S10
S9
S0
RFB
IOUT
AGNDS
AGNDF
*NOTE: VALID FOR MX7535. IN MX7534, 0REFS AND 0REFF ARE REPLACED BY ONE PIN: REF.
Figure 2. Simplified Circuit Diagram
Ze ro -Offs e t Ad ju s t m e n t
(Fig u re s 4 a a n d 4 b )
1) Load the DAC register with all 0s.
R/4
RFB
R
O
2) Adjust the offset of amplifier A1 so that V (see fig-
0
IOUT
ure) is at a minimum (i.e., ≤ 30µV).
+
–
Ga in Ad ju s t m e n t
(Fig u re s 4 a a n d 4 b )
g(V , N)
REF
C
OUT
I
LEAKAGE
1) Load the DAC register with all 1s.
16383
AGNDS
AGNDF
2) Trim potentiometer R1 so that V
= -V
IN
OUT
(
)
16384
In fixed-reference applications, adjust full scale by
omitting R1 and R2 and trimming the reference voltage
magnitude. In many applications, the excellent Gain
Tempco and Gain Error specifications eliminate the
ne e d for g a in a d jus tme nt. Howe ve r, if trims a re
required and the DAC is to operate over a wide temper-
ature range, use low-tempco (>300ppm/°C) resistors.
Figure 3. Equivalent Analog Output Circuit
Table 1. MX7534 Logic States
WR
CS
A1
A2
FUNCTION
X
1
X
X
Device not selected (Note 1)
No data transfer
1
X
X
X
Bip o la r Op e ra t io n
(4 -Qu a d ra n t Mu lt ip lic a t io n )
Bipolar or 4-quadrant operation is shown in Figures 5a
and 5b. This configuration provides for offset binary
c od ing . Ta b le 4 s hows DAC c od e s a nd the c orre -
sponding analog outputs for Figures 5a and 5b. With
the DAC loaded to 10 0000 0000 0000, either adjust R1
DAC loaded directly from
Data Bus (Note 2)
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
MS Input Register loaded
from Data Bus
LS Input Register loaded
from Data Bus
for V
= 0V, or omit R1 and R2 and adjust the ratio of
OUT
DAC Register loaded from
Input Registers
R5 and R6 for V
= 0V. Adjust the amplitude of V
OUT
IN
or vary the value of R7 for full-scale trimming.
Resistors R5, R6, and R7 must be matched to 0.003%.
Mismatch of R5 and R6 causes both offset and full-
scale errors. For wide temperature range operation,
use resistors of the same material so that their tempera-
ture coefficients match and track.
Note 1: X = Don’t Care.
Note 2: When A1 = 0 and A0 = 0, all DAC registers are trans-
parent. By placing all 0s or all 1s on the data inputs, the
user can load the DAC to zero or full-scale output in
one write operation. This simplifies system calibration.
_______________________________________________________________________________________
7
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
R1
20Ω
R2
10Ω
R1
100Ω
V
DD
V
IN
V
R2
33Ω
IN
1
19
2
2
1
26
3
C1
33pF
C1
33pF
REF
RFB
REFF
RFB
REFS
V
DD
16
15
23
22
A0
A1
LDAC
3
4
IOUT
CSMSB
IOUT
A1
18
17
A1
25
24
MX7534
4
MX7535
CS
AGNDS
5
AGNDS
WR
WR
V
O
5
AGNDF
SS
CSLSB
V
O
6
AGNDF
SS
D7–D0
DGND
6
V
D13–DO DGND
8–21
V
7–14
20
7
27
ANALOG
GROUND
ANALOG
GROUND
INPUT
DATA
INPUT
DATA
Figure 4b. Unipolar Binary Operation
Figure 4a. Unipolar Binary Operation
4/MX735
Gro u n d in g Co n s id e ra t io n s
Table 2. Unipolar Binary Code Table
Since IOUT and the output amplifier noninverting input
are sensitive to offset voltages, connect nodes that
must be grounded directly to a single-point ground
through a separate, very-low-resistance path. Note that
the output currents at IOUT and AGNDF vary with input
code and create code-dependent error if these termi-
nals are connected to ground (or a virtual ground)
through a resistive path.
BINARY NUMBER IN
DAC REGISTER
ANALOG OUTPUT
(V
OUT)
MSB
11
LSB
1111 -V
16383
16384
8192
16384
1111
0000
0000
0000
1111
0000
0000
0000
IN
(
(
(
)
)
)
1
2
10
00
00
0000 -V
= -
V
IN
IN
1
0001 -V
IN
To obtain high accuracy, it is important to use a proper
grounding technique. The two AGND pins (AGNDF‚
AGNDS) provide flexibility in this respect. In Figures 4a
a nd 4b , AGNDS a nd AGNDF a re s horte d tog e the r
e xte rna lly a nd a n e xtra op a mp , A2, is not us e d .
Volta ge -drops due to bond-wire re sista nc e a re not
compensated for in this circuit; this could create a lin-
earity error of approximately 0.1LSB due to bond-wire
resistance alone. This can be eliminated by using the
circuits shown in Figures 6a and 6b, where A2 main-
ta ins AGNDS a t s ig na l g round p ote ntia l. By us ing
force/sense techniques, all switch contacts on the DAC
are kept at exactly the same potential, and any error
caused by bond-wire resistance is eliminated.
16384
0000 0V
feedthrough. The traces connecting IOUT and AGNDS
to the inverting and noninverting op amp inputs are
kept as short as possible. Gain trim components, R3
and R4, are omitted.
Ze ro -Offs e t Ad ju s t m e n t
(Fig u re s 6 a a n d 6 b )
1) Load DAC register with all 0s.
2) Adjust offset of amplifier A2 for minimum potential at
AGNDS. This potential should be ≤30µV with respect
to signal ground.
Figure 7 shows a remote voltage reference driving the
MX7535. Op amps A2 and A3 compensate for voltage
d rop s a long the re fe re nc e inp ut line a nd a na log
ground line.
3) Adjust A1’s offset so that V
is at a minimum
OUT
(i.e., ≤30µV).
Figure 8 shows a printed circuit board (PCB) layout with
a single output amplifier for the MX7534. The input to
REF (Pin 1) is shielded to reduce AC feedthrough, while
the d ig ita l inp uts a re s hie ld e d to minimize d ig ita l
8
_______________________________________________________________________________________
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
V
IN
V
IN
R2 10Ω
R1
20Ω
V
DD
R2, 33Ω
V
R6
20k
DD
R1
100Ω
R6
20k
R7
20k
1
19
2
3
C1
33pF
C1
33pF
1
26
R7
20k
2
REF
RFB
REFF REFS RFB
16
23
22
A0
A1
LDAC
R5
10k
3
4
15
18
17
R5 10k
IOUT
CSMSB
IOUT
AGNDS
A1
A1
25
24
MX7534
MX7535
AGNDS
+
CS
+
WR
A2
R8, 5k,10%
A2
R8, 5k,10%
4
5
+
WR
AGNDF
AGNDF
CSLSB
+
V
O
V
O
D7–D0 DGND
6
V
5
D13–D0 DGND
SS
V
SS
6
20
7
27
7–14
8–21
ANALOG
GROUND
ANALOG
GROUND
INPUT
DATA
INPUT
DATA
Figure 5a. Bipolar Operation
Figure 5b. Bipolar Operation
Ga in Ad ju s t m e n t
(Fig u re s 6 a a n d 6 b )
Table 3. MX7535 Logic States
1) Load DAC register with all 1s.
2) Trim potentiometer R3 so that V
CSMSB CSLSB LDAC
WR
0
FUNCTION
16383
16384
= -
V
IN
OUT
(
)
0
1
1
0
1
1
Load MS Input Register
Load LS Input Register
0
Lo w -Le a k a g e Co n fig u ra t io n
Leakage current in the DAC flowing into the I line
can cause gain, linearity, and offset errors. Leakage is
worse at high temperatures.
Load LS and MS Input
Registers
0
1
0
0
1
0
1
0
0
0
OUT
Load DAC Register
from Input Register
X
0
Negatively bias V for a high-temperature, low-leakage
SS
configuration.
All registers are
transparent.
Dyn a m ic Co n s id e ra t io n s
1
1
1
1
X
1
No operation
No operation
In static or DC applications, the output amplifier’s AC
characteristics are not critical. In higher-speed applica-
tions, where either the reference input is an AC signal
or the DAC output must quickly settle to a new pro-
grammed value, the output op amp’s AC parameters
must be considered.
X
X
Note: X = Don’t Care.
Table 4. Offset Binary Bipolar Code Table
Another error source in dynamic applications is the par-
BINARY NUMBER IN
DAC REGISTER
Analog Output
(V
asitic signal coupling from the REF terminal to I
.
OUT
OUT)
This is normally a function of board layout and lead-to-
lead package capacitance. Signals can also be inject-
ed into the DAC outputs when the digital inputs are
switched. This digital feedthrough depends on circuit-
board layout and on-chip capacitive coupling. Minimize
layout-induced feedthrough with guard traces between
digital inputs, REF, and DAC outputs.
MSB
11
LSB
1111 +V
8191
8192
1
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
IN
(
(
)
)
10
10
01
00
0001 +V
IN
8192
0000
0
1
1111 -V
IN
(
(
)
)
8192
8192
8192
0000 -V
= -V
IN
IN
_______________________________________________________________________________________
9
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
V
DD
V
DD
R3
100Ω
R4
33Ω
R2
10Ω
C1
33pF
C1
33pF
R1
20Ω
1
19
2
2
1 26 3
V
DD
REF
RFB
V
DD
REFF REFS
RFB
3
A1
+
A1
4
5
IOUT
+
IOUT
V
IN
VOLTAGE
REFERENCE
MX7534
MX7535
AGNDS
5
R
L
V
O
AGNDS
AGNDF
V
O
R
L
4
AGNDF
SS
A2
D7–D0 DGND
6
A2
V
D13–D0 DGND
7
V
SS
6
+
+
20
27
7–14
8–21
SIGNAL
GROUND
INPUT
DATA
INPUT
DATA
SIGNAL
GROUND
ANALOG
GROUND
4/MX735
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
Figure 6a. Unipolar Binary Operation with Forced Ground
Figure 6b. Unipolar Binary Operation with Forced Ground for
Remote Load
Table 5. Amplifier Performance Comparisons
INPUT OFFSET
INPUT BIAS
CURRENT (I )
B
OFFSET VOLTAGE
SETTLING
TO 0.003% FS
OP AMP
VOLTAGE (V
)
DRIFT (TC V
0.3µV/°C
0.6µV/°C
5µV/°C
)
OS
OS
MAX400
10µV
2nA
2nA
50µs
50µs
5µs
Maxim OP07
AD554L*
HA2620*
25µV
500µV
4mV
25pA
35nA
20µV/°C
0.8µs
* AD544L is an Analog Devices part; HA2620 is a Harris Semiconductor part.
The MX7534/MX7535 ha ve hig h-imp e d a nc e d ig ita l
inp uts. To minimize noise p ic kup , c onne c t the m to
Co m p e n s a t io n
A compensation capacitor, C1, may be needed when
the DAC is used with a high-speed output amplifier.
The capacitor cancels the pole formed by the DAC’s
output capacitance and internal feedback resistance.
Its value depends on the type of op amp used, but typi-
cal values range from 10pF to 33pF. Too small a value
causes output ringing, while excess capacitance over-
damps the output. Minimize C1’s size and improve out-
put settling performance by keeping the PC board
trace as short as possible and stray capacitance at
either V
or GND terminals when not in use. Connect
DD
active inputs to V
or GND through high-value resis-
DD
tors (1MΩ) to prevent static charge accumulation if
these pins are left floating, as might be the case when
a circuit card is left unconnected.
Op -Am p S e le c t io n
Input offset voltage (V ), input bias current (I ), and
OS
B
offset voltage drift (TC V ) are three key parameters in
OS
determining the choice of a suitable amplifier. To main-
I
as small as possible.
OUT
tain specified accuracy with V
of 10V, V
should
REF
OS
be less than 30µV and I should be less than 2nA.
Op e n-loop g a in s hould b e g re a te r tha n 340,000.
Byp a s s in g
Place a 1µF bypass capacitor, in parallel with a 0.01µF
B
Ma xim’s MAX400 ha s low V
(10µV ma x), low I
OS
B
ceramic capacitor, as close to the DAC’s V and GND
DD
(2nA), and low TC V
(0.3µV/°C max). This op amp
OS
pins as possible. Use a 1µF tantalum bypass capacitor
to optimize high-frequency noise rejection. Place a
can be used without requiring any adjustments. For
4.7µF decoupling capacitor at V to minimize the DAC
SS
output leakage current.
10 ______________________________________________________________________________________
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
V+
V-
PIN 1 AD544*
V
DD
A2
+
2
1
26
3
C1
33pF
REFF REFS
V
DD
RFB
OUTPUT
4
IOUT
AGNDS
C1 LOCATION
A1
MX7535
+
V
0
5
R
L
AGNDF
D13–D0 DGND
7
V
REF
SS
6
V
SS
27
8–21
V
DD
INPUT
DATA
PIN 1 MX7534
A3
AGND
DGND
+
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
Figure 7. Driving the MX7535 with a Remote Voltage Reference
NOTE:
LAYOUT IS FOR DOUBLE-SIDED
PCB. BOLD LINE INDICATES
TRACK ON COMPONENT SIDE.
medium-frequency applications, the OP27 is recom-
mended. For higher-frequency applications, the HA-
2620 is re c omme nd e d . Howe ve r, the s e op a mp s
require external offset adjustment (Table 5).
*AD544 IS AN ANALOG DEVICES PART.
Figure 8. Suggested Layout for MX7534 Incorporating Output
Amplifier
________Mic ro p ro c e s s o r In t e rfa c in g
8 0 8 6 w it h MX7 5 3 5
14-bit word is loa d e d in two byte s, using the MOV
instruction. A further MOV loads the DAC register and
causes the analog data to appear at the converter out-
put. For the example given here, the appropriate DAC
register addresses are D002, D004, and D006. Table
6b shows the program for loading the DAC.
The MX7534/MX7535 interface to both 8-bit and 16-bit
processors. Figure 9a shows the 8086 16-bit processor
interfacing to a single MX7535. In this setup, the double-
buffering feature of the DAC is not used. AD0–AD13 of
the 16-bit data bus are connected to the DAC data bus
(D0–D13). The 14-bit word is written to the DAC in one
MOV instruction, and the analog output responds imme-
diately. In this example, the DAC address is D000. Table
6a shows a software routine for Figure 9a.
8 0 8 5 A w it h MX7 5 3 4
A typical interface circuit is shown in Figure 9c. The
DAC is treated as four memory locations addressed by
A0 and A1. In standard operation, three of these memo-
ry locations are used. Table 6c shows a sample pro-
g ra m for loa d ing the DAC with a 14-b it word . The
MX7534 has address locations 3000–3003.
In a multiple DAC system, the double buffering of the
DAC chips allows the user to simultaneously update all
DACs. In Figure 10, a 14-bit word is loaded to each of
the DAC’s input registers in sequence. Then, with one
instruction to the appropriate address, CS4 (i.e., LDAC)
is brought low, updating all the DACs simultaneously.
The six MSBs are written into location 3001, and eight
LSBs are written to 3002. Then, with a write instruction to
3003, the full 14-bit word is loaded to the DAC register.
8 0 8 6 w it h MX7 5 3 4
Figure 9b shows an interface circuit to a 16-bit micro-
processor. The bottom 8 bits (AD0–AD7) of the 16-bit
data bus are connected to the DAC data bus. The
______________________________________________________________________________________ 11
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
MC6 8 0 0 0 w it h MX7 5 3 5
Figure 11a shows an interface diagram. The following
routine writes data to the DAC input registers and then
outputs the data via the DAC register:
ADDRESS BUS
16-BIT
LATCH
ADDRESS
DECODE
CSMSB
CSLSB
LDAC
ALE
WR
01000 MOVE.W #W,D0
DAC d a ta , W, loa d e d
into Data Register 0.
8086
MOVE.W
D0,$E000 Da ta
W tra ns fe rre d
MX7535*
WR
between D0 and DAC
Register.
AD13
AD0
DATA BUS
D0–D13
AD0–AD15
MOVE.B #228,D7
TRAP #14
Control returned to the
System.
*SOME CIRCUITRY OMITTED FOR CLARITY
Monitor Program
MC6 8 0 0 0 w it h MX7 5 3 4
Figure 11b shows the MC68000 interface diagram. The
following routine writes data to the DAC input registers
and then outputs the data via the DAC register:
Figure 9a. MX7535—8086 Interface Circuit
4/MX735
.A2 E003
Ad d re s s Re g is te r 2
loaded with E003.
ADDRESS BUS
A2
A1
01000 MOVE.W #W,D0
DAC d a ta , W, loa d e d
into Data Register 0.
A1 A0
16-BIT
LATCH
ADDRESS
DECODE
CS
ALE
WR
MOVEP.W D0,$0000(A2) Da ta
W tra ns fe rre d
b e twe e n D0 a nd the
DAC’s Input Register.
High-ordered byte trans-
fe rre d firs t. Me mory
address specified using
the a d d re s s re g is te r
indirect plus displace-
ment addressing mode.
Ad d re s s us e d he re
(E003) is odd, so data is
transferred on the low-
ord e r ha lf of the d a ta
bus (D0–D7).
MX7534*
8086
WR
D0–D7
AD0–AD15
DATA BUS
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9b. MX7534—8086 Interface Circuit
MOVE.W D0,$E006
This instruction provides
appropriate signals to
tra ns fe r d a ta W from
the DAC Input Register
to the DAC Re g is te r,
which controls the R-2R
ladder switches.
A8–A15
AE
A1 A0
ADDRESS
DECODE
LATCH
CS
8085A
MX7534*
WR
WR
MOVE.B #228,D7
TRAP #14
Control returned to the
System.
AD0–AD7
DATA BUS
D0–D7
Monitor Program
Since this interfacing system uses only the lower half of
the d a ta b us , it is a ls o s uita b le for us e with the
MC68008, which provides the user with an 8-bit data
bus instead of the MC68000’s 16-bit bus.
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9c. MX7534—8085A Interface Circuit
12 ______________________________________________________________________________________
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
Table 6a. Sample Program for Loading the MX7535
ASSUME DS:DACLOAD,CS:DACLOAD
DACLOAD SEGMENT AT 000
00
02
04
07
0B
0E
8CC9
8ED9
BF00D0
MOV CX,CS
MOVDS,CX
MOVDI,#D000
:DEFINE DATA SEGMENT REGISTER EQUAL
:TO CODE SEGMENT REGISTER
:LOAD DI WITH D000
:DAC LOADED WITH WXYZ
:CONTROL IS RETURNED TO THE MONITOR PROGRAM
C705“YZWX” MOV MEM,#YZWX
EA0000
00FF
Table 6b. Sample Program for Loading the MX7534 from 8086
ASSUME DS:DACLOAD,CS:DACLOAD
DACLOAD SEGMENT AT 000
00
02
04
07
0A
0B
0C
0F
10
11
14
8CC9
8ED9
BF02D0
C605“MS”
47
MOV CX,CS
MOVDS,CX
MOVDI.#D002
MOV MEM,#“MS”
INC DI
INC DI
MOV MEM,#“LS”
INC DI
:DEFINE DATA SEGMENT REGISTER EQUAL
:TO CODE SEGMENT REGISTER
:LOAD DI WITH D002
:DAC LOADED WITH “MS”
47
C605“LS”
47
47
C60500
EA0000
:LS INPUT REGISTER LOADED WITH “LS”
INC DI
MOV MEM,#00
JMP MEM
:CONTENT OF INPUT REGISTERS ARE LOADED TO THE DAC REGISTER
:CONTROL IS RETURNED TO THE MONITOR PROGRAM
Table 6c. Sample Program for Loading
the MX7534 from 8085A
MC6 8 0 9 w it h MX7 5 3 4
Figure 13a shows an interface circuit that enables the
MX7534 to be programmed using the MC6809 8-bit
microprocessor. Use the 16-bit D accumulator to simplify
data transfer. The two key processor instructions are:
2000
01
26
30
MVIH,#30
02
03
2E
01
MVIL,#01
LDD
STD
Load D accumulator from memory
Store D accumulator to memory
04
05
06
07
08
09
0A
0B
0C
200D
3E
“MS”
77
2C
3E
“LS”
77
2C
77
CF
MVIA,#“MS”
MOV M,A
INR L
MVI A#“LS”
MC6 5 0 2 w it h MX7 5 3 4
Figure 13b shows an interface diagram for the MC6502
using the MX7534.
MOV M,A
INR L
MOV M,A
RST I
________________Dig it a l Fe e d t h ro u g h
In the interface diagrams shown in Figures 9–13, the
digital inputs of the DAC are directly connected to the
mic rop roc e s s or b us . Eve n whe n the d e vic e is not
selected, activity on the bus can feed through on the
DAC output through package capacitance and appear
as noise. To minimize noise, isolate the DACs from the
digital bus, as shown in Figures 14a and 14b.
Z8 0 w it h MX7 5 3 4 /MX7 5 3 5
Figure 12a is an interface circuit for the Z80, using the
MX7535. This is an example of an 8-bit processor inter-
face for these DACs. Figure 12b shows the schematic
for the MX7534.
______________________________________________________________________________________ 13
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
ADDRESS BUS
A1–A23
ADDRESS BUS
16-BIT
LATCH
ADDRESS
DECODE
ADDRESS
DECODE
AS
CSMSB
CSLSB
ALE
WR
CSMSB
CSLSB
LDAC
CS1
CS2
MC68000
8086
CS4 CS3
LDAC
WR
DTACK
MX7535*
WR
R/W
MX7535*
D0–D13
D0–D15
DATA BUS
D0–D13
AD0–AD15
DATA BUS
*SOME CIRCUITRY OMITTED FOR CLARITY
CSMSB
CSLSB
Figure 11a. MX7535—MC68000 Interface
LDAC
WR
4/MX735
A1–A23
ADDRESS BUS
MX7535*
D0–D13
A1
A2
A0 A1
CS
ADDRESS
DECODE
AS
MC68000
CSMSB
CSLSB
DTACK
MX7534*
WR
D0–D7
LDAC
WR
R/W
D0–D7
DATA BUS
MX7535*
D0–D13
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 11b. MX7534—MC68000 Interface
Figure 10. MX7535—8086 Interface: Multiple DAC Systems
14 ______________________________________________________________________________________
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
4/MX735
A0–A15
ADDRESS BUS
A0–A15
ADDRESS BUS
A0 A1
CSLSB
CSMSB
ADDRESS
DECODE
ADDRESS
DECODE
MREQ
Z80
CS
MREQ
Z80
LDAC
MX7534*
MX7535*
WR
WR
WR
WR
D8–D13
D0–D7
DATA BUS
D0–D7
D8–D7
DATA BUS
D0–D7
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 12a. MX7535—Z80 Interface
Figure 12b. MX7534—Z80 Interface
ADDRESS BUS
ADDRESS BUS
A0–A15
R/W
A0–A15
A0 A1
CS
A0 A1
R/W
Q
ADDRESS
DECODE
ADDRESS
DECODE
CS
E
6502
MX7534*
WR
MX7534*
2
WR
MC6809
D0–D7
D0–D7
D0–D7
D0–D7
DATA BUS
DATA BUS
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 13a. MX7534—MC6809 Interface Circuit
Figure 13b. MX7534—6502 Interface
ADDRESS
DECODE
ADDRESS
DECODE
A0–A15
A0–A15
A0 A1
CS
A1
A0
MICRO-
PROCESSOR
SYSTEM
EN
CSMSB
CSLSB
LDAC
QUAD LATCH
WR
WR
MICRO-
PROCESSOR
SYSTEM
EN
EN
MX7534*
D0–D7
WR
WR
16-BIT
LATCH
QUAD LATCH
D0–D7
MX7535*
D0–D13
EN
D0–D15
QUAD LATCH
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 14a. MX7534—Interface Circuit Using Latches to
Minimize Digital Feedthrough
Figure 14b. MX7535—Interface Circuit Using Latches to
Minimize Digital Feedthrough
______________________________________________________________________________________ 15
Mic ro p ro c e s s o r-Co m p a t ib le ,
1 4 -Bit DACs
___Fu n c t io n a l Dia g ra m s (c o n t in u e d )
_____P in Co n fig u ra t io n s (c o n t in u e d )
TOP VIEW
V
DD
26
MX7535
28 N.C.
REFS
REFF
1
2
3
4
5
6
7
8
9
3
4
5
6
RFB
IOUT
AGNDS
AGNDF
LDAC
1
2
14-BIT DAC
REFS
REFF
27
26
V
SS
14
V
DD
RFB
23
DAC REGISTER
IOUT
25 WR
8
6
AGNDS
AGNDF
DGND
24 CSLSB
23 LDAC
LS
INPUT
REGISTER
MS
INPUT
REGISTER
24
MX7535
CSLSB
CSMSB
22
21 D0 (LSB)
20
22
25
CSMSB
WR
(MSB) D13
D12
D1
7
27
SS
8–21
D13–D0
4/MX735
DGND
V
19 D2
18 D3
17 D4
16 D5
D11 10
D10 11
D9 12
D8 13
_Ord e rin g In fo rm a t io n (c o n t in u e d )
15
D7
14
D6
PART
TEMP. RANGE PIN PACKAGE INL (LSBs)
MX7535KN
MX7535JN
MX7535KCWI
MX7535JCWI
MX7535KP
MX7535JP
MX7535J/D
MX7535BQ
MX7535AQ
MX7535BD
MX7535AD
MX7535KEWI -40°C to +85°C
MX7535JEWI -40°C to +85°C
MX7535TQ
MX7535SQ
MX7535TD
MX7535SD
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
28 Plastic DIP
28 Plastic DIP
28 Wide SO
28 Wide SO
28 PLCC
±1
±2
±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
±1
±2
±1
±2
DIP/SO/PLCC/Ceramic SB
28 PLCC
Dice*
28 CERDIP
28 CERDIP
28 Ceramic SB
28 Ceramic SB
28 Wide SO
28 Wide SO
28 CERDIP
28 CERDIP
28 Ceramic SB
28 Ceramic SB
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
*Dice are tested at +25°C, DC parameters only.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MX7535JCWI+
D/A Converter, 1 Func, Parallel, Word Input Loading, 0.8us Settling Time, PDSO28, SOP-28
MAXIM
MX7535JCWI+T
D/A Converter, 1 Func, Parallel, Word Input Loading, 0.8us Settling Time, PDSO28, SOP-28
MAXIM
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