MX7705EPE+_技术文档

19-3051; Rev 0; 10/03

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

General Description

Features

The MX7705 low-power, 2-channel, serial-output ana-

log-to-digital converter (ADC) includes a sigma-delta

modulator with a digital filter to achieve 16-bit resolution

with no missing codes. This ADC is pin compatible and

software compatible with the AD7705. The MX7705 fea-

tures an on-chip input buffer and programmable-gain

amplifier (PGA). The device offers an SPI-/QSPI-/

MICROWIRE-compatible serial interface.

The MX7705 operates from a single 2.7V to 5.25V supply.

The operating supply current is 320µA (typ) with a 3V

supply. Power-down mode reduces the supply current to

2µA (typ).

ꢀ Pin Compatible and Software Compatible with the

AD7705

ꢀ 16-Bit Sigma-Delta ADC

ꢀ Two Fully Differential Input Channels

ꢀ 0.003% Integral Nonlinearity with No Missing Codes

ꢀ Interface with Schmitt Triggers on Inputs

ꢀ Internal Analog Input Buffers

ꢀ PGA from 1 to 128

ꢀ Single (2.7V to 3.6V) or (4.75V to 5.25V) Supply

Self-calibration and system calibration allow the MX7705

to correct for gain and offset errors. Excellent DC perfor-

mance ( 0.003ꢀ ꢁSR IꢂN) and low noise (650nV) maꢃe

the MX7705 ideal for measuring low-frequency signals

with a wide dynamic range. The device accepts fully dif-

ferential bipolar/unipolar inputs. An internal input buffer

allows for input signals with high source impedances. An

on-chip digital filter, with a programmable cutoff and out-

put data rate, processes the output of the sigma-delta

modulator. The first notch frequency of the digital filter is

chosen to provide 150dB rejection of common-mode

50Hz or 60Hz noise and 98dB rejection of normal-mode

50Hz or 60Hz noise. A PGA and digital filtering allow sig-

nals to be directly acquired with little or no signal-condi-

tioning requirements.

ꢀ Low Power

1mW (max), 3V Supply

2µA (typ) Power-Down Current

ꢀ SPI-/QSPI-/MICROWIRE-Compatible 3-Wire Serial

Interface

ꢀ 16-Pin PDIP, SO, and TSSOP Packages

Ordering Information

PART

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

16 PDIP

MX7705EPE*

MX7705EWE*

MX7705EUE

The MX7705 is available in 16-pin PDIP, SO, and

TSSOP pacꢃages.

16 WIDE SO

16 TSSOP

Applications

*Future product—contact factory for availability.

Industrial Instruments

Weigh Scales

Strain-Gauge Measurements

Noop-Powered Systems

ꢁlow and Gas Meters

Medical Instrumentation

Pressure Transducers

Thermocouple Measurements

RTD Measurements

Pin Configuration

TOP VIEW

SCLK

1

2

3

4

5

6

7

8

16 GND

15

CLKIN

V

DD

CLKOUT

CS

14 DIN

MX7705

13 DOUT

12 DRDY

11 AIN2-

10 REF-

RESET

AIN2+

AIN1+

AIN1-

9

REF+

PDIP/SO/TSSOP

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

ABSOLUTE MAXIMUM RATINGS

DD

All Other Pins to GꢂD.................................-0.3V to (V

Maximum Current Input into Any Pin ..................................50mA

V

to GꢂD..............................................................-0.3V to +6V

Operating Temperature Range ..........................-40°C to +85°C

Storage Temperature Range.............................-60°C to +150°C

Junction Temperature......................................................+150°C

Nead Temperature (soldering, 10s) .................................+300°C

+ 0.3V)

DD

Continuous Power Dissipation (T = +70°C)

A

PDIP (derate 10.5mW/°C above +70°C)......................842mW

TSSOP (derate 9.4mW/°C above +70°C) ....................755mW

Wide SO (derate 9.5mW/°C above +70°C)..................762mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

= 3V or 5V, GꢂD = 0, V

= 1.225V for V

= 3V and V

= 2.5V for V

= 5V, V

= GꢂD, external f

=

CNKIꢂ

DD

REꢁ+

DD

REꢁ+

DD

REꢁ-

2.4576MHz, CNKDIV bit = 0, C

to GꢂD = 0.1µꢁ, C

- to GꢂD = 0.1µꢁ, T = T

to T

, unless otherwise noted.)

REꢁ+

REꢁ

A

MIꢂ

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution (No Missing Codes)

Output Noise

16

Bits

µV

Tables 1, 3

Integral Nonlinearity

Unipolar Offset Error

Unipolar Offset Drift

Bipolar Zero Error

INL

Gain = 1, unbuffered

After calibration

(Note 2)

±±0±±3 %FSR

(Note 1)

±05

µV

µV/°C

µV

After calibration

Gain = 1 to 4

(Note 1)

±05

Bipolar Zero Drift (Note 2)

µV/°C

Gain = 8 to 128

After calibration

(Notes 2, 4)

±01

Positive Full-Scale Error

Full-Scale Drift

(Notes 1, 3)

±05

µV

µV/°C

µV

Gain Error

After calibration

(Notes 1, 5)

ppm of

FSR/°C

Gain Drift

(Notes 2, 6)

±05

Bipolar Negative Full-Scale Error

After calibration

Gain = 1 to 4

±±0±±3

1

%FSR

Bipolar Negative Full-Scale Drift

(Note 2)

µV/°C

Gain = 8 to 128

±06

ANALOG INPUTS (AIN1+, AIN1-, AIN2+, AIN2-)

V

GAIN

/

REF

Unipolar input range

Bipolar input range

Unbuffered

±

AIN Differential Input Voltage

Range (Note 7)

V

-V

/

V

GAIN

/

REF

GAIN

GND -

3±mV

V

+

DD

3±mV

AIN Absolute Input Voltage

Range (Note 8)

V

GND +

5±mV

V

105V

-

DD

Buffered

AIN DC Leakage Current

Unselected input channel

1

nA

2

_______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

ELECTRICAL CHARACTERISTICS (continued)

(V

= 3V or 5V, GND = ±, V

= 10225V for V

= 3V and V

= 205V for V

= 5V, V

= GND, external f

=

DD

REF+

DD

REF+

DD

REF-

CLKIN

204576MHz, CLKDIV bit = ±, C

to GND = ±01µF, C

- to GND = ±01µF, T = T

to T

, unless otherwise noted0)

MAX

REF+

REF

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

34

MAX

UNITS

Gain = 1

Gain = 2

Gain = 4

38

AIN Input Capacitance

AIN Input Sampling Rate

pF

45

Gain = 8 to 128

6±

f

/

CLKIN

64

f

s

Gain = 1 to 128

MHz

Gain = 1

Gain = 2

Gain = 4

96

1±5

11±

13±

1±5

11±

12±

13±

V

= 5V

= 3V

DD

Gain = 8 to 128

Gain = 1

Input Common-Mode Rejection

CMR

dB

Gain = 2

Gain = 4

Gain = 8 to 128

For filter notches of 25Hz, 5±Hz,

±±0±2 × f

Normal-Mode 5±Hz Rejection

Normal-Mode 6±Hz Rejection

Common-Mode 5±Hz Rejection

Common-Mode 6±Hz Rejection

98

dB

NOTCH

For filter notches of 2±Hz, 6±Hz,

±±0±2 × f

NOTCH

For filter notches of 25Hz, 5±Hz,

±±0±2 × f

15±

NOTCH

For filter notches of 2±Hz, 6±Hz,

±±0±2 × f

NOTCH

EXTERNAL REFERENCE (REF+, REF-)

V

= 4075V to 5025V

= 207V to 306V

10±

10±±

GND

305

DD

REF Differential Input Voltage

Range (Note 9)

V

REF

1075

REF Absolute Input Voltage Range

REF Input Capacitance

V

DD

Gain = 1 to 128

1±

pF

f

/

CLKIN

64

REF Input Sampling Rate

f

s

MHz

DIGITAL INPUTS (DIN, SCLK, CS, RESET)

Input High Voltage

V

2

V

IH

V

= 4075V to 5025V

= 207V to 306V

±08

±04

DD

Input Low Voltage

V

IL

DIN, CS, RESET

25±

5±±

Input Hysteresis

V

mV

HYST

SCLK

Input Current

I

±1

µA

pF

IN

Input Capacitance

5

_______________________________________________________________________________________

3

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

ELECTRICAL CHARACTERISTICS (continued)

(V

= 3V or 5V, GND = ±, V

= 10225V for V

= 3V and V

= 205V for V

= 5V, V

= GND, external f

=

CLKIN

DD

REF+

DD

REF+

DD

REF-

204576MHz, CLKDIV bit = ±, C

to GND = ±01µF, C

- to GND = ±01µF, T = T

to T

, unless otherwise noted0)

MAX

REF+

REF

A

MIN

PARAMETER

CLKIN INPUT

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

= 4075V to 5025V

= 207V to 306V

= 4075V to 5025V

= 207V to 306V

305

205

DD

CLKIN Input High Voltage

V

CLKINH

±08

±04

CLKIN Input Low Voltage

CLKIN Input Current

V

CLKINL

I

±1±

µA

CLKIN

DIGITAL OUTPUTS (DOUT, DRDY, CLKOUT)

DOUT and DRDY,

= 8±±µA

±04

I

SINK

V

= 5V

= 3V

= 5V

= 3V

DD

CLKOUT,

= 1±µA

I

SINK

Output Voltage Low

V

OL

DOUT and DRDY,

= 1±±µA

I

SINK

CLKOUT,

= 1±µA

I

SINK

DOUT and DRDY,

40±

I

= 2±±µA

SOURCE

CLKOUT,

I

= 1±µA

SOURCE

Output Voltage High

V

OH

DOUT and DRDY,

V

-

DD

I

= 1±±µA

±06V

SOURCE

CLKOUT,

V

-

DD

I

= 1±µA

±06V

SOURCE

Tri-State Leakage Current

Tri-State Output Capacitance

SYSTEM CALIBRATION

I

DOUT only

±1±

µA

pF

L

C

9

OUT

-10±5 ×

10±5 ×

GAIN = selected PGA gain (1 to 128)

(Note 1±)

Full-Scale Calibration Range

Offset Calibration Range

Input Span

V

/

V

/

V

REF

GAIN

-10±5 ×

10±5 ×

GAIN = selected PGA gain (1 to 128)

(Note 1±)

V

/

V

/

REF

GAIN

±08 ×

201 ×

GAIN = selected PGA gain (1 to 128)

(Notes 1±, 11)

V

/

V

/

REF

GAIN

4

_______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

ELECTRICAL CHARACTERISTICS (continued)

(V

= 3V or 5V, GND = ±, V

= 10225V for V

= 3V and V

= 205V for V

= 5V, V

= GND, external f

=

DD

REF+

DD

REF+

DD

REF-

CLKIN

204576MHz, CLKDIV bit = ±, C

to GND = ±01µF, C

- to GND = ±01µF, T = T

to T

, unless otherwise noted0)

MAX

REF+

REF

A

MIN

PARAMETER

POWER REQUIREMENTS

Power-Supply Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

207±

5025

±045

V

DD

Unbuffered

=1MHz,

gain =1 to 128

V

= 5V

= 3V

DD

f

CLKIN

±032

±07

Buffered,

V

= 5V

= 3V

= 5V,

DD

f

=1MHz,

CLKIN

±06

gain =1 to 128

±06

±085

±04

±06

±09

103

±07

101

gain = 1 to 4

V

= 5V,

DD

gain = 8 to 128

Unbuffered,

f

= 204576MHz

CLKIN

V

= 3V,

DD

mA

gain = 1 to 4

Power-Supply Current (Note 12)

I

DD

V

= 3V,

DD

gain = 8 to 128

V

= 5V,

DD

gain = 1 to 4

V

= 5V,

DD

gain = 8 to 128

Buffered,

= 204576MHz

V

= 3V,

DD

f

CLKIN

gain = 1 to 4

V

= 3V,

DD

gain = 8 to 128

V

= 5V

= 3V

16

8

DD

Power-down mode

(Note 13)

µA

dB

V

= 4075V to 5025V

= 207V to 306V

(Note 14)

DD

Power-Supply Rejection Ratio

PSRR

EXTERNAL CLOCK TIMING SPECIFICATIONS

CLKIN Frequency

Duty Cycle

f

(Note 15)

4±±

4±

25±±

6±

kHz

%

CLKIN

_______________________________________________________________________________________

5

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

TIMING CHARACTERISTICS

(V

= 3V or 5V, GND = ±, V

= 10225V for V

= 3V and V

= 205V for V

= 5V, V

= GND, external f

=

CLKIN

DD

REF+

DD

REF+

DD

REF-

204576MHz, CLKDIV bit = ±, C

(Figures 8, 9)

to GND = ±01µF, C

- to GND = ±01µF, T = T

to T

, unless otherwise noted0) (Note 16)

REF+

REF

A

MIN

MAX

PARAMETER

DRDY High Time

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

5±± /

CLKIN

1±±

s

f

Reset Pulse-Width Low

ns

DRDY Fall to CS Fall Setup Time

CS Fall to SCLK Rise Setup Time

t

±

12±

±

1

2

V

= 4075V to 5025V

= 207V to 306V

8±

DD

SCLK Fall to DOUT Valid Delay

t

3

ns

±

1±±

SCLK Pulse-Width High

t

1±±

±

ns

4

5

6

SCLK Pulse-Width Low

CS Rise to SCLK Rise Hold Time

V

= 4075V to 5025V

= 207V to 306V

6±

DD

Bus Relinquish Time After SCLK

Rising Edge

t

ns

7

1±±

SCLK Fall to DRDY Rise Delay

DIN to SCLK Setup Time

DIN to SCLK Hold Time

t

ns

8

3±

2±

9

t

1±

6

_______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

TIMING CHARACTERISTICS (continued)

(V

= 3V or 5V, GND = ±, V

= 10225V for V

= 3V and V

= 205V for V

= 5V, V

= GND, external f

=

CLKIN

DD

REF+

DD

REF+

DD

REF-

204576MHz, CLKDIV bit = ±, C

(Figures 8, 9)

to GND = ±01µF, C

- to GND = ±01µF, T = T

to T

, unless otherwise noted0) (Note 16)

MAX

REF+

REF

A

MIN

Note 1: These errors are in the order of the conversion noise shown in Tables 1 and 30 This applies after calibration at the given

temperature0

Note 2: Recalibration at any temperature removes these drift errors0

Note 3: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar

and bipolar input ranges0

Note 4: Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar

input ranges0

Note 5: Gain error does not include zero-scale errors0 It is calculated as (full-scale error - unipolar offset error) for unipolar ranges,

and (full-scale error - bipolar zero error) for bipolar ranges0

Note 6: Gain-error drift does not include unipolar offset drift or bipolar zero drift0 Effectively, it is the drift of the part if only zero-

scale calibrations are performed0

Note 7: The analog input voltage range on AIN+ is given with respect to the voltage on AIN- on the MX77±50

Note 8: This common-mode voltage range is allowed, provided that the input voltage on analog inputs does not go more positive

than (V

+ 3±mV) or more negative than (GND - 3±mV)0 Parts are functional with voltages down to (GND - 2±±mV), but

DD

with increased leakage at high temperature0

Note 9: The REF differential voltage, V

Note 10: Guaranteed by design0

, is the voltage on REF+ referenced to REF- (V

= V

- V

0

REF-)

REF

REF+

Note 11: These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed (V

+

DD

3±mV) or go more negative than (GND - 3±mV)0 The offset calibration limit applies to both the unipolar zero point and the

bipolar zero point0

Note 12: When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the supply

current and power dissipation varies depending on the crystal or resonator type0 Supply current is measured with the digi-

tal inputs connected to ± or V , CLKIN connected to an external clock source, and CLKDIS = 10

DD

Note 13: If the external master clock continues to run in power-down mode, the power-down current typically increases to 67µA at

3V0 When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the

clock generator continues to run in power-down mode and the power dissipation depends on the crystal or resonator type

(see the Power-Down Modes section)0

Note 14: Measured at DC and applied in the selected passband0 PSRR at 5±Hz exceeds 12±dB with filter notches of 25Hz or 5±Hz0

PSRR at 6±Hz exceeds 12±dB with filter notches of 2±Hz or 6±Hz0 PSRR depends on both gain and V

0

DD

PSRR (dB)

(V = 5V)

PSRR (dB)

(V = 3V)

GAIN

DD

1

9±

86

2

4

78

84

91

78

85

93

8 to 128

Note 15: Provide f

whenever the MX77±5 is not in power-down mode0 If no clock is present, the device can draw higher than

CLKIN

specified current and can possibly become uncalibrated0

Note 16: All input signals are specified with t = t = 5ns (1±% to 9±% of V ) and timed from a voltage level of 106V0

r

f

DD

_______________________________________________________________________________________

7

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Table 1. Output RMS Noise vs. Gain and Output Data Rate (V

= 5V)

DD

TYPICAL OUTPUT RMS NOISE (µV)

GAIN

FILTER FIRST

NOTCH AND

-3dB FREQUENCY

OUTPUT DATA RATE

1

2

4

8

16

32

64

128

BUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

4044

5011

2028

2079

1029

1055

±079

±092

±07±

±081

±07±

±08±

±064

±073

2025

9014

±063

±074

2024

9022

25Hz

1±±Hz

2±±Hz

1±2035

586093

49059

272083

230±4

224079

11078

7±078

6032

3063

33094

17057

UNBUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

4032

5016

205±

2085

1035

1063

±081

±096

±073

±083

±07±

±081

±064

±074

2022

8095

±064

±074

2023

90±8

25Hz

1±±Hz

1±5078

52606±

49086

26±051

24067

132016

12016

67025

6042

308±

2±±Hz

340±9

1802±

BUFFERED (f

5±Hz

= 2.4576MHz)

CLKIN

1301Hz

3053

4041

1086

2023

10±9

1029

±073

±083

±072

±079

±071

±077

±067

±072

2032

9043

±066

±073

2035

904±

6±Hz

15072Hz

6505Hz

131Hz

25±Hz

5±±Hz

99066

6±8086

46085

288039

16098

11±08±

12048

67051

6038

3078

36075

17098

UNBUFFERED (f

5±Hz

= 2.4576MHz)

CLKIN

1301Hz

15072Hz

6505Hz

131Hz

3065

4056

1094

2041

1017

1032

±079

±087

±07±

±08±

±069

±079

±066

±071

2036

908±

±065

±074

2036

9044

6±Hz

25±Hz

1±1056

5560±6

49064

278091

25039

142088

12092

74078

6065

3069

5±±Hz

35041

18099

8

_______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Table 2. Peak-to-Peak Resolution vs. Gain and Output Data Rate (V

= 5V)

DD

TYPICAL PEAK-TO-PEAK RESOLUTION (BITS)

GAIN

FILTER FIRST

NOTCH AND

-3dB FREQUENCY

OUTPUT DATA RATE

1

2

4

8

16

32

64

128

BUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

16

12

1±

16

12

1±

16

12

1±

16

12

1±

16

12

1±

15

12

1±

14

12

1±

13

11

9

25Hz

1±±Hz

2±±Hz

UNBUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

16

12

1±

16

12

1±

16

12

1±

16

12

1±

16

12

1±

15

12

1±

14

12

1±

13

11

9

25Hz

1±±Hz

2±±Hz

BUFFERED (f

5±Hz

= 2.4576MHz)

CLKIN

1301Hz

16

12

1±

16

12

1±

16

13

11

16

12

1±

16

12

1±

15

12

1±

14

12

1±

13

11

9

6±Hz

15072Hz

6505Hz

25±Hz

5±±Hz

131Hz

UNBUFFERED (f

5±Hz

= 2.4576MHz)

1301Hz

CLKIN

16

12

1±

16

12

1±

16

12

1±

16

12

1±

16

12

1±

15

12

1±

14

12

1±

13

11

9

6±Hz

15072Hz

6505Hz

25±Hz

5±±Hz

131Hz

_______________________________________________________________________________________

9

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Table 3. Output RMS Noise vs. Gain and Output Data Rate (V

= 3V)

DD

TYPICAL OUTPUT RMS NOISE (µV)

GAIN

FILTER FIRST

NOTCH AND

-3dB FREQUENCY

OUTPUT DATA RATE

1

2

4

8

16

32

64

128

BUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

3052

4024

1084

2023

2019

1019

±073

±084

±066

±074

±062

±069

2023

8076

±062

±069

107±

407±

±062

±069

1069

407±

25Hz

1±±Hz

2±±Hz

5±036

2680±2

25012

175098

120±6

65077

60±4

3038

34089

16073

UNBUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

3058

4016

1092

2027

1013

1027

±072

±083

±066

±074

±064

±07±

8047

±061

±069

1066

4066

±062

±067

1063

4068

25Hz

1±±Hz

5±048

256043

23089

135078

1201±

65062

509±

3026

2±±Hz

33018

16065

BUFFERED (f

5±Hz

= 2.4576MHz)

CLKIN

1301Hz

2084

3027

1068

1084

20±±

1012

±071

±078

±067

±075

±065

±07±

2032

902±

±063

±068

1064

5016

±061

±067

1066

4092

6±Hz

15072Hz

6505Hz

25±Hz

5±±Hz

4709±

2810±3

24043

1±4019

12056

69058

6048

3045

131Hz

34059

17044

UNBUFFERED (f

5±Hz

= 2.4576MHz)

1301Hz

CLKIN

30±4

3035

1074

108±

10±3

1013

±072

±081

±064

±073

±064

±069

2022

9055

±062

±067

1068

409±

±063

±068

1065

5018

6±Hz

15072Hz

6505Hz

25±Hz

49063

279013

23082

134082

130±3

69047

6023

3042

5±±Hz

131Hz

35042

17047

10 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Table 4. Peak-to-Peak Resolution vs. Gain and Output Data Rate (V

= 3V)

DD

TYPICAL PEAK-TO-PEAK RESOLUTION (BITS)

GAIN

FILTER FIRST

NOTCH AND

-3dB FREQUENCY

OUTPUT DATA RATE

1

2

4

8

16

32

64

128

BUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

16

12

1±

16

12

1±

16

12

1±

16

12

1±

15

12

1±

14

12

1±

13

12

1±

12

11

9

25Hz

1±±Hz

2±±Hz

UNBUFFERED (f

2±Hz

= 1MHz)

CLKIN

5024Hz

6055Hz

2602Hz

5204Hz

16

12

1±

16

12

1±

16

12

1±

16

12

1±

15

12

1±

14

1±

13

12

1±

12

11

9

25Hz

1±±Hz

2±±Hz

BUFFERED (f

5±Hz

= 2.4576MHz)

CLKIN

1301Hz

16

12

1±

16

12

11

16

12

1±

16

12

1±

15

12

1±

14

12

1±

13

11

1±

12

11

9

6±Hz

15072Hz

6505Hz

131Hz

25±Hz

5±±Hz

UNBUFFERED (f

5±Hz

= 2.4576MHz)

CLKIN

1301Hz

15072Hz

6505Hz

131Hz

16

12

1±

16

12

1±

16

12

1±

16

12

1±

15

12

1±

14

12

1±

13

11

1±

12

11

9

6±Hz

25±Hz

5±±Hz

Typical Operating Characteristics

(V

= 3V or 5V, V

= 10225V for V

= 3V, V

= 205V for V

= 5V, V

- = GND, T = +25°C, unless otherwise noted0)

DD

REF+

DD

REF+

DD

REF

A

OFFSET ERROR vs. SUPPLY VOLTAGE (3V)

TYPICAL OUTPUT NOISE

HISTOGRAM OF TYPICAL OUTPUT NOISE

0.0015

0.0010

0.0005

0

32776

32774

32772

32770

32768

32766

32764

32762

32760

32758

32756

400

V

= 5V, V = 2.5V

REF

V

= 5V,

= 2.5V

GAIN = 128

ODR = 60Hz

RMS NOISE = 1.3µV

DD

REF

V

= 3V

DD

GAIN = 128

ODR = 60Hz

RMS NOISE = 1.3µV

300

200

100

0

-0.0005

-0.0010

-0.0015

2.70 2.85 3.00 3.15 3.30 3.45 3.60

SUPPLY VOLTAGE (V)

0

400

800

1200

1600

2000

READING NUMBER

CODE

______________________________________________________________________________________ 11

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Typical Operating Characteristics (continued)

(V

= 3V or 5V, V

= 10225V for V

= 3V, V

= 205V for V

= 5V, V

- = GND, T = +25°C, unless otherwise noted0)

REF A

DD

REF+

DD

REF+

DD

OFFSET ERROR vs. SUPPLY VOLTAGE (5V)

OFFSET ERROR vs. TEMPERATURE

GAIN ERROR vs. SUPPLY VOLTAGE (3V)

0.003

0.002

0.001

0

0.003

0.0015

0.0010

0.0005

0

V

= 5V

V

DD

= 3V

DD

V

= 5V

= 3V

0.002

0.001

0

DD

-0.001

-0.002

-0.003

-0.001

-0.002

-0.003

-0.0005

-0.0010

-0.0015

4.75

4.85

4.95

5.05

5.15

5.25

-40

-15

10

35

60

85

2.70 2.85 3.00 3.15 3.30 3.45 3.60

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

GAIN ERROR vs. SUPPLY VOLTAGE (5V)

GAIN ERROR vs. TEMPERATURE

0.005

0.003

0.002

0.001

0

V

= 5V

DD

0.004

0.003

0.002

0.001

0

V

= 3V

DD

-0.001

-0.002

-0.003

-0.004

-0.005

-0.001

-0.002

-0.003

V

= 5V

DD

-40

-15

10

35

60

85

4.75

4.85

4.95

5.05

5.15

5.25

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

12 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Typical Operating Characteristics (continued)

(V

= 3V or 5V, V

= 10225V for V

= 3V, V

= 205V for V

= 5V, V

- = GND, T = +25°C, unless otherwise noted0)

DD

REF+

DD

REF+

DD

REF

A

SUPPLY CURRENT vs. SUPPLY VOLTAGE (5V)

SUPPLY CURRENT vs. SUPPLY VOLTAGE (3V)

0.65

0.6

A

V

= 5V

DD

V

= 3V

DD

A

B

0.55

0.45

0.35

0.25

0.5

0.4

0.3

0.2

B

C

E

C

D

E

4.75

4.85

4.95

SUPPLY VOLTAGE (V)

B: BUFFERED MODE C: BUFFERED MODE

= 2.4576MHz, = 1MHz,

5.05

5.15

5.25

2.70 2.85 3.00 3.15 3.30 3.45 3.60

SUPPLY VOLTAGE (V)

A: BUFFERED MODE

= 2.4576MHz,

A: BUFFERED MODE

= 2.4576MHz,

B: BUFFERED MODE C: BUFFERED MODE

= 2.4576MHz, = 1MHz,

f

CLKIN

GAIN = 1 TO 128

f

CLKIN

GAIN = 1 TO 4

CLKIN

GAIN = 1 TO 4

GAIN = 8 TO 128

GAIN = 1 TO 128

D: UNBUFFERED MODE E: UNBUFFERED MODE

f

= 2.4576MHz, = 1MHz,

f

= 2.4576MHz, = 1MHz,

f

CLKIN

GAIN = 1 TO 128

CLKIN

GAIN = 1 TO 128

SUPPLY CURRENT vs. TEMPERATURE (3V)

SUPPLY CURRENT vs. TEMPERATURE (5V)

0.6

0.5

0.4

0.3

0.2

0.65

0.55

0.45

0.35

0.25

A

V

= 5V

DD

V

= 3V

DD

A

B

C

D

E

-40

-15

10

TEMPERATURE (°C)

B: BUFFERED MODE C: BUFFERED MODE

= 2.4576MHz, = 1MHz,

35

60

85

-40

-15

10

TEMPERATURE (°C)

B: BUFFERED MODE C: BUFFERED MODE

= 2.4576MHz, = 1MHz,

35

60

85

A: BUFFERED MODE

= 2.4576MHz,

GAIN = 8 TO 128

A: BUFFERED MODE

= 2.4576MHz,

GAIN = 8 TO 128

f

CLKIN

GAIN = 1 TO 128

f

CLKIN

GAIN = 1 TO 128

CLKIN

GAIN = 1 TO 4

CLKIN

GAIN = 1 TO 4

D: UNBUFFERED MODE E: UNBUFFERED MODE

f

= 2.4576MHz, = 1MHz,

f

= 2.4576MHz, = 1MHz,

f

CLKIN

GAIN = 1 TO 128

CLKIN

GAIN = 1 TO 128

______________________________________________________________________________________ 13

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Typical Operating Characteristics (continued)

(V

= 3V or 5V, V

= 10225V for V

= 3V, V

= 205V for V

= 5V, V

- = GND, T = +25°C, unless otherwise noted0)

REF A

DD

REF+

DD

REF+

DD

SUPPLY CURRENT vs. f

(3V)

SUPPLY CURRENT vs. f

(5V)

CLKIN

0.6

0.5

0.4

0.3

0.2

0.65

V

= 3V

V

= 5V

DD

B

A

0.55

0.45

0.35

0.25

C

D

E

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

(MHz)

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

(MHz)

f

CLKIN

A: BUFFERED MODE

CLK = 1,

GAIN = 128

B: BUFFERED MODE C: BUFFERED MODE

A: BUFFERED MODE

CLK = 1,

GAIN = 128

B: BUFFERED MODE C: BUFFERED MODE

CLK = 1,

GAIN = 1

CLK = 0,

CLK = 1,

GAIN = 1

CLK = 0,

GAIN = 1, 128

D: UNBUFFERED MODE E: UNBUFFERED MODE

D: UNBUFFERED MODE

CLK = 1,

GAIN = 1, 128

E: UNBUFFERED MODE

CLK = 0,

GAIN = 1, 128

CLK = 1,

CLK = 0,

GAIN = 1, 128

SUPPLY CURRENT vs. GAIN (3V)

SUPPLY CURRENT vs. GAIN (5V)

0.6

0.65

0.55

0.45

0.35

0.25

A

V

= 5V

V

= 3V

DD

A

B

0.5

0.4

0.3

0.2

B

C

D

E

D

E

F

1

2

4

8

16

GAIN

32

64 128

1

2

4

8

16

32

64 128

GAIN

A: BUFFERED MODE

CLK = 1, CLKDIV = 1,

= 2.4576MHz

B: BUFFERED MODE C: BUFFERED MODE

CLK = 1, CLKDIV = 0, CLK = 0, CLKDIV = 0,

A: BUFFERED MODE

CLK = 1, CLKDIV = 0,

CLKIN

B: BUFFERED MODE C: BUFFERED MODE

CLK = 1, CLKDIV = 1, CLK = 0, CLKDIV = 0,

f

= 2.4576MHz

f

= 1MHz

f

= 2.4576MHz

f

= 2.4576MHz

f

= 1MHz

CLKIN

D: UNBUFFERED MODE E: UNBUFFERED MODE F: UNBUFFERED MODE

CLK = 1, CLKDIV = 1, CLK = 1, CLKDIV = 0, CLK = 0, CLKDIV = 0,

= 2.4576MHz = 2.4576MHz = 1MHz

D: UNBUFFERED MODE E: UNBUFFERED MODE F: UNBUFFERED MODE

CLK = 1, CLKDIV = 1, CLK = 1, CLKDIV = 0, CLK = 0, CLKDIV = 0,

= 2.4576MHz = 2.4576MHz = 1MHz

f

CLKIN

f

CLKIN

14 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Typical Operating Characteristics (continued)

(V

= 3V or 5V, V

= 10225V for V

= 3V, V

= 205V for V

= 5V, V

- = GND, T = +25°C, unless otherwise noted0)

REF A

DD

REF+

DD

REF+

DD

POWER-DOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE (3V)

POWER-DOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE (5V)

POWER-DOWN SUPPLY CURRENT

vs. TEMPERATURE

100

200

300

250

200

150

100

50

V

= 3V

DD

V

= 5V

DD

80

60

40

20

0

180

160

140

120

100

V

= 5V

DD

V

= 3V

DD

0

2.70 2.85 3.00 3.15 3.30 3.45 3.60

SUPPLY VOLTAGE (V)

4.75

4.85

4.95

5.05

5.15

5.25

-40

-15

10

35

60

85

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

EXTERNAL OSCILLATOR STARTUP TIME

MX7705 toc20

V

DD

5V/div

4.9152MHz CRYSTAL

CLKOUT

5V/div

CLKOUT

5V/div

2.4576MHz CRYSTAL

2ms/div

______________________________________________________________________________________ 15

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Pin Description

NAME

FUNCTION

Serial Clock Input0 Apply an external serial clock to transfer data to and from the device at data rates

of up to 5MHz0

1

SCLK

Clock Input0 Connect a crystal/resonator between CLKIN and CLKOUT, or drive CLKIN externally with

a CMOS-compatible clock source with CLKOUT left unconnected0

2

3

CLKIN

Clock Output0 Connect a crystal/resonator between CLKIN and CLKOUT0 When enabled, CLKOUT

provides a CMOS-compatible, inverted clock output0 Set CLKDIS = ± in the clock register to enable

CLKOUT0 Set CLKDIS = 1 in the clock register to disable CLKOUT to conserve power0

CLKOUT

Active-Low Chip-Select Input0 CS selects the active device in systems with more than one device on

the serial bus0 Drive CS low to clock data in on DIN and to clock data out on DOUT0 When CS is high,

DOUT is high impedance0 Connect CS to GND for 3-wire operation0

4

CS

5

6

RESET

AIN2+

AIN1+

AIN1-

REF+

REF-

Active-Low Reset Input0 Drive RESET low to reset the MX77±5 to power-on reset status0

Channel 2 Positive Differential Analog Input

7

Channel 1 Positive Differential Analog Input

8

Channel 1 Negative Differential Analog Input

Positive Differential Reference Input

9

1±

11

Negative Differential Reference Input

AIN2-

Channel 2 Negative Differential Analog Input

Active-Low Data-Ready Output0 DRDY goes low when a new conversion result is available in the data

register0 When a read-operation of a full output word completes, DRDY returns high0

12

13

DRDY

Serial Data Output0 DOUT outputs serial data from the data register0 DOUT changes on the falling

edge of SCLK and is valid on the rising edge of SCLK0 When CS is high, DOUT is high impedance0

DOUT

DIN

14

15

16

Serial Data Input0 Data on DIN is clocked in on the rising edge of SCLK when CS is low0

V

Power Input

Ground

DD

GND

16 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Functional Diagram

CLKIN

CLOCK

GENERATOR

DIVIDER

CLKOUT

MX7705

BUFFER

AIN1+

AIN1-

AIN2+

AIN2-

V

2ND-ORDER

SIGMA-DELTA

MODULATOR

DD

SWITCHING

NETWORK

S1

S2

DIGITAL

FILTER

PGA

GND

BUFFER

CS

SERIAL INTERFACE,

REGISTERS,

AND

SCLK

DIN

S1 AND S2 ARE OPEN IN

BUFFERED MODE AND CLOSED

IN UNBUFFERED MODE

DOUT

DRDY

RESET

CONTROL

REF+

REF-

Analog Inputs

Detailed Description

The MX77±5 accepts four analog inputs (AIN1+, AIN1-,

AIN2+, and AIN2-) in buffered or unbuffered mode0

Use Table 8 to select the positive and negative input

pair for a fully differential channel0 The input buffer iso-

lates the inputs from the capacitive load presented by

the PGA/modulator, allowing for high source-imped-

ance analog transducers0 The value of the BUF bit in

the setup register (see the Setup Register section) deter-

mines whether the input buffer is enabled or disabled0

The MX77±5 low-power, 2-channel, serial-output ADC

uses a sigma-delta modulator with a digital filter to

achieve 16-bit resolution with no missing codes0 The

device includes a PGA, an on-chip input buffer, and a

bidirectional communications port0 The MX77±5 oper-

ates with a single 207V to 5025V supply0

Fully differential inputs, an internal input buffer, and an

on-chip PGA (gain = 1 to 128) allow low-level signals to

be directly measured, minimizing the requirements for

external signal conditioning0 Self-calibration corrects for

gain and offset errors0 A programmable digital filter

allows for the selection of the output data rate and first-

notch frequency from 2±Hz to 5±±Hz0

Internal protection diodes, which clamp the analog

input to V

and/or GND, allow the input to swing from

DD

(GND - ±03V) to (V

+ ±03V), without damaging the

DD

device0 If the analog input exceeds 3±±mV beyond the

supplies, limit the input current to 1±mA0

The bidirectional serial SPI-/QSPI-/MICROWIRE-compati-

ble interface consists of four digital control lines (SCLK,

CS, DOUT, and DIN) and provides an easy interface to

microcontrollers (µCs)0 Connect CS to GND to configure

the MX77±5 for 3-wire operation0

Input Buffers

When the analog input buffer is disabled, the analog

input drives a typical 7pF (gain = 1) capacitor, C

,

TOTAL

in series with the 7kΩ typical on-resistance of the track

and hold (T/H) switch (Figure 1)0 C is comprised

TOTAL

of the sampling capacitor, C

, and the stray capac-

SAMP

itance, C

0 During the conversion, C

charges

STRAY

SAMP

to (AIN+ - AIN-)0 The gain determines the value of

(Table 5)0

C

SAMP

______________________________________________________________________________________ 17

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

To minimize gain errors in unbuffered mode, select a

source impedance less than the maximum values

shown in Figures 2 and 30 These are the maximum

external resistance/capacitance combinations allowed

AIN(+)

R

(7kΩ TYP)

SW

HIGH

IMPEDANCE

before gain errors greater than 1 LSB are introduced in

unbuffered mode0

AIN(-)

C

(7pF TYP FOR GAIN = 1)

TOTAL

Enable the internal input buffer for a high source imped-

ance0 This isolates the inputs from the sampling capaci-

tor and reduces the sampling-related gain error0 When

using the internal buffer, limit the absolute input voltage

C

= C

+ C

SAMP STRAY

TOTAL

V

BIAS

range to (V

+ 5±mV) to (V

- 105V)0 Set gain and

DD

GND

common-mode voltage range properly to minimize lin-

earity errors0

Figure 1. Unbuffered Analog Input Structure

Input Voltage Range

In unbuffered mode, the absolute analog input voltage

100

range is from (GND - 3±mV) to (V

+ 3±mV) (see the

DD

GAIN = 1

Electrical Characteristics)0 In buffered mode, the ana-

log input voltage range is reduced to (GND + 5±mV) to

GAIN = 2

(V

- 105V)0 In both buffered and unbuffered modes,

DD

10

GAIN = 4

the differential analog input range (V

- V

)

AIN-

AIN+

decreases at higher gains (see the Programmable-Gain

Amplifier and the Unipolar and Bipolar Modes sections)0

GAIN = 8 TO 128

1

Reference

The MX77±5 provides differential inputs, REF+ and REF-,

for an external reference voltage0 Connect the external

reference directly across REF+ and REF- to obtain the

0.1

1

10

100

1000

10,000

differential reference voltage, V

0 The common-mode

REF-

REF

and V

EXTERNAL CAPACITANCE (pF)

voltage range for V

is between GND

REF+

and V 0 For specified operation, the nominal voltage,

DD

V

(V

- V

), is 10225V for V

DD

= 4075V to

DD

REF

REF+

REF-

Figure 2. Maximum External Resistance vs. Maximum External

Capacitance for Unbuffered Mode (1MHz)

5025V and 205V for V

= 207V to 306V0

The MX77±5 samples REF+ and REF- at f

/ 64

CLKIN

(CLKDIV = ±) or f

/ 128 (CLKDIV = 1) with an

CLKIN

internal 1±pF (typ for gain = 1) sampling capacitor in

series with a 7kΩ (typ) switch on-resistance0

100

GAIN = 1

GAIN = 2

Programmable-Gain Amplifier

A PGA provides selectable levels of gain: 1, 2, 4, 8, 16,

32, 64, and 1280 Bits G±, G1, and G2 in the setup reg-

ister control the gain (Table 9)0 As the gain increases,

10

GAIN = 4

the value of the input sampling capacitor, C

, also

SAMP

increases (Table 5)0 The dynamic load presented to the

analog inputs increases with clock frequency and gain

in unbuffered mode (see the Input Buffers section and

Figure 1)0

1

GAIN = 8 TO 128

0.1

1

10

100

1000

10,000

EXTERNAL CAPACITANCE (pF)

Figure 3. Maximum External Resistance vs. Maximum External

Capacitance for Unbuffered Mode (2.4576MHz)

18 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Table 5. Input Sampling Capacitor vs. Gain

V

REF

/ GAIN

GAIN

INPUT SAMPLING CAPACITOR (C ) (pF)

SAMP

1111 1111 1111 1111

1111 1111 1111 1110

1111 1111 1111 1101

1111 1111 1111 1100

1

3075

705

15

FULL-SCALE TRANSITION

2

4

8–128

3±

V

REF

1 LSB =

(GAIN) (65,536)

Increasing the gain increases the resolution of the ADC

(LSB size decreases), but reduces the differential input

voltage range0 Calculate 1 LSB in unipolar mode using

the following equation:

0000 0000 0000 0011

0000 0000 0000 0010

0000 0000 0000 0001

0000 0000 0000 0000

V

REF

1 LSB=

GAIN (65,536)

where V

= V

- V

REF

REF+ REF-0

0

1

2

3

65,533

DIFFERENTIAL INPUT VOLTAGE (LSB)

65,535

For a gain of one and V

= 205V, the full-scale volt-

REF

age in unipolar mode is 205V and 1 LSB ≈ 3801µV0 For a

Figure 4. MX7705 Unipolar Transfer Function

gain of four, the full-scale voltage in unipolar mode is

±0625V (V

/ GAIN) and 1 LSB ≈ 905µV0 The differen-

REF

tial input voltage range in this example reduces from

205V to ±0625V, and the resolution increases, since the

LSB size decreased from 3801µV to 905µV0

V

/ GAIN

V

REF

/ GAIN

REF

1111 1111 1111 1111

Calculate 1 LSB in bipolar mode using the following

equation:

1111 1111 1111 1110

1111 1111 1111 1101

V

REF

V

REF

1 LSB=

× 2

1 LSB =

x 2

(GAIN) (65,536)

GAIN (65,536)

- V

REF+ REF-0

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

where V

= V

REF

Unipolar and Bipolar Modes

The B/U bit in the setup register (Table 9) configures

the MX77±5 for unipolar or bipolar transfer functions0

Figures 4 and 5 illustrate the unipolar and bipolar trans-

fer functions, respectively0

0000 0000 0000 0010

0000 0000 0000 0001

0000 0000 0000 0000

In unipolar mode, the digital output code is straight

binary0 When AIN+ = AIN-, the outputs are at zero

scale, which is the lower endpoint of the transfer func-

tion0 The full-scale endpoint is given by AIN+ - AIN- =

-32,768

-32,766

-1

0

+1

+32,765 +32,767

DIFFERENTIAL INPUT VOLTAGE (LSB)

Figure 5. MX7705 Bipolar Transfer Function

V

REF

/ GAIN, where V

= V

- V

0

REF-

REF

REF+

In bipolar mode, the digital output code is in offset

binary0 Positive full scale is given by AIN+ - AIN- =

When the MX77±5 is in buffered mode, the absolute and

common-mode analog input voltage ranges reduce to

+V

/ GAIN and negative full scale is given by AIN+ -

REF

AIN- = -V

between (GND + 5±mV) and (V

- 105V)0 The differential

DD

/ GAIN0 When AIN+ = AIN-, the outputs

REF

input voltage range is not affected in buffered mode0

are at zero scale, which is the midpoint of the bipolar

transfer function0

______________________________________________________________________________________ 19

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

The output data rate for the digital filter corresponds with

Modulator

The MX77±5 performs analog-to-digital conversions

using a single-bit, 2nd-order, switched-capacitor,

sigma-delta modulator0 The sigma-delta modulation

converts the input signal into a digital pulse train whose

average duty cycle represents the digitized signal infor-

mation0 A single comparator within the modulator quan-

tizes the input signal at a much higher sample rate than

the bandwidth of the input0

the positioning of the first notch of the filter’s frequency

response0 Therefore, for the plot in Figure 6, where the first

notch of the filter is 6±Hz, the output data rate is 6±Hz0 The

notches of the SINC³filter are repeated at multiples of the

first notch frequency0 The SINC³filter provides an attenua-

tion of better than 1±±dB at these notches0

Determine the cutoff frequency of the digital filter by load-

ing the appropriate values into the CLK, FS±, and FS1

bits in the clock register (Table 13)0 Programming a differ-

ent cutoff frequency with FS± and FS1 changes the fre-

quency of the notches, but it does not alter the profile of

the frequency response0

The MX77±5 modulator provides 2nd-order frequency

shaping of the quantization noise resulting from the sin-

gle-bit quantizer0 The modulator is fully differential for

maximum signal-to-noise ratio and minimum suscepti-

bility to power-supply and common-mode noise0 A sin-

gle-bit data stream is then presented to the digital filter

for processing to remove the frequency-shaped quanti-

zation noise0

For step changes at the input, allow a settling time

before valid data is read0 The settling time depends on

the output data rate chosen for the filter0 The worst-

case settling time of a SINC³filter for a full-scale step

input is four times the output data period0 By synchro-

nizing the step input using FSYNC, the settling time

reduces to three times the output data period0 If FSYNC

is high during the step input, the filter settles in three

times the output data period after FSYNC falls low0

The modulator sampling frequency is f

/ 128,

CLKIN

(CLKDIV = ±) is the

regardless of gain, where f

CLKIN

frequency of the signal at CLKIN0

Digital Filtering

The MX77±5 contains an on-chip, digital lowpass filter

that processes the 1-bit data stream from the modulator

using a SINC³(sinx/x)³response0 The SINC³filter has a

settling time of three output data periods0

Analog Filtering

The digital filter does not provide any rejection close to

the harmonics of the modulator sample frequency0 Due

to the high oversampling ratio of the MX77±5, these

bands occupy only a small fraction of the spectrum and

most broadband noise is filtered0 The analog filtering

requirements in front of the MX77±5 are reduced com-

pared to a conventional converter with no on-chip filtering0

In addition, the devices provide excellent common-mode

rejection of 9±db to reduce the common-mode noise sus-

ceptibility0

Filter Characteristics

Figure 6 shows the filter frequency response0 The

SINC³characteristic -3dB cutoff frequency is ±0262

times the first-notch frequency0 This results in a cutoff

frequency of 15072Hz for a first filter-notch frequency of

6±Hz (output data rate of 6±Hz)0 The response shown

in Figure 5 is repeated at either side of the digital filter’s

sample frequency, f (f = 1902kHz for 6±Hz output

M

Additional filtering prior to the MX77±5 eliminates

unwanted frequencies the digital filter does not reject0

Use additional filtering to ensure that differential noise

signals outside the frequency band of interest do not

saturate the analog modulator0

data rate), and at either side of the related harmonics

(2f , 3f , etc0)0

M

0

-20

-40

-60

-80

f

= 2.4576MHz

CLKIN

CLK = 1

FS1 = 0

FS0 = 1

If passive components are in the path of the analog

inputs when the device is in unbuffered mode, ensure

the source impedance is low enough (Figure 2) not to

introduce gain errors in the system0 This significantly

limits the amount of passive anti-aliasing filtering that

can be applied in front of the MX77±5 in unbuffered

mode0 In buffered mode, large source impedance

causes a small DC-offset error, which can be removed

by calibration0

f

N

= 60Hz

-100

-120

-140

-160

0

20 40 60 80 100 120 140 160 180 200

FREQUENCY (Hz)

3

Figure 6. Frequency Response of the SINC Filter (Notch at 60Hz)

20 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

External Oscillator

The oscillator requires time to stabilize when enabled0

Startup time for the oscillator depends on supply voltage,

temperature, load capacitances, and center frequency0

Depending on the load capacitance, a 1MΩ feedback

resistor across the crystal can reduce the startup time

(Figure 7)0 The MX77±5 was tested with an ECS-24-32-1

(204576MHz crystal) and an ECS-49-2±-1 (409152MHz

crystal) (see the Typical Operating Characteristics)0 In

power-down mode, the supply current with the external

oscillator enabled is typically 67µA with a 3V supply and

227µA with a 5V supply0

CS

t

6

t

2

SCLK

DIN

t

10

t

9

MSB

LSB

Serial-Digital Interface

The MX77±5 interface is fully compatible with SPI-, QSPI-,

and MICROWIRE-standard serial interfaces0 The serial

interface provides access to seven on-chip registers0 The

registers are 8, 16, and 24 bits in size0

Figure 8. Write Timing Diagram

DRDY

t

8

Drive CS low to transfer data in and out of the MX77±50

Clock in data at DIN on the rising edge of SCLK0 Data at

DOUT changes on the falling edge of SCLK and is valid

on the rising edge of SCLK0 DIN and DOUT are trans-

ferred MSB first0 Drive CS high to force DOUT high

impedance and cause the MX77±5 to ignore any signals

on SCLK and DIN0 Connect CS low for 3-wire operation0

Figures 8 and 9 show the timings for write and read

operations, respectively0

t

1

CS

t

6

t

2

t

4

SCLK

DOUT

t

5

t

7

t

3

MSB

LSB

On-Chip Registers

The MX77±5 contains seven internal registers (Figure 1±),

which are accessed by the serial interface0 These regis-

ters control the various functions of the device and allow

the results to be read0 Table 7 lists the address, power-on

default value, and size of each register0

Figure 9. Read Timing Diagram

trols calibration modes, gain setting, unipolar/bipolar

inputs, and buffered/unbuffered modes0 The third register

is the 8-bit clock register, which sets the digital filter char-

acteristics and the clock control bits0 The fourth register is

the 16-bit data register, which holds the output result0 The

24-bit offset and gain registers store the calibration coeffi-

cients for the MX77±50 The 8-bit test register is used for

factory testing only0

The first of these registers is the communications register0

The 8-bit communications register controls the acquisition

channel selection, whether the next data transfer is a read

or write operation, and which register is to be accessed0

The second register is the 8-bit setup register, which con-

The default state of the MX77±5 is to wait for a write to

the communications register0 Any write or read opera-

tion on the MX77±5 is a two-step process0 First, a com-

mand byte is written to the communications register0

This command selects the input channel, the desired

register for the next read or write operation, and

whether the next operation is a read or a write0 The sec-

ond step is to read from or write to the selected regis-

ter0 At the end of the data-transfer cycle, the device

returns to the default state0 See the Performing a

Conversion section for examples0

CRYSTAL OR

CERAMIC

RESONATOR

CLKIN

C

L

MX7705

CLKOUT

L

OPTIONAL

1MΩ

If the serial communication is lost, write 32 ones to the

serial interface to return the MX77±5 to the default

state0 The registers are not reset after this operation0

Figure 7. Using a Crystal or Ceramic Oscillator

______________________________________________________________________________________ 21

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

PD: (Default = ±) Power-Down Control Bit0 Set PD = 1

to initiate power-down mode0 Set PD = ± to take the

device out of power-down mode0 If CLKDIS = ±, CLKOUT

remains active during power-down mode to provide a

clock source for other devices in the system0

DIN

RS2 RS1 RS0

CH0, CH1: (Default = ±, ±) Channel-Select Bit0 Write to

the CH± and CH1 bits to select the conversion channel or

to access the calibration data shown in Table 80 The cali-

bration coefficients of a particular channel are stored in

one of the three offset and gain-register pairs in Table 80

Set CH1 = 1 and CH± = ± to evaluate the noise perfor-

mance of the part without external noise sources0 In this

noise evaluation mode, connect AIN1- to an external volt-

age within the allowable common-mode range0

COMMUNICATIONS REGISTER

SETUP REGISTER (8 BITS)

CLOCK REGISTER (8 BITS)

DATA REGISTER (16 BITS)

TEST REGISTER (8 BITS)*

OFFSET REGISTER (24 BITS)

GAIN REGISTER (24 BITS)

REGISTER

SELECT

DECODER

DOUT

Setup Register

The byte-wide setup register is bidirectional, so it can

be written and read0 The byte written to the setup regis-

ter sets the calibration modes, PGA gain, unipolar/bipo-

lar mode, buffer enable, and conversion start (Table 9)0

MD1, MD0: (Default = ±, ±) Mode-Select Bits0 See

Table 1± for normal operating mode, self-calibration,

zero-scale calibration, or full-scale calibration-mode

selection0

*THE TEST REGISTER IS USED FOR FACTORY TESTING ONLY.

G2, G1, G0: (Default = ±, ±, ±) Gain-Selection Bits0 See

Table 11 for PGA gain settings0

Figure 10. Register Summary

B/U: (Default = ±) Bipolar/Unipolar Mode Selection0 Set

B/U = ± to select bipolar mode0 Set B/U = 1 to select

unipolar mode0

Communications Register

The byte-wide communications register is bidirectional

so it can be written and read0 The byte written to the

communications register indicates the next read or write

operation on the selected register, the power-down

mode, and the analog input channel (Table 6)0 The

DRDY bit indicates the conversion status0

BUF: (Default = ±) Buffer-Enable Bit0 For unbuffered

mode, disable the internal buffer of the MX77±5 to reduce

power consumption by writing a ± to the BUF bit0 Write a

1 to this bit to enable the buffer0 Use the internal buffer

when acquiring high source-impedance input signals0

FSYNC: (Default

= 1) Filter-Synchronization/

0/DRDY: (Default = ±) Communication-Start/Data-Ready

Bit0 Write a ± to the ±/DRDY bit to start a write operation to

the communications register0 If ±/DRDY = 1, then the

device waits until a ± is written to ±/DRDY before continu-

ing to load the remaining bits0 For a read operation, the

±/DRDY bit shows the status of the conversion0 The

DRDY bit returns a ± if the conversion is complete and

the data is ready0 DRDY returns a 1 if the new data has

been read and the next conversion is not yet complete0 It

has the same value as the DRDY output pin0

Conversion-Start Bit0 Set FSYNC = ± to begin calibration

or conversion0 The MX77±5 performs free-running con-

versions while FSYNC = ±0 Set FSYNC = 1 to stop con-

verting data and to hold the nodes of the digital filter, the

filter-control logic, the calibration-control logic, and the

analog modulator in a reset state0 The DRDY output does

not reset high if it is low (indicating that valid data has not

yet been read from the data register) when FSYNC goes

high0 To clear the DRDY output, read the data register0

Clock Register

The byte-wide clock register is bidirectional, so it can

be written and read0 The byte written to the setup regis-

ter sets the clock, filter first-notch frequency, and the

output data rate (Table 12)0

RS2, RS1, RS0: (Default = ±, ±, ±) Register-Select Bits0

RS±, RS1, and RS2 select the next register to be

accessed as shown in Table 70

R/W: (Default = ±) Read-/Write-Select Bit0 Use this bit to

select if the next register access is a read or a write

operation0 Set R/W = ± to select a write operation or set

R/W = 1 for a read operation on the selected register0

MXID: (Default = 1) Maxim-Identifier Bit0 This is a read-

only bit0 Values written to this bit are ignored0

22 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Table 6. Communications Register

FIRST BIT (MSB)

(LSB)

COMMUNICATION

START/DATA READY

READ/WRITE

SELECT

POWER-DOWN

MODE

FUNCTION

REGISTER SELECT

CHANNEL SELECT

Name

±/DRDY

RS2

±

RS1

±

RS±

±

R/W

PD

±

CH1

±

CH±

±

Defaults

±

Table 7. Register Selection

RS2

±

RS1

±

RS0

±

REGISTER

POWER-ON RESET STATUS

REGISTER SIZE (BITS)

Communications Register

Setup Register

Clock Register

Data Register

±x±±

±x±1

8

±

1

±

1

±

±x±5

8

±

1

N/A

16

8

1

±

Test Register*

N/A

1

±

1

No Operation

—

24

1

±

Offset Register

Gain Register

±x1F 4± ±±

±x57 61 AB

1

*The test register is used for factory testing only.

Table 8. Channel Selection

OFFSET/GAIN

REGISTER PAIR

CH1

CH0

AIN+

AIN-

±

1

±

1

±

1

AIN1+

AIN2+

AIN1-

AIN2-

AIN1-

AIN2-

±

1

±

2

Table 9. Setup Register

FIRST BIT (MSB)

(LSB)

BIPOLAR/UNIPOLAR

MODE

FUNCTION

MODE CONTROL

PGA GAIN CONTROL

BUFFER ENABLE

FSYNC

Name

Defaults

MD1

±

MD±

±

G2

±

G1

±

G±

±

B/U

±

BUF

±

FSYNC

1

ZERO: (Default = ±) Zero Bit0 This is a read-only bit0

CLKDIV: (Default = ±) Clock-Divider Control Bit0 The

MX77±5 has an internal clock divider0 Set this bit to 1 to

divide the input clock by two0 When this bit is set to ±, the

MX77±5 operates at the external oscillator frequency0

Values written to this bit are ignored0

CLKDIS: (Default = ±) Clock-Disable Bit0 Set CLKDIS =

1 to disable the clock when using a crystal or resonator

across CLKIN and CLKOUT0 Set CLKDIS = 1 to disable

CLKOUT when using a CMOS clock source at CLKIN0

CLKOUT is held low during clock disable to save

power0 Set CLKDIS = ± to allow other devices to use

the output signal on CLKOUT as a clock source and/or

to enable the external oscillator0

CLK: (Default = 1) Clock Bit0 Set CLK = 1 for f

=

CLKIN

204576MHz with CLKDIV = ±, or 409152MHz with

CLKDIV = 10

______________________________________________________________________________________ 23

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Table 10. Operating-Mode Selection

MD1

MD0

OPERATING MODE

±

Normal Mode0 Use this mode to perform normal conversions on the selected analog input channel0

Self-Calibration Mode0 This mode performs self-calibration on the selected channel determined from CH± and

CH1 selection bits in the communications register (Table 6)0 Upon completion of self-calibration, the device

returns to normal mode with MD±, MD1 returning to ±, ±0 The DRDY output bit goes high when self-calibration is

requested and returns low when the calibration is complete and a new data word is in the data register0 Self-

calibration performs an internal zero-scale and full-scale calibration0 The analog inputs of the device are shorted

±

1

together internally during zero-scale calibration and connected to an internally generated (V

/ selected gain)

REF

voltage during full-scale calibration0 The offset and gain registers for the selected channel are automatically

updated with the calibration data0

Zero-Scale System-Calibration Mode0 This mode performs zero-scale calibration on the selected channel

determined from CH± and CH1 selection bits in the communications register (Table 6)0 The DRDY output bit

goes high when calibration is requested and returns low when the calibration is complete and a new data word

is in the data register0 Performing zero-scale calibration compensates for any DC offset voltage present in the

ADC and system0 Ensure that the analog input voltage is stable within 1/2 LSB for the duration of the calibration

sequence0 The offset register for the selected channel is updated with the zero-scale system-calibration data0

Upon completion of calibration, the device returns to normal mode with MD±, MD1 returning to ±, ±0

1

±

1

Full-Scale System-Calibration Mode0 This mode performs full-scale system calibration on the selected channel

determined by the CH± and CH1 selection bits in the communications register0 This calibration assigns a full-

scale output code to the voltage present on the selected channel0 Ensure that the analog input voltage is stable

within 1/2 LSB for the duration of the calibration sequence0 The DRDY output bit goes high during calibration

and returns low when the calibration is complete and a new data word is in the data register0 The gain register

for the selected channel is updated with the full-scale system-calibration data0 Upon completion of calibration,

the device returns to normal mode with MD±, MD1 returning to ±, ±0

Data Register

Table 11. PGA Gain Selection

The data register is a 16-bit register that can be read

and written0 Figure 9 shows how to read conversion

results using the data register0 A write to the data regis-

ter is not required, but if the data register is written, the

device does not return to its normal state of waiting for

a write to the communications register until all 16 bits

have been written0 The 16-bit data word written to the

data register is ignored0

G2

±

G1

±

G0

±

PGA GAIN

1

2

±

1

±

1

±

4

±

1

8

1

±

16

32

64

128

The data from the data register is read through DOUT0

DOUT changes on the falling edge of SCLK and is valid

on the rising edge of SCLK0 The data register format is

16-bit straight binary for unipolar mode with zero scale

equal to ±x±±±±, and offset binary for bipolar mode

with zero scale equal to ±x1±±±0

1

±

1

±

1

Set CLK = ± for optimal performance if the external

clock frequency is 1MHz with CLKDIV = ± or 2MHz with

CLKDIV = 10

FS1, FS0: (Default = ±, 1) Filter-Selection Bits0 These bits

determine the output data rate and the digital-filter cutoff

frequency0 See Table 13 for FS1 and FS± settings0

Recalibrate when the filter characteristics are changed0

24 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Test Register

This register is reserved for factory testing of the device0

For proper operation of the MX77±5, do not change this

register from its default power-on reset values0

Write to the calibration registers in normal mode only0

After writing to the calibration registers, the devices

implement the new offset and gain-register calibration

coefficients at the beginning of a new acquisition0 To

ensure the results are valid, discard the first conversion

result after writing to the calibration registers0

Offset and Gain-Calibration Registers

The MX77±5 contains one offset register and one gain

register for each input channel0 Each register is 24 bits

wide and can be written and read0 The offset registers

store the calibration coefficients resulting from a zero-

scale calibration, and the gain registers store the cali-

bration coefficients resulting from a full-scale

calibration0 The data stored in these registers are 24-bit

straight binary values representing the offset or gain

errors associated with the selected channel0 A 24-bit

read or write operation can be performed on the cali-

bration registers for any selected channel0 During a

write operation, 24 bits of data must be written to the

register, or no data is transferred0

To ensure that a conversion is not made using invalid

calibration data, drive FSYNC high prior to writing to the

calibration registers, and then release FSYNC low to ini-

tiate conversion0

Power-On Reset

At power-up, the serial-interface, logic, digital-filter, and

modulator circuits are reset0 The registers are set to

their default values0 The device returns to wait for a

write to the communications register0 For accurate

measurements, perform calibration routines after

power-up0 Allow time for the external reference and

oscillator to start up before starting calibration0 See the

Typical Operating Characteristics for typical external-

oscillator startup times0

Table 12. Clock Register

FIRST BIT (MSB)

(LSB)

CLKOUT

DISABLE

CLOCK

DIVIDER

CLOCK

SELECT

FUNCTION

RESERVED

FILTER SELECT

Name

MXID ZERO ZERO

CLKDIS

±

CLKDIV

±

CLK

1

FS1

±

FS±

1

Defaults

1

±

Table 13. Output Data Rate and Notch Frequency vs. Filter Select and CLKIN Frequency

CLKIN FREQUENCY

(MHz)*

OUTPUT DATA RATE

(FIRST NOTCH) (Hz)

-3dB FILTER CUTOFF**

(Hz)

CLK

FS1

FS0

f

CLKIN

1

±

1

±

1

±

1

±

1

±

1

±

1

±

1

2±

25

5024

6055

1

1±±

2±±

5±

2602±

5204±

1301±

1507±

6505±

1310±±

1

204576

6±

25±

5±±

*These values are given for CLKDIV = 0. External clock frequency, f

, can be two times the values in this column if CLKDIV = 1.

**The filter -3dB filter cutoff frequency = 0.262 x filter first-notch frequency.

CLKIN

______________________________________________________________________________________ 25

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Reset

Table 14. Filter Select and Decimation Rate

Drive RESET low to reset the MX77±5 to power-on reset

status0 DRDY goes high and all communication to the

MX77±5 is ignored while RESET is low0 Upon releasing

RESET, the device must be reconfigured to begin a con-

version0 The device returns to waiting for a write to the

communication register after a reset has been performed0

Perform a calibration sequence following a reset for

accurate conversions0

CLK

FS1

FS0

DECIMATION RATE

±

1

±

391

313

78

±

1

±

1

39

±

384

32±

77

±

1

The MX77±5 clock generator continues to run when

RESET is pulled low0 This allows any device running from

CLKOUT to be uninterrupted when the device is in reset0

1

±

1

38

Selecting Custom Output Data Rates and

First-Notch Frequency

Writing to the clock and setup registers after configuring

and initializing the host processor serial port sets up the

MX77±50 Use self- or system calibrations to minimize off-

set and gain errors (see the Calibration section for more

details)0 Set FSYNC = ± to begin calibration or conver-

sion0 The MX77±5 performs free-running acquisitions

when FSYNC is low (see the Using FSYNC section)0 The

µC can poll the DRDY bit of the communications register

and read the data register when the DRDY bit returns a

±0 For hardware polling, the DRDY output goes low when

the new data is valid in the data register0

The recommended frequency range of the external clock

is 4±±kHz to 5MHz0 The output data rate and first notch

frequency are dependent on the decimation rate of the

digital filter0 Table 14 shows the available decimation

rates of the digital filter0 The output data rate and filter first

notch is calculated using the following formula:

f

CLKIN

output data rate =

× ±05

128 × Decimation Rate

(if CLKDIV = 1)

The data register can be read multiple times while the

next conversion takes place0

f

CLKIN

output data rate =

The flow diagram in Figure 11 shows an example

sequence required to perform a conversion on channel

1 (AIN1+ / AIN1-) after a power-on reset0

128 × Decimation Rate

(if CLKDIV = ±)

Note: First-notch filter frequency = output data rate0

Performing a Conversion

At power-on reset, the MX77±5 expects a write to the

communications register0 Writing to the communica-

tions register selects the acquisition channel, read/write

operation for the next register, power-down/normal

mode, and address of the following register to be

accessed0 The MX77±5 has six user-accessible regis-

ters, which control the function of the device and allow

the result to be read0 Write to the communications reg-

ister before accessing any other registers0

26 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

POWER-ON RESET

INITIALIZE µC/µP SERIAL

PORT

WRITE TO THE COMMUNICATIONS

REGISTER. SELECT CHANNEL 1 AND SET

NEXT OPERATION AS A WRITE TO THE

CLOCK REGISTER.

(0x20)

WRITE TO THE CLOCK REGISTER. ENABLE

EXTERNAL OSCILLATOR. SELECT

OUTPUT UPDATE RATE OF 60Hz.

(0xA5)

WRITE TO THE COMMUNICATIONS

REGISTER. SELECT CHANNEL 1 AND SET

NEXT OPERATION AS A WRITE TO THE

SETUP REGISTER.

(0x10)

WRITE TO THE SETUP REGISTER. SET

SELF-CALIBRATION MODE, GAIN TO 0,

UNIPOLAR MODE, UNBUFFERED MODE.

BEGIN SELF-CALIBRATION/CONVERSION

BY CLEARING FSYNC.

(0x44)

HARDWARE POLLING

SOFTWARE POLLING

WRITE TO COMMUNICATIONS REGISTER.

SET NEXT OPERATION AS A READ FROM

THE COMMUNICATIONS REGISTER.

(0x08)

POLL DRDY

OUTPUT

1 (DATA

NOT

READY)

READ THE COMMUNICATIONS REGISTER

(8 BITS)

POLL DRDY

BIT

1 (DATA NOT

READY)

WRITE TO THE COMMUNICATIONS

REGISTER. SET NEXT OPERATION AS A

READ FROM THE DATA REGISTER.

(0x38)

0 (DATA

READY)

0 (DATA

READY)

READ THE DATA REGISTER

(16 BITS)

Figure 11. Sample Flow Diagram for Data Conversion

______________________________________________________________________________________ 27

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Using FSYNC

When FSYNC = 1, the digital filter and analog modula-

tor are in a reset state, inhibiting normal operation0 Set

FSYNC = ± to begin calibration or conversion0

When zero-scale or full-scale calibration is selected,

DRDY goes low 4 x 1/output data rate + t after FSYNC

P

goes low (or while the zero-scale or full-scale calibra-

tion command is issued when FSYNC is already low) to

indicate new data in the data register (see the

Calibration section)0

When configured for normal operation (MD± and MD1

set to ±), DRDY goes low 3 x 1/output data rate after

FSYNC goes low to indicate that the new conversion

result is ready to be read from the data register0 DRDY

returns high when a read operation on the data register

is complete0 As long as FSYNC remains low, the

MX77±5 performs free-running conversions with the

data registers updating at the output data rate0 If the

valid data is not read before the next conversion result

Calibration

To compensate for errors introduced by temperature

variations or system DC offsets, perform an on-chip cal-

ibration0 Select calibration options by writing to the

MD1 and MD± bits in the setup register (Table 9)0

Calibration removes gain and offset errors from the

device and/or the system0 Recalibrate with changes in

ambient temperature, supply voltage, bipolar/unipolar

mode, PGA gain, and output data rate0

is ready, DRDY returns high for 5±± x 1/f

before

CLKIN

going low again to indicate a new conversion0 Set

FSYNC = 1 to stop converting data0

The MX77±5 offers two calibration modes, self-calibra-

tion and system calibration0 The channels of the

MX77±5 are independently calibrated (Table 8)0 The

calibration coefficients resulting from a calibration

sequence on a selected channel are stored in the corre-

sponding offset and gain-register pair0

If FSYNC goes high while DRDY is low (indicating that

valid data has not yet been read from the data regis-

ter), DRDY does not reset high0 DRDY remains low until

the new data is read from the data register or until

FSYNC goes low to begin a new conversion0

Table 15 provides the duration-to-mode bits and dura-

tion-to-DRDY for each calibration sequence0 Duration-to-

mode bits provide the time required for the calibration

sequence to complete (MD1 and MD± return to ±)0

Duration-to-DRDY provides the time until the first conver-

sion result is valid in the data register (DRDY goes low)0

Self- and system calibration automatically calculate the

offset and gain coefficients, which are written to the off-

set and gain registers0 These offset and gain coeffi-

cients provide offset and gain-error correction for the

specified channel0

Self-Calibration

Self-calibration compensates for offset and gain errors

internal to the ADC0 Prior to calibration, set the PGA gain,

unipolar/bipolar mode, and input channel setting0 During

self-calibration, AIN+ and AIN- of the selected channel

are internally shorted together0 The ADC calibrates this

condition as the zero-scale output level0 For bipolar

mode, this zero-scale point is the midscale of the bipolar

transfer function0

The pipeline delay necessary to ensure that the first

conversion result is valid is t (t = 2±±± x 1/f )0

CLKIN

P

When selecting self-calibration (MD1 = ±, MD± = 1),

DRDY goes low 9 x 1/output data rate + t after FSYNC

P

goes low (or after a write operation to the setup register

with MD1 = ± and MD± = 1 is performed while FSYNC

is already low) to indicate new data in the data register0

The pipeline delay required to ensure that the first con-

version result is valid is t (t = 2±±± x 1/f )0

CLKIN

P

Table 15. Calibration Sequences

CALIBRATION TYPE

DURATION-TO-MODE

DURATION TO DRDY**

BITS*

CALIBRATION SEQUENCE

(MD1, MD0)

Internal zero-scale calibration at

Self-calibration (±,1)

selected gain + internal full-scale

calibration at selected gain

6 x 1/output data rate

9 x 1/output data rate + t

P

Zero-scale calibration on AIN at

selected gain

Zero-scale system calibration (1,±)

Full-scale system calibration (1,1)

3 x 1/output data rate

4 x 1/output data rate + t

P

Full-scale calibration on AIN at

selected gain

P

*Duration-to-mode bits represents the completion of the calibration sequence.

**Duration to DRDY represents the time at which a new conversion result is available in the data register.

28 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Next, an internally generated voltage (V

applied across AIN+ and AIN-0 This condition results in

the full-scale calibration0

/ GAIN) is

After performing a zero-scale calibration, connect the

analog inputs to the full-scale voltage level (V

REF

/

REF

GAIN)0 Perform a full-scale calibration by setting MD1 =

1 and MD± = 10 After 3 x 1/output data rate, MD1 and

MD± both return to zero at the completion of full-scale

calibration0 DRDY goes high at the beginning of cali-

bration and returns low after calibration is complete

and new data is in the data register (4 x 1/output data

rate)0 The time until DRDY goes low is comprised of

one full-scale calibration sequence (3 x 1/output data

rate) and one conversion on the AIN voltage (1 x 1/out-

put data rate)0 If DRDY is low before or goes low during

the calibration-command write to the setup register,

DRDY takes up to one additional modulator cycle

Start self-calibration by setting MD1 = ±, MD± = 1, and

FSYNC = ± in the setup register0 Self-calibration com-

pletes in 6 x 1/output data rate0 The MD1 and MD± bits

both return to zero at the end of calibration0 The device

returns to normal acquisition mode and performs a con-

version, which completes in 3 x 1/output data rate after

the self-calibration sequence0

The DRDY output goes high at the start of calibration

and falls low when the calibration is complete and the

next conversion result is valid in the data register0 The

total time for self-calibration and one conversion (time

until DRDY goes low) is 9 x 1/output data rate0 If DRDY

is low before or goes low during the calibration com-

mand write to the setup register, DRDY takes up to one

(128/f

) to return high to indicate a calibration or

CLKIN

conversion in progress0

In bipolar mode, the midpoint (zero scale) and positive

full scale of the transfer function are used to calculate the

calibration coefficients of the gain and offset registers0 In

unipolar mode, system calibration is performed using the

two endpoints of the transfer function (Figures 4 and 5)0

additional modulator cycle (128/f

) to return high to

CLKIN

indicate a calibration or conversion in progress0

System Calibration

System calibration compensates for offset and gain

errors for the entire analog signal path including the

ADC, signal conditioning, and signal source0 System

calibration is a two-step process and requires individ-

ual zero-scale and full-scale calibrations on the select-

ed channel at a specified PGA gain0 Recalibration is

recommended with changes in ambient temperature,

supply voltage, bipolar/unipolar mode, PGA gain, and

output data rate0 Before starting calibration, set the

PGA gain and the desired channel0

Power-Down Modes

The MX77±5 includes a power-down mode to save

power0 Select power-down mode by setting PD = 1 in

the communications register0 The PD bit does not affect

the serial interface or the status of the DRDY line0 While

in power-down mode, the MX77±5 retains the contents

of all of its registers0 Placing the part in power-down

mode reduces current consumption to 2µA (typ) when

in external clock mode and with CLKIN connected to

V

or GND0 If DRDY is high before the part enters

DD

Set the zero-scale reference point across AIN+ and AIN-0

Start the zero-scale calibration by setting MD1 = 1, MD±

= ±, and FSYNC = ± in the setup register0 When zero-

scale calibration is complete (3 x 1/output data rate),

MD1 and MD± both return to zero0 DRDY goes high at the

start of the zero-scale system calibration and returns low

when there is a valid word in the data register (4 x 1/out-

put data rate)0 The time until DRDY goes low is com-

prised of one zero-scale calibration sequence (3 x

1/output data rate) and one conversion on the AIN volt-

age (1 x 1/output data rate)0 If DRDY is low before or

goes low during the calibration command write to the

setup register, DRDY takes up to one additional modula-

power-down mode, then DRDY remains high until the

part returns to normal operation mode and new data is

available in the data register0 If DRDY is low before the

part enters power-down mode, indicating new data in

the data register, the data register can be read during

power-down mode0 DRDY goes high at the end of this

read operation0 If the new data remains unread, DRDY

stays low until the MX77±5 is taken out of power-down

mode and resumes data conversion0 Resume normal

operation by setting PD = ±0 The device begins a new

conversion with a result appearing in 3 x 1/output data

rate + t , where t = 2±±± x 1/f , after PD is set to

CLKIN

P

±0 If the clock is stopped during power-down mode,

allow sufficient time for the clock to start up before

resuming conversion0

tor cycle (128/f

) to return high to indicate a calibra-

CLKIN

tion or conversion in progress0

If CLKDIS = ±, CLKOUT remains active during power-

down mode to provide a clock source for other devices

in the system0

______________________________________________________________________________________ 29

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Applications Information

V

DD

Applications Examples

10µF

Strain-Gauge Measurement

Connect the differential inputs of the MX77±5 to the

bridge network of the strain gauge0 In Figure 12, the ana-

log positive supply voltage powers the bridge network

and the MX77±5, along with the reference voltage in a

ratiometric configuration0 The on-chip PGA allows the

MX77±5 to handle an analog input voltage range as low

0.1µF

CLKIN

REF+

REF-

V

DD

0.1µF

R

REF

as 2±mV to full scale0

CLKOUT

Temperature Measurement

0.1µF

Use the MX77±5 for temperature measurements from a

thermocouple (Figure 13)0 Operate the MX77±5 in

buffered mode to allow large decoupling capacitors at

the analog inputs0 The decoupling capacitors eliminate

any noise pickup from the thermocouple leads0 AIN1- is

biased up at the reference voltage to accommodate the

reduced common-mode input range in buffered mode0

CS

SCLK

DIN

MX7705

ACTIVE

GAUGE

R

AIN1+

AIN1-

DOUT

DRDY

RESET

DUMMY

GAUGE

R

GND

Optical Isolation

For applications that require an optically isolated inter-

face, see Figure 140 With 6N136-type optocouplers,

maximum clock speed is 4MHz0 Maximum clock speed

is limited by the degree of mismatch between the indi-

vidual optocouplers0 Faster optocouplers allow faster

signaling at a higher cost0

Figure 12. Strain-Gauge Measurement

Layout, Grounding, Bypassing

Use PC boards with separate analog and digital

ground planes0 Connect the two ground planes togeth-

er at the MX77±5 GND0 Isolate the digital supply from

the analog with a low-value resistor (1±Ω) or ferrite

bead when the analog and digital supplies come from

the same source0

V

DD

= 3V/5V*

10

µ

F

10

µ

V

DD

CLKIN

Ensure that digital return currents do not pass through

the analog ground and that return-current paths are low

impedance0 A 5mA current flowing through a PC board

ground trace impedance of only ±0±5Ω creates an error

voltage of about 25±µV0

AIN1+

AIN1-

THERMOCOUPLE

JUNCTION

CLKOUT

MX7705

Layout the PC board to ensure digital and analog sig-

nal lines are kept separate0 Do not run digital lines

(especially the SCLK and DOUT) parallel to any analog

lines0 If they must cross another, do so at right angles0

SCLK

DIN

1.225V/2.5V

REFERENCE*

REF+

REF-

0.1

µ

F

DOUT

DRDY

RESET

Bypass V

to the analog ground plane with a ±01µF

DD

0.1

capacitor in parallel with a 1µF to 1±µF low-ESR capac-

itor0 Keep capacitor leads short for best supply-noise

rejection0 Bypass REF+ and REF- with a ±01µF capaci-

tor to GND0 Place all bypass capacitors as close to the

device as possible to achieve the best decoupling0

GND

*USE A 1.225V REFERENCE FOR V = 3V OR A 2.5V REFERENCE FOR V = 5V.

DD

Figure 13. Temperature Measurement

30 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Definitions

ISO

3V/5V

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line0 This

straight line is either a best-straight-line fit or a line

drawn between the endpoints of the transfer function,

once offset and gain errors have been nullified0 INL for

the MX77±5 is measured using the endpoint method0

This is the more conservative method0

+V

DD

V

DD

2kΩ

V

CC

DIN

6N136

470kΩ

MOSI

MX7705

Unipolar Offset Error

For an ideal converter, the first transition occurs at ±05

LSB above zero0 Offset error is the amount of deviation

between the measured first transition point and the

ideal point0

2kΩ

V

CC

SCLK

6N136

470kΩ

Bipolar Zero Error

In bipolar mode, the ideal midscale transition occurs at

AIN+ - AIN- = ±0 Bipolar zero error is the measured

deviation from this ideal value0

SCK

V

CC

2kΩ

6N136

470kΩ

Gain Error

With a full-scale analog input voltage applied to the

ADC (resulting in all ones in the digital code), gain error

is defined as the amount of deviation between the ideal

transfer function and the measured transfer function

(with the offset error or bipolar zero error removed)0

Gain error is usually expressed in LSB or a percent of

full-scale range (%FSR)0

MISO

DOUT

CS

Positive Full-Scale Error

For the ideal transfer curve, the code edge transition

that causes a full-scale transition to occur is 105 LSB

below full scale0 The positive full-scale error is the dif-

ference between this code transition of the ideal trans-

fer function and the actual measured value at this code

transition0 Unlike gain error, unipolar offset error and

bipolar zero error are included in the positive full-scale

error measurement0

Figure 14. Optically Isolated Interface

both input terminals0 The common-mode signal can be

either an AC or a DC signal or a combination of the two0

CMR is often expressed in decibels0 Common-mode

rejection ratio (CMRR) is the ratio of the differential sig-

nal gain to the common-mode signal gain0

Bipolar Negative Full-Scale Error

For the ideal transfer curve, the code edge transition that

causes a negative full-scale transition to occur is ±05 LSB

above negative full scale0 The negative full-scale error is

the difference between this code transition of the ideal

transfer function and the actual measured value at this

code transition0

Power-Supply Rejection Ratio

Power-supply rejection ratio (PSRR) is the ratio of the

input signal change (V) to the change in the converter

output (V)0 It is typically measured in decibels0

Chip Information

TRANSISTOR COUNT: 42,±±±

Input Common-Mode Rejection

Input common-mode rejection (CMR) is the ability of a

device to reject a signal that is common to or applied to

PROCESS: BiCMOS

______________________________________________________________________________________ 31

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications0 For the latest package outline information,

go to www.maxim-ic.com/packages0)

32 ______________________________________________________________________________________

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications0 For the latest package outline information,

go to www.maxim-ic.com/packages0)

INCHES

MILLIMETERS

N

MAX

2.65

0.30

0.49

0.32

DIM

A

MIN

2.35

0.10

0.35

0.23

0.093

0.004

0.014

0.009

0.104

0.012

0.019

0.013

A1

B

C

e

0.050

1.27

H

E

0.291

0.394

0.016

0.299

0.419

0.050

7.40

10.00

0.40

7.60

10.65

1.27

H

L

VARIATIONS:

INCHES

1

MILLIMETERS

TOP VIEW

MAX

0.413

0.463

0.512

0.614

0.713

MAX

DIM

D

MIN

10.10

11.35

12.60

15.20

17.70

N MS013

0.398

0.447

0.496

0.598

0.697

10.50 16 AA

11.75 18 AB

13.00 20 AC

15.60 24 AD

18.10 28 AE

D

C

A

B

e

0 -8

A1

L

FRONT VIEW

SIDE VIEW

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, .300" SOIC

APPROVAL

DOCUMENT CONTROL NO.

REV.

1

21-0042

B

1

______________________________________________________________________________________ 33

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications0 For the latest package outline information,

go to www.maxim-ic.com/packages0)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products0


型号：	MX7705EPE+
厂家：	MAXIM INTEGRATED PRODUCTS
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