MX7837BR+T [MAXIM]
D/A Converter, 2 Func, Parallel, 8 Bits Input Loading, 4us Settling Time, PDSO24, PLASTIC, SOP-24;
| 型号： | MX7837BR+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 2 Func, Parallel, 8 Bits Input Loading, 4us Settling Time, PDSO24, PLASTIC, SOP-24 |
| 文件： | 总12页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0158; Rev 0; 7/93
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
3/MX847
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MX7837/MX7847 are dual, 12-bit, multiplying, volt-
age-output digital-to-analog converters (DACs). Each
DAC has an output amplifier and a feedback resistor.
The output amplifier is capable of developing ±10V
across a 2kΩ load. The amplifier feedback resistor is
internally connected to VOUT on the MX7847. No exter-
nal trims are required to achieve full 12-bit performance
over the entire operating temperature range.
♦ Two 12-Bit Multiplying DACs with Buffered
Voltage Output
♦ Specified with ±12V or ±15V Supplies
♦ No External Adjustments Required
♦ Fast Timing Specifications
♦ 24-Pin DIP and SO Packages
The MX7847 has a 12-bit parallel data input, whereas
the MX7837 operates with a double-buffered 8-bit-bus
interface that loads data in two write operations. All
logic signals are level triggered and are TTL and CMOS
compatible. Fast timing specifications make these
DACs compatible with most microprocessors.
♦ 12-Bit Parallel Interface (MX7847)
8-Bit + 4-Bit Interface (MX7837)
______________Ord e rin g In fo rm a t io n
ERROR
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
________________________Ap p lic a t io n s
MX7837JN
MX7837KN
MX7837JR
MX7837KR
0°C to +70°C 24 Narrow Plastic DIP
0°C to +70°C 24 Narrow Plastic DIP
0°C to +70°C 24 Wide SO
±1
±1/2
±1
Small Component-Count Analog Systems
Digital Offset/Gain Adjustments
Industrial Process Control
Function Generators
0°C to +70°C 24 Wide SO
±1/2
±1
MX7837C/D 0°C to +70°C Dice*
Ordering Information continued on last page.
* Contact factory for availability and processing to MIL-STD-883.
Automatic Test Equipment
Automatic Calibration
_________Typ ic a l Op e ra t in g Circ u it s
Machine and Motion Control Systems
Waveform Reconstruction
Synchro Applications
V
DD
MSB
INPUT
LATCH
LSB
INPUT
LATCH
_________________P in Co n fig u ra t io n s
4
8
DAC LATCH A
12
TOP VIEW
R
FBA
CS
1
2
24 DB0/DB8
V
R
DB1/DB9
DB2/DB10
DB3/DB11
DB4
23
22
21
20
19
18
17
16
15
REFA
V
OUTA
FBA
DAC A
V
REFB
V
3
REFA
AGNDA
V
4
OUTA
AGNDA
5
R
FBB
DB0
DB7
MX7837
V
DD
DB5
6
DAC B
V
OUTB
V
SS
7
DB6
DB7
12
AGNDB
8
DAC LATCH B
AGNDB
LDAC
CS
V
9
OUTB
A0
A1
8
4
LSB
INPUT
LATCH
CONTROL
LOGIC
MSB
INPUT
LATCH
V
10
11
12
WR
A0
REFB
MX7837
DGND
14 LDAC
WR
13
A1
R
FBB
DGND
V
SS
DIP/SO
MX7847 on last page.
MX7847 on last page.
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
ABSOLUTE MAXIMUM RATINGS
V
to DGND, AGNDA, AGNDB............................-0.3V to +17V
to DGND, AGNDA, AGNDB (Note 1) ..............+0.3V to -17V
Operating Temperature Ranges:
DD
V
MX78_7J_/K_ ........................................................0°C to +70°C
MX78_7A_/B_ .................................................. -40°C to +85°C
MX78_7SQ/TQ ............................................... -55°C to +125°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
SS
V
, V
to AGNDA, AGNDB .. (V - 0.3V) to (V + 0.3V)
REFA REFB SS DD
AGNDA, AGNDB to DGND.........................-0.3V to (V + 0.3V)
DD
V
, V
to AGNDA, AGNDB .....(V - 0.3V) to (V + 0.3V)
OUTA OUTB SS DD
R
, R
to AGNDA, AGNDB .......(V - 0.3V) to (V + 0.3V)
FBA FBB SS DD
Digital Inputs to DGND...............................-0.3V to (V + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW
SO (derate 11.76mW/°C above +70°C).........................941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C) ..1000mW
Note 1: If V is open-circuited with V and either AGND applied, the V pin will float positive exceeding the Absolute Maximum Ratings.
SS
DD
SS
If this possibility exists, a Schottky diode connected between V and GND ensures the maximum ratings will be observed.
SS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
3/MX847
ELECTRICAL CHARACTERISTICS
(V = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, V
= V
= +10V, R = 2kΩ, C = 100pF,
DD
SS
REFA
REFB L L
V
connected to R (MX7837), T = T
to T
, unless otherwise noted.) (Note 2)
OUT
FB
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (Note 3)
Resolution
N
12
Bits
LSB
LSB
MX78_7J/A/S
MX78_7K/B/T
±1
±1/2
±1
±2
±4
±3
±5
±5
±2
±7
±4
Relative Accuracy
Differential Nonlinearity
INL
DNL
Guaranteed monotonic
= +25°C
Loaded with all 0s,
tempco =
T
A
MX78_7J/A
Zero-Code Offset Error
mV
T = T
A
to T
MX78_7K/B
MX78_7S/T
MAX
MIN
±5µV/°C typ
MX78_7J/A/S
MX78_7K/B/T
MX78_7J/A/S
MX78_7K/B/T
T
A
= +25°C
Loaded with all 1s,
tempco = ±2ppm
of FSR/°C typ
Gain Error
LSB
T = T
A
to T
MAX
MIN
REFERENCE INPUTS
V
Input Resistance
8
10
13
±3
kΩ
REF
V
, V
Resistance
REFA REFB
Matching
±0.5
%
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
V
2.4
INH
V
V
INL
0.8
±1
8
Input Current
Digital inputs at 0V and V
µA
pF
DD
Input Capacitance (Note 4)
ANALOG OUTPUTS
DC Output Impedance
Short-Circuit Current
0.2
15
Ω
V
connected to AGND
mA
OUT
2
_______________________________________________________________________________________
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
3/MX847
ELECTRICAL CHARACTERISTICS (continued)
(V = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, V
= V
= +10V, R = 2kΩ, C = 100pF,
DD
SS
REFA
REFB L L
V
connected to R (MX7837), T = T
to T
, unless otherwise noted.) (Note 1)
OUT
FB
A
MIN
MAX
PARAMETER
POWER REQUIREMENTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
Range
Range
V
11.4
16.5
-16.5
10
V
V
DD
DD
V
SS
V
SS
-11.4
Positive Supply Current
Negative Supply Current
I
DD
Output unloaded
Output unloaded
5
4
mA
mA
I
SS
6
∆Gain/∆V
V
= 15V ±5%, V
REF
= -10V
= 10V
±0.01
±0.01
±0.01
±0.01
DD
DD
∆Gain/∆V
V
= -15V ±5%, V
SS
SS REF
Power-Supply Rejection
% per %
∆Gain/∆V
V
DD
= 12V ±5%, V
REF
= -8.9V
= 8.9V
DD
∆Gain/∆V
V
= -12V ±5%, V
SS
SS REF
AC CHARACTERISTICS
Voltage-Output Settling
Time
Settling time to within ±1/2LSB of final DAC value;
DAC latch alternately loaded will all 0s and all 1s
t
4
7
µs
S
Slew Rate
V/µs
nV-s
Digital-to Analog Glitch
Impulse
DAC latch alternately loaded with 01…11 and
10…00
Q
60
Channel-to-Channel Isolation
V
= 20p-p, 10kHz sine wave, Alternate DAC
REF
(V
V
REFB
to V
,
)
-95
dB
REFA
OUTB
Latch Loaded with all 0s
V = 20V , 10kHz sine wave, latches loaded
REF_
to V
OUTA
Multiplying Feedthrough
Error
p-p
-90
1
dB
with all 0s
Unity-Gain Small-Signal
Bandwidth
V
REF
with all 1s
= 100mV sine wave, DAC latch loaded
p-p
MHz
V
all 1s
= 20V
Sine wave, DAC latch loaded with
, 1kHz, DAC latch loaded with all 1s
REF
p-p
Full-Power Bandwidth
Total Harmonic Distortion
Digital Crosstalk
125
-88
10
kHz
dB
THD
V
= 6V
REF RMS
Code transition from all 0s to all 1s; see Typical
Operating Characteristics graphs
nV-s
Output Noise Voltage at
+25°C (0.1Hz to 10Hz)
Amplifier noise and Johnson noise of R
2
µV
RMS
FB
Note 2: The analog outputs can swing to within 2.5V of the supply rails. Hence, for good linearity towards full-scale, |V
| and |V
| must
REFA
REFB
be at least 2.5V lower than V and |V |. Tests done with supply voltages below ±12.5V are done with V
= V
= ±8.9V.
DD
SS
REFA
REFB
Note 3: Static performance tested at V = +15V, V = -15V. Performance over supplies guaranteed by PSRR test.
DD
SS
Note 4: Guaranteed by design.
_______________________________________________________________________________________
3
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
TIMING CHARACTERISTICS
(V = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, T = T
to T
, unless otherwise noted.) (Note 5)
DD
SS
A
MIN
MAX
MX78_7J/K/A/B
MX78_7S/T
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
MIN
MAX
CS to WR Setup Time
CS to WR Hold Time
WR Pulse Width
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
0
0
ns
ns
ns
ns
ns
ns
ns
ns
0
0
80
80
10
15
15
80
80
80
10
15
15
80
Data to WR Setup Time
Data to WR Hold Time
Address to WR SetupTime
Address to WR Hold Time
LDAC Pulse Width
MX7837 only
MX7837 only
MX7837 only
Note 5: All input signals are specified with t = t ≤ 5ns. Logic swing is 0V to 5V.
3/MX847
R
F
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, V = 15V, V = -15V, R = 2kΩ, C = 100pF, unless otherwise noted)
A
DD
SS
L
L
OUTPUT VOLTAGE SWING
vs. RESISTIVE LOAD
NOISE SPECTRAL DENSITY
SMALL-SIGNAL FREQUENCY RESPONSE
5
25
20
15
10
5
V
REF
= 20V at 1kHz
p-p
V
= 0V
REF
300
DAC CODE = 11...111
GAIN = -1
0
-5
V
= 100mV
p-p
REF
200
100
DAC CODE = 11...111
GAIN = -1
-10
-15
-20
-25
0
0
10
100
1k
10k
100k
100
1k
10k
100k
1M
10M
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
LOAD RESISTANCE (Ω)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH = 80kHz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH > 500kHz)
MULTIPLYING FEEDTHROUGH ERROR
-35
-40
-45
-50
-55
-94
-60
-65
-70
-75
-80
-85
-90
-95
-100
V
= 6V
RMS
REF
V
= 20V
= AGNDB
V
= 6V
REFA
p-p
REF RMS
DAC CODE = 111...111
V
DAC CODE = 111...111
REFB
-96
-98
DAC CODE = 00...00
-100
-102
-104
-106
-60
-65
-70
-75
-80
-85
1k
10k
100k
1M
100
1k
FREQUENCY (Hz)
10k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
4
_______________________________________________________________________________________
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
3/MX847
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, V = 15V, V = -15V, R = 2kΩ, C = 100pF, unless otherwise noted.)
A
DD
SS
L
L
LARGE-SIGNAL PULSE RESPONSE
SMALL-SIGNAL PULSE RESPONSE
AGNDA
AGNDA
A
A
A = V , 50mV/div
OUTA
A = V , 5V/div
OUTA
TIMEBASE = 2µs/div
= ±100mV SQUARE WAVE
TIMEBASE = 2µs/div
V = ±10V SQUARE WAVE
REFA
V
REFA
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
MX7837 MX7847
1
–
–
1
CS
Chip Select – active-low logic input
CSA
Chip-Select Input for DAC A – active-low logic input
Amplifier Feedback Resistor for DAC A
Chip-Select Input for DAC B – active-low logic input
Reference Input Voltage for DAC A
Analog Output Voltage from DAC A
Analog Ground for DAC A
2
–
R
FBA
–
2
CSB
3
3
V
REFA
4
4
V
OUTA
5
5
AGNDA
6
6
V
DD
Positive Power Supply
7
7
V
SS
Negative Power Supply
8
8
AGNDB
Analog Ground for DAC B
9
9
V
Analog Output Voltage from DAC B
Reference Input Voltage for DAC B
Digital Ground
OUTB
10
11
12
–
10
11
–
V
REFB
DGND
R
Amplifier Feedback Resistor for DAC B
Data Bit 11 (MSB)
FBB
12
DB11
Write Input – active-low logic input (MX7837); positive-edge-triggered input used with
CSA and CSB (MX7847)
13
13
WR
14
–
–
LDAC
DB10-DB0
A1
Asynchronous Load – DAC input, active-low
Data Bit 10 to Data Bit 0 (LSB)
14-24
15
–
–
–
Address Input – most significant address input for input latches
Address Input – least significant address input for input latches
Data Bit 7 to Data Bit 4
16
A0
17-20
DB7-DB4
DB3/DB11-
DB0/DB8
21-24
–
Data Bit 3 to Data Bit 0 (LSB), or Data Bit 11 (MSB) to Data Bit 8
_______________________________________________________________________________________
5
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
In t e rfa c e Lo g ic In fo rm a t io n
(MX7 8 4 7 )
V
REF
R
R
R
Figure 2 shows the MX7847 input control logic. The
device contains two independent DACs, each with its
own CS input and a common WR input. CSA and WR
control data loading to the DAC A latch, and CSB and
WR control data loading to the DAC B latch. The latch-
es are edge triggered so that input data is latched to
the respective latch on WR's rising edge. The same
data will be latched to both DACs if CSA and CSB are
low and WR is taken high. Table 1 shows the device
control-logic truth table, and Figure 3 shows the write-
cycle timing diagram.
2R
C
2R
B
2R
2R
S9
2R
S8
2R
S0
2R
R/
2
A
V
OUT
AGND
SHOWN FOR ALL 1s ON DAC
Table 1. MX7847 Truth Table
Figure 1. D/A Simplified Circuit Diagram
CSA
CSB
WR
1
Function
No Data Transfer
3/MX847
X
1
0
1
0
X
1
1
0
0
1
_______________De t a ile d De s c rip t io n
X
No Data Transfer
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
D/A S e c t io n
Figure 1 shows a simplified circuit diagram for one of
the DACs and the output amplifier. Using a segmented
scheme, the two MSBs of the 12-bit data word are
decoded to drive the three switches (A to C). The
remaining 10 bits drive the switches (S0 to S9) in a
standard R-2R ladder.
0
0
0
1
X = Don't Care
= Rising Edge Triggered
Each switch (A to C) directs 1/4 of the total reference
current, and the remaining current passes through the
R-2R section.
In t e rfa c e Lo g ic In fo rm a t io n
(MX7 8 3 7 )
The output amplifier and feedback resistor convert cur-
rent to voltage as follows: VOUT_ = (-D)(VREF_), where D
is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The MX7837 input loading structure is configured for
interfacing with 8-bit-wide data-bus microprocessors.
Each DAC has two 12-bit latches: an input latch, and a
DAC latch. Each input latch is subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch.
The data held in the DAC latches determines the out-
puts. Figure 4 shows the MX7837 input control logic,
and Figure 5 shows the write-cycle timing diagram.
The output amplifier is capable of developing ±10V
across a 2kΩ load. It is internally compensated and
settles to 0.01% FSR (1/2LSB) in less than 4µs. VOUT
on the MX7837 is not internally connected to RFB
.
CSA, CSB
CSA
DAC A LATCH
t
1
t
2
t
3
WR
WR
DAC B LATCH
CSB
t
5
t
4
DATA
VALID DATA
Figure 3. MX7847 Write-Cycle Timing Diagram
Figure 2. MX7847 Input Control Logic
6
_______________________________________________________________________________________
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
3/MX847
LDAC
DAC B LATCH
DAC A LATCH
A0/A1
ADDRESS VALID
CS
12
12
t
7
t
6
WR
CS
WR
4
DAC A
MS
INPUT
LATCH
4
t
1
t
t
2
3
A0
A1
8
8
DAC A
LS
INPUT
LATCH
t
5
t
4
DATA
VALID DATA
DAC B
MS
INPUT
LATCH
t
8
DAC B
LS
LDAC
INPUT
LATCH
Figure 5. MX7837 Write-Cycle Timing Diagram
8
and independent of WR. This is useful in many appli-
cations, especially in updating multiple MX7837s simul-
taneously. However, be careful when exercising LDAC
during a write cycle; if an LDAC operation overlaps a
CS and WR operation, invalid data may be latched to
the output. To avoid this, LDAC must remain low after
CS or WR have returned high for a period equal to or
greater than t8, the minimum LDAC pulse width.
DB7 DB0
Figure 4. MX7837 Input Control Logic
CS, WR, A0, and A1 control data loading to the input
latches. The eight data inputs accept right-justified
data, which can be loaded to the input latches in any
sequence. If LDAC is held high, loading data to the
input latches will not change the analog output. A0
and A1 determine which input latch will receive the
data when CS and WR are low. Table 2 shows the
control logic truth table.
Un ip o la r Bin a ry Op e ra t io n
Figure 6 shows DAC A (MX7837/MX7847) connected
for unip ola r b ina ry op e ra tion. Simila r c onne c tions
apply for DAC B. When V is an AC signal, the circuit
IN
performs 2-quadrant multiplication. Table 3 shows the
code table for this circuit. On the MX7847, the RFB
Table 2. MX7837 Truth Table
CS WR A1 A0 LDAC
Function
No Data Transfer
feedback resistor is internally connected to VOUT
.
1
X
0
0
0
0
X
1
0
0
0
0
X
X
0
X
X
0
1
1
1
1
1
1
Table 3. Unipolar Code Table
DAC Latch Contents
No Data Transfer
Analog Output, V
DAC A LS Input Latch Transparent
DAC A MS Input Latch Transparent
DAC B LS Input Latch Transparent
DAC B MS Input Latch Transparent
OUT
MSB
LSB
0
1
4095
1
0
−V
×
1111 1111 1111
1000 0000 0000
IN
4096
1
1
Updated Simultaneously from
the Respective Input Latches
2048
4096
1
2
1
1
X
X
0
−V
×
×
=
−
V
IN
IN
X = Don't Care
1
−V
0000 0000 0001
0000 0000 0000
IN
4096
The LDAC input controls 12-bit data transfer from the
input latches to the DAC latches. When LDAC is taken
low, both DAC latches (thus, both analog outputs) are
updated simultaneously. When LDAC is low, the DAC
latches are transparent; DAC data is latched on the ris-
ing edge of LDAC. The LDAC input is asynchronous
0V
V
IN
Note : 1LSB =
4096
_______________________________________________________________________________________
7
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
Bip o la r Op e ra t io n (4 -Qu a d ra n t
Mu lt ip lic a t io n )
Figure 7 shows the MX7837/MX7847 connected for
binary operation. The offset-binary coding is shown in
__________Ap p lic a t io n s In fo rm a t io n
Gro u n d Ma n a g e m e n t
The use of an uninterrupted ground plane is strongly
recommended. AC or transient voltages between ana-
log and digital grounds (between AGNDA/AGNDB and
DGND) c a n inje c t nois e into the a na log c irc uitry.
Conne c t the MX7837/MX7847 AGNDs a nd DGND
dire c tly to the g round pla ne or to a sta r g round to
ensure that they are at the same potential. In complex
s ys te ms with s e p a ra te a na log a nd d ig ita l g round
planes, connect two diodes (1N914 or equivalent) in
inverse parallel between the AGND and DGND pins.
Table 4. When V is an AC signal, the circuit performs
IN
4-quadrant multiplication. R1, R2, and R3 resistors
should be 0.01% ratio matched to maintain gain-error
s p e c ific a tions . On the MX7847, the RFB fe e d b a c k
resistor is internally connected to VOUT
.
Table 4. Bipolar Code Table
DAC Latch Contents
Analog Output, V
OUT
MSB
LSB
2047
P o w e r-S u p p ly De c o u p lin g
To minimize noise, decouple the VDD and VSS lines to
DGND using a 10µF capacitor in parallel with a 0.1µF
ceramic capacitor. Minimize capacitor lead lengths for
best noise rejection.
+V
×
1111 1111 1111
IN
2048
3/MX847
1
+V
×
1000 0000 0001
1000 0000 0000
0111 1111 1111
IN
2048
Op e ra t io n w it h Re d u c e d
0V
P o w e r-S u p p ly Vo lt a g e s
The MX7837/MX7847 are specified for operation with
VDD/VSS = ±11.4V to ±16.5V. However, the output
amplifier requires 2.5V of headroom, so the reference
input should not come within 2.5V of VDD/VSS in order to
maintain accuracy at full scale.
1
−V
×
×
IN
2048
2048
2048
0000 0000 0000
−V
= − V
IN
IN
V
IN
Note : 1LSB =
2048
R2
20k
R1
V
DD
20k
V
OUT
V
DD
R
*
FBA
V
DD
MAX427
R3
V
10k
DD
R
*
V
REFA
V
*
FBA
OUTA
V
IN
V
IN
V
REFA
DAC A
V
OUT
MX7837
MX7847
V
OUTA
DAC A
DGND
AGNDA V
V
SS
SS
V
SS
MX7837
MX7847
* INTERNALLY CONNECTED
ON MX7847
* INTERNALLY CONNECTED ON MX7847
DGND
AGNDA
V
SS
V
SS
Figure 6. Unipolar Binary Operation
Figure 7. Bipolar Offset Binary Operation
8
_______________________________________________________________________________________
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
3/MX847
______P in Co n fig u ra t io n s (c o n t in u e d )
____Ord e rin g In fo rm a t io n (c o n t in u e d )
ERROR
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
TOP VIEW
MX7837AN -40°C to +85°C
MX7837BN -40°C to +85°C
MX7837AR -40°C to +85°C
MX7837BR -40°C to +85°C
MX7837AQ -40°C to +85°C
MX7837BQ -40°C to +85°C
24 Narrow Plastic DIP
24 Narrow Plastic DIP
24 Wide SO
±1
±1/2
±1
CSA
CSB
1
2
24 DB0
DB1
DB2
DB3
DB4
DB5
23
22
21
20
19
18
17
16
15
V
REFA
3
24 Wide SO
±1/2
±1
V
4
24 Narrow CERDIP
24 Narrow CERDIP
OUTA
±1/2
±1
AGNDA
5
MX7847
MX7837SQ -55°C to +125°C 24 Narrow CERDIP
MX7837TQ -55°C to +125°C 24 Narrow CERDIP
V
DD
6
±1/2
±1
V
SS
7
DB6
DB7
MX7847JN
MX7847KN
MX7847JR
MX7847KR
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
24 Narrow Plastic DIP
24 Narrow Plastic DIP
24 Wide SO
AGNDB
8
±1/2
±1
V
9
OUTB
DB8
DB9
V
REFB
24 Wide SO
±1/2
±1
10
11
12
MX7847C/D 0°C to +70°C
MX7847AN -40°C to +85°C
MX7847BN -40°C to +85°C
MX7847AR -40°C to +85°C
MX7847BR -40°C to +85°C
MX7847AQ -40°C to +85°C
MX7847BQ -40°C to +85°C
Dice*
DGND
DB11
14 DB10
WR
24 Narrow Plastic DIP
24 Narrow Plastic DIP
24 Wide SO
±1
13
±1/2
±1
DIP/SO
24 Wide SO
±1/2
±1
24 Narrow CERDIP
24 Narrow CERDIP
±1/2
±1
Typic a l Ope ra ting Circ uits (c ontinue d)
MX7847SQ -55°C to +125°C 24 Narrow CERDIP
MX7847TQ -55°C to +125°C 24 Narrow CERDIP
±1/2
V
DD
DAC LATCH A
DAC A
V
REFA
V
OUTA
V
REFB
AGNDA
DB0
DB11
DAC B
V
OUTB
WR
CSA
CSB
CONTROL
LOGIC
DAC LATCH B
AGNDB
MX7847
DGND
V
SS
_______________________________________________________________________________________
9
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
__________________________________________________________Ch ip To p o g ra p h ie s
MX7837
MX7847
VREFA RFBA
CS DB0/DB8 DB1/DB9 DB2/DB10
V
REFA
CSB CSA DB0
DB1 DB2
DB3/
DB11
DB3
VOUTA
V
OUTA
DB4
DB5
DB4
DB5
AGNDA
AGNDA
3/MX847
0. 250"
(6. 35mm)
0. 250"
(6. 35mm)
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
DB6
DB7
DB6
DB7
AGNDB
VOUTB
AGNDB
V
OUTB
A0
A1
DB8
DB9
V
REFB
DGND R
WR
LDAC
FBB
V
REFB
DGND
DB11 WR
DB10
0. 140"
0. 140"
(3. 56mm)
(3. 56mm)
TRANSISTOR COUNT: 1240;
TRANSISTOR COUNT: 1240;
SUBSTRATE CONNECTED TO V
DD.
SUBSTRATE CONNECTED TO V
DD.
10 ______________________________________________________________________________________
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
3/MX847
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
A
–
D1
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.27
0.20
31.37
1.27
7.62
6.10
0.150
0.080
0.022
0.065
0.012
1.265
0.080
0.325
0.280
3.81
2.03
0.56
1.65
0.30
32.13
2.03
8.26
7.11
B
0.016
B1 0.050
C
D
0.008
1.235
D1 0.050
0.300
E1 0.240
E
E
E1
D
e
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
A
A2
e
A
B
A3
e
–
0.115
0˚
0.400
0.150
15˚
–
10.16
3.81
L
2.92
0˚
α
15˚
21-337A
α
A1
24-PIN PLASTIC
DUAL-IN-LINE
(NARROW)
L
C
e
B1
e
e
A
B
B
PACKAGE
INCHES
MILLIMETERS
DIM
MIN
0.093
MAX
0.104
0.012
0.019
0.013
0.614
0.299
MIN
2.35
0.10
0.35
0.23
15.20
7.40
MAX
2.65
0.30
0.49
0.32
15.60
7.60
A
A1 0.004
B
C
D
E
e
0.014
0.009
0.598
0.291
E
H
0.050 BSC
1.27 BSC
H
h
0.394
0.010
0.016
0˚
0.419
0.030
0.050
8˚
10.00
0.25
0.40
0˚
10.65
0.75
1.27
L
α
8˚
21-338A
D
h x 45˚
α
A
0.127mm
0.004in.
24-PIN PLASTIC
SMALL-OUTLINE
PACKAGE
A1
C
B
e
L
______________________________________________________________________________________ 11
Co m p le t e , Du a l, 1 2 -Bit
Mu lt ip lyin g DACs
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
INCHES
MIN
MILLIMETERS
DIM
MAX
0.200
0.023
0.065
0.015
1.280
0.310
0.320
MIN
–
MAX
5.08
0.58
1.65
0.38
32.51
7.87
8.13
A
B
–
0.014
0.36
0.97
0.20
–
S1
S
B1 0.038
C
D
E
0.008
–
0.220
5.59
7.37
E1 0.290
e
L
0.100 BSC
2.54 BSC
0.125
0.150
0.015
–
0.200
–
3.18
3.81
0.38
–
5.08
–
E1
E
L1
Q
S
0.060
0.098
–
1.52
2.49
–
D
3/MX847
A
S1 0.005
0˚
0.13
0˚
α
15˚
15˚
21-340B
α
Q
24-PIN CERAMIC
DUAL-IN-LINE
(NARROW)
L
L1
C
e
B1
B
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1993 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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