MXD1000SE45 [MAXIM]
Delay Line, 1-Func, 5-Tap, CMOS;
| 型号： | MXD1000SE45 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Delay Line, 1-Func, 5-Tap, CMOS 延迟线 |
| 文件： | 总8页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1310; Rev 0; 10/97
5 -Ta p S ilic o n De la y Lin e
MXD10
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Improved Second Source to DS1000
♦ Available in Space-Saving 8-Pin µMAX Package
♦ 20mA Supply Current (vs. Dallas’ 35mA)
♦ Low Cost
The MXD1000 s ilic on d e la y line offe rs five e q ua lly
spaced taps with delays ranging from 4ns to 500ns and
a nomina l a c c ura c y of ± 2ns or ± 5%, whic he ve r is
greater. Relative to hybrid solutions, this device offers
e nha nc e d p e rforma nc e a nd hig he r re lia b ility, a nd
reduces overall cost. Each tap can drive up to ten 74LS
loads.
♦ Delay Tolerance of ±2ns or ±5%, whichever is
The MXD1000 is available in multiple versions, each
offering a different combination of delay times. It comes
in the space-saving 8-pin µMAX package, as well as an
8-pin SO or DIP, allowing full compatibility with the
DS1000 and other delay line products.
Greater
♦ TTL/CMOS-Compatible Logic
♦ Leading- and Trailing-Edge Accuracy
♦ Custom Delays Available
______________Ord e rin g In fo rm a t io n
________________________Ap p lic a t io n s
Clock Synchronization
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
Dice*
MXD1000C/D__
MXD1000PA__
MXD1000PD__
MXD1000SA__
MXD1000SE__
MXD1000UA__
Digital Systems
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 Plastic DIP
14 Plastic DIP
8 SO
16 Narrow SO
8 µMAX
*Dice are tested at T = +25°C.
A
Functional Diagram appears at end of data sheet.
Note: To complete the ordering information, fill in the blank
with the part number extension from the Part Number and Delay
Times table (located at the end of this data sheet) to indicate
the desired delay per output.
__________________________________________________________P in Co n fig u ra t io n s
TOP VIEW
IN
N.C.
1
2
3
4
5
6
7
14
V
IN
N.C.
1
2
3
4
5
6
7
8
16 V
CC
CC
IN
TAP2
TAP4
GND
1
2
3
4
8
7
6
5
V
CC
13 N.C.
12 TAP1
11 N.C.
10 TAP3
15 N.C.
14 N.C.
13 TAP1
12 N.C.
11 TAP3
10 N.C.
TAP1
TAP3
TAP5
MXD1000
N.C.
N.C.
TAP2
N.C.
MXD1000
TAP2
N.C.
MXD1000
TAP4
GND
9
8
N.C.
TAP4
N.C.
DIP/SO/µMAX
TAP5
GND
9 TAP5
DIP
SO
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
5 -Ta p S ilic o n De la y Lin e
ABSOLUTE MAXIMUM RATINGS
V
to GND..............................................................-0.5V to +6V
8-Pin SO (derate 5.9mW/°C above +70°C)....................471mW
16-Pin Narrow SO (derate 8.7mW/°C above +70°C) .....696mW
8-Pin µMAX (derate 4.1mW/°C above +70°C) ...............330mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
All Other Pins ..............................................-0.5V to (V + 0.5V)
Short-Circuit Output Current (1sec)....................................50mA
Continuous Power Dissipation (T = +70°C)
8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) .......727mW
14-Pin Plastic DIP (derate 10.0mW/°C above +70°C) ...800mW
CC
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MXD10
ELECTRICAL CHARACTERISTICS
(V = +5.0V ±5%, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
4.75
2.2
TYP
MAX
UNITS
V
Supply Voltage
V
CC
(Note 3)
(Note 3)
(Note 3)
5.00
5.25
Input Voltage High
Input Voltage Low
Input Leakage Current
Active Current
V
IH
V
V
IL
0.8
1
V
I
L
0V ≤ V ≤ V
CC
-1
µA
mA
mA
mA
pF
IN
I
CC
V
CC
= 5.25V, period = minimum (Notes 4, 5)
20
5
75
-1
Output Current High
Output Current Low
Input Capacitance
I
OH
V
= 4.75V, V = 4.0V
CC OH
I
OL
V
= 4.75V, V = 0.5V
CC OL
12
C
T
A
= +25°C (Note 6)
10
IN
TIMING CHARACTERISTICS
(V = +5.0V ±5%, T = +25°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
40% of TAP5
Input Pulse Width
t
WI
(Note 7)
ns
t
PLH
Input-to-Tap Delay
(leading edge)
See Part Number and
Delay Times table
t
t
(Notes 1, 8–12)
(Notes 1, 8–12)
ns
ns
PLH
PHL
Input-to-Tap Delay
(trailing edge)
See Part Number and
Delay Times table
Power-Up Time
Period
t
100
ms
ns
PU
(Note 7)
4(t )
WI
Note 1: Contact factory for ordering information.
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
Note 3: All voltages referenced to GND.
Note 4: Measured with output open.
Note 5:
I
is a function of frequency and TAP5 delay. Only an MXD1000_ _25 operating with a 40ns period and V = +5.25V will have
C
C
C
C
an I = 75mA. For example, an MXD1000_ _100 will never exceed 30mA. See Supply Current vs. Input Frequency in Typical
CC
Operating Characteristics.
Note 6: Guaranteed by design.
Note 7: Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling,
etc.). The device will remain functional with pulse widths down to 20% of TAP5 delay, and input periods as short as 2(t ).
WI
Note 8: Typical initial tolerances are ± with respect to the nominal value at +25°C and V = 5V.
CC
Note 9: Typical temperature tolerance is ± with respect to the initial delay value over a temperature range of -40°C to +85°C.
Note 10: The delay will also vary with supply voltage, typically by less than 4% over the supply range of V = +4.75V to +5.25V.
CC
Note 11: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP1 slows down, all other
taps will also slow down; i.e., TAP3 can never be faster than TAP2.
2
_______________________________________________________________________________________
5 -Ta p S ilic o n De la y Lin e
MXD10
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, T = +25°C, unless otherwise noted.)
CC
A
MXD1000_ _75
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
ACTIVE CURRENT
vs. FREQUENCY
20
2.0
1.5
1.0
0.5
0
50% DUTY CYCLE
18
16
14
12
10
8
t
PHL
t
PLH
MXD1000_ _50
MXD1000_ _75
t
PLH
t
PHL
-0.5
-1.0
-1.5
-2.0
MXD1000_ _200
MXD1000_ _500
RELATIVE TO NOMINAL (+25°C)
0.001
0.01
0.1
1
10
100
-40 -20
0
20
40
60
80 100
FREQUENCY (MHz)
TEMPERATURE (°C)
MXD1000_ _100 TO MXD1000_ _200
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
MXD1000_ _250 TO MXD1000_ _500
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
t
PLH
t
PLH
RELATIVE TO NOMINAL (+25°C)
RELATIVE TO NOMINAL (+25°C)
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
5 -Ta p S ilic o n De la y Lin e
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
8-PIN
DIP/SO/µMAX
14-PIN DIP
16-PIN SO
1
2
3
4
5
6
7
8
1
4
1
4
IN
Signal Input
TAP2
TAP4
GND
TAP5
TAP3
TAP1
40% of specified maximum delay
80% of specified maximum delay
Device Ground
6
6
MXD10
7
8
8
9
100% of maximum specified delay
60% of specified maximum delay
20% of specified maximum delay
Power-Supply Input
10
12
14
11
13
16
V
CC
2, 3, 5, 9, 11,
13
2, 3, 5, 7, 10,
12, 14, 15
—
N.C.
No Connection. Not internally connected.
Note: Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.
_______________De fin it io n s o f Te rm s
____________________Te s t Co n d it io n s
Period: The time elapsed between the first pulse’s
Ambient Temperature: +25°C ±3°C
leading edge and the following pulse’s leading edge.
Supply Voltage (V ):
CC
+5V ±0.1V
Pulse Width (t ): The time elapsed on the pulse
between the 1.5V level on the leading edge and the
1.5V level on the trailing edge, or vice-versa.
WI
Input Pulse:
High = 3.0V ±0.1V
Low = 0.0V ±0.1V
50Ω max
Source Impedance:
Rise and Fall Times:
Pulse Width:
Input Rise Time (t
): The time elapsed between
RISE
the 20% and 80% points on the input pulse’s leading
edge.
3.0ns max
500ns max (1ns for -500)
1µs (2ns for -500)
Input Fall Time (t
): The time elapsed between
FALL
Period:
the 80% and 20% points on the input pulse’s trailing
edge.
Each output is loaded with a 74F04 input gate. Delay is
measured at the 1.5V level on the rising and falling
edges. The time delay due to the 74F04 is subtracted
from the measured delay.
Time Delay, Rising (t ): The time elapsed between
PLH
the 1.5V level on the input pulse’s leading edge and the
corresponding output pulse’s leading edge.
Time Delay, Falling (t ): The time elapsed between
PHL
the 1.5V level on the input pulse’s trailing edge and the
corresponding output pulse’s trailing edge.
4
_______________________________________________________________________________________
5 -Ta p S ilic o n De la y Lin e
MXD10
(+5V)
V
CC
0.1µF
PERIOD
TIME
MEASUREMENT
UNIT
t
t
FALL
RISE
V
IH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
1.5V
IN
IN
50Ω
20%
20%
20%
20%
20%
TAP1
TAP2
V
IL
t
WI
MXD1000
t
PHL
TAP3
TAP4
t
PLH
1.5V
1.5V
TAP5
OUT
74FO4
Figure 2. Test Circuit
Figure 1. Timing Diagram
Ca p a c it a n c e a n d Lo a d in g
Effe c t s o n De la y
The outp ut loa d c a n a ffe c t the ta p d e la ys . La rg e r
capacitances tend to lengthen the rising and falling
edges, thus increasing the tap delays. As the taps are
loaded with other logic devices, the increased load will
increase the tap delays.
__________Ap p lic a t io n s In fo rm a t io n
S u p p ly a n d Te m p e ra t u re
Effe c t s o n De la y
Variations in supply voltage may affect the MXD1000’s
fixed tap delays. Supply voltages beyond the specified
range may result with larger variations. The devices are
internally compensated to reduce the effects of temper-
ature variations. Although these devices might vary with
supply and temperature, the delays vary unilaterally,
which suggests that TAP3 can never be faster than
TAP2.
Bo a rd La yo u t Co n s id e ra t io n s /De c o u p lin g
The device should be driven with a source that can
deliver the required current for proper operation. A
0.1µF ceramic bypassing capacitor could be used. The
board should be designed to reduce stray capaci-
tance.
_______________________________________________________________________________________
5
5 -Ta p S ilic o n De la y Lin e
_________________________________________________P a rt Nu m b e r a n d De la y Tim e s
TAP1
Tolerance
TAP2
Tolerance
TAP3
Tolerance
TAP4
Tolerance
TAP5
Tolerance
Part
Number
Extension
(MXD1000__)
Nom.
Delay
(ns)
Nom.
Delay
(ns)
Nom.
Delay
(ns)
Nom.
Delay
(ns)
Nom.
Delay
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
Init. Temp.
Init. Temp.
Init. Temp.
Init. Temp.
Init. Temp.
20
(Note 1)
4
5
6
2
2
2
1
1
1
8
2
2
2
1
1
1
12
15
18
2
2
2
1
1
1
16
20
24
2
2
2
1
1
1
20
25
30
2
2
2
1
1
1
MXD10
25
(Note 1)
10
12
30
(Note 1)
35
40
7
8
2
2
1
1
14
16
2
2
1
1
21
24
2
2
1
28
32
2
2
1
35
40
2
2
1.1
1.2
1.4
1.5
1.8
2.3
3
1
1
45
9
2
1
18
2
1
27
2
1
36
2
1.1
1.2
1.5
1.8
2.4
3
45
2.3
2.5
3
50
10
12
15
20
25
30
35
40
50
100
2
1
20
2
1
30
2
1
40
2
50
60
2
1
24
2
1
36
2
1.1
1.4
1.8
2.3
2.7
3.2
3.6
4.5
9
48
2.4
3
60
75
2
1
30
2
1
45
2.3
3
60
75
3.8
5
100
125
150
175
200
250
500
2
1
40
2
1.2
1.5
1.8
2.1
2.4
3
60
80
4
100
125
150
175
200
250
500
2
1
50
2.5
3
75
3.8
4.5
5.3
6
100
120
140
160
200
400
5
6.3
7.5
8.8
10
12.5
25
3.8
4.5
5.3
6
2
1
60
90
6
3.6
4.2
4.8
6
2
1.1
1.2
1.5
3
70
3.5
4
105
120
150
300
7
2
80
8
2.5
5
100
200
5
7.5
15
10
20
7.5
15
10
6
12
Note 1: Contact factory for ordering information.
6
_______________________________________________________________________________________
5 -Ta p S ilic o n De la y Lin e
MXD10
_________________________________________________________Fu n c t io n a l Dia g ra m
TAP1
TAP2
TAP3
TAP4
TAP5
20%
20%
20%
20%
20%
IN
MXD1000
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 824
_______________________________________________________________________________________
7
5 -Ta p S ilic o n De la y Lin e
________________________________________________________P a c k a g e In fo rm a t io n
MXD10
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
_____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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