MXL1543 [MAXIM]
+5V Multiprotocol, 3Tx/3Rx, Software-Selectable Clock/Data Transceivers; + 5V多协议， 3TX / 3Rx ，软件可选的时钟/数据收发器
| 型号： | MXL1543 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +5V Multiprotocol, 3Tx/3Rx, Software-Selectable Clock/Data Transceivers |
| 文件： | 总18页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1929; Rev 1; 9/01
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
General Description
Features
The MXL1543 is a three-driver/three-receiver multipro-
tocol transceiver that operates from a +5V single sup-
ply. The MXL1543, along with the MXL1544/MAX3175
and the MXL1344A, form a complete software-selec-
table data terminal equipment (DTE) or data communi-
cation equipment (DCE) interface port that supports the
V.28 (RS-232), V.10/V.11 (RS-449/V.36, EIA-530, EIA-
530A, X.21), and V.35 protocols. The MXL1543 trans-
ceivers carry the high-speed clock and data signals
while the MXL1544/MAX3175 carry the control signals.
The MXL1543 can be terminated by the MXL1344A
software-selectable resistor termination network or by
discrete termination networks.
An internal charge pump and a proprietary low-dropout
transmitter output stage allow V.11- , V.28- , and V.35-
compliant operation from a +5V single supply. A no-
cable mode is entered when all mode pins (M0, M1,
and M2) are pulled high or left unconnected. In no-
cable mode, supply current decreases to 0.5µA and all
transmitter and receiver outputs are disabled (high
impedance). Short-circuit current limiting and thermal
shutdown circuitry protect the drivers against excessive
power dissipation.
o MXL1543, MXL1544/MAX3175, and MXL1344A
Chipset Is Pin Compatible with LTC1543,
LTC1544, and LTC1344A
o Supports RS-232, RS-449, EIA-530, EIA-530A,
V.35, V.36, and X.21
o Software-Selectable Cable Termination Using the
MXL1344A
o Complete DTE or DCE Port with MXL1544/
MAX3175, and MXL1344A
o +5V Single-Supply Operation
o 0.5µA No-Cable Mode
o TUV-Certified NET1/NET2 and TBR1/TBR2-
Compliant
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MXL1543CAI
0° to +70°C
28 SSOP
Applications
Data Networking
CSU and DSU
Data Routers
PCI Cards
Pin Configuration appears at end of data sheet.
Telecommunications
Equipment
Typical Operating Circuit
LL
R4
CTS DSR
DCD DTR RTS
RXD RXC
TXC SCTE TXD
MXL1544
MAX3175
MXL1543
D4
D3
D3
D2
D1
D2
D1
R3
R2
R1
R3
R2
R1
MXL1344A
18 13 5 10 8
22 6 23 20 19 4
1
7
16 3 9 17
12 15 11 24 14 2
DB-25 CONNECTOR
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
ABSOLUTE MAXIMUM RATINGS
All Voltages Referenced to GND Unless Otherwise Noted.
Supply Voltages
Receiver Input
R_IN_T3OUT_/R1IN_..........................................-15V to +15V
V
V
EE
.......................................................................-0.3V to +6V
....................................................................-0.3V to +7.3V
Continuous Power Dissipation (T = +70°C)
A
28-Pin SSOP (derate 11.1mW/°C above +70°C) .........889mW
Operating Temperature Range
MXL1543CAI .......................................................0°C to 70°C
Junction Temperature .......................................................150°C
Storage Temperature Range ...........................-65°C to +150°C
Lead Temperature (soldering, 10s) ...............................+300°C
CC
DD
V
.....................................................................+0.3V to -6.5V
V
to V (Note 1)................................................................13V
DD
EE
Logic Input Voltages
M0, M1, M2, DCE/DTE, T_IN................................-0.3V to +6V
Logic Output Voltages
R_OUT....................................................-0.3V to (V
Transmitter Outputs
+ 0.3V)
CC
T_OUT_, T3OUT_/R1IN_.....................................-15V to +15V
Short-Circuit Duration............................................Continuous
Note 1: V
and V absolute difference cannot exceed 13V.
EE
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
CC
(V
= +5.0V, C1 = C2 = C4 = 1µF, C3 = C5 = 4.7µF, (Figure 10), T = T
to T
. Typical values are at T = +25°C, unless oth-
MAX A
MIN
A
erwise noted.)
PARAMETER
DC CHARACTERISTICS
Operating Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.25
130
UNITS
V
V
4.75
V
CC
CC
CC
RS-530, RS-530A, X.21, no load
RS-530, RS-530A, X.21, full load
V.35 mode, no load
13
100
20
Supply Current
(DCE Mode)
(Digital Inputs = GND or
mA
I
V.35 mode, full load
126
20
170
V
)
CC
V.28 mode, no load
(Transmitter Outputs Static)
V.28 mode, full load
40
75
10
No-cable mode
0.5
230
600
140
6.8
6.8
6.8
-5.6
-5.6
-5.6
-5.6
500
µA
RS-530, RS-530A, X.21, full load
V.35 mode, full load
Internal Power Dissipation
(DCE Mode)
P
mW
D
V.28 mode, full load
Any mode (except no-cable mode), no load
V.28 mode, with load
6.4
6.4
6.4
Positive Charge-Pump
Output Voltage
V
V
DD
V.28, V.35 modes, with load, I
V.28, V.35, no load
= 10mA
DD
V.28 mode, full load
-5.4
-5.4
-5.4
Negative Charge-Pump
Output Voltage
V
V
µs
V
EE
V.35 mode, full load
RS-530, RS-530A, X.21, full load
No-cable mode or power-up to turn on
Supply Rise Time
t
r
LOGIC INPUTS (M0, M1, M2, DCE/DTE, T1IN, T2IN, T3IN)
Input High Voltage
Input Low Voltage
V
2.0
IH
V
0.8
10
IL
T1IN, T2IN, T3IN
Logic Input Current
I
µA
M0, M1, M2, DCE/DTE = GND
-100
-50
-30
10
IN
M0, M1, M2, DCE/DTE = V
CC
2
_______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5.0V, C1 = C2 = C4 = 1µF, C3 = C5 = 4.7µF, (Figure 10), T = T
to T
. Typical values are at T = +25°C, unless oth-
MAX A
CC
MIN
A
erwise noted.)
PARAMETER
LOGIC OUTPUTS (R1OUT, R2OUT, R3OUT)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
Output Low Voltage
V
I
I
= 4mA
SOURCE
3
4.5
0.3
OH
V
V
= 4mA
SINK
0.8
50
OL
SC
Output Short-Circuit Current
Output Pullup Current
V.11 TRANSMITTER
I
0 ≤ V
≤ V
mA
OUT
CC
I
V
= 0, no-cable mode
OUT
70
µA
L
Open-Circuit Differential Output
Voltage
V
Open circuit, R = 1.95kΩ (Figure 1)
5
V
V
ODO
✕
✕
0.5
V
0.67
V
ODO
R = 50Ω (Figure 1), T = +25oC
Loaded Differential Output
Voltage
A
V
ODO
ODL
R = 50Ω (Figure 1)
R = 50Ω (Figure 1)
2
Change in Magnitude of Output
Differential Voltage
∆V
0.2
3.0
V
V
OD
Common-Mode Output Voltage
V
R = 50Ω (Figure 1)
R = 50Ω (Figure 1)
OC
Change in Magnitude of Output
Common-Mode Voltage
∆V
0.2
V
OC
Short-Circuit Current
Output Leakage Current
Rise or Fall Time
I
V
= GND
OUT
150
100
25
mA
µA
ns
SC
-0.25V ≤ V
no-cable mode
≤ +0.25V, power-off or
OUT
I
Z
1
10
40
t , t
(Figures 2, 6)
2
r
f
Transmitter Input to Output
Delay
t
, t
PHL PLH
(Figures 2, 6)
80
ns
Data Skew
It
- t
I
(Figures 2, 6)
(Figures 2, 6)
3
3
12
ns
ns
PHL PLH
Output to Output Skew
V.11 RECEIVER
t
SKEW
Differential Threshold Voltage
Input Hysteresis
V
-7V ≤ V
-7V ≤ V
≤ 7V
-200
15
200
40
mV
mV
mA
kΩ
ns
TH
CM
CM
∆V
≤ 7V
15
TH
Receiver Input Current
Receiver Input Resistance
Rise or Fall Time
I
-10V ≤ V
-10V ≤ V
≤10V
0.66
IN
A, B
A, B
R
≤ 10V
30
15
50
4
IN
t , t
r
(Figures 2, 7)
(Figures 2, 7)
(Figures 2, 7)
f
Receiver Input to Output Delay
Data Skew
t
,t
80
16
ns
PHL PLH
|t
- t
|
ns
PHL PLH
V.35 TRANSMITTER
Open circuit (Figure 3)
7
0.66
-9
Differential Output Voltage
V
V
OD
With load, -4V ≤ V
≤ 4V (Figure 3)
0.44
-13
9
0.55
-11
11
CM
Output High Current
Output Low Current
I
V
V
= 0
= 0
mA
mA
OH
A,B
A,B
I
13
OL
_______________________________________________________________________________________
3
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5.0V, C1 = C2 = C4 = 1µF, C3 = C5 = 4.7µF, (Figure 10), T = T
to T
. Typical values are at T = +25°C, unless oth-
MAX A
CC
MIN
A
erwise noted.)
PARAMETER
SYMBOL
CONDITIONS
≤ +0.25V, power-off or no-
MIN
TYP
1
MAX
UNITS
µA
-0.25V ≤ V
cable mode
OUT
Output Leakage Current
Rise or Fall Time
I
Z
100
t , t
r
(Figures 3, 6)
5
ns
f
Transmitter Input to Output
Delay
t
t
(Figures 3, 6)
35
80
16
ns
PHL, PLH
Data Skew
|t
–t
|
(Figures 3, 6)
(Figures 3, 6)
4
4
ns
ns
PHL PLH
Output-to-Output Skew
V.35 RECEIVER
t
SKEW
Differential Input Voltage
Input Hysteresis
V
-2V ≤ V
-2V ≤ V
≤ 2V (Figure 3)
-200
15
200
40
mV
mV
mA
kΩ
ns
TH
CM
CM
∆V
≤ 2V (Figure 3)
15
TH
Receiver Input Current
Receiver Input Resistance
Rise or Fall Time
I
-10V ≤ V , ≤ 10V
0.66
IN
A B
R
-10V ≤ V , ≤ 10V
30
15
50
4
IN
A B
t , t
r
(Figures 3, 7)
(Figures 3, 7)
(Figures 3, 7)
f
Receiver Input to Output Delay
Data Skew
t
, t
PHL PLH
80
16
ns
|t
–t
|
ns
PHL PLH
V.28 TRANSMITTER
Open circuit
7
Output Voltage Swing (Figure 4)
Short-Circuit Current
V
V
mA
µA
O
R = 3kΩ
L
5
4
6
1
I
150
100
30
SC
-0.25V ≤ V
≤ +0.25V, power-off or no-
OUT
Output Leakage Current
Output Slew Rate
I
Z
cable mode
SR
R = 3kΩ, C = 2500pF (Figures 4, 8)
V/µs
µs
L
L
Transmitter Input to Output
Delay
t
t
R = 3kΩ, C = 2500pF (Figures 4, 8)
1.5
1.5
2.5
PHL
L
L
Transmitter Input to Output
Delay
R = 3kΩ, C = 2500pF (Figures 4, 8)
3
µs
PLH
L
L
V.28 RECEIVER
Input Threshold Low
Input Threshold High
Input Hysteresis
V
0.8
3
1.2
1.2
0.05
5
V
V
IL
V
2.0
0.3
7
IH
V
V
HYST
Input Resistance
R
IN
-15V ≤ V ≤ +15V
kΩ
ns
ns
ns
IN
Rise or Fall Time
t , t
r
(Figures 5, 9)
(Figures 5, 9)
(Figures 5, 9)
15
f
Receiver Input to Output Delay
Receiver Input to Output Delay
t
60
100
250
PHL
PLH
t
160
4
_______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Typical Operating Characteristics
(V
= +5.0V, C1 = C2 = C4 =1µF, C3 = C5 = 4.7µF, (Figure 10), T = T
to T
, T = +25°C, unless otherwise noted.)
CC
A
MIN
MAX
A
V.28 SUPPLY CURRENT
vs. DATA RATE
V.11 SUPPLY CURRENT
vs. DATA RATE
V.35 SUPPLY CURRENT
vs. DATA RATE
200
160
140
120
100
80
60
40
20
0
DCE MODE ALL TRANSMITTERS
180
OPERATING AT THE SPECIFIED DATA RATE
R = 3kΩ, C = 2500pF
160
140
L
L
100
80
120
100
80
60
40
20
0
60
40
DCE MODE, R = 50Ω, ALL TRANSMITTERS
OPERATING AT THE SPECIFIED DATA RATE
DCE MODE, FULL LOAD, ALL TRANSMITTERS
OPERATING AT THE SPECIFIED DATA RATE
20
0
0
50
100
150
200
250
0.1
1
10
100
1000 10,000
0.1
0.1
10
100
1000 10,000
DATA RATE (kbps)
DATA RATE (kbps)
DATA RATE (kbps)
V.11 DRIVER DIFFERENTIAL OUTPUT
VOLTAGE vs. TEMPERATURE
V.28 OUTPUT VOLTAGE
vs. TEMPERATURE
V.35 OUTPUT VOLTAGE
vs. TEMPERATURE
10
8
5
4
3
2
1
0
0.66
0.44
0.22
0
DCE MODE, R = 3kΩ
DCE MODE, R = 50Ω
L
V
OH
DCE MODE, V = 0
CM
V
OUT+
6
FULL LOAD
V
OUT+
4
2
0
-2
-1
-2
-3
-4
-5
-0.22
-0.44
-0.66
V
OUT-
-4
-6
V
OUT-
V
OL
50
-8
-10
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
0
10
20
30
40
60
70
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
V.35 DIFFERENTIAL OUTPUT VOLTAGE
vs. COMMON-MODE VOLTAGE
V.28 RECEIVER INPUT CURRENT
vs. INPUT VOLTAGE
V.11/V.35 RECEIVER INPUT CURRENT
vs. INPUT VOLTAGE
600
590
580
570
560
550
540
530
520
2.5
2.0
300
200
100
0
DCE MODE
DCE MODE
1.5
1.0
|V
|
OD
0.5
0
-0.5
-1.0
-100
-200
-300
-1.5
-2.0
-2.5
-4 -3 -2 -1
0
1
2
3
4
-10 -8 -6 -4 -2
0
2
4
6
8
10
-10 -8 -6 -4 -2
0
2
4
6
8
10
COMMON-MODE VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Typical Operating Characteristics (continued)
(V
= +5.0V, C1= C2 = C4 =1µF, C3 = C5 = 4.7µF (Figure 10), T = +25°C, unless otherwise noted.)
CC
A
V.11 LOOPBACK OPERATION
V.28 LOOPBACK OPERATION
V.35 LOOPBACK OPERATION
MXL1543 toc10
MXL1543 toc11
MXL1543 toc12
R = 50Ω
FULL LOAD
C
R
= 2500pF
= 3kΩ
L
T
L
5V/div
T
5V/div
IN
IN
5V/div
5V/div
5V/div
T
IN
T
/R
OUT IN
T
/R
5V/div
5V/div
OUT IN
T
/R
OUT IN
1V/div
5V/div
R
OUT
R
R
OUT
OUT
200ns/div
1µs/div
200ns/div
V.11 TRANSMITTER PROPAGATION DELAY
vs. TEMPERATURE
V.11 RECEIVER PROPAGATION DELAY
vs. TEMPERATURE
V.28 SLEW RATE vs. C
LOAD
80
70
60
50
40
80
70
60
50
40
24
22
20
18
16
14
12
t
PHL
+SLEW
-SLEW
t
PLH
10
8
6
30
20
t
30
20
PLH
t
PHL
R = 3kΩ
L
4
2
0
10
0
1 TRANSMITTER SWITCHING AT 250kbps.
10
0
OTHER TRANSMITTERS SWITCHING AT 15kbps
0
10
20
30
50
60
70
40
0
1000
2000
C
3000
(pF)
4000
5000
0
10
20
30
50
60
70
40
TEMPERATURE (°C)
TEMPERATURE (°C)
LOAD
V.35 TRANSMITTER PROPAGATION DELAY
vs. TEMPERATURE
V.35 RECEIVER PROPAGATION DELAY
vs. TEMPERATURE
100
80
70
60
50
40
90
80
70
60
50
40
t
t
PHL
PLH
t
t
PLH
30
20
30
20
PHL
30
10
0
10
0
0
10
20
50
60
70
40
0
10
20
30
50
60
70
40
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Test Circuits
100pF
R
B
B
D
R
R
100Ω
A
A
V
OD
15pF
V
OC
100pF
Figure 1. V.11 DC Test Circuit
Figure 2. V.11 AC Test Circuit
50Ω
50Ω
V
CM
B
125Ω
125Ω
B
R
D
V
OD
A
A
50Ω
50Ω
15pF
Figure 3. V.35 Transmitter/Receiver Test Circuit
A
A
D
D
R
C
R
L
V
L
O
15pF
Figure 5. V.28 Receiver Test Circuit
Figure 4. V.28 Driver Test Circuit
_______________________________________________________________________________________
7
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Timing Diagrams
5V
0
f = 1MHz: t ≤10ns: t ≤ 10ns
r
f
D
1.5V
1.5V
t
t
PHL
PLH
V
0
90%
10%
90%
V
= V(A) - V(B)
DIFF
50%
50%
B — A
10%
1/2 V
0
-V
0
t
t
f
r
A
V
0
B
t
t
SKEW
SKEW
Figure 6. V.11, V.35 Driver Propagation Delays
V
0
0
f = 1MHz: t ≤10ns: t ≤ 10ns
INPUT
B — A
r
f
0
0
-V
t
t
PHL
PLH
V
0H
OUTPUT
1.5V
1.5V
R
V
0L
Figure 7. V.11, V.35 Receiver Propagation Delays
3V
1.5V
t
1.5V
D
A
0
t
PHL
PLH
V
0
3V
3V
0
0
-3V
-3V
-V
0
t
r
t
r
Figure 8. V.28 Driver Propagation Delays
V
IH
1.7V
A
1.3V
V
IL
t
PLH
t
PHL
V
R
V
0H
2.4V
0.8V
0L
Figure 9. V.28 Receiver Propagation Delays
8
_______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Pin Description
PIN
1
NAME
FUNCTION
Capacitor C1 Negative Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-.
Capacitor C1 Positive Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-.
Generated Positive Supply. Connect a 4.7µF ceramic capacitor to ground.
+5V Supply Voltage ( 5%). Decouple with a 1µF capacitor to ground.
Transmitter 1 TTL-Compatible Input
C1-
2
C1+
3
V
V
DD
CC
4
5
T1IN
T2IN
6
Transmitter 2 TTL-Compatible Input
7
T3IN
Transmitter 3 TTL-Compatible Input
8
R1OUT
R2OUT
R3OUT
M0
Receiver 1 CMOS Output
9
Receiver 2 CMOS Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Receiver 3 CMOS Output
Mode-Select Pin with Internal Pullup to V
Mode-Select Pin with Internal Pullup to V
Mode-Select Pin with Internal Pullup to V
CC
CC
CC
M1
M2
DCE/DTE
R3INB
DCE/DTE Mode-Select Pin with Internal Pullup to V
Noninverting Receiver Input
CC
R3INA
Inverting Receiver Input
R2INB
Noninverting Receiver Input
R2INA
Inverting Receiver Input
T3OUTB/R1INB
T3OUTA/R1INA
T2OUTB
T2OUTA
T1OUTB
T1OUTA
GND
Noninverting Transmitter Output/Noninverting Receiver Input
Inverting Transmitter Output/Inverting Receiver Input
Noninverting Transmitter Output
Inverting Transmitter Output
Noninverting Transmitter Output
Inverting Transmitter Output
Ground
V
Generated Negative Supply. Connect a 4.7µF ceramic capacitor to ground.
Capacitor C2 Negative Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-.
Capacitor C2 Positive Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-.
EE
C2-
C2+
safe operation, and thermal shutdown circuitry. Thermal
Detailed Description
shutdown protects the drivers against excessive power
dissipation. When activated, the thermal shutdown cir-
cuitry places the driver outputs into a high-impedance
state.
The MXL1543 is a three-driver/three-receiver, multipro-
tocol transceiver that operates from a single +5V sup-
ply. The MXL1543, along with the MXL1544/MAX3175
and MXL1344A, form a complete software-selectable
DTE or DCE interface port that supports the V.28 (RS-
232), V.10/V.11 (RS-449/V.36, EIA-530, EIA-530A,
X.21), and V.35 protocols. The MXL1543 transceivers
carry the high-speed clock and data signals, while the
MXL1544/MAX3175 transceivers carry serial interface
control signaling. The MXL1543 can be terminated by
the MXL1344A software-selectable resistor termination
network or by a discrete termination network. The
MXL1543 features a 0.5µA no-cable mode, true fail-
Mode Selection
The state of the mode-select pins M0, M1, and M2
determines which serial interface protocol is selected
(Table 1). The state of the DCE/DTE input determines
whether the transceiver will be configured as a DTE or
DCE serial port. When the DCE/DTE input is logic
HIGH, driver T3 is activated and receiver R1 is dis-
abled. When the DCE/DTE input is logic LOW, driver T3
_______________________________________________________________________________________
9
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Table 1. Mode Selection
DCE/
DTE
MXL1543
MODE NAME
M2
M1
M0
T1
T2
T3
R1
R2
R3
Not Used (Default V.11)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
0
0
V.11
V.11
V.11
V.11
V.35
V.11
V.11
V.11
V.11
V.35
Z
Z
Z
Z
Z
V.11
V.11
V.11
V.11
V.35
V.11
V.11
V.11
V.11
V.35
V.11
V.11
V.11
V.11
V.35
RS-530A
RS-530
X.21
V.35
RS-449/V.361
V.28/RS-232
No Cable
0
1
0
V.11
V.11
Z
V.11
V.11
V.11
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
1
1
1
1
V.28
Z
V.28
Z
Z
Z
V.28
Z
V.28
Z
V.28
Z
Not Used (Default V.11)
RS-530A
V.11
V.11
V.11
V.11
V.35
V.11
V.11
V.11
V.11
V.35
V.11
V.11
V.11
V.11
V.35
Z
V.11
V.11
V.11
V.11
V.35
V.11
V.11
V.11
V.11
V.35
Z
RS-530
Z
X.21
Z
V.35
Z
RS-449/V.361
V.28/RS-232
No Cable
0
1
1
V.11
V.11
V.11
V.28
Z
V.11
V.11
1
1
1
1
0
1
1
1
V.28
Z
V.28
Z
Z
Z
V.28
Z
V.28
Z
Z
is disabled and receiver R1 is activated. M0, M1, M2,
Each charge pump requires a flying capacitor (C1, C2)
and DCE/DTE are internally pulled up to V
to ensure
and a reservoir capacitor (C3, C5) to generate the V
DD
CC
a logic HIGH if left unconnected.
and V supplies. Figure 10 shows charge-pump con-
EE
nections.
No-Cable Mode
Fail-Safe Receivers
The MXL1543 will enter no-cable mode when the
mode-select pins are left unconnected or connected
high (M0 = M1 = M2 = 1). In this mode, the multiproto-
col drivers and receivers are disabled and the supply
current drops to 0.5µA. The receivers’ outputs enter a
high-impedance state in no-cable mode, which allow
these output lines to be shared with other receivers’
outputs (the receivers’ outputs have internal pullup
resistors to pull the outputs HIGH if not driven). Also, in
no-cable mode, the transmitter outputs enter a high-
impedance state so that these output lines can be
shared with other devices.
The MXL1543 guarantees a logic-high receiver output
when the receiver inputs are shorted or open, or when
they are connected to a terminated transmission line
with all the drivers disabled. This is done by setting the
receivers’ threshold between -25mV and -200mV in the
MXL1543
V
C2+
C2-
DD
C2
1µF
C3
4.7µF
C1+
C1-
Dual Charge-Pump Voltage Converter
C1
1µF
The MXL1543’s internal power supply consists of a reg-
ulated dual charge pump that provides positive and
negative output voltages from a +5V supply. The
charge pump operates in discontinuous mode. If the
output voltage is less than the regulated voltage, the
charge pump is enabled. If the output voltage exceeds
the regulated voltage, the charge pump is disabled.
V
EE
C5
4.7µF
V
CC
GND
5V
C4
1µF
Figure 10. Charge Pump
10 ______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
C6
C7 C8
100pF 100pF 100pF
3
8
11 12 13
V
CC
5V
MXL1344A
14
V
CC
EE
C13
21
1µF
28
3
1
LATCH
C2
C3
4.7µF
1µF
27
26
C1
2
CHARGE
PUMP
1µF
V
2
4
C5
4.7µF
25
C12
5
4
6
7
9 10 16 15 18 17 19 20 22 23 24 1
C4
1µF
1µF
DTE
DCE
V
CC
2
14
24
11
24
23
22
21
5
6
RXD A
RXD B
RXC A
RXC B
TXD A
TXD B
SCTE A
SCTE B
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
D1
D2
7
8
D3
R1
20
19
15
12
TXC A TXC A
DTE_TXC/DCE_TXC
TXC B
TXC B
17
9
18
17
16
15
9
SCTE A
SCTE B
RXC A
RXC B
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
R2
R3
3
16
7
TXD A
TXD B
10
RXD A
RXD B
SG
11
MXL1543
M0
M1
M2
12
13
14
1
SHIELD
NC
DCE/DTE
DB-25
CONNECTOR
C9
1µF
V
CC
28
27
1
2
V
V
V
EE
CC
DD
C10
C11
1µF
25
1µF
DCE/DTE
M1
M0
GND
21
18
4
19
20
23
26
25
24
23
3
4
CTS A
RTS A
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
D1
D2
D3
RTS B CTS B
DSR A
DSR B
DTR A
DTR B
5
6
8
10
22
21
DCD A
DCD B
DCD A
DCD B
DTE_DCD/DCE_DCD
R1
6
22
5
20
19
18
17
7
8
DTR A
DTR B
DSR A
DSR B
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
R2
R3
R4
RTS A
RTS B
CTS A
CTS B
13
10
9
16
D4
11
MXL1544
MAX3175
M0
M1
M2
12
13
14
NC
15
DCE/DTE INVERT
Figure 11. Cable-Selectable Multiprotocol DTE/DCE Port
______________________________________________________________________________________ 11
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
BALANCED
INTERCONNECTING
CABLE
I
Z
3.25mA
V
LOAD
GENERATOR
CABLE
RECEIVER
TERMINATION
-3V
-10V
A′
Z
A
+10V
+3V
100Ω
MIN
-3.25mA
B′
B
C′
C
Figure 13. Receiver Input Impedance
GND
GND
Cable-Selectable Mode
Figure 12. Typical V.11 Interface
A cable-selectable multiprotocol interface is shown in
Figure 11. The mode control lines M0, M1, and
DCE/DTE are wired to the DB-25 connector. To select
the serial interface mode, the appropriate combination
of M0, M1, and DCE/DTE are grounded within the cable
wiring. The control lines that are not grounded are
pulled high by the internal pullups on the MXL1543.
The serial interface protocol of the MXL1543,
MXL1544/MAX3175, and MXL1344A is selected based
on the cable that is connected to the DB-25 interface.
V.11 and V.35 modes. If the differential receiver input
voltage (B - A) is ≥ -25mV, R_OUT is logic HIGH. If (B -
A) is ≤ -200mV, R_OUT is logic LOW. In the case of a
terminated bus with all transmitters disabled, the
receiver’s differential input voltage is pulled to zero by
the termination. With the receiver thresholds of the
MXL1543, this results in a logic HIGH with a 25mV mini-
mum noise margin.
Applications Information
V.11 Interface
Capacitor Selection
As shown in Figure 12, the V.11 protocol is a fully bal-
anced differential interface. The V.11 driver generates a
minimum of 2V between nodes A and B when a 100Ω
(min) resistance is presented at the load. The V.11
receiver is sensitive to 200mV differential signals at
receiver inputs A’ and B’. The V.11 receiver rejects
common-mode signals developed across the cable
(referenced from C to C’) of up to 7V, allowing for
error-free reception in noisy environments. The receiver
inputs must comply with the impedance curve shown in
Figure 13.
For high-speed data transmission, the V.11 specifica-
tion recommends terminating the cable at the receiver
with a 100Ω resistor. This resistor, although not
required, prevents reflections from corrupting transmit-
ted data. In Figure 14, the MXL1344A is used to termi-
nate the V.11 receiver. Internal to the MXL1344A, S1 is
closed and S2 is open to present a 100Ω minimum dif-
ferential resistance. The MXL1543’s internal V.28 termi-
nation is disabled by opening S3.
The capacitors used for the charge pumps, as well as
for supply bypassing, should have a low equivalent
series resistance (ESR) and low temperature coeffi-
cient. Multilayer ceramic capacitors with an X7R dielec-
tric offer the best combination of performance, size,
and cost. The flying capacitors (C1, C2) and the
bypass capacitor (C4) should have a value of 1µF,
while the reservoir capacitors (C3, C5) should have a
minimum value of 4.7µF (Figure 10). To reduce the rip-
ple present on the transmitter outputs, capacitors C3,
C4, and C5 can be increased. The values of C1 and C2
should not be increased.
Cable Termination
The MXL1344A software-selectable resistor network is
designed to be used with the MXL1543. The MXL1344A
multiprotocol termination network provides V.11- and
V.35-compliant termination, while V.28 receiver termina-
tion is internal to the MXL1543. These cable termination
networks provide compatibility with V.11, V.28, and
V.35 protocols. Using the MXL1344A termination net-
works provide the advantage of not having to build
expensive termination networks out of resistors and
relays, manually changing termination modules, or
building custom termination networks
V.35 Interface
Figure 15 shows a fully-balanced, differential standard
V.35 interface. The generator and the load must both
present a 100Ω 10Ω differential impedance and a
150Ω 15Ω common-mode impedance as shown by
the resistive T networks in Figure 15. The V.35 driver
generates a current output ( 11mA, typ) that develops
an output voltage of 550mV across the generator and
12 ______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
A′
A
MXL1543
R5
30kΩ
R8
5kΩ
R1
52Ω
MXL1344A
R6
10kΩ
RECEIVER
S3
S1
S2
R3
124Ω
R7
10kΩ
R2
52Ω
R4
30kΩ
B′
C′
B
GND
Figure 14. V.11 Termination and Internal Resistance Networks
BALANCED
INTERCONNECTING
CABLE
LOAD
GENERATOR
CABLE
TERMINATION
RECEIVER
A′
A
50Ω
50Ω
50Ω
125Ω
125Ω
50Ω
B′
C′
B
C
GND
GND
Figure 15. Typical V.35 Interface
A′
A
MXL1543
R5
30kΩ
R8
5kΩ
R1
52Ω
MXL1344A
R6
10kΩ
RECEIVER
S1
S3
R3
124Ω
S2
R7
10kΩ
R2
52Ω
R4
30kΩ
B′
C′
B
GND
Figure 16. V.35 Termination and Internal Resistance Networks
______________________________________________________________________________________ 13
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
UNBALANCED
INTERCONNECTING
CABLE
LOAD
GENERATOR
CABLE
TERMINATION
RECEIVER
A
A′
C′
C
GND
GND
Figure 17. Typical V.28 Interface
A′
A
MXL1543
R5
30kΩ
R8
5kΩ
R1
52Ω
MXL1344A
R6
10kΩ
RECEIVER
S1
S3
R3
124Ω
S2
R7
10kΩ
R2
52Ω
R4
30kΩ
B′
C′
B
GND
Figure 18. V.28 Termination and Internal Resistance Networks
load termination networks. The V.35 receiver is sensi-
tive to 200mV differential signals at receiver inputs A’
and B’. The V.35 receiver rejects common-mode sig-
nals developed across the cable (referenced from C to
C’) of up to 4V, allowing for error-free reception in
noisy environments.
In Figure 16, the MXL1344A is used to implement the
resistive T network that is needed to properly terminate
the V.35 driver and receiver. Internal to the MXL1344A,
S1 and S2 are closed to connect the T-network resis-
tors to the circuit. The V.28 termination resistor (internal
to the MXL1543) is disabled by opening S3 to avoid
interference with the T-network impedance.
in rejecting system noise, the MXL1543’s V.28 receiver
has a typical hysteresis of 0.05V.
Figure 18 shows the MXL1344A’s termination network
disabled by opening S1 and S2. The MXL1543’s inter-
nal 5kΩ V.28 termination is enabled by closing S3.
DTE vs. DCE Operation
Figure 19 shows a DCE or DTE controller-selectable
interface. DCE/DTE (pin 14) switches the port’s mode
of operation. See Table 1.
This application requires only one DB-25 connector,
but separate cables for DCE or DTE signal routing. See
Figure 19 for complete signal routing in DCE and DTE
modes.
V.28 Interface
Complete Multiprotocol X.21 Interface
The V.28 interface is an unbalanced single-ended inter-
face (Figure 17). The V.28 driver generates a minimum
of 5V across a 3kΩ load impedance between A’ and
C’. The V.28 receiver has a single-ended input. To aid
A complete DTE-to-DCE interface operating in X.21
mode is shown in Figure 20. The MXL1543 is used to
generate the clock and data signals, and the
14 ______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
C6
C7 C8
100pF 100pF 100pF
3
8
11 12 13
V
CC
5V
MXL1344A
14
V
V
CC
EE
C13
21
1µF
28
3
1
LATCH
C2
C3
4.7µF
1µF
27
26
C1
2
CHARGE
PUMP
1µF
2
4
C5
4.7µF
25
C12
5
4
6
7
9 10 16 15 18 17 19 20 22 23 24 1
C4
1µF
1µF
DTE
DCE
2
14
24
11
24
23
22
21
5
6
RXD A
RXD B
RXC A
RXC B
TXD A
TXD B
SCTE A
SCTE B
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
D1
D2
7
8
D3
R1
20
19
15
12
TXC A TXC A
DTE_TXC/DCE_TXC
TXC B
TXC B
17
9
18
17
16
15
9
SCTE A
SCTE B
RXC A
RXC B
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
R2
R3
3
16
7
TXD A
TXD B
10
RXD A
RXD B
SG
11
MXL1543
M0
M1
M2
12
13
14
1
SHIELD
DCE/DTE
DB-25
CONNECTOR
C9
1µF
V
CC
28
27
1
2
V
V
V
EE
CC
DD
C10
C11
1µF
1µF
GND
4
19
20
23
26
25
24
23
3
4
CTS A
RTS B CTS B
RTS A
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
D1
D2
D3
DSR A
DSR B
DTR A
DTR B
5
6
8
10
22
21
DCD A
DCD B
DCD A
DCD B
DTE_DCD/DCE_DCD
R1
6
22
5
20
19
18
17
7
8
DTR A
DTR B
DSR A
DSR B
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_LL/DCE_LL
R2
R3
R4
RTS A
RTS B
CTS A
CTS B
13
18
10
9
16
LLA
LLA
D4
MXL1544
MAX3175
11
M0
M1
M2
12
13
14
15
INVERT
DCE/DTE
DCE/DTE
M2
M1
M0
Figure 19. Multiprotocol DCE/DTE Port
______________________________________________________________________________________ 15
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
DTE
DCE
MXL1543
R3
SERIAL
CONTROLLER
SERIAL
CONTROLLER
MXL1543
MXL1344A
MXL1344A
104Ω
D1
TXD
TXD
TXD
104Ω
SCTE
SCTE
D2
D3
R2
R1
SCTE
104Ω
104Ω
104Ω
TXC
RXC
RXD
TXC
RXC
RXD
R3
D1
TXC
RXC
RXD
R2
R1
D2
D3
MXL1544
MAX3175
MXL1544
MAX3175
D1
R3
RTS
DTR
RTS
DTR
RTS
DTR
D2
D3
R2
R1
DCD
DSR
DCD
DSR
R1
D3
DCD
DSR
R2
R3
D2
D1
CTS
LL
CTS
LL
CTS
LL
D4
R4
R4
D4
Figure 20. DCE-to-DTE X.21 Interface
MXL1544/MAX3175 generate the control signals and
local loopback (LL). The MXL1344A is used to termi-
nate the clock and data signals to support the V.11 pro-
tocol for cable termination. The control signals do not
need external termination.
Compliance Testing
A European Standard EN 45001 test report is pending
for the MXL1543/MXL1544/MXL1344A chipset. A copy
of the test report will be available from Maxim upon
completion.
16 ______________________________________________________________________________________
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Chip Information
TRANSISTOR COUNT: 2619
PROCESS: BiCMOS
Pin Configuration
TOP VIEW
C1-
C1+
1
2
3
4
5
6
7
8
9
28 C2+
27 C2-
V
DD
V
CC
26 V
EE
25 GND
T1IN
T2IN
24 T1OUTA
23 T1OUTB
22 T2OUTA
21 T2OUTB
20 T3OUTA/R1INA
19 T3OUTB/R1INB
18 R2INA
MXL1543
T3IN
R1OUT
R2OUT
R3OUT 10
M0 11
M1 12
17 R2INB
M2 13
16 R3INA
DCE/DTE 14
15 R3INB
SSOP
______________________________________________________________________________________ 17
+5V Multiprotocol, 3Tx/3Rx, Software-
Selectable Clock/Data Transceivers
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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