MX27C1024TC-12 [Macronix]
1M-BIT [128K x 8/64K x 16] CMOS EPROM; 1M - BIT [ 128K ×8 / 64K ×16 ]的CMOS EPROM
| 型号： | MX27C1024TC-12 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 1M-BIT [128K x 8/64K x 16] CMOS EPROM |
| 文件： | 总20页 (文件大小：967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX27C1100/27C1024
1M-BIT [128K x 8/64K x 16] CMOS EPROM
FEATURES
• 64K x 16 organization(MX27C1024, JEDEC pin
out)
• 128K x 8 or 64K x 16 organization(MX27C1100,
ROM pin out compatible)
• +12.5V programming voltage
• Fast access time: 55/70/85/100/120/150 ns
• Totally static operation
• Operating current: 40mA
• Standby current: 100uA
• Package type:
- 40 pin plastic DIP
- 40 pin plastic SOP
- 44 pin PLCC
- 40pin 10 x 14mm TSOP(I)
• Completely TTL compatible
GENERAL DESCRIPTION
EPROMprogrammersmaybeused. TheMX27C1100/
1024 supports a intelligent fast programming algorithm
which can result in programming time of less than thirty
seconds.
The MX27C1024 is a 5V only, 1M-bit, One Time
Programmable Read Only Memory. It is organized as
64K words by 16 bits per word(MX27C1024), 128K x 8
or 64K x 16(MX27C1100), operates from a single + 5
volt supply, has a static standby mode, and features
fastsingleaddresslocationprogramming. Allprogram-
mingsignalsareTTLlevels,requiringasinglepulse.For
programming outside from the system, existing
This EPROM is packaged in industry standard 40 pin
dual-in-linepackages, 40leadSOP,44leadPLCC,and
40 lead TSOP(I) packages.
PIN CONFIGURATIONS
PDIP/SOP(MX27C1100)
BLOCK DIAGRAM (MX27C1100)
A8
NC
A7
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
CE
Q0~Q14
Q15/A-1
CONTROL
LOGIC
OUTPUT
A9
2
OE
A10
A11
A12
A13
A14
A15
NC
BUFFERS
A6
3
BYTE/VPP
A5
4
A4
5
A3
6
A2
7
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Y-DECODER
X-DECODER
Y-SELECT
A1
8
A0
9
BYTE/VPP
GND
Q15/A-1
Q7
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
10
11
12
13
14
15
16
17
18
19
20
A0~A15
1M BIT
CELL
ADDRESS
INPUTS
MAXTRIX
Q14
Q6
Q13
Q5
VCC
GND
Q12
Q4
VCC
P/N: PM0156
REV. 4.4 , AUG. 20, 2001
1
MX27C1100/27C1024
PIN CONFIGURATIONS
PDIP/SOP(MX27C1024)
PLCC(MX27C1024)
VCC
PGM
NC
A15
A14
A13
A12
A11
A10
A9
VPP
CE
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
Q15
Q14
Q13
Q12
Q11
Q10
Q9
3
6
1
44
40
39
4
A13
A12
A11
A10
A9
Q12
Q11
Q10
Q9
7
5
6
7
8
Q8
9
MX27C1024
GND
NC
A8
GND
NC
12
17
34
Q8
10
11
12
13
14
15
16
17
18
19
20
GND
A8
GND
Q7
Q7
A7
Q6
A7
Q6
A6
Q5
A6
Q5
A5
Q4
A5
Q4
29
28
A4
Q3
18
23
A3
Q2
A2
Q1
A1
Q0
A0
OE
TSOP(I)
BLOCK DIAGRAM (MX27C1024)
1
A9
A10
A11
A12
A13
A14
A15
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
CE
2
CONTROL
LOGIC
OUTPUT
Q0~Q15
3
A7
PGM
OE
BUFFERS
4
A6
5
A5
6
A4
7
A3
8
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
A2
Y-DECODER
X-DECODER
Y-DECODER
9
PGM
VCC
VPP
CE
A1
10
11
12
13
14
15
16
17
18
19
20
A0
A0~A15
MX27C1024
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
ADDRESS
INPUTS
1M BIT
CELL
Q15
Q14
Q13
Q12
Q11
Q10
Q9
MAXTRIX
VCC
VPP
GND
Q8
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
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MX27C1100/27C1024
PIN DESCRIPTION(MX27C1024)
PIN DESCRIPTION(MX27C1100)
SYMBOL
A0~A15
Q0~Q15
CE
PIN NAME
SYMBOL
A0~A15
Q0~Q14
CE
PIN NAME
Address Input
Address Input
Data Input/Output
Chip Enable Input
Output Enable Input
Program Enable Input
Program Supply Voltage
Power Supply Pin (+5V)
Ground Pin
Data Input/Output
Chip Enable Input
OE
OE
Output Enable Input
Word/Byte Selection
/Program Supply Voltage
Q15(Word mode)/LSB addr. (Byte mode)
Power Supply Pin (+5V)
Ground Pin
PGM
BYTE/VPP
VPP
VCC
Q15/A-1
VCC
GND
GND
TRUTH TABLE OF BYTE FUNCTION(MX27C1100)
BYTE MODE(BYTE = GND)
CE
H
OE
X
Q15/A-1
MODE
Q0-Q7
High Z
High Z
DOUT
SUPPLY CURRENT
Standby(ICC2)
X
Non selected
Non selected
Selected
L
H
X
Operating(ICC1)
Operating(ICC1)
L
L
A-1 input
WORD MODE(BYTE = VCC)
CE
OE
X
Q15/A-1
High Z
High Z
DOUT
MODE
Q0-Q14
High Z
High Z
DOUT
SUPPLY CURRENT
Standby(ICC2)
H
Non selected
Non selected
Selected
L
H
Operating(ICC1)
Operating(ICC1)
L
L
NOTE : X = H or L
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
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MX27C1100/27C1024
FUNCTIONAL DESCRIPTION
VIL(for MX27C1024), OE at VIL, CE at VIH(for
MX27C1100)and VPP at its programming voltage.
THE PROGRAMMING OF THE MX27C1100/1024
When the MX27C1100/1024 is delivered, or it is
erased, the chip has all 1M bits in the "ONE" or HIGH
state. "ZEROs" are loaded into the MX27C1100/1024
through the procedure of programming.
AUTO IDENTIFY MODE
Theautoidentifymodeallowsthereadingoutofabinary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient
temperature range that is required when programming
the MX27C1100/1024.
Forprogramming, thedatatobeprogrammedisapplied
with 16 bits in parallel to the data pins.
VCCmustbeappliedsimultaneouslyorbeforeVPP,and
removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.
To activate this mode, the programming equipment
mustforce12.0±0.5VonaddresslineA9ofthedevice.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
FAST PROGRAMMING
Thedeviceissetupinthefastprogrammingmodewhen
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm
is shown in Figure 1). The programming is achieved by
applying a single TTL low level 100us pulse to the PGM
inputafteraddressesanddatalinearestable. Ifthedata
is not verified, an additional pulse is applied for a
maximum of 25 pulses. This process is repeated while
sequencing through each address of the device. When
the programming mode is completed, the data in all
address is verified at VCC = VPP = 5V ±10%.
Byte 0 ( A0 = VIL) represents the manufacturer code,
andbyte1(A0=VIH),thedeviceidentifiercode. Forthe
MX27C1100/1024, these two identifier bytes are given
intheModeSelectTable. Allidentifiersformanufacturer
and device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.
READ MODE
The MX27C1100/1024 has two control functions, both
ofwhichmustbelogicallysatisfiedinordertoobtaindata
at the outputs. Chip Enable (CE) is the power control
andshouldbeusedfordeviceselection. OutputEnable
(OE) is the output control and should be used to gate
datatotheoutputpins,independentofdeviceselection.
Assuming that addresses are stable, address access
time(tACC)isequaltothedelayfromCEtooutput(tCE).
DataisavailableattheoutputstOEafterthefallingedge
of OE's, assuming that CE has been LOW and
addresses have been stable for at least tACC - t OE.
PROGRAM INHIBIT MODE
Programming of multiple MX27C1100/1024's in parallel
with different data is also easily accomplished by using
theProgramInhibitMode. ExceptforCEandOE,alllike
inputs of the parallel MX27C1100/1024 may be
common. A TTL low-level program pulse applied to an
MX27C1100/1024 CE input with VPP = 12.5±0.5 V will
program the MX27C1100/1024. A high-level CE input
inhibits the other MX27C1100/1024s from being
programmed.
WORD-WIDE MODE
PROGRAM VERIFY MODE
With BYTE/VPP at VCC ±0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
TheverificationshouldbeperformedwithOEandCE at
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
4
MX27C1100/27C1024
BYTE-WIDE MODE
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.
With BYTE/VPP at GND ±0.2V, outputs Q8-15 are tri-
stated. IfQ15/A-1=VIH, outputsQ0-7presentdatabits
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.
The location of the capacitor should be close to where
the power supply is connected to the array.
STANDBY MODE
The MX27C1100/1024 has a CMOS standby mode
which reduces the maximum VCC current to 100 uA. It
is placed in CMOS standby when CE is at VCC ±0.3 V.
The MX27C1100/1024 also has a TTL-standby mode
which reduces the maximum VCC current to 1.5 mA. It
is placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connectedtotheREADlinefromthesystemcontrolbus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
outputcapacitanceloadingofthedevice. Ataminimum,
a0.1uFceramiccapacitor(highfrequency,lowinherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
5
MX27C1100/27C1024
MODE SELECT TABLE (MX27C1024)
PINS
MODE
CE
OE
VIL
VIH
X
PGM
X
A0
X
A9
X
VPP
VCC
VCC
VCC
VCC
VPP
VPP
VPP
VCC
VCC
OUTPUTS
DOUT
High Z
High Z
High Z
DIN
Read
VIL
Output Disable
Standby (TTL)
Standby (CMOS)
Program
VIL
X
X
X
VIH
X
X
X
VCC±0.3V
VIL
X
X
X
X
VIH
VIL
X
VIL
VIH
X
X
X
Program Verify
Program Inhibit
Manufacturer Code(3)
Device Code(3)
VIL
X
X
DOUT
High Z
00C2H
0115H
VIH
X
X
VIL
VIL
VIL
X
VIL
VIH
VH
VH
VIL
X
NOTES:1. VH = 12.0 V ±0.5 V
3. A1 - A8 = A10 - A15 = VIL(For auto select)
2 . X = Either VIH or VIL
4. See DC Programming Characteristics for VPP voltage during
programming.
MODE SELECT TABLE (MX27C1100)
BYTE/
MODE
CE
OE
VIL
VIL
VIL
VIH
X
A9
X
A0
X
Q15/A-1
Q15 Out
VIH
VPP(5)
VCC
GND
GND
X
Q8-14
Q0-7
Read (Word)
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIH
VIL
VIL
Q8-14 Out
High Z
High Z
High Z
High Z
Q8-14 In
Q8-14 Out
High Z
00H
Q0-7 Out
Q8-15 Out
Q0-7 Out
High Z
High Z
Q0-7 In
Q0-7 Out
High Z
C2H
Read (Upper Byte)
Read (Lower Byte)
Output Disable
Standby
X
X
X
X
VIL
X
X
High Z
High Z
Q15 In
Q15 Out
High Z
0B
X
X
X
Program
VIH
VIL
VIH
VIL
VIL
X
X
VPP
VPP
VPP
VCC
VCC
Program Verify
Program Inhibit
Manufacturer Code(3)
Device Code(3)
X
X
X
X
VH
VH
VIL
VIH
0B
01H
12H
NOTES: 1. VH = 12.0V ±0.5V
4. See DC Programming Characteristics for VPP voltages.
5. BYTE/VPP is intended for operation under DC Voltage conditions
only.
2. X = Either VIH or VIL
3. A1 - A8, A10 - A15 = VIL(For auto select)
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
6
MX27C1100/27C1024
FIGURE 1. FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X = 0
PROGRAM ONE 50us PULSE
INCREMENT X
INTERACTIVE
SECTION
YES
X = 25?
NO
FAIL
VERIFY WORD
?
PASS
NO
LAST ADDRESS
INCREMENT ADDRESS
FAIL
YES
VCC = VPP = 5.25V
VERIFY SECTION
FAIL
DEVICE FAILED
VERIFY ALL WORDS
?
PASS
DEVICE PASSED
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
7
MX27C1100/27C1024
SWITCHING TEST CIRCUITS
DEVICE
UNDER
TEST
1.8K ohm
+5V
DIODES = IN3064
CL
OR EQUIVALENT
6.2K ohm
CL = 100 pF including jig capacitance (30pF for 55/70ns parts)
SWITCHING TEST WAVEFORMS
2.0V
0.8V
2.0V
0.8V
TEST POINTS
AC driving levels
OUTPUT
INPUT
AC TESTING: AC driving levels are 2.4V/0.4V .
Input pulse rise and fall times are <20ns.
1.5V
1.5V
TEST POINTS
AC driving levels
OUTPUT
INPUT
AC TESTING: (1) AC driving levels are 3.0V/0V.
Input pulse rise and fall times are < 10ns.
(2) For MX27C1100/1024-55/70
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
8
MX27C1100/27C1024
ABSOLUTE MAXIMUM RATINGS
NOTICE:
RATING
VALUE
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9 & Vpp
-40oC to 85oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to VCC + 0.5V
-0.5V to 7.0V
NOTICE:
Specifications contained within the following tables are subject to
change.
-0.5V to 13.5V
DC/AC Operating Conditions for Read Operation
MX27C1100/1024
-55*
-70
0°C to 70°C
-85
-10
-12
-15
Operating Temperature
Vcc Power Supply
Commercial
Industrial **
0°C to 55°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
-40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C
Vcc ±5%
Vcc ±10%
Vcc ±10%
Vcc ±10%
Vcc ±10%
Vcc ±10%
* : 55ns for MX27C1024 only
**:Industrial grade for MX27C1024 only
DC CHARACTERISTICS
SYMBOL
VOH
VOL
VIH
PARAMETER
MIN.
MAX.
UNIT
V
CONDITIONS
IOH = -0.4mA
IOL = 2.1mA
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
2.4
0.4
V
2.0
-0.3
-10
-10
VCC + 0.5
0.8
V
VIL
V
ILI
Input Leakage Current
Output Leakage Current
VCC Power-Down Current
VCC Standby Current
VCC Active Current
10
uA
uA
uA
mA
mA
uA
VIN = 0 to 5.5V
ILO
10
VOUT = 0 to 5.5V
ICC3
ICC2
ICC1
IPP
100
1.5
CE = VCC ±0.3V
CE = VIH
40
CE = VIL, f=5MHz, Iout = 0mA
CE = OE = VIL, VPP = 5.5V
VPP Supply Current Read
10
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
CIN
PARAMETER
TYP.
8
MAX.
12
UNIT
pF
CONDITIONS
VIN = 0V
Input Capacitance
Output Capacitance
VPP Capacitance
COUT
CVPP
8
12
pF
VOUT = 0V
VPP = 0V
18
25
pF
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
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MX27C1100/27C1024
AC CHARACTERISTICS
27C1024-55
27C1100/1024-70 27C1100/1024-85
SYMBOL PARAMETER
MIN.
MAX.
55
MIN.
MAX.
70
MIN. MAX.
UNIT CONDITIONS
tACC
tCE
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
OE High to Output Float,
or CE High to Output Float
Output Hold from Address,
CE or OE which ever occurred first
BYTE Access Time
85
85
40
ns
ns
ns
ns
CE = OE = VIL
OE = VIL
55
70
tOE
tDF
30
35
CE = VIL
0
0
20
0
0
20
0
0
25
tOH
ns
*tBHA
*tOHB
*tBHZ
*tBLZ
70
70
85
70
ns
ns
ns
ns
BYTE Output Hold Time
BYTE Output Delay Time
BYTE Output Set Time
0
0
10
10
* : for MX27C1100 only
AC CHARACTERISTICS
27C1100/1024-10 27C1100/1024-12 27C1100/1024-15
SYMBOL PARAMETER
MIN.
MAX.
100
100
45
MIN.
MAX.
120
120
50
MIN. MAX.
UNIT
ns
CONDITIONS
CE = OE = VIL
OE = VIL
tACC
tCE
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
OE High to Output Float,
or CE High to Output Float
Output Hold from Address,
CE or OE which ever occurred first
BYTE Access Time
150
150
65
ns
tOE
tDF
ns
CE = VIL
0
0
30
0
0
35
0
0
50
ns
tOH
ns
*tBHA
*tOHB
*tBHZ
*tBLZ
100
70
120
70
150
70
ns
ns
ns
ns
BYTE Output Hold Time
BYTE Output Delay Time
BYTE Output Set Time
0
0
0
10
10
10
* : for MX27C1100 only
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
10
MX27C1100/27C1024
DC PROGRAMMING CHARACTERISTICS TA = 25oC ±5oC
SYMBOL
VOH
VOL
VIH
PARAMETER
MIN.
MAX.
UNIT
V
CONDITIONS
IOH = -0.40mA
IOL = 2.1mA
Output High Voltage
2.4
Output Low Voltage
0.4
V
Input High Voltage
2.0
VCC + 0.5
0.8
V
VIL
Input Low Voltage
-0.3
-10
V
ILI
Input Leakage Current
A9 Auto Select Voltage
VCC Supply Current (Program & Verify)
VPP Supply Current(Program)
Fast Programming Supply Voltage
Fast Programming Voltage
10
uA
V
VIN = 0 to 5.5V
VH
11.5
12.5
50
ICC3
IPP2
VCC1
VPP1
mA
mA
V
30
CE = VIL, OE = VIH
6.00
12.5
6.50
13.0
V
AC PROGRAMMING CHARACTERISTICS TA = 25oC ±5°C
SYMBOL
tAS
PARAMETER
MIN.
2.0
2.0
2.0
0
MAX.
UNIT
us
us
CONDITIONS
Address Setup Time
OE Setup Time
tOES
tDS
Data Setup Time
us
us
us
ns
us
tAH
Address Hold Time
Data Hold Time
tDH
2.0
0
tDFP
tVPS
tPW
Output Enable to Output Float Delay
VPP Setup Time
130
105
2.0
95
PGM Program Pulse Width
VCC Setup Time
us
us
us
ns
tVCS
tCES
tOE
2.0
2.0
CE Setup Time
Data valid from OE
150
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
11
MX27C1100/27C1024
WAVEFORMS(MX27C1024)
READ CYCLE(WORD MODE)
ADDRESS
INPUTS
DATA ADDRESS
tACC
CE
OE
tCE
tDF
DATA
OUT
VALID DATA
tOE
tOH
FAST PROGRAMMING ALGORITHM WAVEFORMS
PROGRAM
PROGRAM VERIFY
VIH
Addresses
VIL
tAH
tAS
Hi-z
DATA OUT VALID
DATA
VPP
DATA IN STABLE
tDH
tDS
tDFP
VPP1
VCC
tVPS
tVCS
VCC1
VCC
VCC
CE
VIH
VIL
tCES
VIH
VIL
PGM
OE
tOE
Max
tOES
tPW
VIH
VIL
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
12
MX27C1100/27C1024
WAVEFORMS(MX27C1100)
READ CYCLE(BYTE MODE)
HIGH-Z
HIGH-Z
A-1
tACC
tOH
BYTE/VPP
Q0-Q7
VALID DATA
VALID DATA
VALID DATA
tBHA
tOHB
Q15-Q8
tBHZ
tBLZ
FAST PROGRAMMING ALGORITHM WAVEFORM
PROGRAM
VERIFY
VIH
Addresses
VALID ADDRESS
VIL
tAH
tAS
DATA OUT VALID
DATA SET
DATA
tDFP
tDS
tDH
VPP1
VCC
BYTE/VPP
tVPS
tVCS
VCC1
VCC
VCC
CE
VIH
VIL
tOE
tOES
tPW
VIH
VIL
OE
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
13
MX27C1100/27C1024
ORDER INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
OPERATING CURRENT
STANDBY CURRENT
PACKAGE
(ns)
70
MAX.(mA)
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
MAX.(uA)
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
MX27C1100PC-70
MX27C1100PC-85
MX27C1100PC-10
MX27C1100PC-12
MX27C1100PC-15
MX27C1100MC-70
MX27C1100MC-85
MX27C1100MC-10
MX27C1100MC-12
MX27C1100MC-15
MX27C1024PC-55
MX27C1024PC-70
MX27C1024PC-85
MX27C1024PC-10
MX27C1024PC-12
MX27C1024PC-15
MX27C1024QC-55
MX27C1024QC-70
MX27C1024QC-85
MX27C1024QC-10
MX27C1024QC-12
MX27C1024QC-15
MX27C1024MC-55
MX27C1024MC-70
MX27C1024MC-85
MX27C1024MC-10
MX27C1024MC-12
MX27C1024MC-15
MX27C1024TC-55
MX27C1024TC-70
MX27C1024TC-85
MX27C1024TC-10
MX27C1024TC-12
MX27C1024TC-15
MX27C1024TI-70
MX27C1024TI-85
MX27C1024TI-10
MX27C1024TI-12
40 Pin DIP(ROM pin out)
40 Pin DIP(ROM pin out)
40 Pin DIP(ROM pin out)
40 Pin DIP(ROM pin out)
40 Pin DIP(ROM pin out)
40 Pin SOP
85
100
120
150
70
85
40 Pin SOP
100
120
150
55
40 Pin SOP
40 Pin SOP
40 Pin SOP
40 Pin DIP(JEDEC pin out)
40 Pin DIP(JEDEC pin out)
40 Pin DIP(JEDEC pin out)
40 Pin DIP(JEDEC pin out)
40 Pin DIP(JEDEC pin out)
40 Pin DIP(JEDEC pin out)
44 Pin PLCC
70
85
100
120
150
55
70
44 Pin PLCC
85
44 Pin PLCC
100
120
150
55
44 Pin PLCC
44 Pin PLCC
44 Pin PLCC
40 Pin SOP
70
40 Pin SOP
85
40 Pin SOP
100
120
150
55
40 Pin SOP
40 Pin SOP
40 Pin SOP
40 Pin TSOP(I)
70
40 Pin TSOP(I)
85
40 Pin TSOP(I)
100
120
150
70
40 Pin TSOP(I)
40 Pin TSOP(I)
40 Pin TSOP(I)
40 Pin TSOP(I)
85
40 Pin TSOP(I)
100
120
40 Pin TSOP(I)
40 Pin TSOP(I)
MX27C1024TI-15
150
40
100
40 Pin TSOP(I)
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
14
MX27C1100/27C1024
PACKAGE INFORMATION
40-PIN PLASTIC DIP(600 mil)
REV. 4.4 , AUG. 20, 2001
15
P/N: PM0156
MX27C1100/27C1024
44-PIN PLASTIC LEADED CHIP CARRIER(PLCC)
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
16
MX27C1100/27C1024
40-PIN PLASTIC SOP(450 mil)
REV. 4.4 , AUG. 20, 2001
17
P/N: PM0156
MX27C1100/27C1024
40-PIN PLASTIC TSOP
REV. 4.4 , AUG. 20, 2001
18
P/N: PM0156
MX27C1100/27C1024
REVISION HISTORY
Revision No. Description
Page
Date
3.0
Revise speed grade from 70/90/120/150ns to 55/70/85/100/
10/15/1996
120/150ns.
Add 40 pin SOP package type.
4.0
1) Eliminate Interactive Programming Mode.
2) 40-CDIP package quartz lens, change to square shape.
IPP : 100uA ----> 10uA
Add industrial grade 70/85/100/120/150ns 40-TSOP(I)
Cancel ceramic DIP package type
06/14/1997
4.1
4.2
4.3
4.4
08/08/1997
11/19/1998
P1,2,4,15,16 FEB/25/2000
P15
Cancel "Ultraviolet Erasable" wording in General Description
To modify Package Information
P1
P15~18
AUG/20/2001
REV. 4.4 , AUG. 20, 2001
P/N: PM0156
19
MX27C1100/27C1024
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
20
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