128M8 [MDTIC]
1Gb: x4, x8, x16 DDR3 SDRAM; 1GB ： X4，X8 ， X16 DDR3 SDRAM
| 型号： | 128M8 |
| 厂家： | 
Micon Design Technology Corporation |
| 描述： | 1Gb: x4, x8, x16 DDR3 SDRAM |
| 文件： | 总181页 (文件大小：8341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1Gb : x4, x8, x16 DDR3 SDRAM
Fe a t u re s
DDR3 SDRAM
MT41J256M4 – 32 Me g x 4 x 8 Ba n ks
MT41J128M8 – 16 Me g x 8 x 8 Ba n ks
MT41J64M16 – 8 Me g x 16 x 8 Ba n ks
Op t io n s
Ma rkin g
Fe a t u re s
• VDD = VDDQ = +1.5V ±0.075V
• Configuration
– 256 Meg x 4
– 128 Meg x 8
– 64 Meg x 16
• 1.5V center-terminated push/ pull I/ O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
256M4
128M8
64M16
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on CK
• FBGA package (Pb-free) - x4, x8
– 78-ball FBGA (8mm x 11.5mm) Rev. F
– 78-ball FBGA (9mm x 11.5mm) Rev. D
– 86-ball FBGA (9mm x 15.5mm) Rev. B
• FBGA package (Pb-free) - x16
– 96-ball FBGA (9mm x 15.5mm) Rev. B
• Timing - cycle time
JP
HX
BY
LA
t
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.25ns @ CL = 10 (DDR3-1600)
– 1.25ns @ CL = 9 (DDR3-1600)
– 1.5ns @ CL = 10 (DDR3-1333)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.5ns @ CL = 8 (DDR3-1333)
– 1.87ns @ CL = 8 (DDR3-1066)
– 1.87ns @ CL = 7 (DDR3-1066)
– 2.5ns @ CL = 6 (DDR3-800)
– 2.5ns @ CL = 5 (DDR3-800)
• Revision
-125
-125E
-125F
-15
-15E
-15F
-187
-187E
-25
-25E
:B/ :D/ :F
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
o
o
• T of 0 C to 95 C
C
o
o
– 64ms, 8,192 cycle refresh at 0 C to 85 C
– 32ms at 85 C to 95 C
o
o
• Clock frequency range of 300–800 MHz
• Self refresh temperature (SRT)
• Autom atic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Ta b le 1:
Ke y Tim in g Pa ra m e t e rs
Sp e e d Gra d e
-125
Da t a Ra t e (MT/s)
Ta rg e t t RCD-t RP-CL
t RCD (n s)
t RP (n s)
CL (n s)
1600
1600
1600
1333
1333
1333
1066
1066
800
11-11-11
10-10-10
9-9-9
13.75
12.5
11.25
15
13.75
12.5
11.25
15
13.75
12.5
11.25
15
-125E
-125F
-15
10-10-10
9-9-9
-15E
-15F
-187
-187E
-25
13.5
12
13.5
12
13.5
12
8-8-8
8-8-8
15
15
15
7-7-7
13.1
15
13.1
15
13.1
15
6-6-6
-25E
800
5-5-5
12.5
12.5
12.5
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D1 .fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1
Products and specifications discussed herein are subject to change by Micron without notice.
1Gb : x4, x8, x16 DDR3 SDRAM
Fe a t u re s
Ta b le 2:
Ad d re ssin g
Pa ra m e t e r
256 Me g x 4
128 Me g x 8
64 Me g x 16
Configuration
Refresh count
32 Meg x 4 x 8 banks
8K
16 Meg x 8 x 8 banks
8K
8 Meg x 16 x 8 banks
8K
Row addressing
Bank addressing
Column addressing
16K (A[13:0])
8 (BA[2:0])
16K (A[13:0])
8 (BA[2:0])
8K (A[12:0])
8 (BA[2:0])
1K (A[9:0])
2K (A[11, 9:0])
1K (A[9:0])
Fig u re 1:
1Gb DDR3 Pa rt Nu m b e rs
Example Part Number: M T4 1 J2 5 6 M 4 BY-1 5 :B
-
:
MT41J
Configuration
Package
Speed
Revision
:B/:D/:F Revision
Temperature
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
256M4
128M8
64M16
Commercial
None
IT
Industrial temperature
Speed Grade
t
Package
Rev. Mark
-125
-125E
-125F
-15
CK = 1.25ns, CL = 11
t
78-ball 8mm x 11.5mm FBGA
78-ball 9mm x 11.5mm FBGA
86-ball 9mm x 15.5mm FBGA
96-ball 9mm x 15.5mm FBGA
F
D
B
B
JP
CK = 1.25ns, CL = 10
t
HX
BY
LA
CK = 1.25ns, CL = 9
t
CK = 1.5ns, CL = 10
t
-15E
-15F
-187
-187E
-25
CK = 1.5ns, CL = 9
t
CK = 1.5ns, CL = 8
t
CK = 1.87ns, CL = 8
t
CK = 1.87ns, CL = 7
t
CK = 2.5ns, CL = 6
t
-25E
CK = 2.5ns, CL = 5
FBGA Pa rt Ma rkin g De co d e r
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. For a quick conversion of an FBGA code,
see the FBGA Part Marking Decoder on Micron’s Web site: www.micron.com.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D1 .fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Ta b le o f Co n t e n t s
Ta b le o f Co n t e n t s
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input/ Output Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Electrical Specifications – IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Electrical Characteristics – IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AC Overshoot/ Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Slew Rate Definitions for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Slew Rate Definitions for Differential Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
ODT Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ODT Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ODT Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
34Ω Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
34Ω Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
34Ω Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Alternative 40Ω Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Output Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Reference Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Slew Rate Definitions for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Slew Rate Definitions for Differential Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Speed Bin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Command and Address Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Data Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
DESELECT (DES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Input Clock Frequency Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_TOC.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
3
1Gb : x4, x8, x16 DDR3 SDRAM
Ta b le o f Co n t e n t s
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Mode Register 0 (MR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Mode Register 1 (MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Mode Register 2 (MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Mode Register 3 (MR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Extended Temperature Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Nominal ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Dynamic ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Synchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
ODT Off During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Asynchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry). . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_TOC.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
4
1Gb : x4, x8, x16 DDR3 SDRAM
List o f Fig u re s
List o f Fig u re s
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1Gb DDR3 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
256 Meg x 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
128 Meg x 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
64 Meg x 16 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
78-Ball FBGA – x4, x8 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
86-Ball FBGA – x4, x8 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
96-Ball FBGA – x16 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
78-Ball FBGA – x4, x8; “JP” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
78-Ball FBGA – x4, x8; “HX” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
86-Ball FBGA – x4, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
96-Ball FBGA – x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Thermal Measurement Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IDD1 Example – DDR3-800, 5-5-5, x8 (-25E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
IDD2N/ IDD3N Example – DDR3-800, 5-5-5, x8 (-25E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
IDD4R Example – DDR3-800, 5-5-5, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Single-Ended Requirements for Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
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Definition of Differential AC-Swing and DVAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Nominal Slew Rate Definition for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# . . . . . . . . . . . . . . . . . .48
ODT Levels and I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ODT Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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AON and AOF Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
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AONPD and AOFPD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
ADC Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
DQ Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Differential Output Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Reference Output Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Nominal Slew Rate Definition for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Nominal Differential Output Slew Rate Definition for DQS, DQS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
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Nominal Slew Rate and VAC for IS (Command and Address – Clock) . . . . . . . . . . . . . . . . . . . . . . . . .80
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Nominal Slew Rate for IH (Command and Address – Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
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Tangent Line for IS (Command and Address – Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
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Tangent Line for IH (Command and Address – Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
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Nominal Slew Rate and VAC for DS (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
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Nominal Slew Rate for DH (DQ – Strobe). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
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Tangent Line for DS (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
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Tangent Line for DH (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
DLL Enable Mode to DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
DLL Disable Mode to DLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
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DLL Disable DQSCK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Change Frequency During Precharge Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Write Leveling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Exit Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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MRS-to-MRS Command Timing ( MRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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MRS-to-nonMRS Command Timing ( MOD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Mode Register 0 (MR0) Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Mode Register 1 (MR1) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_LOF.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
5
1Gb : x4, x8, x16 DDR3 SDRAM
List o f Fig u re s
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READ Latency (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Mode Register 2 (MR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
CAS Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Mode Register 3 (MR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Multipurpose Register (MPR) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MPR System Read Calibration with BL8: Fixed Burst Order Single Readout. . . . . . . . . . . . . . . . . . . 122
MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout . . . . . . . . . . . 123
MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble . . . . . . . . . . . . . . . . . . 124
MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble . . . . . . . . . . . . . . . . . . 125
ZQ Calibration Timing (ZQCL and ZQCS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Example: Meeting RRD (MIN) and RCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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Example: FAW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Consecutive READ Bursts (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Consecutive READ Bursts (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
READ (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
READ to PRECHARGE (BL8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
READ to PRECHARGE (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
READ to PRECHARGE (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
READ with Auto Precharge (AL = 4, CL = 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Data Output Timing – DQSQ and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Data Strobe Timing – READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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Method for Calculating LZ and HZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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RPRE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
WPRE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
WPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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Write Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Consecutive WRITE (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
WRITE (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
WRITE to READ (BC4 Mode Register Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
WRITE (BC4 OTF) to READ (BC4 OTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
WRITE (BL8) to PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
WRITE (BC4 Mode Register Setting) to PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
WRITE (BC4 OTF) to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Self Refresh Entry/ Exit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Active Power-Down Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Precharge Power-Down (Fast-Exit Mode) Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 100: Precharge Power-Down (Slow-Exit Mode) Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 101: Power-Down Entry After READ or READ with Auto Precharge (RDAP) . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 102: Power-Down Entry After WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 103: Power-Down Entry After WRITE with Auto Precharge (WRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 104: REFRESH to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 105: ACTIVATE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 106: PRECHARGE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 107: MRS Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 108: Power-Down Exit to Refresh to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 109: RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 110: On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 111: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 112: Dynamic ODT: Without WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_LOF.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
6
1Gb : x4, x8, x16 DDR3 SDRAM
List o f Fig u re s
Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 . . . . 165
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 116: Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 117: Synchronous ODT (BC4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 118: ODT During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 119: Asynchronous ODT Timing with Fast ODT Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry . . . . 175
Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit. . . . . . 177
Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping . . . . . . . . . 179
Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping. . . . . . . . . 180
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_LOF.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
7
1Gb : x4, x8, x16 DDR3 SDRAM
List o f Ta b le s
List o f Ta b le s
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
78-Ball FBGA – x4, x8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
86-Ball FBGA – x4, x8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
96-Ball FBGA – x16 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input/ Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IDD Measurement Conditions Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Definition of Switching for Command and Address Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Definition of Switching for Data Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
IDD Measurement Conditions for IDD0 and IDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
IDD Measurement Conditions for Power-Down Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
IDD Measurement Conditions for IDD4R, IDD4W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
IDD Measurement Conditions for IDD5B, IDD6, IDD6ET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
IDD Measurement Conditions for IDD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
IDD7 Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
IDD Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DC Electrical Characteristics and Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Control and Address Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Clock, Data, Strobe, and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Differential Input Operating Conditions (CK, CK# and DQS, DQS#) . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
Table 31:
Table 32:
Table 33:
Table 34:
Table 35:
Table 36:
Table 37:
Table 38:
Table 39:
Table 40:
Table 41:
Table 42:
Table 43:
Table 44:
Table 45:
Table 46:
Table 47:
Table 48:
Table 49:
Table 50:
Table 51:
t
Allowed Time Before Ringback ( DVAC) for CK - CK# and DQS - DQS#. . . . . . . . . . . . . . . . . . . . . . . . .45
Single-Ended Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Differential Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
On-Die Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
RTT Effective Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
ODT Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
ODT Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Reference Settings for ODT Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
34Ω Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
34Ω Driver Pull-Up and Pull-Down Impedance Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
34Ω Driver IOH/ IOL Characteristics: VDD = VDDQ = 1.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Driver IOH/ IOL Characteristics: VDD = VDDQ = 1.575V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Driver IOH/ IOL Characteristics: VDD = VDDQ = 1.425V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Single-Ended Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Differential Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Single-Ended Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
DDR3-800 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
DDR3-1066 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
DDR3-1333 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_LOT.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
8
1Gb : x4, x8, x16 DDR3 SDRAM
List o f Ta b le s
Table 52:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
Table 62:
Table 63:
Table 64:
Table 65:
Table 66:
Table 67:
Table 68:
Table 69:
Table 70:
Table 71:
Table 72:
Table 73:
Table 74:
Table 75:
Table 76:
Table 77:
Table 78:
Table 79:
Table 80:
Table 81:
Table 83:
DDR3-1600 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Command and Address Setup and Hold Values Referenced at 1 V/ ns – AC/ DC-Based . . . . . . . . . . .77
t
t
DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for IS/ IH – AC/ DC-Based78
t
t
DDR3-1333 and DDR3-1600 Derating Values for IS/ IH – AC/ DC-Based . . . . . . . . . . . . . . . . . . . . . . .78
t
Minimum Required Time VAC Above VIH(AC) for Valid Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Data Setup and Hold Values at 1 V/ ns (DQS, DQS# at 2 V/ ns) – AC/ DC-Based . . . . . . . . . . . . . . . . . .84
t
t
DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for DS/ DH – AC/ DC-Based85
t
t
DDR3-1333and DDR3-1600 Derating Values for DS/ DH – AC/ DC-Based . . . . . . . . . . . . . . . . . . . . .85
t
Required Time VAC Above VIH(AC) (Below VIL[AC]) for Valid Transition . . . . . . . . . . . . . . . . . . . . . . . .86
Truth Table – Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
READ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
WRITE Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
READ Electrical Characteristics, DLL Disable Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Write Leveling Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Burst Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MPR Functional Description of MR3 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MPR Readouts and Burst Order Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Self Refresh Temperature and Auto Self Refresh Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Self Refresh Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Command to Power-Down Entry Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Truth Table – ODT (Nominal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
ODT Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Dynamic ODT Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Mode Registers for Rtt_nom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Mode Registers for Rtt_wr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Timing Diagrams for Dynamic ODT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Synchronous ODT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period . . . . . . . . . . . . . . . . 175
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_LOT.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
9
1Gb : x4, x8, x16 DDR3 SDRAM
St a t e Dia g ra m
St a t e Dia g ra m
Fig u re 2:
Sim p lifie d St a t e Dia g ra m
CKE L
Power
applied
MRS, MPR,
write
leveling
Reset
procedure
Power
on
Self
refresh
Initialization
SRE
SRX
ZQCL
MRS
From any
state
RESET
REF
ZQCL/ZQCS
ZQ
calibration
Idle
Refreshing
PDE
PDX
ACT
Active
power-
down
Precharge
power-
down
Activating
PDX
PDE
CKE L
CKE L
Bank
active
WRITE
READ
READ
WRITE
WRITE AP
WRITE
READ AP
READ
Writing
Reading
WRITE AP
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
Reading
PRE, PREA
PRE, PREA
Precharging
Automatic
sequence
Command
sequence
ACT = ACTIVATE
PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
10
1Gb : x4, x8, x16 DDR3 SDRAM
Fu n ct io n a l De scrip t io n
Fu n ct io n a l De scrip t io n
The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/ O pins. A single read or write
access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data
transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-
cycle data transfers at the I/ O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control,
command, and address signals are registered at every positive edge of CK. Input data is
registered on the first rising edge of DQS after the WRITE preamble, and output data is
referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE commands are used to select the
bank and the starting column location for the burst access.
DDR3 SDRAM use READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row
precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Ge n e ra l No t e s
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise.
• The terms “DQS” and “CK” found throughout the data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the entire document, and any
page or diagram may have been simplified to convey a topic and may not be inclusive
of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated herewithin is considered undefined, illegal,
and not supported and can result in unknown operation.
• Row addressing is denoted as A[n:0](1Gb: n = 12 [x16]; 1Gb: n = 13 [x4, x8]).
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Fu n ct io n a l Blo ck Dia g ra m s
Fu n ct io n a l Blo ck Dia g ra m s
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Fig u re 3:
256 Me g x 4 Fu n ct io n a l Blo ck Dia g ra m
ODT
control
ODT
ZQ
To pull-up/pull-down
ZQ CAL
networks
RESET#
RZQ
ZQCL, ZQCS
CKE
Control
logic
VSSQ
A12
CK, CK#
CS#
VDDQ/2
BC4 (burst chop)
RTT_NOM
RTT_WR
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
RAS#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
CK, CK#
OTF
sw2
sw1
CAS#
WE#
DLL
(1 . . . 4)
Refresh
counter
14
READ
FIFO
and
data
MUX
Mode registers
16
Bank 0
memory
array
Bank 0
row-
address
latch
32
Row-
address
MUX
4
14
DQ[3:0]
DQS, DQS#
READ
drivers
16,384
DQ[3:0]
(16,384 x 256 x 32)
14
and
decoder
VDDQ/2
Sense amplifiers
32
BC4
RTT_NOM
RTT_WR
8,192
BC4
OTF
sw1
sw2
I/O gating
DM mask logic
3
DM
DQS, DQS#
(1, 2)
Bank
control
logic
A[13:0]
BA[2:0]
Address
register
17
3
V
DDQ/2
256
(x32)
WRITE
drivers
and
input
logic
4
32
RTT_NOM
RTT_WR
Data
interface
Data
sw2
Column
decoder
sw1
Column-
address
counter/
latch
8
3
DM
11
Columns 0, 1, and 2
Column
(select upper or
lower nibble for BC4)
2
CK, CK#
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
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©2006 Micron Technology, Inc. All rights reserved.
12
1Gb : x4, x8, x16 DDR3 SDRAM
Fu n ct io n a l Blo ck Dia g ra m s
Fig u re 4:
128 Me g x 8 Fu n ct io n a l Blo ck Dia g ra m
ODT
control
ODT
ZQ
To ODT/output drivers
ZQ CAL
RESET#
CKE
RZQ
Control
logic
ZQCL, ZQCS
VSSQ
A12
CK, CK#
CS#
VDDQ/2
BC4 (burst chop)
RTT_NOM
RTT_WR
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
RAS#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
CK, CK#
OTF
sw2
sw1
CAS#
WE#
DLL
(1 . . . 8)
Refresh
counter
DQ8
14
READ
FIFO
and
data
MUX
TDQS#
Mode registers
16
Bank 0
memory
array
Bank 0
Row-
address
MUX
8
14
64
DQ[7:0]
DQS, DQS#
row-
address
latch
READ
drivers
16,384
DQ[7:0]
(16,384 x 128 x 64)
14
and
decoder
VDDQ/2
Sense amplifiers
64
BC4
RTT_NOM
RTT_WR
8,192
BC4
OTF
sw2
sw1
I/O gating
3
DM mask logic
DQS, DQS#
(1, 2)
Bank
control
logic
A[13:0]
BA[2:0]
Address
register
17
3
V
DDQ/2
(128
x64)
WRITE
drivers
and
input
logic
8
64
RTT_NOM
RTT_WR
Data
interface
Data
sw2
Column
decoder
sw1
Column-
address
counter/
latch
7
3
DM/TDQS
(shared pin)
10
Columns 0, 1, and 2
CK, CK#
Column
2
(select upper or
lower nibble for BC4)
Fig u re 5:
64 Me g x 16 Fu n ct io n a l Blo ck Dia g ra m
ODT
control
ODT
ZQ
ZQ CAL
To ODT/output drivers
RESET#
CKE
RZQ
Control
logic
ZQCL, ZQCS
VSSQ
A12
CK, CK#
CS#
V
DDQ/2
BC4 (burst chop)
RTT_NOM
RTT_WR
Column 0, 1, and 2
Bank
Bank
7
RAS#
Bank
Bank
Bank
Bank
Bank
Bank
Bank
7
CK, CK#
OTF
6
6
sw2
sw1
Bank
5
CAS#
5
Bank
Bank
Bank
Bank
4
4
3
WE#
3
DLL
2
2
(1 . . . 16)
1
1
Refresh
counter
13
READ
FIFO
and
data
MUX
Mode registers
16
Bank
0
Bank
0
Row-
address
MUX
16
13
128
DQ[15:0]
LDQS, LDQS#, UDQS, UDQS#
memory
array
row-
address
latch
READ
drivers
DQ[15:0]
8,192
(8192 x 128 x 128)
13
and
decoder
V
DDQ/2
Sense amplifiers
16,384
BC4
128
RTT_NOM
RTT_WR
sw2
BC4
OTF
sw1
LDQS, LDQS#
UDQS, UDQS#
I/O gating
DM mask logic
3
Bank
control
logic
(1 . . . 4)
A[12:0]
BA[2:0]
Address
register
16
3
VDDQ/2
(128
WRITE
drivers
and
input
logic
x128)
128
16
Data
RTT_NOM
Data
interface
RTT_WR
sw2
Column
decoder
sw1
Column-
address
counter/
latch
7
3
LDM/UDM
10
(1, 2)
Columns 0, 1, and 2
Column
(select upper or
lower nibble for BC4)
2
CK, CK#
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
13
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Ba ll Assig n m e n t s a n d De scrip t io n s
Fig u re 6:
78-Ba ll FBGA – x4, x8 Ba ll Assig n m e n t s (To p Vie w )
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
V
SS
V
DD
NC
NF, NF/TDQS#
DM, DM/TDQS
DQ1
V
SS
VDD
VSS
VSS
Q
DQ0
DQS
VSS
Q
V
DD
Q
Q
Q
VDD
Q
DQ2
DQ3
VSS
VSS
Q
NF, DQ6 DQS#
VDD
VSS
VSS
V
REFDQ
VDD
Q
NF, DQ4
RAS#
CAS#
WE#
BA2
A0
NF, DQ7 NF, DQ5
VDDQ
NC
ODT
NC
V
SS
CK
CK#
VSS
NC
G
H
J
VDD
VDD
CKE
NC
CS#
BA0
A3
A10/AP
NC
ZQ
VSS
V
REFCA
VSS
K
L
M
N
VDD
A12/BC# BA1
VDD
VSS
A5
A2
A1
A11
NC
A4
A6
A8
VSS
VDD
A7
A9
VDD
VSS
RESET#
A13
VSS
Notes: 1. Ball descriptions listed in Table 3 on page 17 are listed as “x4, x8” if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to
the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined
in Table 3 on page 17).
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
14
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Fig u re 7:
86-Ba ll FBGA – x4, x8 Ba ll Assig n m e n t s (To p Vie w )
1
2
3
4
5
6
7
8
9
A
B
C
NC
NC
NC
NC
D
E
V
SS
V
DD
NC
NF, NF/TDQS#
DM, DM/TDQS
DQ1
V
SS
VDD
VSS
VSS
Q
DQ0
DQS
VSS
Q
VDDQ
F
VDD
Q
DQ2
DQ3
VSSQ
G
H
J
V
SS
Q
NF, DQ6 DQS#
V
DD
V
SS
V
SS
Q
VREFDQ
V
DD
Q
NF, DQ4
RAS#
CAS#
WE#
BA2
A0
NF, DQ7 NF, DQ5
VDD
Q
NC
ODT
NC
V
SS
CK
CK#
VSS
NC
K
L
V
DD
VDD
CKE
NC
CS#
BA0
A3
A10/AP
NC
ZQ
M
N
P
V
SS
V
REFCA
VSS
V
DD
A12/BC# BA1
VDD
V
SS
A5
A2
A1
A11
NC
A4
A6
A8
VSS
R
T
V
DD
A7
A9
VDD
V
SS
RESET#
A13
VSS
U
V
W
NC
NC
NC
NC
Notes: 1. Ball descriptions listed in Table 4 on page 19 are listed as “x4, x8” if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to
the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined
in Table 4 on page 19).
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
15
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Fig u re 8:
96-Ba ll FBGA – x16 Ba ll Assig n m e n t s (To p Vie w )
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQ13
VDD
DQ15
VSS
DQ12
VDDQ
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
UDQS# DQ14
UDQS DQ10
DQ11
VDDQ
VSSQ
DQ2
DQ9
UDM
DQ0
LDQS
LDQS#
DQ4
RAS#
CAS#
WE#
BA2
A0
DQ8
LDM
DQ1
VDD
VSSQ
VSSQ
DQ3
VSS
VDDQ
VSSQ
G
H
J
DQ6
VREFDQ VDDQ
DQ7
CK
DQ5
VSS
NC
ODT
NC
VSS
VDD
CS#
K
L
M
N
P
CK#
VDD
CKE
NC
A10/AP
NC
ZQ
VSS
BA0
A3
VREFCA
VSS
VDD
VSS
A12/BC# BA1
VDD
VSS
A5
A2
A1
A11
NC
A4
A6
A8
R
T
VDD
VSS
A7
A9
VDD
VSS
RESET#
NC
Notes: 1. Ball descriptions listed in Table 5 on page 21 are listed as “x4, x8” if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to
the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined
in Table 5 on page 21).
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
16
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 3:
78-Ba ll FBGA – x4, x8 Ba ll De scrip t io n s
Ba ll Assig n m e n t s
Sym b o l
Typ e
De scrip t io n
K3, L7, L3, K2,
L8, L2, M8, M2,
N8, M3, H7, M7,
K7, N3
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9, A10/AP,
A11, A12/BC#,
A13
Input
Ad d re ss in p u t s: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to VREFCA. A12/BC#: When enabled in the
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).
See Table 62 on page 91.
J2, K8, J3
BA0, BA1, BA2
Input
Ba n k a d d re ss in p u t s: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
F7, G7
G9
CK, CK#
CKE
Input
Input
Clo ck: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
Clo ck e n a b le : CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to VREFCA.
H2
B7
G1
CS#
DM
Input
Input
Input
Ch ip se le ct : CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to VREFCA.
In p u t d a t a m a sk: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with the input data
during a write access. Although the DM ball is input-only, the DM
loading is designed to match that of the DQ and DQS balls. DM is
referenced to VREFDQ. DM has an optional use as TDQS on the x8.
ODT
On -d ie t e rm in a t io n : ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;
DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if
disabled via the LOAD MODE command. ODT is referenced to
VREFCA.
F3, G3, H3
RAS#, CAS#, WE#
Input
Co m m a n d in p u t s: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to VREFCA.
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
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17
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 3:
78-Ba ll FBGA – x4, x8 Ba ll De scrip t io n s (co n t in u e d )
Ba ll Assig n m e n t s
Sym b o l
Typ e
De scrip t io n
N2
RESET#
Input
Re se t : RESET# is an active LOW CMOS input referenced to VSS. The
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET#
assertion and desertion are asynchronous.
B3, C7,
C2, C8
DQ0, DQ1,
DQ2, DQ3
I/O
I/O
Da t a in p u t /o u t p u t : Bidirectional data bus for the x4 configuration.
DQ[3:0] are referenced to VREFDQ.
B3, C7, C2,
C8, E3, E8,
D2, E7
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
Da t a in p u t /o u t p u t : Bidirectional data bus for the x8 configuration.
DQ[7:0] are referenced to VREFDQ.
C3, D3
DQS, DQS#
I/O
Da t a st ro b e : Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
B7, A7
TDQS, TDQS#
Output Te rm in a t io n d a t a st ro b e : Applies to the x8 configuration only.
When TDQS is enabled, DM is disabled, and the TDQS and TDQS#
balls provide termination resistance.
A2, A9, D7, G2, G8,
K1, K9, M1, M9
VDD
VDDQ
Supply Po w e r su p p ly: 1.5V ±0.075V.
B9, C1, E2, E9
Supply DQ p o w e r su p p ly: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
J8
VREFCA
Supply Re fe re n ce vo lt a g e fo r co n t ro l, co m m a n d , a n d a d d re ss: VREFCA
must be maintained at all times (including self refresh) for proper
device operation.
E1
VREFDQ
VSS
Supply Re fe re n ce vo lt a g e fo r d a t a : VREFDQ must be maintained at all
times (including self refresh) for proper device operation.
A1, A8, B1, D8, F2,
F8, J1, J9, L1, L9, N1,
N9
Supply Ground.
B2, B8, C9, D1, D9
H8
VSSQ
ZQ
Supply DQ g ro u n d : Isolated on the device for improved noise immunity.
Reference Ext e rn a l re fe re n ce b a ll fo r o u t p u t d rive ca lib ra t io n : This ball is
tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
A3, J7, N7, F9, H1, F1,
H9
NC
NF
–
No co n n e ct : These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
A7, D2, E3, E7, E8
–
No fu n ct io n : When configured as a x4 device, these balls are NF.
When configured as a x8 device, these balls are defined as TDQS#,
DQ[7:4].
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
18
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 4:
86-Ba ll FBGA – x4, x8 Ba ll De scrip t io n s
Ba ll Assig n m e n t s
Sym b o l
Typ e
De scrip t io n
N3, P7, P3, N2,
P8, P2, R8, R2,
T8, R3,
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9
A10/AP,
A11, A12/BC#,
A13
Input
Ad d re ss in p u t s: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to VREFCA. A12/BC#: When enabled in the
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).
See Table 62 on page 91.
L7,
R7, N7,
T3
M2, N8, M3
BA0, BA1, BA2
Input
Ba n k a d d re ss in p u t s: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
J7, K7
K9
CK, CK#
CKE
Input
Input
Clo ck: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
Clo ck e n a b le : CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to VREFCA.
L2
E7
K1
CS#
DM
Input
Input
Input
Ch ip se le ct : CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to VREFCA.
In p u t d a t a m a sk: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with the input data
during a write access. Although the DM ball is input-only, the DM
loading is designed to match that of the DQ and DQS balls. DM is
referenced to VREFDQ. DM has an optional use as TDQS on the x8.
ODT
On -d ie t e rm in a t io n : ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;
DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if
disabled via the LOAD MODE command. ODT is referenced to
VREFCA.
J3, K3, L3
RAS#, CAS#, WE#
Input
Co m m a n d in p u t s: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to VREFCA.
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
19
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 4:
86-Ba ll FBGA – x4, x8 Ba ll De scrip t io n s (co n t in u e d )
Ba ll Assig n m e n t s
Sym b o l
Typ e
De scrip t io n
T2
RESET#
Input
Re se t : RESET# is an active LOW CMOS input referenced to VSS. The
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET#
assertion and desertion are asynchronous.
E3, F7,
F2, F8
DQ0, DQ1,
DQ2, DQ3
I/O
I/O
Da t a in p u t /o u t p u t : Bidirectional data bus for the x4 configuration.
DQ[3:0] are referenced to VREFDQ.
E3, F7, F2,
F8, H3, H8,
G2, H7
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
Da t a in p u t /o u t p u t : Bidirectional data bus for the x8 configuration.
DQ[7:0] are referenced to VREFDQ.
F3, G3
DQS, DQS#
I/O
Da t a st ro b e : Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
E7, D7
TDQS, TDQS#
Output Te rm in a t io n d a t a st ro b e : Applies to the x8 configuration only.
When TDQS is enabled, DM is disabled, and the TDQS and TDQS#
balls provide termination resistance.
D2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
VDDQ
Supply Po w e r su p p ly: 1.5V ±0.075V.
E9, F1, H2, H9
Supply DQ p o w e r su p p ly: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
M8
VREFCA
Supply Re fe re n ce vo lt a g e fo r co n t ro l, co m m a n d , a n d a d d re ss: VREFCA
must be maintained at all times (including self refresh) for proper
device operation.
H1
VREFDQ
VSS
Supply Re fe re n ce vo lt a g e fo r d a t a : VREFDQ must be maintained at all
times (including self refresh) for proper device operation.
D1, D8, E1, G8, J2, J8,
M1, M9, P1, P9, T1,
T9
Supply Ground.
E2, E8, F9, G1, G9
L8
VSSQ
ZQ
Supply DQ g ro u n d : Isolated on the device for improved noise immunity.
Reference Ext e rn a l re fe re n ce b a ll fo r o u t p u t d rive ca lib ra t io n : This ball is
tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
A1, A3, A7, A9, D3,
J1, J9, L1, L9, M7, T7,
W1, W3, W7, W9
NC
NF
–
No co n n e ct : These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
D7, G2, H3, H7, H8
–
No fu n ct io n : When configured as a x4 device, these balls are NF.
When configured as a x8 device, these balls are defined as TDQS#,
DQ[7:4].
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
20
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 5:
96-Ba ll FBGA – x16 Ba ll De scrip t io n s
Ba ll Assig n m e n t s
Sym b o l
Typ e
De scrip t io n
N3, P7, P3, N2,
P8, P2, R8, R2,
T8, R3,
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9
A10/AP,
A11, A12/BC#
Input
Ad d re ss in p u t s: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to VREFCA. A12/BC#: When enabled in the
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See
Table 62 on page 91.
L7,
R7, N7
M2, N8, M3
BA0, BA1, BA2
Input
Ba n k a d d re ss in p u t s: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
J7, K7
K9
CK, CK#
CKE
Input
Input
Clo ck: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
Clo ck e n a b le : CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle),or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to VREFCA.
L2
E7
K1
CS#
LDM
ODT
Input
Input
Input
Ch ip se le ct : CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to VREFCA.
In p u t d a t a m a sk: LDM is a lower-byte, input mask signal for write
data. Lower-byte input data is masked when LDM is sampled HIGH
along with the input data during a write access. Although the LDM
ball is input-only, the LDM loading is designed to match that of the
DQ and DQS balls. LDM is referenced to VREFDQ.
On -d ie t e rm in a t io n : ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#,
LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/
TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and
DM for the x4. The ODT input is ignored if disabled via the LOAD
MODE command. ODT is referenced to VREFCA.
J3, K3, L3
RAS#, CAS#, WE#
Input
Co m m a n d in p u t s: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to VREFCA.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
21
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Ta b le 5:
96-Ba ll FBGA – x16 Ba ll De scrip t io n s (co n t in u e d )
Ba ll Assig n m e n t s
Sym b o l
Typ e
De scrip t io n
T2
RESET#
Input
Re se t : RESET# is an active LOW CMOS input referenced to VSS. The
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET#
assertion and desertion are asynchronous.
D3
UDM
Input
In p u t d a t a m a sk: UDM is an upper-byte, input mask signal for
write data. Upper-byte input data is masked when UDM is sampled
HIGH along with that input data during a WRITE access. Although
the UDM ball is input-only, the UDM loading is designed to match
that of the DQ and DQS balls. UDM is referenced to VREFDQ.
E3, F7, F2,
F8, H3, H8,
G2, H7
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
I/O
I/O
Da t a in p u t /o u t p u t : Lower byte of bidirectional data bus for the x16
configuration. DQ[7:0] are referenced to VREFDQ.
D7, C3,
C8, C2,
A7, A2,
B8, A3
DQ8, DQ9,
DQ10, DQ11,
DQ12, DQ13,
DQ14, DQ15
Da t a in p u t /o u t p u t : Upper byte of bidirectional data bus for the x16
configuration. DQ[15:8] are referenced to VREFDQ.
F3, G3
LDQS, LDQS#
I/O
I/O
Lo w e r b yt e d a t a st ro b e : Output with read data. Edge-aligned
with read data. Input with write data. Center-aligned to write data.
C7, B7
UDQS, UDQS#
Up p e r b yt e d a t a st ro b e : Output with read data. Edge-aligned
with read data. Input with write data. DQS is center-aligned to write
data.
B2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
VDDQ
Supply Po w e r su p p ly: 1.5V ±0.075V.
A1, A8, C1, C9, D2,
E9, F1, H2, H9
Supply DQ p o w e r su p p ly: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
M8
VREFCA
Supply Re fe re n ce vo lt a g e fo r co n t ro l, co m m a n d , a n d a d d re ss: VREFCA
must be maintained at all times (including self refresh) for proper
device operation.
H1
VREFDQ
VSS
Supply Re fe re n ce vo lt a g e fo r d a t a : VREFDQ must be maintained at all
times (including self refresh) for proper device operation.
A9, B3, E1, G8, J2, J8,
M1, M9, P1, P9, T1,
T9
Supply Ground.
B1, B9, D1, D8, E2,
E8, F9, G1, G9
VSSQ
ZQ
Supply DQ g ro u n d : Isolated on the device for improved noise immunity.
L8
Reference Ext e rn a l re fe re n ce b a ll fo r o u t p u t d rive ca lib ra t io n : This ball is
tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
J1, J9, L1, L9, M7, T3,
T7
NC
–
No co n n e ct : These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
22
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Pa cka g e Dim e n sio n s
Pa cka g e Dim e n sio n s
Fig u re 9:
78-Ba ll FBGA – x4, x8; “ JP”
0.8 ±0.1
Seating
plane
0.12 A
A
8 ±0.15
78X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.33
Ball A1 ID
Ball A1 ID
9
8
7
3
2
1
NSMD ball pads.
A
B
C
D
E
F
0.8 TYP
9.6
CTR
G
H
J
11.5 ±0.15
K
L
M
N
0.8
TYP
1.2 MAX
0.25 MIN
6.4 CTR
Notes: 1. All dimensions are in millimeters.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
23
1Gb : x4, x8, x16 DDR3 SDRAM
Pa cka g e Dim e n sio n s
Fig u re 10: 78-Ba ll FBGA – x4, x8; “ HX”
0.8 ±0.1
Seating
plane
A
0.12
A
78X Ø0.45
Solder ball
material: SAC305.
Dimensions apply to
solder balls post-
reflow on Ø0.33
NSMD ball pads.
Ball A1 ID
Ball A1 ID
9
8
7
3
2
1
A
B
C
D
E
F
9.6
CTR
G
H
J
11.5 ±0.15
K
L
M
N
0.8 TYP
0.8 TYP
6.4 CTR
9 ±0.15
1.2 MAX
0.25 MIN
Notes: 1. All dimensions are in millimeters.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
24
1Gb : x4, x8, x16 DDR3 SDRAM
Pa cka g e Dim e n sio n s
Fig u re 11: 86-Ba ll FBGA – x4, x8
0.8 ±0.1
Seating
plane
A
0.12 A
86X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.33 NSMD
Ball A1 ID
Ball A1 ID
9
8
7
3
2
1
ball pads.
A
D
E
F
0.8 TYP
G
H
J
14.4 CTR
15.5 ±0.15
K
L
M
N
P
R
T
2.4 TYP
W
0.8 TYP
6.4 CTR
9 ±0.15
1.2 MAX
0.25 MIN
Notes: 1. All dimensions are in millimeters.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
25
1Gb : x4, x8, x16 DDR3 SDRAM
Pa cka g e Dim e n sio n s
Fig u re 12: 96-Ba ll FBGA – x16
0.8 ±0.1
Seating
plane
A
0.12 A
96X Ø0.45
Solder ball
Ball A1 ID
Ball A1 ID
material: SAC305.
Dimensions
9
8
7
3
2
1
apply to solder
balls post-reflow
on Ø0.33 NSMD
ball pads.
A
B
C
D
E
F
G
H
J
12 CTR
15.5 ±0.15
K
L
M
N
P
R
S
0.8 TYP
0.8 TYP
1.2 MAX
0.25 MIN
6.4 CTR
9 ±0.15
Notes: 1. All dimensions are in millimeters.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
26
1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s
Ele ct rica l Sp e cifica t io n s
Ab so lu t e Ra t in g s
Stresses greater than those listed in Table 6 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
adversely affect reliability.
Ta b le 6:
Sym b o l
Ab so lu t e Ma xim u m Ra t in g s
Pa ra m e t e r
Min
Ma x
Un it s
No t e s
VDD
VDDQ
VIN, VOUT
TC
VDD supply voltage relative to VSS
VDD supply voltage relative to VSSQ
Voltage on any pin relative to VSS
Operating case temperature
Storage temperature
–0.4
–0.4
–0.4
0
1.975
1.975
1.975
95
V
V
1
V
°C
°C
2, 3
TSTG
–55
150
Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤300mV.
2. MAX operating case temperature. TC is measured in the center of the package (see
Figure 13 on page 28).
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during
operation.
In p u t /Ou t p u t Ca p a cit a n ce
Ta b le 7:
In p u t /Ou t p u t Ca p a cit a n ce
Note 1 applies to the entire table
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Ca p a cit a n ce Pa ra m e t e rs
Sym b o l
Min Ma x Min Ma x Min Ma x Min Ma x Un it s No t e s
CK and CK#
CCK
CDCK
CIO
0.8
0
1.6
0.15
3.0
0.8
0
1.6
0.15
3.0
0.8
0
1.4
0.15
2.5
0.8
0
1.4
0.15
2.3
pF
pF
pF
pF
ΔC: CK to CK#
Single-end I/O: DQ, DM
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
3
Differential I/O:
CIO
3.0
3.0
2.5
2.3
DQS, DQS#, TDQS, TDQS#
ΔC: DQS to DQS#, TDQS, TDQS#
ΔC: DQ to DQS
CDDQS
CDIO
0
0.2
0.3
1.5
0.3
0.5
0
0.2
0.3
1.5
0.3
0.5
0
0.15
0.3
1.3
0.2
0.4
0
0.15
0.3
1.3
0.2
0.4
pF
pF
pF
pF
pF
3
4
5
6
7
–0.5
0.75
–0.5
–0.5
0.75
–0.5
–0.5
–0.5
0.75
–0.4
–0.4
–0.5
0.75
–0.4
–0.4
Inputs (CTRL, CMD, ADDR)
ΔC: CTRL to CK
CI
CDI_CTRL
ΔC: CMD_ADDR to CK
CDI_CMD_ADDR –0.5
Notes: 1. VDD = +1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C.
VOUT(DC) = 0.5 × VDDQ, VOUT (peak-to-peak) = 0.1V.
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO (DQ) - 0.5 × (CIO [DQS] + CIO [DQS#]).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n:0],
BA[2:0].
6. CDI_CTRL = CI (CTRL) - 0.5 × (CCK [CK] + CCK [CK#]).
7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]).
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
27
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Th e rm a l Ch a ra ct e rist ics
Th e rm a l Ch a ra ct e rist ics
Ta b le 8:
Th e rm a l Ch a ra ct e rist ics
Pa ra m e t e r/Co n d it io n
Sym b o l
Va lu e
Un it s
No t e s
Operating case temperature
Junction-to-case (TOP)
TC
TC
0 to 85
0 to 95
3.2
°C
°C
1, 2, 3
1, 2, 3, 4
5
78-ball
86-ball
96-ball
ΘJC
°C/W
2.8
2.8
Notes: 1. MAX operating case temperature. TC is measured in the center of the package (see
Figure 13).
2. A thermal solution must be designed to ensure the DRAM device does not exceed the maxi-
mum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate. The use of SRT or ASR (if available) must be enabled.
5. The thermal resistance data is based off of a number of samples from multiple lots and
should be viewed as a typical number.
Fig u re 13: Th e rm a l Me a su re m e n t Po in t
(L/2)
T
test point
c
L
(W/2)
W
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
The following definitions are used within the IDD measurement tables:
• LOW: VIN ≤ VIL(AC) MAX; HIGH: VIN ≥ VIH(AC) MIN
• Stable: Inputs are stable at a HIGH or LOW level
• Floating: Inputs are VREF = VDDQ/ 2
• Switching: See Tables 10 and 11
Ta b le 9:
IDD Me a su re m e n t Co n d it io n s Re fe re n ce
Ta b le Nu m b e r
Me a su re m e n t Co n d it io n s
Table 13 on page 31
Table 14 on page 33
Table 15 on page 35
Table 16 on page 37
Table 17 on page 38
IDD0 and IDD1
IDD2Ps, IDD2Pf, IDD2Q, IDD2N, IDD3P, and IDD3N
IDD4R, IDD4W
IDD5B, IDD6, IDD6ET
IDD7 (see Table 18 on page 38)
Ta b le 10:
De fin it io n o f Sw it ch in g fo r Co m m a n d a n d Ad d re ss In p u t Sig n a ls
Sw it ch in g fo r Ad d re ss (Ro w /Co lu m n ) a n d Co m m a n d Sig n a ls (CS#, RAS#, CAS#, a n d /o r WE#)
Address (row/column)
If not otherwise stated, inputs are stable at HIGH or LOW during 4 clocks and then change to
the opposite value (Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax . . . )
Bank address
If not otherwise stated, the bank addresses should be switched in a similar fashion as the
row/column addresses
Command
(CS#, RAS#, CAS#, WE#)
Define command background pattern = D D D D D D D D D D D D . . . where:
D = (CS#, RAS#, CAS#, WE#) = (HIGH, LOW, LOW, LOW)
D = (CS#, RAS#, CAS#, WE#) = (HIGH, HIGH, HIGH, HIGH)
If other commands are necessary (ACTIVATE for IDD0 or READ for IDD4R), the background
pattern command is substituted by the respective CS#, RAS#, CAS#, and WE# levels of the
necessary command
Ta b le 11:
De fin it io n o f Sw it ch in g fo r Da t a Pin s
Sw it ch in g fo r Da t a Pin s (DQ, DQS, DM)
Data strobe (DQS)
Data (DQ)
Data strobe is changing between HIGH and LOW after every clock cycle
Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for
DQ signals, which means that data DQ is stable during one clock
Data masking (DM)
No switching; DM must always be driven LOW
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ta b le 12:
Tim in g Pa ra m e t e rs
DDR3-800
DDR3-1066
DDR3-1333
-15E
DDR3-1600
-125E -125
-25E
-25
-187E
7-7-7
-187
-15F
-15
-125F
IDD Pa ra m e t e r
5-5-5
6-6-6
8-8-8
8-8-8
9-9-9 10-10-10 9-9-9 10-10-10 11-11-11 Un it s
tCK (MIN) IDD
2.5
1.875
1.5
9
1.25
10
ns
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL IDD
5
6
15
7
8
15
8
12
48
36
12
30
45
6
10
15
51
36
15
30
45
6
9
11.25
46.25
35
11
13.75
48.75
35
tRCD (MIN) IDD
tRC (MIN) IDD
tRAS (MIN) IDD
tRP (MIN)
12.5
50
13.13
50.63
37.5
13.13
37.5
50
13.5
49.5
36
12.5
47.5
35
52.5
37.5
15
52.50
37.5
15
37.5
12.5
40
13.5
30
11.25
30
12.5
30
13.75
30
tFAW
x4, x8
40
37.5
50
x16
50
50
45
40
40
40
tRRD IDD
tRFC
x4, x8
x16
10
10
7.5
7.5
6
6
6
6
10
10
10
10
7.5
110
7.5
110
7.5
110
7.5
7.5
110
7.5
110
110
110
110
110
110
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC parametric test conditions.
3. IDD parameters are specified with ODT and the output buffer is disabled (MR1[12]).
4. Optional ASR is disabled unless stated otherwise.
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ta b le 13:
IDD Te st
IDD Me a su re m e n t Co n d it io n s fo r IDD0 a n d IDD1
IDD1: Op e ra t in g Cu rre n t 1
On e Ba n k ACTIVATE t o READ
t o PRECHARGE
IDD0: Op e ra t in g Cu rre n t 0
On e Ba n k ACTIVATE t o PRECHARGE
No t e s
Timing example
–
Figure 14 on page 32
CKE
HIGH
HIGH
On
External clock
tCK
tRC
tRAS
tRCD
tRRD
tRC
On
tCK (MIN) IDD
tRC (MIN) IDD
tRAS (MIN) IDD
tCK (MIN) IDD
tRC (MIN) IDD
tRAS (MIN) IDD
tRCD (MIN) IDD
n/a
n/a
n/a
n/a
n/a
CL
n/a
CL IDD
AL
n/a
0
CS#
HIGH between ACTIVATE and PRECHARGE
HIGH between ACTIVATE, READ, and
PRECHARGE
Command inputs
Switching—the only exceptions are
ACTIVATE and PRECHARGE commands;
Example of -25E IDD0 pattern:
Switching—the only exceptions are
ACTIVATE and PRECHARGE commands;
Example of -25E IDD1 pattern:
1
A0DDDDDDDDDDDDDDP0
A0DDDDR0DDDDDDDDDP0
Row/column addresses
Row addresses switching;
Address input A10 must be LOW at all times Address input A10 must be LOW at all times
Row addresses switching;
1
2
Bank addresses
Data I/O
Bank address is fixed (bank 0)
Bank address is fixed (bank 0)
Switching
Read data: Output data switches after
every clock cycle, which means that read
data is stable during falling DQS; I/O should
be floating when no read data
Output buffer DQ, DQS
ODT
Off
Off
Disabled
Disabled
Burst length
Active banks
n/a
8 fixed (via MR0)
Bank 0; ACTIVATE-to-PRECHARGE loop
Bank 0; ACTIVATE-to-READ-to-PRECHARGE
loop
Idle banks
All other
n/a
All other
n/a
Special notes
Notes: 1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Fig u re 14: IDD1 Exa m p le – DDR3-800, 5-5-5, x8 (-25E)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18
CK
BA[2:0]
A[9:0]
0
000
0
3FF
3
000
3FF
3
000
0
3FF
A10
A[12:11]
0
CS#
RAS#
CAS#
WE#
ACT
D
D#
D#
D
RD
D#
D#
D
D
D#
D#
D
D
D#
PRE
D
D
D# D#
Command
0
0
1
1
0
0
1
1
DQ
DM
IDD1 measurement loop
Notes: 1. Data DQ is shown, but the output buffer should be switched off (per MR1[12] = 1) to
achieve IOUT = 0mA (MR1[12] = 0 is reflected in this example; however, test conditions are
MR1[12] = 1). Address inputs are split into three parts.
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ta b le 14:
IDD Me a su re m e n t Co n d it io n s fo r Po w e r-Do w n Cu rre n t s
IDD2Ps
IDD2Pf
IDD2Q
Pre ch a rg e
Qu ie t
St a n d b y
Cu rre n t
Pre ch a rg e
Pre ch a rg e
IDD2N
Pre ch a rg e
St a n d b y
Cu rre n t
IDD3P
Act ive
Po w e r-Do w n
Cu rre n t
IDD3N
Act ive
St a n d b y
Cu rre n t
Po w e r-Do w n Po w e r-Do w n
Cu rre n t
Cu rre n t
Na m e
(Slo w Exit )1
(Fa st Exit )1
No t e s
Timing example
n/a
n/a
n/a
Figure 15 on
page 34
n/a
Figure 15 on
page 34
CKE
LOW
On
LOW
On
HIGH
On
HIGH
On
LOW
On
HIGH
On
External clock
tCK
tCK (MIN) IDD
tCK(MIN) IDD
tCK(MIN) IDD
tCK (MIN) IDD tCK (MIN) IDD tCK (MIN) IDD
tRC
tRAS
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
tRCD
n/a
n/a
n/a
n/a
n/a
n/a
tRRD
n/a
n/a
n/a
n/a
n/a
n/a
tRC
n/a
n/a
n/a
n/a
n/a
n/a
CL
n/a
n/a
n/a
n/a
n/a
n/a
AL
n/a
n/a
n/a
n/a
n/a
n/a
CS#
Stable
Stable
Stable
Stable
Stable
Stable
HIGH
Stable
Stable
HIGH
Switching
Switching
Stable
Stable
Stable
HIGH
Switching
Switching
Command inputs
2
2
Row/column
addresses
Bank addresses
Data I/O
Stable
Floating
Off
Stable
Floating
Off
Stable
Floating
Off
Switching
Switching
Off
Stable
Floating
Off
Switching
Switching
Off
2
3
Output buffer
DQ, DQS
ODT
Disabled
n/a
Disabled
n/a
Disabled
n/a
Disabled
n/a
Disabled
n/a
Disabled
n/a
Burst length
Active banks
Idle banks
Special notes
None
All
None
All
None
All
None
All
All
All
None
n/a
None
n/a
n/a
n/a
n/a
n/a
Notes: 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit,
MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).
2. For further definition of input switching, see Table 10 on page 29.
3. For further definition of data switching, see Table 11 on page 29.
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Fig u re 15: IDD2N/IDD3N Exa m p le – DDR3-800, 5-5-5, x8 (-25E)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK
BA[2:0]
A[12:0]
CS#
0
7
0
0000
1FFF
0000
RAS#
CAS#
WE#
Command
DQ[7:0]
D#
00
D#
FF
D
D
D#
00
D#
FF
D
D
D#
00
D#
FF
D
FF
00
FF 00
00
FF
FF
00
FF
00
00
FF
FF
00
FF 00
DM
IDD2N/IDD3N measurement loop
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ta b le 15:
IDD Te st
IDD Me a su re m e n t Co n d it io n s fo r IDD4R, IDD4W
IDD4R: Bu rst Re a d Op e ra t in g Cu rre n t
IDD4W: Bu rst Writ e Op e ra t in g Cu rre n t No t e s
Timing diagram example
Figure 16 on page 36
–
CKE
HIGH
HIGH
External clock
On
On
tCK
tCK (MIN) IDD
tCK (MIN) IDD
tRC
n/a
n/a
tRAS
n/a
n/a
tRCD
n/a
n/a
tRRD
n/a
n/a
tRC
n/a
n/a
CL
CL IDD
CL IDD
AL
0
0
CS#
HIGH between valid commands
HIGH between valid commands
Command inputs
Switching;
Switching;
1
READ command/pattern:
R0DDDR1DDDR2DDDR3DDDR4 . . .
Rx = READ from bank x
WRITE command/pattern:
W0DDDW1DDDW2DDDW3DDDW4 . . .
Wx = WRITE to bank x
Row/column addresses
Column addresses switching;
Address input A10 must always be LOW
Column addresses switching;
Address input A10 must always be LOW
1
2
Bank addresses
Data I/O
Bank address looping (0-to-1-to-2-to-3 . . . ) Bank address looping (0-to-1-to-2-to-3 . . . )
Seamless read data burst (BL8): Output
data switches after every clock cycle, which
means that read data is stable during
falling DQS
Seamless write data burst (BL8): Input data
switches after every clock cycle, which
means that write data is stable during
falling DQS
Output buffer DQ, DQS
ODT
Off
Disabled
8 fixed (via MR0)
All
Off
Disabled
Burst length
Active banks
Idle banks
8 fixed (via MR0)
All
None
None
Special notes
n/a
DM always LOW
Notes: 1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Fig u re 16: IDD4R Exa m p le – DDR3-800, 5-5-5, x8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
BA[2:0]
0
1
2
3
A[9:0]
A10
000
3FF
000
3FF
A[12:11]
0
3
0
3
CS#
RAS#
CAS#
WE#
CMD[2:0]
RD
D
D#
D#
RD
D
D#
D#
RD
D
D#
D#
RD
D
DQ[7:0]
DM
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF
Start measurement loop
Notes: 1. Data DQ is shown, but the output buffer should be switched off (per MR1[12] = 1) to
achieve IOUT = 0mA (MR1[12] = 0 is reflected in this example; however, test conditions are
MR1[12] = 1). Address inputs are split into three parts.
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ta b le 16:
IDD Te st
IDD Me a su re m e n t Co n d it io n s fo r IDD5B, IDD6, IDD6ET
IDD6: Se lf Re fre sh Cu rre n t
IDD6ET: Se lf Re fre sh Cu rre n t
Ext e n d e d Te m p e ra t u re
Ra n g e
No rm a l Te m p e ra t u re
Ra n g e
IDD5B: Re fre sh
Cu rre n t
TC = 0°C t o 85°C
TC = 0°C t o 95°C
No t e s
CKE
HIGH
LOW
LOW
External clock
tCK
tRC
On
Off, CK and CK# = LOW
Off, CK and CK# = LOW
tCK (MIN) IDD
n/a
n/a
n/a
n/a
n/a
tRAS
tRCD
tRRD
tRC
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
tRFC (MIN) IDD
n/a
n/a
CL
n/a
n/a
n/a
n/a
AL
n/a
n/a
CS#
HIGH between valid
commands
Floating
Floating
Command inputs
Row/column addresses
Bank addresses
Data I/O
Switching
Switching
Switching
Switching
Disabled
Disabled
n/a
Floating
Floating
Floating
Floating
Disabled
Disabled
n/a
Floating
Floating
Floating
Floating
Disabled
Disabled
n/a
1
1
1
2
Output buffer DQ, DQS
ODT
Burst length
Active banks
REFRESH command
every tRFC (MIN)
n/a
n/a
Idle banks
None
n/a
n/a
n/a
Special notes
SRT disabled
SRT enabled
Notes: 1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ta b le 17:
IDD Te st
IDD Me a su re m e n t Co n d it io n s fo r IDD7
IDD7: All Ba n ks In t e rle a ve d Re a d Cu rre n t
CKE
HIGH
External clock
On
tCK
tCK (MIN) IDD
tRC
tRC (MIN) IDD
tRAS
tRAS (MIN) IDD
tRCD
tRCD (MIN) IDD
tRRD
tRRD (MIN) IDD
tRC
n/a
CL
CL IDD
AL
CL - 1
CS#
HIGH between valid commands
See Table 10 on page 29 for patterns
Stable during DESELECTs (DES)
Looping (see Table 10 on page 29 for patterns)
Command inputs
Row/column addresses
Bank addresses
Data I/O
Read data (BL8): output data switches after every clock cycle, which means that read data is
stable during falling DQS; I/O should be floating when no read data is being driven
Output buffer DQ, DQS
ODT
Off
Disabled
8 fixed (via MR0)
All, rotational
n/a
Burst length
Active banks
Idle banks
Ta b le 18:
Sp e e d Bin
IDD7 Pa t t e rn s
Wid t h IDD7 Pa t t e rn
DDR3-800
(-25, -25E)
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
D D A0 . . .
x16 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
A7 RA7 D D D D D D A0 . . .
DDR3-1066
(-187, -187E)
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
A7 RA7 D D D D D D A0 . . .
x16 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5
RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D A0 . . .
DDR3-1333
(-15, -15E, -15F)
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
A7 RA7 D D D D D D A0 . . .
x16 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D
A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D A0 . . .
DDR3-1600
(-125E, -125F, -125)
x4, x8 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D
D A6 RA6 D D D A7 RA7 D D D D D D D A0 . . .
x16 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D
D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D D D D A0 . . .
Notes: 1. A0 = ACTIVATE bank 0; RA0 = READ with auto precharge bank 0; D = DESELECT.
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Ch a ra ct e rist ics – IDD Sp e cifica t io n s
Ele ct rica l Ch a ra ct e rist ics – IDD Sp e cifica t io n s
IDD values are for full operating range of voltage and temperature unless otherwise
noted.
Ta b le 19:
IDD Ma xim u m Lim it s
Sp e e d Bin
IDD
Wid t h
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Un it s
No t e s
IDD0
x4
x8
65
90
75
100
100
95
85
110
110
105
130
150
10
95
120
120
115
140
170
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2, 3
2, 4
1, 2
1, 2
1, 2
x16
x4
90
IDD1
85
x8
110
110
10
120
130
10
x16
Slow (s)
Fast (f)
All
IDD2P
25
25
25
25
IDD2Q
IDD2N
IDD3P
IDD3N
40
45
50
55
All
45
50
55
60
All
25
30
35
40
x4, x8
x16
x4
50
55
60
65
50
55
60
65
IDD4R
130
130
190
130
130
210
200
6
160
160
230
160
160
265
220
6
200
200
270
190
190
325
240
6
250
250
315
225
225
400
260
6
x8
x16
x4
IDD4W
x8
x16
All
IDD5B
IDD6
All
IDD6ET
IDD7
All
9
9
9
9
x4
230
350
350
250
390
380
315
490
420
400
600
460
x8
x16
Notes: 1. TC = 85°C; SRT and ASR are disabled.
2. Enabling ASR could increase IDDx by up to an additional 2mA.
3. Restricted to TC (MAX) = 85°C.
4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.
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1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Ele ct rica l Sp e cifica t io n s – DC a n d AC
DC Op e ra t in g Co n d it io n s
Ta b le 20:
DC Ele ct rica l Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
All voltages are referenced to VSS
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
No m
Ma x
Un it s No t e s
Supply voltage
VDD
VDDQ
II
1.425
1.425
–2
1.5
1.5
–
1.575
1.575
2
V
V
1, 2
1, 2
I/O supply voltage
Input leakage current
µA
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
VREF supply leakage current
IVREF
–1
–
1
µA
3, 4
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
Notes: 1. VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC
(0Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing
parameters.
3. VREF (see Table 21).
4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin
should be minimal.
In p u t Op e ra t in g Co n d it io n s
Ta b le 21:
DC Ele ct rica l Ch a ra ct e rist ics a n d In p u t Co n d it io n s
All voltages are referenced to VSS
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
No m
Ma x
Un it s No t e s
Input reference voltage command/address bus
I/O reference voltage DQ bus
VREFCA(DC)
VREFDQ(DC)
VTT
0.49 × VDD
0.49 × VDD
–
0.5 × VDD
0.5 × VDD
0.5 × VDDQ
0.51 × VDD
0.51 × VDD
–
V
V
V
1, 2
2, 3
4
Command/address termination voltage
(system level, not direct DRAM input)
Notes: 1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed ±1
percent × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not
exceed ±2 percent of VREFCA(DC).
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifica-
tions if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed ±1
percent × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not
exceed ±2 percent of VREFDQ(DC).
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resis-
tors. MIN and MAX values are system-dependent.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Ta b le 22:
AC In p u t Op e ra t in g Co n d it io n s
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Pa ra m e t e r/Co n d it io n
Sym b o l
Un it s
Co m m a n d a n d Ad d re ss
Input high AC voltage: Logic 1
Input high DC voltage: Logic 1
Input low DC voltage: Logic 0
Input low AC voltage: Logic 0
VIH(AC) MIN
VIH(DC) MIN
VIL(DC) MAX
VIL(AC) MAX
+175
+150 or +175
+100
mV
mV
mV
mV
+100
–100
–175
–100
–150 or –175
DQ a n d DM
Input high AC voltage: Logic 1
Input high DC voltage: Logic 1
Input low DC voltage: Logic 0
Input low AC voltage: Logic 0
VIH(AC) MIN
VIH(DC) MIN
VIL(DC) MAX
VIL(AC) MAX
+175
+100
–100
–175
+150
+100
–100
–150
mV
mV
mV
mV
Notes: 1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All
slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and
DM inputs.
t
2. Input setup timing parameters (tIS and DS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).
t
3. Input hold timing parameters (tIH and DH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).
4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV
(peak-to-peak).
t
5. For VIH(AC) and VIL(AC) levels of 150mV, special setup and hold derating and different VAC
numbers apply.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Fig u re 17: In p u t Sig n a l
VIL and VIH levels with ringback
V
DDQ + 0.4V narrow
1.90V
1.50V
pulse width
VDDQ
Minimum VIL and VIH levels
VIH(AC)
0.925V
0.850V
0.925V
0.850V
V
IH
(
AC
)
)
VIH(DC)
VIH(
DC
0.780V
0.765V
0.750V
0.735V
0.720V
0.780V
0.765V
0.750V
0.735V
0.720V
V
REF + AC noise
V
REF + DC error
V
REF - DC error
V
REF - AC noise
0.650V
V
IL
(
DC
)
)
0.650V
V
IL
(
DC
)
)
0.575V
0.575V
VIL(
AC
VIL(
AC
0.0V
VSS
–0.40V
VSS - 0.4V narrow
pulse width
Notes: 1. Numbers in diagrams reflect nominal values.
AC Ove rsh o o t /Un d e rsh o o t Sp e cifica t io n
Ta b le 23:
Pa ra m e t e r
Co n t ro l a n d Ad d re ss Pin s
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Maximum peak amplitude allowed for overshoot area
(see Figure 18 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
(see Figure 19 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above VDD (see Figure 18 on page 43)
0.67 Vns
0.5 Vns
0.5 Vns
0.4 Vns
0.4 Vns
0.33 Vns
0.33 Vns
Maximum undershoot area below VSS (see Figure 19 on page 43) 0.67 Vns
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Ta b le 24:
Pa ra m e t e r
Clo ck, Da t a , St ro b e , a n d Ma sk Pin s
DDR3-800
DDR3-1066 DDR3-1333 DDR3-1600
Maximum peak amplitude allowed for overshoot area
(see Figure 18 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
(see Figure 19 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above VDD/VDDQ
(see Figure 18 on page 43)
0.25 Vns
0.25 Vns
0.19 Vns
0.19 Vns
0.15 Vns
0.15 Vns
0.13 Vns
0.13 Vns
Maximum undershoot area below VSS/VSSQ
(see Figure 19 on page 43)
Fig u re 18: Ove rsh o o t
Maximum amplitude
Overshoot area
Volts (V)
VDD/VDDQ
Time (ns)
Fig u re 19: Un d e rsh o o t
VSS/VSSQ
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Ta b le 25:
Diffe re n t ia l In p u t Op e ra t in g Co n d it io n s (CK, CK# a n d DQS, DQS#)
All voltages are referenced to VSS
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
Differential input voltage
VIN
VMP(DC)
VIHDIFF
VILDIFF
VIX
–400
650
VDD + 400
850
mV
mV
mV
mV
mV
mV
mV
Differential input midpoint voltage
Differential input voltage logic high
Differential input voltage logic low
200
VDD + 400
–200
VSSQ - 400
VREF(DC) - 150
VREF(DC) - 175
VREF(DC) - 150
Differential input crossing voltage relative
to VDD/2 for CK, CK#
VREF(DC) + 150
VREF(DC) + 175
VREF(DC) + 150
Differential input crossing voltage relative
to VDD/2 for DQS, DQS#
Notes: 1. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#) level.
VMP(DC) is expected to be about 0.5 × VDDQ.
2. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which dif-
ferential input signals must cross.
3. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe.
4. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.
5. Differential input slew rate = 2 V/ns.
6. The VIX extended range (±175mV) is allowed only for the clock. Additionally, the VIX
extended range is only allowed when the following conditions are met: The single-ended
input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2
±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns.
Fig u re 20: Sin g le -En d e d Re q u ire m e n t s fo r Diffe re n t ia l Sig n a ls
VDD or VDDQ
VSEH (MIN)
VDD/2 or VDDQ/2
VSEH
CK or DQS
VSEL (MAX)
VSEL
VSS or VSSQ
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
t
Fig u re 21: De fin it io n o f Diffe re n t ia l AC-Sw in g a n d DVAC
t
DVAC
VIHDIFF(AC) MIN
VIHDIFF (MIN)
VIHDIFF(DC) MIN
CK - CK#
DQS - DQS#
0.0
VILDIFF(DC) MAX
VILDIFF (MAX)
VILDIFF(AC) MAX
t
half cycle
DVAC
t
Ta b le 26:
Allo w e d Tim e Be fo re Rin g b a ck ( DVAC) fo r CK - CK# a n d DQS - DQS#
Below VIL(AC)
t DVAC (p s) a t |VIHDIFF(AC)/VILDIFF(AC)|
Sle w Ra t e (V/n s)
350m V
300m V
>4.0
4.0
3.0
2.0
1.9
1.6
1.4
1.2
1.0
<1.0
75
57
50
38
34
29
22
13
0
175
170
167
163
162
161
159
155
150
150
0
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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45
1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Sle w Ra t e De fin it io n s fo r Sin g le -En d e d In p u t Sig n a ls
t
t
Setup ( IS and DS) nominal slew rate for a rising signal is defined as the slew rate
t
between the last crossing of VREF and the first crossing of VIH(AC) MIN. Setup ( IS and
t
DS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VREF and the first crossing of VIL(AC) MAX (see Figure 22 on page 47).
t
t
Hold ( IH and DH) nominal slew rate for a rising signal is defined as the slew rate
t
between the last crossing of VIL(DC) MAX and the first crossing of VREF. Hold ( IH and
t
DH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(DC) MIN and the first crossing of VREF (see Figure 22 on page 47).
Ta b le 27:
Sin g le -En d e d In p u t Sle w Ra t e De fin it io n
In p u t Sle w Ra t e s
(Lin e a r Sig n a ls)
Me a su re d
In p u t
Ed g e
Fro m
To
Ca lcu la t io n
Setup
Rising
VREF
VIH(AC) MIN
VIL(AC) MAX
VREF
VIH(AC) MIN - VREF
ΔTRS
Falling
Rising
Falling
VREF
V
REF - VIL
(
AC) MAX
ΔTFS
Hold
VIL(DC) MAX
VIH(DC) MIN
V
REF - VIL
(
DC) MAX
ΔTFH
VREF
VIH(DC) MIN - VREF
ΔTRSH
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Fig u re 22: No m in a l Sle w Ra t e De fin it io n fo r Sin g le -En d e d In p u t Sig n a ls
ΔTRS
Setup
VIH(AC) MIN
VIH(DC) MIN
VREFDQ or
VREFCA
VIL(DC) MAX
VIL(AC) MAX
ΔTFS
ΔTRH
Hold
VIH(AC) MIN
VIH(DC) MIN
VREFDQ or
VREFCA
VIL(DC) MAX
VIL(AC) MAX
ΔTFH
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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47
1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Sle w Ra t e De fin it io n s fo r Diffe re n t ia l In p u t Sig n a ls
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and
measured, as shown in Table 28 and Figure 23. The nominal slew rate for a rising signal
is defined as the slew rate between VIL(DIFF ) MAX and VIH(DIFF ) MIN. The nominal slew
rate for a falling signal is defined as the slew rate between VIH(DIFF ) MIN and
VIL(DIFF) MAX.
Ta b le 28:
Diffe re n t ia l In p u t Sle w Ra t e De fin it io n
Diffe re n t ia l In p u t
Sle w Ra t e s (Lin e a r
Sig n a ls)
Me a su re d
In p u t
Ed g e
Fro m
To
Ca lcu la t io n
CK and DQS
reference
Rising
VIL(DIFF) MAX
VIH(DIFF) MIN
VIH(DIFF) MIN - VIL(DIFF) MAX
ΔTR(DIFF)
Falling
VIH(DIFF) MIN
VIL(DIFF) MAX
VIH(DIFF) MIN - VIL(DIFF) MAX
ΔTF(DIFF)
Fig u re 23: No m in a l Diffe re n t ia l In p u t Sle w Ra t e De fin it io n fo r DQS, DQS# a n d CK, CK#
ΔTRDIFF
VIH(DIFF) MIN
0
VIL(DIFF) MAX
ΔTFDIFF
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
ODT Ch a ra ct e rist ics
ODT Ch a ra ct e rist ics
ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the DQ,
DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values are
listed in Table 29 and Table 30 on page 50. A functional representation of the ODT is
shown in Figure 24. The individual pull-up and pull-down resistors (RTT and RTT
)
PU
PD
are defined as follows:
• RTT = (VDDQ - VOUT)/ |IOUT|, under the condition that RTT is turned off
PU
PD
• RTT = (VOUT)/ |IOUT|, under the condition that RTT is turned off
PD
PU
Fig u re 24: ODT Le ve ls a n d I-V Ch a ra ct e rist ics
Chip in termination mode
ODT
VDDQ
IPU
IOUT = IPD - IPU
To
RTT
PU
other
circuitry
such as
RCV, . . .
DQ
IOUT
RTT
PD
VOUT
IPD
VSSQ
Ta b le 29:
On -Die Te rm in a t io n DC Ele ct rica l Ch a ra ct e rist ics
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
No m
Ma x
Un it s
No t e s
RTT effective impedance
RTT_EFF
See Table 30 on page 50
+5
1, 2
Deviation of VM with respect to VDDQ/2
ΔVM
–5
%
1, 2, 3
Notes: 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable
temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to "ODT Sensitivity" on page 50 if
either the temperature or voltage changes after calibration.
2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current
I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]:
VIH(AC) – VIL(AC)
|I(VIH(AC))–I(VIL(AC))|
--------------------------------------------------------------
RTT =
3. Measure voltage (VM) at the tested pin with no load:
2 × VM
VDDQ
⎛
⎝
⎞
-----------------
ΔVM =
– 1 × 100
⎠
ODT Re sist o rs
Table 30 on page 50 provides an overview of the ODT DC electrical characteristics. The
values provided are not specification requirements; however, they can be used as design
guidelines to indicate what RTT is targeted to provide:
• RTT 120Ω is made up of RTT
• RTT 60Ω is made up of RTT
and RTT
120PD240
120PU240
60PU120
and RTT
60PD120
• RTT 40Ω is made up of RTT
• RTT 30Ω is made up of RTT
• RTT 20Ω is made up of RTT
and RTT
40PD80
30PD60
20PD40
40PU80
30PU60
20PU40
and RTT
and RTT
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1Gb : x4, x8, x16 DDR3 SDRAM
ODT Ch a ra ct e rist ics
Ta b le 30:
RTT Effe ct ive Im p e d a n ce s
MR1
[9, 6, 2]
RTT
Re sist o r
VOUT
Min
No m
Ma x
Un it s
0, 1, 0
0, 0, 1
0, 1, 1
1, 0, 1
1, 0, 0
120Ω
RTT
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/4
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/6
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/8
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/12
120PD240
RTT
120PU240
120Ω
60Ω
40Ω
30Ω
20Ω
RTT
60PD120
60PU120
RTT
60Ω
RTT
RTT
40PD80
40PU80
40Ω
30Ω
20Ω
RTT
RTT
30PD60
30PU60
RTT
RTT
20PD40
20PU40
Notes: 1. Values assume an RZQ of 240Ω (±1 percent).
ODT Se n sit ivit y
If either the temperature or voltage changes after I/ O calibration, the tolerance limits
listed in Table 29 on page 49 and Table 30 can be expected to widen according to
Tables 31 and 32 on page 51.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
ODT Ch a ra ct e rist ics
Ta b le 31:
ODT Se n sit ivit y De fin it io n
Sym b o l
Min
Ma x
1.6 + dRTTdT × |DT| + dRTTdV × |DV|
Un it s
RTT
0.9 - dRTTdT × |DT| - dRTTdV × |DV|
RZQ/(2, 4, 6, 8, 12)
Notes: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ.
Ta b le 32:
ODT Te m p e ra t u re a n d Vo lt a g e Se n sit ivit y
Ch a n g e
Min
Ma x
Un it s
dRTTdT
dRTTdV
0
0
1.5
% /°C
0.15
% /mV
Notes: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ.
ODT Tim in g De fin it io n s
ODT loading differs from that used in AC timing measurements. The reference load for
ODT timings is shown in Figure 25. Two parameters define when ODT turns on or off
synchronously, two define when ODT turns on or off asynchronously, and another
defines when ODT turns on or off dynamically. Table 33 outlines and provides definition
and measurement reference settings for each parameter (see Figure 34 on page 52).
ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to
turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance
begins to turn off.
Fig u re 25: ODT Tim in g Re fe re n ce Lo a d
VDDQ/2
VREF
DUT
RTT = 25Ω
DQ, DM
DQS, DQS#
CK, CK#
VTT = VSSQ
TDQS, TDQS#
Timing reference point
RZQ = 240Ω
ZQ
VSSQ
Ta b le 33:
ODT Tim in g De fin it io n s
Sym b o l
Be g in Po in t De fin it io n
En d Po in t De fin it io n
Fig u re
tAON
Rising edge of CK - CK# defined by the end
point of ODTL on
Extrapolated point at VSSQ
Figure 26 on page 52
tAOF
Rising edge of CK - CK# defined by the end
point of ODTL off
Extrapolated point at VRTT_NOM
Extrapolated point at VSSQ
Figure 26 on page 52
Figure 27 on page 53
Figure 27 on page 53
Figure 28 on page 53
tAONPD Rising edge of CK - CK# with ODT first being
registered HIGH
tAOFPD
tADC
Rising edge of CK - CK# with ODT first being
registered LOW
Extrapolated point at VRTT_NOM
Rising edge of CK - CK# defined by the end
point of ODTLCNW, ODTLCWN4, or ODTLCWN8
Extrapolated points at VRTT_WR and
VRTT_NOM
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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51
1Gb : x4, x8, x16 DDR3 SDRAM
ODT Ch a ra ct e rist ics
Ta b le 34:
Re fe re n ce Se t t in g s fo r ODT Tim in g Me a su re m e n t s
Me a su re d Pa ra m e t e r
RTT_NOM Se t t in g
RTT_WR Se t t in g
VSW1
VSW2
tAON
RZQ/4 (60Ω)
RZQ/12 (20Ω)
RZQ/4 (60Ω)
RZQ/12 (20Ω)
RZQ/4 (60Ω)
RZQ/12 (20Ω)
RZQ/4 (60Ω)
RZQ/12 (20Ω)
RZQ/12 (20Ω)
n/a
50mV
100mV
50mV
100mV
200mV
100mV
200mV
100mV
200mV
100mV
200mV
300mV
n/a
tAOF
tAONPD
tAOFPD
tADC
n/a
n/a
100mV
50mV
n/a
n/a
n/a
100mV
50mV
n/a
100mV
200mV
RZQ/2 (120Ω)
Notes: 1. Assume an RZQ of 240Ω (±1 percent) and that proper ZQ calibration has been performed at
a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).
t
t
Fig u re 26: AON a n d AOF De fin it io n s
t
AON
t
AOF
Begin point: Rising edge of CK - CK#
defined by the end point of ODTL on
Begin point: Rising edge of CK - CK#
defined by the end point of ODTL off
CK
CK
VDDQ/2
CK#
CK#
t
t
AON
AOF
End point: Extrapolated point at VRTT_NOM
TSW2
VRTT_NOM
TSW1
TSW1
DQ, DM
TSW1
DQS, DQS#
TDQS, TDQS#
VSW2
VSW2
VSW1
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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52
1Gb : x4, x8, x16 DDR3 SDRAM
ODT Ch a ra ct e rist ics
t
t
Fig u re 27: AONPD a n d AOFPD De fin it io n
t
t
AONPD
AOFPD
Begin point: Rising edge of CK - CK#
with ODT first registered HIGH
Begin point: Rising edge of CK - CK#
with ODT first registered LOW
CK
CK
VDDQ/2
CK#
CK#
t
t
AONPD
AOFPD
End point: Extrapolated point at VRTT_NOM
VRTT_NOM
TSW2
TSW2
TSW1
DQ, DM
TSW1
DQS, DQS#
TDQS, TDQS#
VSW2
VSW2
VSW1
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
t
Fig u re 28: ADC De fin it io n
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLCNW
Begin point: Rising edge of CK - CK# defined by
the end point of ODTLCWN4 or ODTLCWN8
CK
VDDQ/2
CK#
t
t
ADC
ADC
VRTT_NOM
VRTT_NOM
TSW21
TSW11
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point:
Extrapolated
point at VRTT_NOM
TSW22
VSW2
TSW12
End point: Extrapolated point at VRTT_WR
VSW1
VRTT_WR
VSSQ
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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53
1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Drive r Im p e d a n ce
Ou t p u t Drive r Im p e d a n ce
The output driver impedance is selected by MR1[5,1] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is
performed. Output specifications refer to the default output driver unless specifically
stated otherwise. A functional representation of the output buffer is shown in Figure 29
on page 54. The output driver impedance RON is defined by the value of the external
reference resistor RZQ as follows:
• RON = RZQ/ y (with RZQ = 240Ω ±1 percent; x = 34Ω or 40Ω with y = 7 or 6, respec-
x
tively)
The individual pull-up and pull-down resistors (RON and RON ) are defined as
PU
PD
follows:
• RON
= (VDDQ - VOUT)/ |IOUT|, when RON is turned off
PU
PD
• RON = (VOUT)/ |IOUT|, when RON is turned off
PD
PU
Fig u re 29: Ou t p u t Drive r
Chip in drive mode
Output driver
VDDQ
IPU
To
other
RON
PU
circuitry
such as
RCV, . . .
DQ
IOUT
RON
PD
VOUT
IPD
VSSQ
34Ω Ou t p u t Drive r Im p e d a n ce
The 34Ω driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings
and specifications listed herein apply to the 34Ω driver only. Its impedance RON is
defined by the value of the external reference resistor RZQ as follows: RON = RZQ/ 7
34
(with nominal RZQ = 240Ω ±1 percent) and is actually 34.3Ω ±1 percent. The 34Ω output
driver impedance characteristics are listed in Table 35 on page 55.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Drive r Im p e d a n ce
Ta b le 35:
34Ω Drive r Im p e d a n ce Ch a ra ct e rist ics
MR1[5,1]
RON
Re sist o r
VOUT
Min
No m
Ma x
Un it s
No t e s
0,1
34.3Ω
Ron34PD
0.2/VDDQ
0.5/VDDQ
0.8/VDDQ
0.2/VDDQ
0.5/VDDQ
0.8/VDDQ
0.5/VDDQ
0.6
0.9
1.0
1.0
1.0
1.0
1.0
1.0
n/a
1.1
1.1
1.4
1.4
1.1
1.1
10
RZQ/ 7
RZQ/ 7
RZQ/ 7
RZQ/ 7
RZQ/ 7
RZQ/ 7
%
1
1
0.9
1
RON
34PU
0.9
1
0.9
1
0.6
1
Pull-up/pull-down mismatch (MMPUPD
)
–10%
1, 2
Notes: 1. Tolerance limits assume RZQ of 240Ω (±1 percent) and are applicable after proper ZQ cali-
bration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).
Refer to "34Ω Driver Output Sensitivity" on page 56 if either the temperature or the volt-
age changes after calibration.
2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure
both RONPU and RONPD at 0.5 × VDDQ:
RONPU – RON
PD
MMPUPD = ------------------------------------ X100
RONNOM
34Ω Drive r
The 34Ω driver’s current range has been calculated and summarized in Table 37 on
page 56 for VDD = 1.5V, Table 38 on page 56 for VDD = 1.575V, and Table 39 on page 56
for VDD = 1.425V. The individual pull-up and pull-down resistors (RON
are defined as follows:
and RON
)
34PD
34PU
• RON
• RON
= (VOUT)/ |IOUT|; RON
is turned off
34PU
34PD
34PU
= (VDDQ - VOUT)/ |IOUT|; RON
is turned off
34PD
Ta b le 36:
34Ω Drive r Pu ll-Up a n d Pu ll-Do w n Im p e d a n ce Ca lcu la t io n s
RON
Min
No m
Ma x
Un it s
RZQ = 240Ω ±1 percent
237.6
33.9
240
242.4
34.6
Ω
RZQ/7 = (240Ω ±1 percent)/7
34.3
Ω
MR1[5,1]
RON
Re sist o r
VOUT
Min
No m
Ma x
Un it s
0, 1
34.3Ω
RON
34PD
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
20.4
30.5
30.5
30.5
30.5
20.4
34.3
34.3
34.3
34.3
34.3
34.3
38.1
38.1
48.5
48.5
38.1
38.1
Ω
Ω
Ω
Ω
Ω
Ω
RON
34PU
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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55
1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Drive r Im p e d a n ce
Ta b le 37:
34Ω Drive r IOH/IOL Ch a ra ct e rist ics: VDD = VDDQ = 1.5V
MR1[5,1]
RON
Re sist o r
VOUT
Ma x
No m
Min
Un it s
0, 1
34.3Ω
RON
34PD
IOL @ 0.2 × VDDQ
IOL @ 0.5 × VDDQ
IOL @ 0.8 × VDDQ
IOH @ 0.2 × VDDQ
IOH @ 0.5 × VDDQ
IOH @ 0.8 × VDDQ
14.7
24.6
39.3
39.3
24.6
14.7
8.8
21.9
35.0
35.0
21.9
8.8
7.9
19.7
24.8
24.8
19.7
7.9
mA
mA
mA
mA
mA
mA
RON
34PU
Ta b le 38:
34Ω Drive r IOH/IOL Ch a ra ct e rist ics: VDD = VDDQ = 1.575V
MR1[5,1]
RON
Re sist o r
VOUT
Ma x
No m
Min
Un it s
0, 1
34.3Ω
RON
34PD
IOL @ 0.2 × VDDQ
IOL @ 0.5 × VDDQ
IOL @ 0.8 × VDDQ
IOH @ 0.2 × VDDQ
IOH @ 0.5 × VDDQ
IOH @ 0.8 × VDDQ
15.5
25.8
41.2
41.2
25.8
15.5
9.2
23
8.3
20.7
26
mA
mA
mA
mA
mA
mA
36.8
36.8
23
RON
34PU
26
20.7
8.3
9.2
Ta b le 39:
34Ω Drive r IOH/IOL Ch a ra ct e rist ics: VDD = VDDQ = 1.425V
MR1[5,1]
RON
Re sist o r
VOUT
Ma x
No m
Min
Un it s
0, 1
34.3Ω
RON
34PD
IOL @ 0.2 × VDDQ
IOL @ 0.5 × VDDQ
IOL @ 0.8 × VDDQ
IOH @ 0.2 × VDDQ
IOH @ 0.5 × VDDQ
IOH @ 0.8 × VDDQ
14.0
23.3
37.3
37.3
23.3
14.0
8.3
20.8
33.3
33.3
20.8
8.3
7.5
18.7
23.5
23.5
18.7
7.5
mA
mA
mA
mA
mA
mA
RON
34PU
34Ω Drive r Ou t p u t Se n sit ivit y
If either the temperature or the voltage changes after ZQ calibration, the tolerance limits
listed in Table 35 on page 55 can be expected to widen according to Table 40 and
Table 41 on page 57.
Ta b le 40:
34Ω Ou t p u t Drive r Se n sit ivit y De fin it io n
Sym b o l Min
0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
Ma x
Un it s
RON @ 0.8 × VDDQ
RON @ 0.5 × VDDQ
RON @ 0.2 × VDDQ
1.1 + dRONdTH × |ΔT| + dRONdVH × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/ 7
RZQ/7
RZQ/ 7
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
Notes: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration), and VDD = VDDQ.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Drive r Im p e d a n ce
Ta b le 41:
34Ω Ou t p u t Drive r Vo lt a g e a n d Te m p e ra t u re Se n sit ivit y
Ch a n g e
Min
Ma x
Un it s
dRONdTM
dRONdVM
dRONdTL
dRONdVL
dRONdTH
dRONdVH
0
0
0
0
0
0
1.5
0.13
1.5
% /°C
% /mV
% /°C
0.13
1.5
% /mV
% /°C
0.13
% /mV
Alt e rn a t ive 40Ω Drive r
Ta b le 42:
40Ω Drive r Im p e d a n ce Ch a ra ct e rist ics
MR1[5,1]
RON
Re sist o r
VOUT
Min
No m
Ma x
Un it s
No t e s
0,0
40Ω
RON
40PD
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.5 × VDDQ
0.6
0.9
1.0
1.0
1.0
1.0
1.0
1.0
n/a
1.1
1.1
1.4
1.4
1.1
1.1
10
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
%
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
0.9
RON
40PU
0.9
0.9
0.6
Pull-up/pull-down mismatch (MMPUPD
)
–10%
Notes: 1. Tolerance limits assume RZQ of 240Ω (±1 percent) and are applicable after proper ZQ cali-
bration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).
Refer to "40Ω Driver Output Sensitivity" on page 57 if either the temperature or the volt-
age changes after calibration.
2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure
both RONPU and RONPD at 0.5 × VDDQ:
RON – RON
PU
PD
MM
= ------------------------------------x100
PUPD
RONNo m
40Ω Drive r Ou t p u t Se n sit ivit y
If either the temperature or the voltage changes after I/ O calibration, the tolerance
limits listed in Table 42 can be expected to widen according to Table 43 and Table 44 on
page 58.
Ta b le 43:
40Ω Ou t p u t Drive r Se n sit ivit y De fin it io n
Sym b o l Min
0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
Ma x
Un it s
RON @ 0.8 × VDDQ
RON @ 0.5 × VDDQ
RON @ 0.2 × VDDQ
1.1 + dRONdTH × |ΔT| + dRONdVH × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/6
RZQ/6
RZQ/6
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
Notes: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration), and VDD = VDDQ.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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57
1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
Ta b le 44:
40Ω Ou t p u t Drive r Vo lt a g e a n d Te m p e ra t u re Se n sit ivit y
Ch a n g e
Min
Ma x
Un it
dRONdTM
dRONdVM
dRONdTL
dRONdVL
dRONdTH
dRONdVH
0
0
0
0
0
0
1.5
0.15
1.5
% /°C
% /mV
% /°C
0.15
1.5
% /mV
% /°C
0.15
% /mV
Ou t p u t Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
The DRAM uses both single-ended and differential output drivers. The single-ended
output driver is summarized in Table 45 while the differential output driver is summa-
rized in Table 46 on page 59.
Ta b le 45:
Sin g le -En d e d Ou t p u t Drive r Ch a ra ct e rist ics
All voltages are referenced to Vss
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s No t e s
Output leakage current: DQ are disabled;
IOZ
–5
+5
µA
1
0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH
Output slew rate: Single-ended; For rising and falling
edges, measure between VOL(AC) = VREF - 0.1 × VDDQ and
VOH(AC) = VREF + 0.1 × VDDQ
SRQSE
2.5
5
V/ns
1, 2, 3
Single-ended DC high-level output voltage
Single-ended DC mid-point level output voltage
Single-ended DC low-level output voltage
Single-ended AC high-level output voltage
Single-ended AC low-level output voltage
Delta RON between pull-up and pull-down for DQ/DQS
Test load for AC timing and output slew rates
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
MMPUPD
0.8 × VDDQ
0.5 × VDDQ
0.2 × VDDQ
V
V
V
V
V
%
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3, 5
1, 2, 3, 5
1, 6
VTT + 0.1 × VDDQ
VTT - 0.1 × VDDQ
–10
+10
Output to VTT (VDDQ/2) via 25Ω resistor
3
Notes: 1. RZQ of 240Ω (±1 percent) with RZQ/7 enabled (default 34Ω driver) and is applicable after
proper ZQ calibration has been performed at a stable temperature and voltage
(VDDQ = VDD, VSSQ = VSS).
2. VTT = VDDQ/2.
3. See Figure 32 on page 60 for the test load configuration.
4. See Table 35 on page 55 for IV curve linearity. Do not use AC test load.
5. See Table 47 on page 61 for output slew rate.
6. See Table 35 on page 55 for additional information.
7. See Figure 30 on page 59 for an example of a single-ended output signal.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
Ta b le 46:
Diffe re n t ia l Ou t p u t Drive r Ch a ra ct e rist ics
All voltages are referenced to Vss
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s No t e s
Output leakage current: DQ are disabled;
IOZ
–5
+5
µA
1
0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH
Output slew rate: Differential; For rising and falling
edges, measure between VOLDIFF(AC) = –0.2 × VDDQ
and VOHDIFF(AC) = +0.2 × VDDQ
SRQDIFF
5
10
V/ns
1
Output differential cross-point voltage
VOX(AC)
VOHDIFF(AC)
VOLDIFF(AC)
MMPUPD
VREF - 100
VREF + 100
mV
V
1, 2, 3
1, 4
1, 4
1, 5
3
Differential high-level output voltage
+0.2 × VDDQ
–0.2 × VDDQ
Differential low-level output voltage
V
Delta RON between pull-up and pull-down for DQ/DQS
Test load for AC timing and output slew rates
–10
+10
%
Output to VTT (VDDQ/2) via 25Ω resistor
Notes: 1. RZQ of 240Ω (±1 percent) with RZQ/7 enabled (default 34Ω driver) and is applicable after
proper ZQ calibration has been performed at a stable temperature and voltage
(VDDQ = VDD, VSSQ = VSS).
2. VREF = VDDQ/2.
3. See Figure 32 on page 60 for the test load configuration.
4. See Table 48 on page 62 for the output slew rate.
5. See Table 35 on page 55 for additional information.
6. See Figure 31 on page 60 for an example of a differential output signal.
Fig u re 30: DQ Ou t p u t Sig n a l
MAX output
VOH(AC)
VOL(AC)
MIN output
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1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
Fig u re 31: Diffe re n t ia l Ou t p u t Sig n a l
MAX output
VOH(DIFF)
VOX(AC) MAX
X
X
X
VOX(AC) MIN
X
VOL(DIFF)
MIN output
Re fe re n ce Ou t p u t Lo a d
Figure 32 on page 60 represents the effective reference load of 25Ω used in defining the
relevant device AC timing parameters (except ODT reference timing) as well as the
output slew rate measurements. It is not intended to be a precise representation of a
particular system environment or a depiction of the actual load presented by a produc-
tion tester. System designers should use IBIS or other simulation tools to correlate the
timing reference load to a system environment.
Fig u re 32: Re fe re n ce Ou t p u t Lo a d fo r AC Tim in g a n d Ou t p u t Sle w Ra t e
VDDQ/2
VREF
DUT
DQ
DQS
RTT = 25Ω
VTT = VDDQ/2
DQS#
Timing reference point
RZQ = 240Ω
ZQ
VSS
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1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
Sle w Ra t e De fin it io n s fo r Sin g le -En d e d Ou t p u t Sig n a ls
The single-ended output driver is summarized in Table 45 on page 58. With the refer-
ence load for timing measurements, the output slew rate for falling and rising edges is
defined and measured between VOL(AC) and VOH(AC) for single-ended signals, as shown
in Table 47 and Figure 33.
Ta b le 47:
Sin g le -En d e d Ou t p u t Sle w Ra t e De fin it io n
Sin g le -En d e d Ou t p u t
Sle w Ra t e s
(Lin e a r Sig n a ls)
Me a su re d
Fro m
Ou t p u t
Ed g e
To
Ca lcu la t io n
DQ
Rising
VOL(AC)
VOH(AC)
VOH(AC) - VOL(AC)
ΔTRSE
Falling
VOH(AC)
VOL(AC)
VOH(AC) - VOL(AC)
ΔTFSE
Fig u re 33: No m in a l Sle w Ra t e De fin it io n fo r Sin g le -En d e d Ou t p u t Sig n a ls
ΔTRSE
VOH(AC)
VTT
VOL(AC)
ΔTFSE
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1Gb : x4, x8, x16 DDR3 SDRAM
Ou t p u t Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
Sle w Ra t e De fin it io n s fo r Diffe re n t ia l Ou t p u t Sig n a ls
The differential output driver is summarized in Table 46 on page 59. With the reference
load for timing measurements, the output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for differential signals, as shown in
Table 48 and Figure 34.
Ta b le 48:
Diffe re n t ia l Ou t p u t Sle w Ra t e De fin it io n
Diffe re n t ia l Ou t p u t Sle w
Ra t e s
(Lin e a r Sig n a ls)
Me a su re d
Ou t p u t
Ed g e
Fro m
To
Ca lcu la t io n
DQS, DQS#
Rising
VOLDIFF(AC)
VOHDIFF(AC)
VOHDIFF(AC) - VOLDIFF(AC)
ΔTRDIFF
Falling
VOHDIFF(AC)
VOLDIFF(AC)
VOHDIFF(AC) - VOLDIFF(AC)
ΔTFDIFF
Fig u re 34: No m in a l Diffe re n t ia l Ou t p u t Sle w Ra t e De fin it io n fo r DQS, DQS#
ΔTRDIFF
VOH(DIFF)AC
0
VOL(DIFF)AC
ΔTFDIFF
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
Sp e e d Bin Ta b le s
Ta b le 49:
DDR3-800 Sp e e d Bin s
DDR3-800 Sp e e d Bin
CL-t RCD-t RP
-25E
-25
5-5-5
6-6-6
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Un it s
No t e s
ACTIVATE to internal READ or WRITE delay
time
tRCD
12.5
–
15
–
ns
PRECHARGE command period
tRP
tRC
12.5
50
–
–
15
–
–
ns
ns
ACTIVATE-to-ACTIVATE or REFRESH
command period
52.5
t
t
ACTIVATE-to-PRECHARGE command period
tRAS
tCK (AVG)
tCK (AVG)
37.5
2.5
9 × REFI
3.3
37.5
9 × REFI
ns
ns
1
2, 3
2
CL = 5
CWL = 5
CWL = 5
Reserved
2.5
CL = 6
2.5
3.3
3.3
ns
Supported CL settings
Supported CWL settings
5, 6
6
5
CK
CK
5
Notes: 1. tREFI depends on TOPER
.
t
t
2. The CL and CWL settings result in CK requirements. When making a selection of CK, both
CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
Ta b le 50:
DDR3-1066 Sp e e d Bin s
DDR3-1066 Sp e e d Bin
CL-t RCD-t RP
-187E
7-7-7
-187
8-8-8
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Un it s
No t e s
ACTIVATE to internal READ or WRITE
delay time
tRCD
13.125
13.125
50.625
37.5
–
15
–
ns
PRECHARGE command period
tRP
tRC
–
–
15
–
–
ns
ns
ns
ACTIVATE-to-ACTIVATE or REFRESH
command period
52.5
37.5
t
t
ACTIVATE-to-PRECHARGE command
period
tRAS
9 × REFI
9 × REFI
1
CL = 5
CL = 6
CL = 7
CL = 8
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
Reserved
Reserved
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
2, 3
3
Reserved
Reserved
2.5
3.3
2.5
3.3
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2, 3
3
1.875
<2.5
2, 3
3
Reserved
1.875
<2.5
1.875
<2.5
2
Supported CL settings
Supported CWL settings
6, 7, 8
5, 6
6, 8
5, 6
Notes: 1. tREFI depends on TOPER
.
t
t
2. The CL and CWL settings result in CK requirements. When making a selection of CK, both
CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
Ta b le 51:
DDR3-1333 Sp e e d Bin s
DDR3-1333 Sp e e d Bin
CL-t RCD-t RP
-15F
-15E
-15
8-8-8
9-9-9
10-10-10
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Min
Ma x
Un it s No t e s
ACTIVATE to internal READ or
WRITE delay time
tRCD
12
–
13.5
–
15
–
ns
PRECHARGE command period
tRP
tRC
12
48
–
–
13.5
49.5
–
–
15
51
–
–
ns
ns
ACTIVATE-to-ACTIVATE or
REFRESH command period
t
t
t
ACTIVATE-to-PRECHARGE
command period
tRAS
36
9 × REFI
36
9 × REFI
36
9 × REFI ns
1
CL = 5
CWL = 5
CWL = 6, 7 tCK (AVG)
tCK (AVG)
2.5
3.3
Reserved
Reserved
2.5 3.3
Reserved
Reserved
2.5 3.3
Reserved
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2, 3
3
Reserved
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5, 6 tCK (AVG)
CWL = 7
tCK (AVG)
CWL = 5, 6 tCK (AVG)
CWL = 7
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG) 1.875
tCK (AVG)
tCK (AVG)
tCK (AVG) 1.875
tCK (AVG)
2.5
3.3
2
Reserved
Reserved
Reserved
Reserved
2, 3
3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CL = 7
CL = 8
CL = 9
3
<2.5
Reserved
Reserved
1.875
<2.5
2, 3
2, 3
3
Reserved
Reserved
<2.5
1.875
<2.5
1.875
<2.5
2
1.5
<1.875
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2, 3
3
Reserved
1.5
<1.875
1.5
Reserved
1.5 <1.875
<1.875
2, 3
3
CL = 10
Reserved
1.5
<1.875
1.5
<1.875
ns
2
Supported CL settings
5, 6, 7, 8, 9, 10
5, 6, 7
6, 7, 8, 9, 10
5, 6, 7
6, 8, 10
5, 6, 7
CK
Supported CWL settings
CK
Notes: 1. tREFI depends on TOPER
.
t
t
2. The CL and CWL settings result in CK requirements. When making a selection of CK, both
CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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65
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
Ta b le 52:
DDR3-1600 Sp e e d Bin s
DDR3-1600 Sp e e d Bin
CL-t RCD-t RP
-125F
9-9-9
-125E
-125
10-10-10
11-11-11
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Min
Ma x
Un it s
No t e s
ACTIVATE to internal READ
or WRITE delay time
tRCD
11.25
11.25
46.25
35
–
12.5
12.5
47.5
35
–
13.75
–
ns
PRECHARGE command
period
tRP
tRC
–
–
–
–
13.75
48.75
35
–
–
ns
ns
ns
ACTIVATE-to-ACTIVATE or
REFRESH command period
t
t
t
ACTIVATE-to-PRECHARGE
command period
tRAS
9 × REFI
9 × REFI
9 × REFI
1
CL = 5
CWL = 5
CWL = 6, 7, 8
CWL = 5
CWL = 6
CWL = 7, 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 5, 6, 7
CWL = 8
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
2.5
3.3
2.5
3.3
Reserved
Reserved
2.5 3.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2, 3
3
Reserved
Reserved
CL = 6
2.5
3.3
2.5
3.3
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2, 3
3
Reserved
Reserved
Reserved
Reserved
CL = 7
CL = 8
3
1.875
<2.5
1.875
<2.5
2, 3
2, 3
3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
1.875
1.5
<2.5
1.875
<2.5
1.875
<2.5
2
<1.875
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2, 3
2, 3
3
Reserved
Reserved
CL = 9
1.5
<1.875
<1.5
1.5
<1.875
2, 3
2, 3
3
1.25
Reserved
Reserved
CL = 10
CL = 11
Reserved
1.5
<1.875
<1.5
1.5
<1.875
<1.5
1.5
<1.875
2
1.25
1.25
Reserved
Reserved
2, 3
3
Reserved
Reserved
1.25
<1.5
1.25
<1.5
1.25
<1.5
ns
2
Supported CL settings
Supported CWL settings
5, 6, 7, 8, 9, 10, 11 5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8 5, 6, 7, 8
6, 8, 10, 11
5, 6, 7, 8
CK
CK
Notes: 1. tREFI depends on TOPER
.
t
t
2. The CL and CWL settings result in CK requirements. When making a selection of CK, both
CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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66
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Ta b le 53:
Ele ct rica l Ch a ra ct e rist ics a n d AC Op e ra t in g Co n d it io n s (Sh e e t 1 o f 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Min
Ma x
Min
Ma x
Un it s No t e s
Clo ck Tim in g
Clock period average: TC = 0°C to 85°C
tCKDLL_DIS
8
8
7,800
3,900
8
8
7,800
3,900
8
8
7,800
3,900
8
8
7,800
3,900
ns
ns
9
DLL disable mode
TC = >85°C to 95°C
t
Clock period average: DLL enable mode
High pulse width average
tCK (AVG)
tCH (AVG)
tCL (AVG)
tJITPER
See “Speed Bin Tables” on page 63 for CK range allowed
ns
10, 11
12
0.47
0.47
–100
–90
0.53
0.53
100
90
0.47
0.47
–90
0.53
0.53
90
0.47
0.47
–80
0.53
0.53
80
0.47
0.47
–70
0.53
0.53
70
CK
CK
ps
Low pulse width average
12
Clock period jitter
DLL locked
DLL locking
13
tJITPER, LCK
–80
80
–70
70
–60
60
ps
13
t
t
t
t
Clock absolute period
tCK(ABS) MIN = CK (AVG) MIN + JITPER MIN; MAX = CK (AVG) MAX + JITPER MAX
ps
Clock absolute high pulse width
tCH (ABS)
0.43
–
0.43
–
0.43
–
0.43
–
tCK
(AVG)
tCK
14
15
Clock absolute low pulse width
tCL (ABS)
0.43
–
0.43
–
0.43
–
0.43
–
(AVG)
Cycle-to-cycle jitter
DLL locked
DLL locking
2 cycles
tJITCC
tJITCC, LCK
tERR2PER
tERR3PER
tERR4PER
tERR5PER
tERR6PER
tERR7PER
tERR8PER
tERR9PER
tERR10PER
tERR11PER
tERR12PER
tERRnPER
200
180
180
160
160
140
140
120
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
16
16
17
17
17
17
17
17
17
17
17
17
17
17
Cumulative error
across
–147
–175
–194
–209
–222
–232
–241
–249
–257
–263
–269
147
175
194
209
222
232
241
249
257
263
269
–132
–157
–175
–188
–200
–209
–217
–224
–231
–237
–242
132
157
175
188
200
209
217
224
231
237
242
–118
–140
–155
–168
–177
–186
–193
–200
–205
–210
–215
118
140
155
168
177
186
193
200
205
210
215
–103
–122
–136
–147
–155
–163
–169
–175
–180
–184
–188
103
122
136
147
155
163
169
175
180
184
188
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
t
n = 13, 14 . . . 49, 50
cycles
tERRnPER MIN = (1 + 0.68ln[n]) × JITPER MIN
tERRnPER MAX = (1 + 0.68ln[n]) × JITPER MAX
t
Ta b le 53:
Pa ra m e t e r
Ele ct rica l Ch a ra ct e rist ics a n d AC Op e ra t in g Co n d it io n s (Sh e e t 2 o f 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
DDR3-800
Min Ma x
DQ In p u t Tim in g
DDR3-1066
DDR3-1333
DDR3-1600
Sym b o l
Min
Ma x
Min
Ma x
Min
Ma x
Un it s No t e s
Data setup time to
DQS, DQS#
Base (specification)
VREF @ 1 V/ns
tDS
AC175
75
250
150
250
–
–
–
–
–
–
25
200
100
200
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ps
ps
ps
ps
ps
18, 19
19, 20
18,19
19, 20
Data hold time from Base (specification)
DQS, DQS#
tDH
AC175
–
–
VREF @ 1 V/ns
–
–
Data setup time to
DQS, DQS#
Base (specification)
tDS
AC150
30
10
18,
19, 21
VREF @ 1 V/ns
–
–
–
–
–
–
–
–
–
–
–
–
180
65
–
–
–
–
160
45
–
–
–
–
ps
ps
ps
ps
19,
20,21
Data hold time from Base (specification)
DQS, DQS#
tDH
AC150
18,
19, 21
VREF @ 1 V/ns
–
–
165
400
145
360
19,
20, 21
Minimum data pulse width
tDIPW
600
490
42
DQ Ou t p u t Tim in g
DQS, DQS# to DQ skew, per access
tDQSQ
tQH
–
200
–
–
150
–
–
125
–
–
100
–
ps
tCK
DQ output hold time from DQS, DQS#
0.38
0.38
0.38
0.38
22
(AVG)
DQ Low-Z time from CK, CK#
DQ High-Z time from CK, CK#
tLZ (DQ)
tHZ (DQ)
–800
–
400
400
–600
–
300
300
–500
–
250
250
–450
–
225
225
ps
ps
23, 24
23, 24
DQ St ro b e In p u t Tim in g
DQS, DQS# rising to CK, CK# rising
tDQSS
tDQSL
tDQSH
tDSS
tDSH
tWPRE
tWPST
–0.25
0.45
0.45
0.2
0.25
0.55
0.55
–
–0.25
0.45
0.45
0.2
0.25
0.55
0.55
–
–0.25
0.45
0.45
0.2
0.25
0.55
0.55
–
–0.27
0.45
0.45
0.18
0.18
0.9
0.27
0.55
0.55
–
CK
CK
CK
CK
CK
CK
CK
26
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# falling setup to CK, CK# rising
DQS, DQS# falling hold from CK, CK# rising
DQS, DQS# differential WRITE preamble
DQS, DQS# differential WRITE postamble
26
26
0.2
–
0.2
–
0.2
–
–
0.9
–
0.9
–
0.9
–
–
0.3
–
0.3
–
0.3
–
0.3
–
Ta b le 53:
Ele ct rica l Ch a ra ct e rist ics a n d AC Op e ra t in g Co n d it io n s (Sh e e t 3 o f 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
DDR3-800
Min Ma x
DQ St ro b e Ou t p u t Tim in g
DDR3-1066
DDR3-1333
DDR3-1600
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Min
Ma x
Un it s No t e s
DQS, DQS# rising to/from rising CK, CK#
tDQSCK
tDQSCK
–400
1
400
10
–300
1
300
10
–255
1
255
10
–225
1
225
10
ps
ns
24
27
DQS, DQS# rising to/from rising CK, CK# when
DLL is disabled
DLL_DIS
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# Low-Z time (RL - 1)
tQSH
tQSL
tLZ (DQS)
tHZ (DQS)
tRPRE
0.38
0.38
–800
–
–
–
0.38
0.38
–600
–
–
–
0.40
0.40
–500
–
–
–
0.40
0.40
–450
–
–
–
CK
CK
ps
22
22
400
300
250
225
23, 24
23, 24
24, 25
24, 28
DQS, DQS# High-Z time (RL + BL/2)
DQS, DQS# differential READ preamble
DQS, DQS# differential READ postamble
400
300
250
225
ps
0.9
Note 25
Note 28
0.9
Note 25
Note 28
0.9
Note 25
Note 28
0.9
Note 25
Note 28
CK
CK
tRPST
0.3
0.3
0.3
0.3
Ta b le 53:
Ele ct rica l Ch a ra ct e rist ics a n d AC Op e ra t in g Co n d it io n s (Sh e e t 4 o f 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
DDR3-800
Min Ma x
Co m m a n d a n d Ad d re ss Tim in g
DDR3-1066
DDR3-1333
DDR3-1600
Pa ra m e t e r
Sym b o l
Min Ma x
Min
Ma x
Min
Ma x
Un it s No t e s
DLL locking time
tDLLK
tIS
512
200
375
275
375
–
–
–
–
–
–
–
512
125
300
200
300
–
–
–
–
–
–
–
512
65
–
–
–
–
–
–
512
45
–
–
–
–
–
–
CK
ps
ps
ps
ps
ps
29
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
VREF @ 1 V/ns
30, 31
20, 31
30, 31
20, 31
AC175
240
140
240
190
220
120
220
170
CTRL, CMD, ADDR
hold from CK,CK#
Base (specification)
VREF @ 1 V/ns
tIH
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
tIS
AC150
21,
30, 31
VREF @ 1 V/ns
–
–
–
–
–
–
340
620
–
–
320
560
–
–
ps
20,
21, 31
Minimum CTRL, CMD, ADDR pulse width
ACTIVATE to internal READ or WRITE delay
PRECHARGE command period
tIPW
tRCD
tRP
tRAS
tRC
900
780
ps
ns
ns
ns
ns
CK
42
32
t
See “Speed Bin Tables” on page 63 for RCD
t
See “Speed Bin Tables” on page 63 for RP
32
t
ACTIVATE-to-PRECHARGE command period
ACTIVATE-to-ACTIVATE command period
See “Speed Bin Tables” on page 63 for RAS
32, 33
32
t
See “Speed Bin Tables” on page 63 for RC
ACTIVATE-to-
ACTIVATE minimum
command period
1KB page size
tRRD
MIN = greater of MIN = greater of MIN = greater of MIN = greater of
4CK or 10ns 4CK or 7.5ns 4CK or 6ns 4CK or 6ns
MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns
32
2KB page size
CK
ns
ns
ns
32
32
32
Four ACTIVATE windows for 1KB page size
Four ACTIVATE windows for 2KB page size
Write recovery time
tFAW
40
50
–
–
37.5
50
–
–
30
45
–
–
30
40
–
–
tWR
MIN = 15ns; MAX = n/a
32,
33, 34
Delay from start of internal WRITE transaction
to internal READ command
tWTR
MIN = greater of 4CK or 7.5ns; MAX = n/a
CK
32, 35
READ-to-PRECHARGE time
tRTP
tCCD
tDAL
MIN = greater of 4CK or 7.5ns; MAX = n/a
MIN = 4CK; MAX = n/a
CK
CK
CK
32, 33
CAS#-to-CAS# command delay
t
Auto precharge write recovery + precharge
time
MIN = WR + RP/ tCK (AVG); MAX = n/a
MODE REGISTER SET command cycle time
MODE REGISTER SET command update delay
tMRD
tMOD
tMPRR
MIN = 4CK; MAX = n/a
MIN = greater of 12CK or 15ns; MAX = n/a
MIN = 1CK; MAX = n/a
CK
CK
CK
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register
exit
Ta b le 53:
Ele ct rica l Ch a ra ct e rist ics a n d AC Op e ra t in g Co n d it io n s (Sh e e t 5 o f 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
DDR3-800
Min Ma x
Ca lib ra t io n Tim in g
DDR3-1066
DDR3-1333
DDR3-1600
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Min
Ma x
Un it s No t e s
ZQCL command: Long POWER-UP and RESET
tZQINIT
512
–
512
–
512
–
512
–
CK
calibration time
operation
Normal operation
tZQOPER
tZQCS
256
64
–
–
256
64
–
–
256
64
–
–
256
64
–
–
CK
CK
ZQCS command: Short calibration time
In it ia liza t io n a n d Re se t Tim in g
t
Exit reset from CKE HIGH to a valid command
tXPR
tVDDPR
MIN = greater of 5CK or RFC + 10ns; MAX = n/a
MIN = n/a; MAX = 200
CK
ms
Begin power supply ramp to power supplies
stable
RESET# LOW to power supplies stable
RESET# LOW to I/O and RTT High-Z
tRPS
tIOz
MIN = 0; MAX = 200
MIN = n/a; MAX = 20
ms
ns
36
Re fre sh Tim in g
t
REFRESH-to-ACTIVATE or REFRESH command
period
tRFC
–
MIN = 110; MAX = 9 × REFI (REFRESH-to-REFRESH command period)
ns
Maximum refresh
period
TC = 0°C to 85°C
TC = >85°C to 95°C
TC = 0°C to 85°C
TC = >85°C to 95°C
64 (1X)
32 (2X)
ms
ms
µs
37
37
37
37
Maximum average
periodic refresh
tREFI
7.8 (64ms/8,192)
3.9 (32ms/8,192)
µs
Se lf Re fre sh Tim in g
t
Exit self refresh to commands not requiring a
locked DLL
tXS
MIN = greater of 5CK or RFC + 10ns; MAX = n/a
CK
CK
CK
CK
CK
t
Exit self refresh to commands requiring a
locked DLL
tXSDLL
tCKESR
tCKSRE
tCKSRX
MIN = DLLK (MIN); MAX = n/a
29
t
Minimum CKE low pulse width for self refresh
entry to self refresh exit timing
MIN = CKE (MIN) + CK; MAX = n/a
Valid clocks after self refresh entry or power-
down entry
MIN = greater of 5CK or 10ns; MAX = n/a
MIN = greater of 5CK or 10ns; MAX = n/a
Valid clocks before self refresh exit, power-
down exit, or reset exit
Ta b le 53:
Ele ct rica l Ch a ra ct e rist ics a n d AC Op e ra t in g Co n d it io n s (Sh e e t 6 o f 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
DDR3-800
Min Ma x
Po w e r-Do w n Tim in g
tCKE (MIN) Greater of 3CK or Greater of 3CK or Greater of 3CK or Greater of 3CK or
DDR3-1066
DDR3-1333
DDR3-1600
Pa ra m e t e r
Sym b o l
Min Ma x
Min Ma x
Min Ma x
Un it s No t e s
CKE MIN pulse width
CK
7.5ns
5.625ns
5.625ns
5ns
Command pass disable delay
tCPDED
tPD
tANPD
MIN = 1; MAX = n/a
CK
CK
CK
t
t
Power-down entry to power-down exit timing
MIN = CKE (MIN); MAX = 9 × REFI
WL - 1CK
Begin power-down period prior to CKE
registered HIGH
t
t
Power-down entry period: ODT either
synchronous or asynchronous
PDE
PDX
Greater of ANPD or RFC - REFRESH command to CKE LOW time
CK
CK
t
Power-down exit period: ODT either
synchronous or asynchronous
tANPD + XPDLL
Po w e r-Do w n En t ry Min im u m Tim in g
ACTIVATE command to power-down entry
tACTPDEN
tPRPDEN
MIN = 1
MIN = 1
CK
CK
PRECHARGE/PRECHARGE ALL command to
power-down entry
REFRESH command to power-down entry
MRS command to power-down entry
tREFPDEN
tMRSPDEN
tRDPDEN
MIN = 1
CK
CK
CK
38
t
MIN = MOD (MIN)
READ/READ with auto precharge command to
power-down entry
MIN = RL + 4 + 1
t
WRITE command to
power-down entry
BL8 (OTF, MRS)
BC4OTF
tWRPDEN
MIN = WL + 4 + WR/ tCK (AVG)
CK
t
BC4MRS
tWRPDEN
tWRAPDEN
MIN = WL + 2 + WR/ tCK (AVG)
CK
CK
WRITE with auto
precharge command BC4OTF
BL8 (OTF, MRS)
MIN = WL + 4 + WR + 1
tWRAPDEN
MIN = WL + 2 + WR + 1
CK
to power-down entry
BC4MRS
Po w e r-Do w n Exit Tim in g
DLL on, any valid command, or DLL off to
commands not requiring locked DLL
tXP
MIN = greater of 3CK or 7.5ns;
MAX = n/a
MIN = greater of 3CK or 6ns;
MAX = n/a
CK
CK
Precharge power-down with DLL off to
tXPDLL
MIN = greater of 10CK or 24ns; MAX = n/a
29
commands requiring a locked DLL
Ta b le 53:
Pa ra m e t e r
Ele ct rica l Ch a ra ct e rist ics a n d AC Op e ra t in g Co n d it io n s (Sh e e t 7 o f 7)
Notes: 1–8 apply to the entire table; notes appear on page 74
DDR3-800
DDR3-1066
Min Ma x
ODT Tim in g
DDR3-1333
DDR3-1600
Sym b o l
Min
Ma x
Min
Ma x
Min
Ma x
Un it s No t e s
RTT synchronous turn-on delay
ODTL on
ODTL off
tAON
tAOF
tAONPD
CWL + AL - 2CK
CWL + AL - 2CK
CK
CK
ps
39
41
RTT synchronous turn-off delay
RTT turn-on from ODTL on reference
RTT turn-off from ODTL off reference
–400
0.3
400
0.7
–300
0.3
300
0.7
–250
0.3
250
0.7
–225
0.3
225
0.7
24, 39
40, 41
39
CK
ns
Asynchronous RTT turn-on delay
(power-down with DLL off)
MIN = 1; MAX = 9
MIN = 1; MAX = 9
MIN = 6; MAX = n/a
MIN = 4; MAX = n/a
Asynchronous RTT turn-off delay
(power-down with DLL off)
tAOFPD
ODTH8
ODTH4
ns
41
ODT HIGH time with WRITE command and
BL8
CK
CK
ODT HIGH time without WRITE command or
with WRITE command and BC4
Dyn a m ic ODT Tim in g
RTT_NOM-to-RTT_WR change skew
RTT_WR-to-RTT_NOM change skew - BC4
RTT_WR-to-RTT_NOM change skew - BL8
RTT dynamic change skew
ODTLCNW
ODTLCNW4
ODTLCNW8
tADC
WL - 2CK
CK
CK
CK
CK
4CK + ODTL off
6CK + ODTL off
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
40
Writ e Le ve lin g Tim in g
First DQS, DQS# rising edge
DQS, DQS# delay
tWLMRD
tWLDQSEN
tWLS
40
25
–
–
–
40
25
–
–
–
40
25
–
–
–
40
25
–
–
–
CK
CK
ps
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
325
245
195
163
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
325
–
245
–
195
–
163
–
ps
Write leveling output delay
Write leveling output error
tWLO
tWLOE
0
0
9
2
0
0
9
2
0
0
9
2
0
0
7.5
2
ns
ns
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
No t e s
1. Parameters are applicable with 0°C ≤ T ≤ +95°C and VDD/ VDDQ = +1.5V ±0.075V.
C
2. All voltages are referenced to VSS.
3. Output timings are only valid for RON output buffer selection.
34
t
t
4. Unit “ CK (AVG)” represents the actual CK (AVG) of the input clock under operation.
Unit “CK” represents one clock cycle of the input clock, counting the actual clock
edges.
5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test envi-
t
t
t
t
ronment, but input timing is still referenced to VREF (except IS, IH, DS, and DH use
the AC/ DC trip points and CK, CK# and DQS, DQS# use their crossing points). The
minimum slew rate for the input signals used to test the device is 1 V/ ns for single-
ended inputs and 2 V/ ns for differential inputs in the range between VIL(AC) and
VIH(AC).
t
6. All timings that use time-based values (ns, µs, ms) should use CK (AVG) to determine
t
the correct number of clocks (Table 53 on page 67 uses “CK” or “ CK [AVG]” inter-
changeably). In the case of noninteger results, all minimum limits are to be rounded
up to the nearest whole integer, and all maximum limits are to be rounded down to
the nearest whole integer.
7. The use of “strobe” or “DQSDIFF” refers to the DQS and DQS# differential crossing
point when DQS is the rising edge. The use of “clock” or “CK” refers to the CK and
CK# differential crossing point when CK is the rising edge.
8. This output load is used for all AC timing (except ODT reference timing) and slew
rates. The actual test load may be different. The output signal voltage reference point
is VDDQ/ 2 for single-ended signals and the crossing point for differential signals (see
Figure 32 on page 60).
9. When operating in DLL disable mode, Micron does not warrant compliance with nor-
mal mode timings or functionality.
t
10. The clock’s CK (AVG) is the average clock over any 200 consecutive clocks and
t
CK(AVG) MIN is the smallest clock rate allowed, with the exception of a deviation
due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
11. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz
t
with an additional 1 percent of CK (AVG) as a long-term jitter component; however,
the spread-spectrum may not use a clock rate below tCK (AVG) MIN.
t
t
12. The clock’s CH (AVG) and CL (AVG) are the average half clock period over any 200
consecutive clocks and is the smallest clock half period allowed, with the exception of
a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed
values specified and must be of a random Gaussian distribution in nature.
13. The period jitter (tJITPER) is the maximum deviation in the clock period from the aver-
age or nominal clock. It is allowed in either the positive or negative direction.
t
14. CH(ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
t
15. CL(ABS) is the absolute instantaneous clock low pulse width as measured from one
falling edge to the following rising edge.
16. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one
cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the
DLL locking time.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
74
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
17. The cumulative jitter error (tERRnPER), where n is the number of clocks between 2 and
50, is the amount of clock time allowed to accumulate consecutively away from the
average clock over n number of clock cycles.
t
t
18. DS (base) and DH (base) values are for a single-ended 1 V/ ns DQ slew rate and
2 V/ ns differential DQS, DQS# slew rate.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth)
transition edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ ns. These values, with a slew
rate of 1 V/ ns, are for reference only.
t
21. Special setup and hold derating and different VAC numbers apply when using 150mV
AC threshold.
22. When the device is operated with input clock jitter, this parameter needs to be der-
t
ated by the actual JITPER of the input clock (output deratings are relative to the
SDRAM input clock).
23. Single-ended signal parameter.
24. The DRAM output timing is aligned to the nominal or average clock. Most output
parameters must be derated by the actual jitter error when input clock jitter is
present, even when within specification. This results in each parameter becoming
larger. The following parameters are required to be derated by subtracting
t
t
t
t
t
ERR
(MAX): DQSCK (MIN), LZ (DQS) MIN, LZ (DQ) MIN, and AON (MIN).
10PER
t
The following parameters are required to be derated by subtracting ERR
(MIN):
10PER
t
t
t
t
t
DQSCK (MAX), HZ (MAX), LZ (DQS) MAX, LZ (DQ) MAX, and AON (MAX). The
t
t
t
parameter RPRE (MIN) is derated by subtracting JITPER (MAX), while RPRE (MAX) is
derated by subtracting JITPER (MIN).
25. The maximum preamble is bound by LZDQS (MAX).
t
t
26. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its
respective clock signal (CK, CK#) crossing. The specification values are not affected by
the amount of clock jitter applied, as these are relative to the clock signal crossing.
These parameters should be met whether clock jitter is present.
t
27. The DQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command.
t
28. The maximum postamble is bound by HZDQS (MAX).
29. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT
t
commands. In addition, after any change of latency XPDLL, timing must be met.
t
t
30. IS (base) and IH (base) values are for a single-ended 1 V/ ns control/ command/
address slew rate and 2 V/ ns CK, CK# differential slew rate.
31. These parameters are measured from a command/ address signal transition edge to
its respective clock (CK, CK#) signal crossing. The specification values are not affected
by the amount of clock jitter applied as the setup and hold times are relative to the
clock signal crossing that latches the command/ address. These parameters should be
met whether clock jitter is present.
t
32. For these parameters, the DDR3 SDRAM device supports nPARAM (nCK) =
t
t
RU( PARAM [ns]/ CK[AVG] [ns]), assuming all input clock jitter specifications are sat-
t
t
t
isfied. For example, the device will support nRP (nCK) = RU( RP/ CK[AVG]) if all
input clock jitter specifications are met. This means for DDR3-800 6-6-6, of which
t
t
t
t
RP = 15ns, the device will support nRP = RU( RP/ CK[AVG]) = 6 as long as the input
clock jitter specifications are met. That is, the PRECHARGE command at T0 and the
ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to
input clock jitter.
33. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the
t
internal PRECHARGE command until RAS (MIN) has been satisfied.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
75
©2006 Micron Technology, Inc. All rights reserved.
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
34. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for WR.
35. The start of the write recovery time is defined as follows:
– For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
– For BC4 (OTF): Rising clock edge four clock cycles after WL
– For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
36. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in
excessive current, depending on bus activity.
37. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. How-
ever, nine REFRESH commands must be asserted at least once every 70.3µs.
38. Although CKE is allowed to be registered LOW after a REFRESH command when
t
REFPDEN (MIN) is satisfied, there are cases where additional time such as
XPDLL (MIN) is required.
t
39. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins
to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The
ODT reference load is shown in Figure 24 on page 49.
t
t
40. Half-clock output parameters must be derated by the actual ERR
and JITDTY
10PER
when input clock jitter is present. This results in each parameter becoming larger.
t
t
The parameters ADC (MIN) and AOF (MIN) are each required to be derated by sub-
t
t
t
tracting both ERR
AOF (MAX) are required to be derated by subtracting both ERR
JITDTY (MAX).
(MAX) and JITDTY (MAX). The parameters ADC (MAX) and
10PER
t
t
(MAX) and
10PER
t
41. ODT turn-off time minimum is when the device starts to turn off ODT resistance.
ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT refer-
ence load is shown in Figure 25 on page 51. This output load is used for ODT timings
(see Figure 32 on page 60).
42. Pulse width of a input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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76
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
Co m m a n d a n d Ad d re ss Se t u p , Ho ld , a n d De ra t in g
t
t
The total IS (setup time) and IH (hold time) required is calculated by adding the data
t
t
sheet IS (base) and IH (base) values (see Table 54; values come from Table 53 on
page 67) to the Δ IS and Δ IH derating values (see Table 55 on page 78 and Table 56 on
page 78), respectively. Example: IS (total setup time) = IS (base) + Δ IS. For a valid tran-
sition, the input signal has to remain above/ below VIH(AC)/ VIL(AC) for some time VAC
t
t
t
t
t
t
(see Table 56 on page 78).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached VIH[AC]/ VIL[AC] at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach VIH(AC)/
VIL(AC) (see Figure 17 on page 42 for input signal requirements). For slew rates which fall
between the values listed in Table 56 on page 78 and Table 57 on page 79, the derating
values may be obtained by linear interpolation.
t
Setup ( IS) nominal slew rate for a rising signal is defined as the slew rate between the
t
last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup ( IS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC)
and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the
nominal slew rate line between the shaded “VREF(DC)-to-AC region,” use the nominal
slew rate for derating value (see Figure 35 on page 80). If the actual signal is later than
the nominal slew rate line anywhere between the shaded “VREF(DC)-to-AC region,” the
slew rate of a tangent line to the actual signal from the AC level to the DC level is used for
derating value (see Figure 37 on page 82).
t
Hold ( IH) nominal slew rate for a rising signal is defined as the slew rate between the
t
last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold ( IH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of
VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the
nominal slew rate line between the shaded “DC-to-VREF(DC) region,” use the nominal
slew rate for derating value (see Figure 36 on page 81). If the actual signal is earlier than
the nominal slew rate line anywhere between the shaded “DC-to-VREF(DC) region,” the
slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is
used for derating value (see Figure 38 on page 83).
Ta b le 54:
Co m m a n d a n d Ad d re ss Se t u p a n d Ho ld Va lu e s Re fe re n ce d a t 1 V/n s – AC/DC-Ba se d
Sym b o l
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Un it s
Re fe re n ce
tIS (base)
tIH (base)
tIS (base): AC150
200
275
n/a
125
200
n/a
65
45
ps
ps
ps
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
VIH(AC)/VIL(AC)
140
190
120
170
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
t
Ta b le 55:
DDR3-800, DDR3-1066, DDR3-1333, a n d DDR3-1600 De ra t in g Va lu e s fo r IS/ IH – AC/DC-
Ba se d
AC175 threshold
Δt IS, Δt IH De ra t in g (p s) – AC/DC-Ba se d
AC175 Th re sh o ld : VIH(AC) = VREF(DC) + 175m V, VIL(AC) = VREF(DC) - 175m V
CK, CK# Diffe re n t ia l Sle w Ra t e
CMD/
ADDR
4.0 V/n s
3.0 V/n s
2.0 V/n s
1.8 V/n s
1.6 V/n s
1.4 V/n s
1.2 V/n s
1.0 V/n s
Sle w Ra t e
V/n s
Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IH Δt IH Δt IS Δt IH Δt IS Δt IH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
50
34
88
59
50
34
88
59
50
34
96
67
8
58
42
8
104
75
16
14
10
5
66
50
16
12
6
112
83
74
58
24
20
14
8
120
91
84
68
34
30
24
18
8
128
99
40
38
34
29
23
5
100
84
0
0
0
0
0
0
24
32
50
–2
–4
–2
–4
–2
–4
6
4
22
30
46
–6
–10
–16
–26
–40
–60
–6
–10
–16
–26
–40
–60
–6
–10
–16
–26
–40
–60
2
–2
18
26
40
–11
–17
–35
–62
–11
–17
–35
–62
–11
–17
–35
–62
–3
–9
–27
–54
–8
0
13
21
34
–18
–32
–52
–1
–10
–24
–44
7
–2
15
24
–19
–46
–11
–38
–16
–36
–2
–6
–26
10
–30
–22
–10
t
t
Ta b le 56:
DDR3-1333 a n d DDR3-1600 De ra t in g Va lu e s fo r IS/ IH – AC/DC-Ba se d
AC150 threshold
Δt IS, Δt IH De ra t in g (p s) – AC/DC-Ba se d
AC150 Th re sh o ld : VIH(AC) = VREF(DC) + 150m V, VIL(AC) = VREF(DC) - 150m V
CK, CK# Diffe re n t ia l Sle w Ra t e
CMD/
ADDR
4.0 V/n s
3.0 V/n s
2.0 V/n s
1.8 V/n s
1.6 V/n s
1.4 V/n s
1.2 V/n s
1.0 V/n s
Sle w Ra t e
V/n s
Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IH Δt IH Δt IS Δt IH Δt IS Δt IH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
50
34
75
50
0
50
34
75
50
0
50
34
83
58
8
58
42
8
91
66
16
16
16
16
15
6
66
50
16
12
6
99
74
24
24
24
24
23
14
–1
74
58
24
20
14
8
107
82
32
32
32
32
31
22
7
84
68
34
30
24
18
8
115
90
40
40
40
40
39
30
15
100
84
0
0
0
50
0
–4
0
–4
0
–4
8
4
46
0
–10
–16
–26
–40
–60
0
–10
–16
–26
–40
–60
0
–10
–16
–26
–40
–60
8
–2
40
0
0
0
8
–8
0
34
–1
–10
–25
–1
–10
–25
–1
–10
–25
7
–18
–32
–52
–10
–24
–44
–2
24
–2
–17
–16
–36
–6
–26
10
–9
–10
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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78
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
Ta b le 57:
Min im u m Re q u ire d Tim e VAC Ab o ve VIH(AC) fo r Va lid Tra n sit io n
Below VIL(AC)
Sle w Ra t e (V/n s)
t VAC a t 175m V (p s)
t VAC a t 150m V (p s)
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
75
57
50
38
34
29
22
13
0
175
170
167
163
162
161
159
155
150
150
0
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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79
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
t
Fig u re 35: No m in a l Sle w Ra t e a n d VAC fo r IS (Co m m a n d a n d Ad d re ss – Clo ck)
t
t
t
t
IH
IS
IH
IS
CK
CK#
DQS#
DQS
VDDQ
t
VAC
VIH(AC) MIN
VIH(DC) MIN
VREF to AC
region
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC) MAX
VIL(DC) MAX
VREF to AC
region
t
VAC
VSS
ΔTF
ΔTR
VREF(DC) - VIL(AC) MAX
ΔTF
VIH(AC) MIN - VREF(DC)
ΔTR
Setup slew rate
falling signal
Setup slew rate
rising signal
=
=
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
Fig u re 36: No m in a l Sle w Ra t e fo r IH (Co m m a n d a n d Ad d re ss – Clo ck)
t
t
IS
IH
t
t
IH
IS
CK
CK#
DQS#
DQS
VDDQ
VIH(AC) MIN
VIH(DC) MIN
Nominal
slew rate
DC to VREF
region
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTF
ΔTR
VREF(DC) - VIL(DC) MAX
ΔTR
VIH(DC) MIN - VREF(DC)
ΔTF
Hold slew rate
rising signal
Hold slew rate
falling signal
=
=
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
Fig u re 37: Ta n g e n t Lin e fo r IS (Co m m a n d a n d Ad d re ss – Clo ck)
t
t
t
t
IS
IH
IS
IH
CK
CK#
DQS#
DQS
VDDQ
t
VAC
Nominal
line
VIH(AC) MIN
VIH(DC) MIN
VREF to AC
region
Tangent
line
VREF(DC)
Tangent
line
VIL(DC) MAX
VIL(AC) MAX
VREF to AC
region
Nominal
line
t
VAC
ΔTR
VSS
Tangent line (VIH[DC] MIN - VREF[DC])
ΔTR
Setup slew rate
rising signal
=
=
Tangent line (VREF[DC] - VIL[AC] MAX)
ΔTF
ΔTF
Setup slew rate
falling signal
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
Fig u re 38: Ta n g e n t Lin e fo r IH (Co m m a n d a n d Ad d re ss – Clo ck)
t
t
t
t
IH
IS
IH
IS
CK
CK#
DQS#
DQS
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to VREF
region
Ta n ge n t
line
VREF(DC)
Ta n ge n t
line
DC to VREF
region
Nominal
line
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTR
ΔTR
Tangent line (VREF[DC] - VIL[DC] MAX)
ΔTR
Hold slew rate
rising signal
=
=
Tangent line (VIH[DC] MIN - VREF[DC])
ΔTF
Hold slew rate
falling signal
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
Da t a Se t u p , Ho ld , a n d De ra t in g
t
t
The total DS (setup time) and DH (hold time) required is calculated by adding the data
t
t
sheet DS (base) and DH (base) values (see Table 58; values come from Table 53 on
t
t
page 67) to the Δ DS and Δ DH derating values (see Table 59 on page 85), respectively.
t
t
t
Example: DS (total setup time) = DS (base) + Δ DS. For a valid transition, the input
t
signal has to remain above/ below VIH(AC)/ VIL(AC) for some time VAC (see Table 61 on
page 86).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached VIH[AC]/ VIL[AC]) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach VIH/
VIL(AC). For slew rates which fall between the values listed in Table 59 on page 85, the
derating values may obtained by linear interpolation.
t
Setup ( DS) nominal slew rate for a rising signal is defined as the slew rate between the
t
last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup ( DS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC)
and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the
nominal slew rate line between the shaded “VREF(DC)-to-AC region,” use the nominal
slew rate for derating value (see Figure 39 on page 87). If the actual signal is later than
the nominal slew rate line anywhere between the shaded “VREF(DC)-to-AC region,” the
slew rate of a tangent line to the actual signal from the AC level to the DC level is used for
derating value (see Figure 41 on page 89).
t
Hold ( DH) nominal slew rate for a rising signal is defined as the slew rate between the
t
last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold ( DH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of
VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the
nominal slew rate line between the shaded “DC-to-VREF(DC) region,” use the nominal
slew rate for derating value (see Figure 40 on page 88). If the actual signal is earlier than
the nominal slew rate line anywhere between the shaded “DC-to-VREF(DC) region,” the
slew rate of a tangent line to the actual signal from the “DC-to-VREF(DC) region” is used
for derating value (see Figure 42 on page 90).
Ta b le 58:
Sym b o l
Da t a Se t u p a n d Ho ld Va lu e s a t 1 V/n s (DQS, DQS# a t 2 V/n s) – AC/DC-Ba se d
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Un it s
Re fe re n ce
tDS AC175 (base)
tDH AC175 (base)
tDS AC150 (base)
tDH AC150 (base)
75
150
–
25
100
–
–
–
–
–
ps
ps
ps
ps
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
30
65
10
45
–
–
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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84
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
t
Ta b le 59:
DDR3-800, DDR3-1066, DDR3-1333, a n d DDR3-1600 De ra t in g Va lu e s fo r DS/ DH – AC/DC-
Ba se d
AC175 threshold; shaded cells indicate slew rate combinations not supported
Δt DS, Δt DH De ra t in g (p s) – AC/DC-Ba se d
DQS, DQS# Diffe re n t ia l Sle w Ra t e
4.0 V/n s
3.0 V/n s
2.0 V/n s
1.8 V/n s
1.6 V/n s
1.4 V/n s
1.2 V/n s
1.0 V/n s
DQ Sle w
Ra t e V/n s Δt DS Δt DH Δt DS Δt DH Δt DS Δt DH Δt DS Δt DH Δt DS Δt DH Δt DS Δt DH Δt DS Δt DH Δt DS Δt DH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
50
34
0
88
59
0
50
34
0
88
59
0
50
34
0
67
8
42
8
16
14
10
5
16
12
6
–2
–4
–2
–6
–4
–10
6
4
22
18
13
7
20
14
8
2
–2
–8
26
21
24
18
8
–3
0
29
23
5
34
24
–1
–10
–2
–16
15
–11
–2
–6
–26
10
–30
–22
–10
t
t
Ta b le 60:
DDR3-1333a n d DDR3-1600 De ra t in g Va lu e s fo r DS/ DH – AC/DC-Ba se d
AC150 threshold; shaded cells indicate slew rate combinations not supported
Δt DS, Δt DH De ra t in g (p s) – AC/DC-Ba se d
DQS, DQS# Diffe re n t ia l Sle w Ra t e
CMD/
ADDR
4.0 V/n s
3.0 V/n s
2.0 V/n s
1.8 V/n s
1.6 V/n s
1.4 V/n s
1.2 V/n s
1.0 V/n s
Sle w Ra t e
V/n s
Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IS Δt IH Δt IH Δt IH Δt IS Δt IH Δt IS Δt IH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
50
34
0
75
50
0
50
34
0
75
50
0
50
34
0
58
8
42
8
16
16
16
16
15
16
12
6
0
–4
0
–4
–10
8
4
24
24
24
23
14
20
14
8
0
8
–2
–8
32
32
31
22
7
24
18
8
8
0
40
39
30
15
34
24
–10
–2
–16
–6
–26
10
–10
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
85
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
Ta b le 61:
Re q u ire d Tim e VAC Ab o ve VIH(AC) (Be lo w VIL[AC]) fo r Va lid Tra n sit io n
t VAC a t 175m V (p s)
Min
t VAC a t 150m V (p s)
Sle w Ra t e (V/n s)
Min
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
75
57
50
38
34
29
22
13
0
175
170
167
163
162
161
159
155
150
150
0
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1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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86
1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
t
t
Fig u re 39: No m in a l Sle w Ra t e a n d VAC fo r DS (DQ – St ro b e )
CK
CK#
DQS#
DQS
t
t
t
t
DH
DS
DH
DS
VDDQ
t
VAC
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
VREF(DC)
Nominal
slew rate
Nominal
slew rate
VIL(DC) MAX
VIL(AC) MAX
VREF to AC
region
t
VAC
VSS
ΔTF
ΔTR
VREF(DC) - VIL(AC) MAX
ΔTF
VIH(AC) MIN - VREF(DC)
ΔTR
Setup slew rate
falling signal
Setup slew rate
rising signal
=
=
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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Sp e e d Bin Ta b le s
t
Fig u re 40: No m in a l Sle w Ra t e fo r DH (DQ – St ro b e )
CK
CK#
DQS#
DQS
t
t
t
t
DH
DS
DH
DS
VDDQ
VIH(AC) MIN
VIH(DC) MIN
Nominal
slew rate
DC to VREF
region
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTF
ΔTR
VREF(DC) - VIL(DC) MAX
ΔTR
VIH(DC) MIN - VREF(DC)
ΔTF
Hold slew rate
rising signal
Hold slew rate
falling signal
=
=
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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t
Fig u re 41: Ta n g e n t Lin e fo r DS (DQ – St ro b e )
CK
CK#
DQS#
DQS
t
t
t
t
DH
DS
DH
DS
VDDQ
t
VAC
Nominal
line
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Tangent
line
VREF(DC)
Tangent
line
VIL(DC) MAX
VIL(AC) MAX
VREF to AC
region
Nominal
line
t
VAC
ΔTR
VSS
Tangent line (VIH[AC] MIN - VREF[DC])
ΔTR
Setup slew rate
rising signal
=
=
ΔTF
Setup slew rate
falling signal
Tangent line (VREF[DC] - VIL[AC] MAX)
ΔTF
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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Sp e e d Bin Ta b le s
t
Fig u re 42: Ta n g e n t Lin e fo r DH (DQ – St ro b e )
CK
CK#
DQS#
DQS
t
t
t
t
DH
DS
DH
DS
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
DC to VREF
region
Nominal
line
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTR
ΔTF
Tangent line (VREF[DC] - VIL[DC] MAX)
ΔTR
Hold slew rate
rising signal
=
=
Tangent line (VIH[DC] MIN - VREF[DC])
ΔTF
Hold slew rate
falling signal
Notes: 1. Both the clock and the strobe are drawn on different time scales.
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Co m m a n d s
Co m m a n d s
Tru t h Ta b le s
Ta b le 62:
Tru t h Ta b le – Co m m a n d
Notes 1–5 apply to the entire table
CKE
Pre v Ne xt
BA
A[11,
9:0] No t e s
Fu n ct io n
Sym b o l Cycle Cycle CS# RAS# CAS# WE# [2:0]
An
A12 A10
MODE REGISTER SET
REFRESH
MRS
REF
SRE
SRX
H
H
H
L
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
V
H
L
L
L
H
L
L
L
H
H
V
H
L
BA
V
OP code
V
V
V
V
V
V
V
V
V
V
Self refresh entry
Self refresh exit
L
V
V
V
6
H
V
H
H
H
H
L
V
6, 7
Single-bank PRECHARGE
PRECHARGE all banks
Bank ACTIVATE
PRE
PREA
ACT
WR
H
H
H
H
H
H
H
H
BA
V
V
V
V
V
L
V
V
L
H
H
L
BA
BA
Row address (RA)
WRITE
BL8MRS,
BC4MRS
RFU
V
L
CA
8
BC4OTF
BL8OTF
WRS4
WRS8
WRAP
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
L
L
BA
BA
BA
RFU
RFU
RFU
L
H
V
L
L
CA
CA
CA
8
8
8
WRITEwith BL8MRS,
H
auto
precharge
BC4MRS
BC4OTF
BL8OTF
WRAPS4
WRAPS8
RD
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
L
BA
BA
BA
RFU
RFU
RFU
L
H
V
H
H
L
CA
CA
CA
8
8
8
READ
BL8MRS,
BC4MRS
H
BC4OTF
BL8OTF
RDS4
RDS8
RDAP
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA
BA
BA
RFU
RFU
RFU
L
H
V
L
L
CA
CA
CA
8
8
8
READ with BL8MRS,
H
auto
precharge
BC4MRS
BC4OTF
BL8OTF
RDAPS4
RDAPS8
NOP
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
L
H
L
L
H
H
H
X
H
V
H
V
H
H
L
L
H
H
H
X
H
V
H
V
L
BA
BA
V
RFU
RFU
V
L
H
V
X
V
H
H
V
X
V
CA
CA
V
8
8
NO OPERATION
H
X
H
V
H
V
H
H
9
Device DESELECTED
Power-down entry
DES
X
X
X
10
6
PDE
V
V
V
Power-down exit
PDX
L
H
V
V
V
V
V
6, 11
12
ZQ CALIBRATION LONG
ZQCL
H
H
H
H
X
X
X
X
X
X
H
L
X
X
ZQ CALIBRATION SHORT ZQCS
L
Notes: 1. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the
clock. The MSB of BA, RA, and CA are device-density and configuration-dependent.
2. RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be held
HIGH during any normal operation.
3. The state of ODT does not affect the states described in this table.
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4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four
mode registers.
5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
6. See Table 63 for additional information on CKE transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are
defined in MR0.
9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted
commands. A NOP will not terminate an operation that is executing.
10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH operations.
12. ZQ CALIBRATION LONG is used for either ZQINIT (first ZQCL command during initialization)
or ZQOPER (ZQCL command after initialization).
Ta b le 63:
Tru t h Ta b le – CKE
Notes 1–2 apply to the entire table; see Table 62 on page 91 for additional command details
CKE
Pre vio u s Cycle 4 Pre se n t Cycle 4
Co m m a n d 5
(RAS#, CAS#, WE#, CS#)
Cu rre n t St a t e 3
(n - 1)
(n )
Act io n 5
No t e s
Power-down
L
L
L
H
L
H
L
L
L
L
L
L
L
“Don’t Care”
DES or NOP
“Don’t Care”
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
REFRESH
Maintain power-down
Power-down exit
Self refresh
L
Maintain self refresh
Self refresh exit
L
Bank(s) active
Reading
H
H
H
H
H
H
H
Active power-down entry
Power-down entry
Writing
Power-down entry
Precharging
Refreshing
All banks idle
Power-down entry
Precharge power-down entry
Precharge power-down entry
Self refresh
6
Notes: 1. All states and sequences not shown are illegal or reserved unless explicitly described else-
where in this document.
2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE
must remain at the valid input level the entire time it takes to achieve the required number
of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid
t
t
t
level during the time period of IS + CKE (MIN) + IH.
3. Current state = The state of the DRAM immediately prior to clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the pre-
vious clock edge.
5. COMMAND is the command registered at the clock edge (must be a legal command as
defined in Table 62 on page 91). Action is a result of COMMAND. ODT does not affect the
states described in this table and is not listed.
6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings
from previous operations are satisfied. All self refresh exit and power-down exit parameters
are also satisfied.
DESELECT (DES)
The DES command (CS# HIGH) prevents new commands from being executed by the
DRAM. Operations already in progress are not affected.
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NO OPERATION (NOP)
The NOP command (CS# LOW) prevents unwanted commands from being registered
during idle or wait states. Operations already in progress are not affected.
ZQ CALIBRATION
ZQ CALIBRATION LONG (ZQCL)
The ZQCL command is used to perform the initial calibration during a power-up initial-
ization and reset sequence (see Figure 51 on page 107). This command may be issued at
any time by the controller depending on the system environment. The ZQCL command
triggers the calibration engine inside the DRAM. After calibration is achieved, the cali-
brated values are transferred from the calibration engine to the DRAM I/ O, which are
reflected as updated RON and ODT values.
t
t
The DRAM is allowed a timing window defined by either ZQINIT or ZQOPER to perform
the full calibration and transfer of values. When ZQCL is issued during the initialization
t
sequence, the timing parameter ZQINIT must be satisfied. When initialization is
t
complete, subsequent ZQCL commands require the timing parameter ZQOPER to be
satisfied.
ZQ CALIBRATION SHORT (ZQCS)
The ZQCS command is used to perform periodic calibrations to account for small
voltage and temperature variations. The shorter timing window is provided to perform
t
the reduced calibration and transfer of values as defined by timing parameter ZQCS. A
ZQCS command can effectively correct a minimum of 0.5 percent RON and RTT
impedance error within 64 clock cycles, assuming the maximum sensitivities specified
in Table 40 on page 56 and Table 41 on page 57.
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA[2:0] inputs selects the bank, and the address
provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses
until a PRECHARGE command is issued to that bank.
A PRECHARGE command must be issued before opening a different row in the same
bank.
READ
The READ command is used to initiate a burst read access to an active row. The address
provided on inputs A[2:0] selects the starting column address depending on the burst
length and burst type selected (see Table 68 on page 111 for additional information).
The value on input A10 determines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be precharged at the end of the READ
burst. If auto precharge is not selected, the row will remain open for subsequent
accesses. The value on input A12 (if enabled in the mode register) when the READ
command is issued determines whether BC4 (chop) or BL8 is used. After a READ
command is issued, the READ burst may not be interrupted. A summary of READ
commands is shown in Table 64 on page 94.
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Ta b le 64:
READ Co m m a n d Su m m a ry
CKE
Pre vio u s Ne xt
BA
A[11,
9:0]
Fu n ct io n
Sym b o l
Cycle Cycle CS# RAS# CAS# WE# [3:0]
An
A12 A10
READ
BL8MRS, BC4MRS
BC4OTF
RD
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
BA
BA
BA
BA
BA
BA
RFU
RFU
RFU
RFU
RFU
RFU
V
L
L
L
CA
CA
CA
CA
CA
CA
RDS4
RDS8
BL8OTF
H
V
L
L
READ
with auto
precharge
BL8MRS, BC4MRS RDAP
H
H
H
BC4OTF
BL8OTF
RDAPS4
RDAPS8
H
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or
not auto precharge is used. The value on input A12 (if enabled in the MR) when the
WRITE command is issued determines whether BC4 (chop) or BL8 is used. The WRITE
command summary is shown in Table 65.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/ column location.
Ta b le 65:
WRITE Co m m a n d Su m m a ry
CKE
Pre v Ne xt
BA
Sym b o l Cycle Cycle CS# RAS# CAS# WE# [3:0]
A[11,
9:0]
Fu n ct io n
An
A12 A10
WRITE
BL8MRS, BC4MRS
BC4OTF
WR
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
BA
BA
BA
BA
BA
BA
RFU
RFU
RFU
RFU
RFU
RFU
V
L
L
L
CA
CA
CA
CA
CA
CA
WRS4
WRS8
BL8OTF
H
V
L
L
WRITE with
auto
precharge
BL8MRS, BC4MRS WRAP
H
H
H
BC4OTF
BL8OTF
WRAPS4
WRAPS8
H
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or in
t
all banks. The bank(s) are available for a subsequent row access a specified time ( RP)
after the PRECHARGE command is issued, except in the case of concurrent auto
precharge. A READ or WRITE command to a different bank is allowed during concurrent
auto precharge as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all
banks are precharged. In the case where only one bank is precharged, inputs BA[2:0]
select the bank; otherwise, BA[2:0] are treated as “Don’t Care.” After a bank is
precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command is treated as a NOP if
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Co m m a n d s
there is no open row in that bank (idle state) or if the previously open row is already in
the process of precharging. However, the precharge period is determined by the last
PRECHARGE command issued to the bank.
REFRESH
REFRESH is used during normal operation of the DRAM and is analogous to CAS#-
before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be
issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care” during a REFRESH command. The
DRAM requires REFRESH cycles at an average interval of 7.8µs (maximum when T ≤
C
85°C or 3.9µs MAX when T ≤ 95°C). To allow for improved efficiency in scheduling and
C
switching between tasks, some flexibility in the absolute refresh interval is provided. A
maximum of eight REFRESH commands can be posted to any given DRAM, meaning
that the maximum absolute interval between any REFRESH command and the next
REFRESH command is nine times the maximum average interval refresh rate. The
t
REFRESH period begins when the REFRESH command is registered and ends RFC
(MIN) later.
Fig u re 43: Re fre sh Mo d e
T0
Ta0
Ta1
T4
T2
T3
Tb0
Tb1
Tb2
T1
CK#
CK
t
t
t
CL
CK
CH
1
1
1
CKE
Valid
Valid
Valid
2
REF
1
1
1
1
1
1
Command
NOP
PRE
NOP
NOP
REF
NOP
NOP
NOP
ACT
Address
A10
RA
RA
All banks
One bank
3
BA[2:0]
Bank(s)
BA
4
DQS, DQS#
4
DQ
4
DM
t
t
t
2
RFC
RP
RFC (MIN)
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH com-
mands, but may be inactive at other times (see " Power-Down Mode" on page 151).
2. The second REFRESH is not required but depicts two back-to-back REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
bank is active (must precharge all active banks).
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
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SELF REFRESH
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in the self refresh mode, the DRAM retains data without
external clocking. The self refresh mode is also a convenient method used to enable/
disable the DLL (see “DLL Disable Mode” on page 96) as well as to change the clock
frequency within the allowed synchronous operating range (see “Input Clock Frequency
Change” on page 99). All power supply inputs (including VREFCA and VREFDQ) must be
maintained at valid levels upon entry/ exit and during SELF REFRESH operation.
DLL Disa b le Mo d e
If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode with a few notable exceptions:
• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS
WRITE latency (CWL = 6).
t
• DLL disable mode affects the read data clock-to-data strobe relationship ( DQSCK),
t
t
but not the read data-to-data strobe relationship ( DQSQ, QH). Special attention is
needed to line the read data up with the controller time domain when the DLL is
disabled.
t
• In normal operation (DLL on), DQSCK starts from the rising clock edge AL + CL
t
cycles after the READ command. In DLL disable mode, DQSCK starts AL + CL - 1
cycles after the READ command. Additionally, with the DLL disabled, the value of
t
t
DQSCK could be larger than CK.
The ODT feature is not supported during DLL disable mode (including dynamic ODT).
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming RTT_NOM MR1[9, 6, 2] and RTT_WR MR2[10, 9] to “0” while in the DLL
disable mode.
Specific steps must be followed to switch between the DLL enable and DLL disable
t
modes due to a gap in the allowed clock rates between the two modes ( CK [AVG] MAX
t
and CK [DLL disable] MIN, respectively). The only time the clock is allowed to cross this
clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh (see Figure 44 on page 97):
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is
turned off, and RTT_NOM and RTT_WR are High-Z), set MR1[0] to “1” to disable the
DLL.
t
2. Enter self refresh mode after MOD has been satisfied.
t
3. After CKSRE is satisfied, change the frequency to the desired clock rate.
t
4. Self refresh may be exited when the clock is stable with the new frequency for CKSRX.
t
After XS is satisfied, update the mode registers with appropriate values.
5. The DRAM will be ready for its next command in the DLL disable mode after the
t
t
greater of MRD or MOD has been satisfied. A ZQCL command should be issued with
appropriate timings met as well.
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Co m m a n d s
Fig u re 44: DLL En a b le Mo d e t o DLL Disa b le Mo d e
T0
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
CK#
CK
1
CKE
Valid
2
3
4
5
MRS
Command
NOP
NOP
NOP
NOP
MRS
SRE
SRX
t
t
CKSRE
t
8
CKSRX
t
7
t
6
MOD
MOD
XS
t
CKESR
9
1
ODT
Valid
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Any valid command.
2. Disable DLL by setting MR1[0] to “1.”
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, RTT is in the High-Z state.
7. Change frequency.
t
8. Clock must be stable CKSRX.
9. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 45 on page 98).
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is
turned off, and RTT_NOM and RTT_WR are High-Z), enter self refresh mode.
t
2. After CKSRE is satisfied, change the frequency to the new clock rate.
t
3. Self refresh may be exited when the clock is stable with the new frequency for CKSRX.
t
After XS is satisfied, update the mode registers with the appropriate values. At a min-
t
imum, set MR1[0] to “0” to enable the DLL. Wait MRD, then set MR0[8] to “1” to
enable DLL RESET.
t
4. After another MRD delay is satisfied, then update the remaining mode registers with
the appropriate values.
5. The DRAM will be ready for its next command in the DLL enable mode after the
t
t
greater of MRD or MOD has been satisfied. However, before applying any command
t
or function requiring a locked DLL, a delay of DLLK after DLL RESET must be satis-
fied. A ZQCL command should be issued with the appropriate timings met as well.
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Co m m a n d s
Fig u re 45: DLL Disa b le Mo d e t o DLL En a b le Mo d e
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Tg0
Th0
CK#
CK
CKE
Valid
t
DLLK
1
2
3
4
5
6
Valid
Command
NOP
NOP
SRE
SRX
MRS
MRS
MRS
t
t
9
CKSRX
t
t
t
MRD
7
8
CKSRE
XS
MRD
t
ODTL off + 1 × CK
t
CKESR
10
ODT
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Enter SELF REFRESH.
2. Exit SELF REFRESH.
t
3. Wait XS, then set MR1[0] to “0” to enable DLL.
t
4. Wait MRD, then set MR0[8] to “1” to begin DLL RESET.
t
5. Wait MRD, update registers (CL, CWL, and write recovery may be necessary).
t
6. Wait MOD, any valid command.
7. Starting with the idle state.
8. Change frequency.
9. Clock must be stable at least CKSRX.
t
10. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH.
The clock frequency range for the DLL disable mode is specified by the parameter
t
CKDLL_DIS. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.
t
DLL disable mode will affect the read data clock to data strobe relationship ( DQSCK)
t
t
but not the data strobe to data relationship ( DQSQ, QH). Special attention is needed to
line up read data to the controller time domain.
t
Compared to the DLL on mode where DQSCK starts from the rising clock edge AL + CL
t
cycles after the READ command, the DLL disable mode DQSCK starts AL + CL - 1 cycles
after the READ command (see Figure 46 on page 99).
WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.
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Co m m a n d s
t
Fig u re 46: DLL Disa b le DQSCK Tim in g
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
Valid
Address
RL = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQS, DQS# DLL on
DI
DI
b + 1
DI
b + 2
DI
b + 3
DI
b + 4
DI
b + 5
DI
b + 6
DI
b + 7
DQ BL8 DLL on
b
RL (DLL disable) = AL + (CL - 1) = 5
t
DQSCK (DLL_DIS) MIN
DQS, DQS# DLL off
DQ BL8 DLL disable
DI
DI
DI
b + 2
DI
DI
DI
DI
DI
b
b + 1
b + 3
b + 4
b + 5
b + 6
b + 7
t
DQSCK (DLL_DIS) MAX
DQS, DQS# DLL off
DQ BL8 DLL disable
DI
DI
DI
DI
DI
DI
DI
DI
b + 7
b
b + 1
b + 2
b + 3
b + 4
b + 5
b + 6
Transitioning Data
Don’t Care
Ta b le 66:
READ Ele ct rica l Ch a ra ct e rist ics, DLL Disa b le Mo d e
Pa ra m e t e r
Sym b o l
tDQSCK (DLL_DIS)
Min
Ma x
Un it s
Access window of DQS from CK, CK#
1
10
ns
In p u t Clo ck Fre q u e n cy Ch a n g e
When the DDR3 SDRAM is initialized, it requires the clock to be stable during most
normal states of operation. This means that after the clock frequency has been set to the
stable state, the clock period is not allowed to deviate except what is allowed for by the
clock jitter and spread spectrum clocking (SSC) specifications.
The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. Outside of these
two modes, it is illegal to change the clock frequency. For the self refresh mode condi-
tion, when the DDR3 SDRAM has been successfully placed into self refresh mode and
t
CKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the clock
becomes a “Don’t Care,” changing the clock frequency is permissible, provided the new
t
clock frequency is stable prior to CKSRX. When entering and exiting self refresh mode
for the sole purpose of changing the clock frequency, the self refresh entry and exit spec-
ifications must still be met.
The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or RTT_NOM and RTT_WR must be disabled via MR1 and MR2. This ensures
RTT_NOM and RTT_WR are in an off state prior to entering precharge power-down mode,
t
and CKE must be at a logic LOW. A minimum of CKSRE must occur after CKE goes LOW
before the clock frequency can change. The DDR3 SDRAM input clock frequency is
allowed to change only within the minimum and maximum operating frequency
t
t
specified for the particular speed grade ( CK [AVG] MIN to CK [AVG] MAX). During the
input clock frequency change, CKE must be held at a stable LOW level. When the input
t
clock frequency is changed, a stable clock must be provided to the DRAM CKSRX before
t
precharge power-down may be exited. After precharge power-down is exited and XP has
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been satisfied, the DLL must be reset via the MRS. Depending on the new clock
frequency, additional MRS commands may need to be issued. During the DLL lock time,
RTT_NOM and RTT_WR must remain in an off state. After the DLL lock time, the DRAM is
ready to operate with a new clock frequency. This process is depicted in Figure 47.
Fig u re 47: Ch a n g e Fre q u e n cy Du rin g Pre ch a rg e Po w e r-Do w n
Previous clock frequency
New clock frequency
Te0
Tc1
Td0
Td1
Te1
T0
T1
T2
Ta0
Tb0
Tc0
CK#
CK
t
t
t
t
t
t
CL
t
t
CL
CH
CL
CH
CL
CH
CH
b
b
b
b
b
b
t
t
t
CK
t
CK
CK
CK
b
b
b
t
t
CKSRX
CKSRE
t
t
IS
t
IH
CKE
t
IH
CKE
t
IS
t
CPDED
Command
NOP
Valid
Valid
NOP
NOP
NOP
NOP
MRS
NOP
Address
DLL RESET
t
t
AOFPD/ AOF
t
t
t
IS
XP
IH
ODT
DQS, DQS#
DQ
High-Z
High-Z
DM
t
DLLK
Enter precharge
Frequency
change
Exit precharge
power-down mode
power-down mode
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Applicable for both slow-exit and fast-exit precharge power-down modes.
t
2. tAOFPD and AOF must be satisfied and outputs High-Z prior to T1 (see "On-Die Termina-
tion (ODT)" on page 160 for exact requirements).
3. If the RTT_NOM feature was enabled in the mode register prior to entering precharge
power-down mode, the ODT signal must be continuously registered LOW ensuring RTT is in
an off state. If the RTT_NOM feature was disabled in the mode register prior to entering pre-
charge power-down mode, RTT will remain in the off state. The ODT signal can be regis-
tered either LOW or HIGH in this case.
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Writ e Le ve lin g
For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for
the commands, addresses, control signals, and clocks. Write leveling is a scheme for the
memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship
at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is
generally used as part of the initialization process, if required. For normal DRAM opera-
tion, this feature must be disabled. This is the only DRAM operation where the DQS
functions as an input (to capture the incoming clock) and the DQ function as outputs (to
report the state of the clock). Note that nonstandard ODT schemes are required.
The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from “0” to “1” is detected. The DQS delay established
t
t
t
through this procedure helps ensure DQSS, DSS, and DSH specifications in systems
that use fly-by topology by deskewing the trace length mismatch. A conceptual timing of
this procedure is shown in Figure 48.
Fig u re 48: Writ e Le ve lin g Co n ce p t
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
Source
Differential DQS
Tn
T0
T1
T2
T3
T4
T5
T6
CK#
CK
Destination
Differential DQS
0
0
DQ
Destination
Tn
T0
T1
T2
T3
T4
T5
T6
CK#
CK
Push DQS to capture
0–1 transition
Differential DQS
1
1
DQ
Don’t Care
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101
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Co m m a n d s
When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ
outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with
all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the
lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS and
UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a x16
enable each byte lane to be leveled independently.
The write leveling mode register interacts with other mode registers to correctly
configure the write leveling functionality. Besides using MR1[7] to disable/ enable write
leveling, MR1[12] must be used to enable/ disable the output buffers. The ODT value,
burst length, and so forth need to be selected as well. This interaction is shown in
Table 67. It should also be noted that when the outputs are enabled during write leveling
mode, the DQS buffers are set as inputs, and the DQ are set as outputs. Additionally,
during write leveling mode, only the DQS strobe terminations are activated and deacti-
vated via the ODT ball. The DQ remain disabled and are not affected by the ODT ball
(see Table 67).
Ta b le 67:
MR1[7]
Writ e Le ve lin g Ma t rix
Note 1 applies to the entire table
DRAM
RTT_NOM
MR1[12] MR1[3, 6, 9]
Writ e
Le ve lin g
Ou t p u t
Bu ffe rs
RTT_NOM
Va lu e
DRAM
ODT Ba ll DQS
DQ
DRAM St a t e
Ca se No t e s
Disabled
See normal operations
Write leveling not enabled
0
Enabled
(1)
Disabled
(1)
n/a
Low
High
Low
High
Off
On
Off
On
Off
DQS not receiving: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
1
2
3
4
2
20Ω, 30Ω,
40Ω, 60Ω, or
120Ω
DQS not receiving: terminated by RTT
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
Enabled
(0)
n/a
DQS receiving: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
3
40Ω, 60Ω, or
120Ω
DQS receiving: terminated by RTT
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
Notes: 1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a
dual-rank module and on the rank not being levelized or on any rank of a module not
being levelized on a multislotted system. Case 2 may be used when DRAM are on any rank
of a module not being levelized on a multislotted system. Case 3 is generally not used. Case
4 is generally used when DRAM are on the rank that is being leveled.
2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe, and
all RTT_NOM values are allowed. This simulates a normal standby state to DQS.
3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and only
some RTT_NOM values are allowed. This simulates a normal write state to DQS.
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Co m m a n d s
Writ e Le ve lin g Pro ce d u re
A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a “1,”
assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and
the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from
a High-Z state to an undefined driving state, so the DQ bus should not be driven. During
write leveling mode, only the NOP or DES commands are allowed. The memory
controller should attempt to level only one rank at a time; thus, the outputs of other
ranks should be disabled by setting MR1[12] to a “1” in the other ranks. The memory
t
controller may assert ODT after a MOD delay as the DRAM will be ready to process the
ODT transition. ODT should be turned on prior to DQS being driven LOW by at least
t
t
ODTL on delay (WL - 2 CK), provided it does not violate the aforementioned MOD
delay requirement.
t
The memory controller may drive DQS LOW and DQS# HIGH after WLDQSEN has been
t
satisfied. The controller may begin to toggle DQS after WLMRD (one DQS toggle is DQS
transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH
state to a LOW state, then both transition back to their original states). At a minimum,
t
ODTL on and AON must be satisfied at least one clock prior to DQS toggling.
t
t
After WLMRD and a DQS LOW preamble ( WPRE) have been satisfied, the memory
controller may provide either a single DQS toggle or multiple DQS toggles to sample CK
t
for a given DQS-to-CK skew. Each DQS toggle must not violate DQSL (MIN) and
DQSH (MIN) specifications. DQSL (MAX) and DQSH (MAX) specifications are not
applicable during write leveling mode. The DQS must be able to distinguish the CK’s
rising edge within WLS and WLH. The prime DQ will output the CK’s status
asynchronously from the associated DQS rising edge CK capture within WLO. The
t
t
t
t
t
t
t
remaining DQ that always drive LOW when DQS is toggling must be LOW within WLOE
after the first WLO is satisfied (the prime DQ going LOW). As previously noted, DQS is
t
an input and not an output during this process. Figure 49 on page 104 depicts the basic
timing parameters for the overall write leveling procedure.
The memory controller will likely sample each applicable prime DQ state and determine
whether to increment or decrement its DQS delay setting. After the memory controller
performs enough DQS toggles to detect the CK’s “0-to-1” transition, the memory
controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting, leveling for the rank will have been achieved, and the write leveling mode for the
rank should be disabled or reprogrammed (if write leveling of another rank follows).
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Co m m a n d s
Fig u re 49: Writ e Le ve lin g Se q u e n ce
T1
T2
t
t
WLH
WLH
t
t
WLS
WLS
CK#
CK
1
2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
MRS
t
MOD
ODT
t
3
t
3
DQSH
t
3
DQSL
t
3
DQSH
t
DQSL
WLDQSEN
4
Differential DQS
t
t
t
t
WLMRD
WLO
WLO
WLO
5
Prime DQ
t
WLOE
Early remaining DQ
Late remaining DQ
t
WLO
Indicates A Break in
Time Scale
Undefined Driving Mode
Don’t Care
Notes: 1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and
tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent.
4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the
zero crossings. The solid line represents DQS; the dotted line represents DQS#.
5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are
driven low and remain in this state throughout the leveling procedure.
Writ e Le ve lin g Mo d e Exit Pro ce d u re
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 50 on page 105 depicts a general procedure in exiting write
leveling mode. After the last rising DQS (capturing a “1” at T0), the memory controller
t
should stop driving the DQS signals after WLO (MAX) delay plus enough delay to enable
the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls
become undefined when DQS no longer remains LOW, and they remain undefined until
t
MOD after the MRS command (at Te1).
The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the
t
DQS is no longer driving LOW. When ODT LOW satisfies IS, ODT must be kept LOW (at
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
t
disabled via the MRS command (at Tc2). After MOD is satisfied (at Te1), any valid
command may be registered by the DRAM. Some MRS commands may be issued after
t
MRD (at Td1).
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Fig u re 50: Exit Writ e Le ve lin g
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
CK#
CK
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
Valid
NOP
Valid
Valid
t
MRD
Address
Valid
MR1
t
t
IS
MOD
ODT
t
AOF (MIN)
ODTL off
RTT DQS, RTT DQS#
RTT_NOM
t
AOF (MAX)
DQS, DQS#
RTT_DQ
t
t
WLO + WLOE
DQ
CK = 1
Indicates A Break in
Time Scale
Undefined Driving Mode
Transitioning
Don’t Care
Notes: 1. The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK
HIGH just after the T0 state.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Op e ra t io n s
In it ia liza t io n
The following sequence is required for power up and initialization, as shown in
Figure 51 on page 107:
1. Apply power. RESET# is recommended to be below 0.2 × VDDQ during power ramp to
ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z). All
other inputs, including ODT, may be undefined.
During power up, either of the following conditions may exist and must be met:
• Condition A:
– VDD and VDDQ are driven from a single-power converter output and are ramped
with a maximum delta voltage between them of ΔV ≤ 300mV. Slope reversal of any
power supply signal is allowed. The voltage levels on all balls other than VDD,
VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side, and
must be greater than or equal to VSSQ and VSS on the other side.
– Both VDD and VDDQ power supplies ramp to VDD (MIN) and VDDQ (MIN) within
t
VDDPR = 200ms.
– VREFDQ tracks VDD × 0.5, VREFCA tracks VDD × 0.5.
– VTT is limited to 0.95V when the power ramp is complete and is not applied directly
t
to the device; however, VTD should be greater than or equal to zero to avoid device
latchup.
• Condition B:
– VDD may be applied before or at the same time as VDDQ.
– VDDQ may be applied before or at the same time as VTT, VREFDQ, and VREFCA.
– No slope reversals are allowed in the power supply ramp for this condition.
2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled
(High-Z). After the power is stable, RESET# must be LOW for at least 200µs to begin
the initialization process. ODT will remain in the High-Z state while RESET# is LOW
and until CKE is registered HIGH.
3. CKE must be LOW 10ns prior to RESET# transitioning HIGH.
4. After RESET# transitions HIGH, wait 500µs (minus one clock) with CKE LOW.
5. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP
or DES commands may be issued. The clock must be present and valid for at least
t
10ns (and a minimum of five clocks) and ODT must be driven LOW at least IS prior to
CKE being registered HIGH. When CKE is registered HIGH, it must be continuously
registered HIGH until the full initialization process is complete.
t
6. After CKE is registered HIGH and after XPR has been satisfied, MRS commands may
be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings
(provide LOW to BA2 and BA0 and HIGH to BA1).
7. Issue an MRS command to MR3 with the applicable settings.
8. Issue an MRS command to MR1 with the applicable settings, including enabling the
DLL and configuring ODT.
9. Issue an MRS command to MR0 with the applicable settings, including a DLL RESET
t
command. DLLK (512) cycles of clock input are required to lock the DLL.
10. Issue a ZQCL command to calibrate RTT and RON values for the process voltage tem-
t
perature (PVT). Prior to normal operation, ZQINIT must be satisfied.
t
t
11. When DLLK and ZQINIT have been satisfied, the DDR3 SDRAM will be ready for nor-
mal operation.
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Op e ra t io n s
Fig u re 51: In it ia liza t io n Se q u e n ce
T (MAX) = 200ms
V
DD
See power-up
conditions
in the
initialization
sequence text,
set up 1
VDDQ
V
TT
VREF
Stable and
valid clock
Tc0
Td0
Tb0
T1
T0
Ta0
Power-up
ramp
t
t
CK
VTD
CK#
CK
t
t
t
CL
CL
CKSRX
t
IO
= 20ns
z
RESET#
t
IS
T (MIN) = 10ns
Valid
Valid
CKE
ODT
t
IS
NOP
Command
MRS
MRS
MRS
MRS
ZQCL
Valid
DM
Address
A10
Valid
Code
Code
Code
Code
Code
Code
Code
Code
Valid
Valid
A10 = H
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
BA[2:0]
DQS
DQ
RTT
t
t
t
MOD
T = 200µs (MIN)
T = 500µs (MIN)
t
t
t
ZQINIT
MRD
MRD
XPR
MRD
MR0 with
DLL reset
MR1 with
DLL enable
MR2
MR3
ZQ calibration
All voltage
supplies valid
and stable
t
DLLK
DRAM ready for
external commands
Normal
operation
Indicates A Break in
Time Scale
Don’t Care
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107
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Mo d e Re g ist e rs
Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the MODE REGISTER
SET (MRS) command during initialization, and it retains the stored information (except
for MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or
until the device loses power.
Contents of a mode register can be altered by reexecuting the MRS command. If the user
chooses to modify only a subset of the mode register’s variables, all variables must be
programmed when the MRS command is issued. Reprogramming the mode register will
not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or reissued) when all banks are idle and in the
t
precharged state ( RP is satisfied and no data bursts are in progress). After an MRS
t
t
command has been issued, two parameters must be satisfied: MRD and MOD.
t
The controller must wait MRD before initiating any subsequent MRS commands (see
Figure 52).
t
Fig u re 52: MRS-t o -MRS Co m m a n d Tim in g ( MRD)
T0
T1
T2
Ta0
Ta1
Ta2
CK#
CK
1
2
MRS
NOP
NOP
NOP
NOP
MRS
Command
t
MRD
Address
Valid
Valid
3
CKE
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN) must
be satisfied, and no data bursts can be in progress.
2. tMRD specifies the MRS-to-MRS command minimum cycle time.
3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see "Power-
Down Mode" on page 151).
t
4. For a CAS latency change, XPDLL timing must be met before any nonMRS command.
t
The controller must also wait MOD before initiating any nonMRS commands
(excluding NOP and DES), as shown in Figure 53 on page 109. The DRAM requires MOD
t
in order to update the requested features, with the exception of DLL RESET, which
t
requires additional time. Until MOD has been satisfied, the updated features are to be
assumed unavailable.
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108
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
t
Fig u re 53: MRS-t o -n o n MRS Co m m a n d Tim in g ( MOD)
T0
T1
T2
Ta0
Ta1
Ta2
CK#
CK
non
MRS
NOP
NOP
NOP
NOP
Command
MRS
t
MOD
Address
CKE
Valid
Valid
Valid
Old
setting
New
setting
Updating setting
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP
must be satisfied, and no data bursts can be in progress).
t
2. Prior to Ta2 when MOD (MIN) is being satisfied, no commands (except NOP/DES) may be
issued.
3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied
prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until
tMOD (MIN) is satisfied at Ta2.
4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which time
power-down may occur (see "Power-Down Mode" on page 151).
Mo d e Re g ist e r 0 (MR0)
The base register, MR0, is used to define various DDR3 SDRAM modes of operation.
These definitions include the selection of a burst length, burst type, CAS latency, oper-
ating mode, DLL RESET, write recovery, and precharge power-down mode, as shown in
Figure 54 on page 110.
Bu rst Le n g t h
Burst length is defined by MR0[1: 0] (see Figure 54 on page 110). Read and write accesses
to the DDR3 SDRAM are burst-oriented, with the burst length being programmable to
“4” (chop mode), “8” (fixed), or selectable using A12 during a READ/ WRITE command
(on-the-fly). The burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to “01”
during a READ/ WRITE command, if A12 = 0, then BC4 (chop) mode is selected. If
A12 = 1, then BL8 mode is selected. Specific timing diagrams, and turnaround between
READ/ WRITE, are shown in the READ/ WRITE sections of this document.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[i:2] when the burst length is set to “4” and by A[i:3] when the
burst length is set to “8” (where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies to both READ
and WRITE bursts.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 54: Mo d e Re g ist e r 0 (MR0) De fin it io n s
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
16 15 14 13 12 11 10
9
8
7
1
6
5
4
3
2
1
0
Mode register 0 (MR0)
1
1
0
0
PD
WR
DLL
0
CAS# latency BT
0
0
M1 M0
Burst Length
M15 M14
Mode Register
0
0
1
1
0
1
0
1
Fixed BL8
4 or 8 (on-the-fly via A12)
Fixed BC4 (chop)
Reserved
0
0
1
1
0
1
0
1
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
M8 DLL Reset
M12 Precharge PD
0
1
No
0
1
DLL off (slow exit)
DLL on (fast exit)
Yes
M11 M10 M9 Write Recovery
M6 M5 M4
CAS Latency
M3
READ Burst Type
Sequential (nibble)
Interleaved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
0
1
5
5
6
6
7
7
8
10
8
9
10
12
Reserved
11 (DDR3-1600)
Notes: 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to “0.”
Bu rst Typ e
Accesses within a given burst may be programmed to either a sequential or an inter-
leaved order. The burst type is selected via MR0[3], as shown in Figure 54. The ordering
of accesses within a burst is determined by the burst length, the burst type, and the
starting column address, as shown in Table 68 on page 111. DDR3 only supports 4-bit
burst chop and 8-bit burst access modes. Full interleave address ordering is supported
for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries.
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110
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Ta b le 68:
Bu rst Ord e r
St a rt in g Co lu m n
Bu rst
Le n g t h
READ/
WRITE
Ad d re ss
Bu rst Typ e = Se q u e n t ia l
(De cim a l)
Bu rst Typ e = In t e rle a ve d
(A[2, 1, 0])
(De cim a l)
No t e s
4 chop
READ
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 V V
1 V V
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
V V V
0, 1, 2, 3, Z, Z, Z, Z
1, 2, 3, 0, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 0, 1, 2, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 6, 7, 4, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 4, 5, 6, Z, Z, Z, Z
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, Z, Z, Z, Z
1, 0, 3, 2, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 3, 4
1, 3, 4
1
WRITE
READ
8
1
1
1
1
1
1
1
WRITE
1, 3
Notes: 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for
BL8.
2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins.
4. X = “Don’t Care.”
DLL RESET
DLL RESET is defined by MR0[8] (see Figure 54 on page 110). Programming MR0[8] to
“1” activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a
value of “0” after the DLL RESET function has been initiated.
Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held
t
stable for 512 ( DLLK) clock cycles before a READ command can be issued. This is to
allow time for the internal clock to be synchronized with the external clock. Failing to
wait for synchronization to occur may result in invalid output timing specifications,
t
such as DQSCK timings.
Writ e Re co ve ry
WRITE recovery time is defined by MR0[11:9] (see Figure 54 on page 110). Write
recovery values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user
is required to program the correct value of write recovery and is calculated by dividing
t
t
WR (ns) by CK (ns) and rounding up a noninteger value to the next integer: WR (cycles)
t
t
= roundup ( WR [ns]/ CK [ns]).
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111
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Pre ch a rg e Po w e r-Do w n (Pre ch a rg e PD)
The precharge PD bit applies only when precharge power-down mode is being used.
When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a
t
lower standby current mode; however, XPDLL must be satisfied when exiting. When
MR0[12] is set to “1,” the DLL continues to run during precharge power-down mode to
t
enable a faster exit of precharge power-down mode; however, XP must be satisfied when
exiting (see "Power-Down Mode" on page 151).
CAS La t e n cy (CL)
The CL is defined by MR0[6:4], as shown in Figure 54 on page 110. CAS latency is the
delay, in clock cycles, between the internal READ command and the availability of the
first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not
support half-clock latencies.
Examples of CL = 6 and CL = 8 are shown in Figure 55. If an internal READ com mand is
registered at clock edge n, and the CAS latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 49 on page 63 through Table 51 on
page 65 indicate the CLs supported at various operating frequencies.
Fig u re 55: READ La t e n cy
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
AL = 0, CL = 6
DQS, DQS#
DQ
DI
DI
DI
DI
DI
n
n + 1
n + 2
n + 3
n + 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Command
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
AL = 0, CL = 8
DQS, DQS#
DQ
DI
n
Transitioning Data
Don’t Care
Notes: 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal tDQSCK and nominal tDSDQ.
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112
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Mo d e Re g ist e r 1 (MR1)
The mode register 1 (MR1) controls additional functions and features not available in
the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration
only), DLL ENABLE/ DLL DISABLE, RTT_NOM value (ODT), WRITE LEVELING, POSTED
CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are
controlled via the bits shown in Figure 56. The MR1 register is programmed via the MRS
command and retains the stored information until it is reprogrammed, until RESET#
goes LOW, or until the device loses power. Reprogramming the MR1 register will not
alter the contents of the memory array, provided it is performed correctly.
The MR1 register must be loaded when all banks are idle and no bursts are in progress.
t
t
The controller must satisfy the specified timing parameters MRD and MOD before
initiating a subsequent operation.
Fig u re 56: Mo d e Re g ist e r 1 (MR1) De fin it io n
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA2
Address bus
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode register 1 (MR1)
1
1
1
1
WL RTT ODS
0
0
1
Q Off TDQS
R
TT
AL
RTT ODS DLL
0
0
0
M0
0
DLL Enable
Enable (normal)
Disable
M15 M14
Mode Register
M12
Q Off
M11
TDQS
0
0
1
1
0
1
0
1
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
1
0
1
Enabled
0
1
Disabled
Enabled
Disabled
M5 M1 Output Drive Strength
0
0
1
1
0
1
0
1
RZQ/6 (40Ω [NOM])
RZQ/7 (34Ω [NOM])
Reserved
2
3
M7
0
Write Levelization
Disable (normal)
Enable
R
TT
_
NOM (ODT)
Non-Writes
NOM disabled
RTT
_
NOM (ODT)
Writes
M9 M6 M2
1
RTT
_
RTT_NOM disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
RZQ/4 (60Ω [NOM]) RZQ/4 (60Ω [NOM])
RZQ/2 (120Ω [NOM]) RZQ/2 (120Ω [NOM])
RZQ/6 (40Ω [NOM]) RZQ/6 (40Ω [NOM])
Additive Latency (AL)
Disabled (AL = 0)
AL = CL - 1
M4 M3
0
0
1
1
0
1
0
1
RZQ/12 (20Ω [NOM])
RZQ/8 (30Ω [NOM])
Reserved
n/a
n/a
AL = CL - 2
Reserved
Reserved
Reserved
Reserved
Notes: 1. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to “0.”
2. During write leveling, if MR1[7] and MR1[12] are “1” then all RTT_NOM values are available
for use.
3. During write leveling, if MR1[7] is a “1,” but MR1[12] is a “0,” then only RTT_NOM write val-
ues are available for use.
DLL En a b le /DLL Disa b le
The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE
command, as shown in Figure 56. The DLL must be enabled for normal operation. DLL
enable is required during power-up initialization and upon returning to normal opera-
tion after having disabled the DLL for the purpose of debugging or evaluation. Enabling
the DLL should always be followed by resetting the DLL using the appropriate LOAD
MODE command.
If the DLL is enabled prior to entering self refresh mode, the DLL is automatically
disabled when entering SELF REFRESH operation and is automatically reenabled and
reset upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self
refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation
until it is reenabled and reset.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:
1. ODT is not allowed to be used.
2. The output data is no longer edge-aligned to the clock.
3. CL and CWL can only be six clocks.
When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see “DLL Disable Mode” on page 96). Disabling
the DLL also implies the need to change the clock frequency (see “Input Clock
Frequency Change” on page 99).
Ou t p u t Drive St re n g t h
The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/ 7 (34Ω [NOM]) is the primary output
driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver
impedance, an external precision resistor (RZQ) is connected between the ZQ ball and
VSSQ. The value of the resistor must be 240Ω ±1 percent.
The output impedance is set during initialization. Additional impedance calibration
updates do not affect device operation, and all data sheet timings and current specifica-
tions are met during an update.
To meet the 34Ω specification, the output drive strength must be set to 34Ω during
initialization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset proce-
dure.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 56 on
page 113. When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in
the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
t
during IDD characterization of the READ current and during DQSS margining (write
leveling) only.
TDQS En a b le
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration,
which provides termination resistance (RTT), that may be useful in some system config-
urations. TDQS is not supported in x4 or x16 configurations. When enabled via the mode
register (MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and
TDQS#. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termina-
tion resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not provided
by TDQS; thus, RON does not apply to TDQS and TDQS#. The TDQS and DM functions
share the same ball. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is
provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3
SDRAM configuration only and must be disabled via the mode register for the x4 and x16
configurations.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
On -Die Te rm in a t io n
ODT resistance RTT_NOM is defined by MR1[9, 6, 2] (see Figure 56 on page 113). The RTT
termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple RTT termination values based on RZQ/ n where n can be 2, 4, 6, 8, or 12
and RZQ is 240Ω.
Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. RTT_NOM termination is allowed any time after the DRAM is
initialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT enabled (RTT_WR) temporarily
replaces RTT_NOM with RTT_WR.
The actual effective termination, RTT_EFF, may be different from the RTT targeted due to
nonlinearity of the termination. For RTT_EFF values and calculations (see "On-Die
Termination (ODT)" on page 160).
The ODT feature is designed to improve signal integrity of the memory channel by
enabling the DDR3 SDRAM controller to independently turn on/ off ODT for any or all
devices. The ODT input control pin is used to determine when RTT is turned on (ODTL
on) and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2].
Timings for ODT are detailed in "On-Die Termination (ODT)" on page 160.
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 56 on
page 113. Write leveling is used (during initialization) to deskew the DQS strobe to clock
offset as a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM
memory modules adopted fly-by topology for the commands, addresses, control signals,
and clocks.
The fly-by topology benefits from a reduced number of stubs and their lengths. However,
fly-by topology induces flight time skews between the clock and DQS strobe (and DQ) at
t
each DRAM on the DIMM. Controllers will have a difficult time maintaining DQSS,
t
t
DSS, and DSH specifications without supporting write leveling in systems which use
fly-by topology-based modules. Write leveling timing and detailed operation informa-
tion is provided in “Write Leveling” on page 101.
POSTED CAS ADDITIVE La t e n cy (AL)
AL is supported to make the command and data bus efficient for sustainable band-
widths in DDR3 SDRAM. MR1[4, 3] define the value of AL as shown in Figure 57 on
page 116. MR1[4, 3] enable the user to program the DDR3 SDRAM with an AL = 0, CL - 1,
or CL - 2.
With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued
t
after the ACTIVATE command for that bank prior to RCD (MIN). The only restriction is
t
ACTIVATE to READ or WRITE + AL ≥ RCD (MIN) must be satisfied. Assuming
t
t
t
RCD (MIN) = CL, a typical application using this feature sets AL = CL - 1 CK =
t
RCD (MIN) - 1 CK. The READ or WRITE command is held for the time of the AL before
it is released internally to the DDR3 SDRAM device. READ latency (RL) is controlled by
the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of
CAS WRITE latency and AL, WL = AL + CWL (see "Mode Register 2 (MR2)" on page 116).
Examples of READ and WRITE latencies are shown in Figure 57 on page 116 and
Figure 59 on page 117.
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Op e ra t io n s
Fig u re 57: READ La t e n cy (AL = 5, CL = 6)
BC4
T2
T11
T0
T1
T6
T12
T13
T14
CK#
CK
Command
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
NOP
t
RCD (MIN)
DQS, DQS#
AL = 5
CL = 6
DO
DO
DO
DO
DQ
n
n + 1
n + 2
n + 3
RL = AL + CL = 11
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Mo d e Re g ist e r 2 (MR2)
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL),
AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC
ODT (RTT_WR). These functions are controlled via the bits shown in Figure 58. The MR2
is programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register will
not alter the contents of the memory array, provided it is performed correctly. The MR2
register must be loaded when all banks are idle and no data bursts are in progress, and
t
t
the controller must wait the specified time MRD and MOD before initiating a subse-
quent operation.
Fig u re 58: Mo d e Re g ist e r 2 (MR2) De fin it io n
A13
BA2 BA1 BA0
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode register 2 (MR2)
1
1
1
1
RTT_WR
1
1
1
1
0
SRT ASR
CWL
1
0
0
0
0
0
0
0
0
M15 M14
Mode Register
M7 Self Refresh Temperature
M5 M4 M3
CAS Write Latency (CWL)
t
0
0
1
1
0
1
0
1
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
1
Normal (0°C to 85°C)
Extended (0°C to 95°C)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5 CK ( CK ≥ 2.5ns)
t
6 CK (2.5ns > CK ≥ 1.875ns)
t
7 CK (1.875ns > CK ≥ 1.5ns)
t
8 CK (1.5ns > CK ≥ 1.25ns)
Reserved
Reserved
Reserved
Reserved
Auto Self Refresh
(Optional)
Dynamic ODT
M6
0
M10 M9
( RTT_WR )
Disabled: Manual
Enabled: Automatic
0
0
1
1
0
1
0
1
RTT_WR disabled
1
RZQ/4
RZQ/2
Reserved
Notes: 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.”
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116
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
CAS Writ e La t e n cy (CWL)
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 58 on page 116). The overall WRITE
latency (WL) is equal to CWL + AL (Figure 56 on page 113), as shown in Figure 59.
Fig u re 59: CAS Writ e La t e n cy
BC4
T11
T0
T1
T2
T6
T12
T13
T14
CK#
CK
ACTIVE n
WRITE n
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
RCD (MIN)
DQS, DQS#
AL = 5
CWL = 6
DI
DI
DI
DI
DQ
n
n + 1
n + 2
n + 3
WL = AL + CWL = 11
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/ enable the ASR function.
When ASR is disabled, the self refresh mode’s refresh rate is assumed to be at the normal
85°C limit (sometimes referred to as 1X refresh rate). In the disabled mode, ASR requires
the user to ensure the DRAM never exceeds a T of 85°C while in self refresh unless the
C
user enables the SRT feature listed below when the T is between 85°C and 95°C.
C
Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1X to
2X when the case temperature exceeds 85°C. This enables the user to operate the DRAM
beyond the standard 85°C limit up to the optional extended temperature range of 95°C
while in self refresh mode.
The standard self refresh current test specifies test conditions to normal case tempera-
ture (85°C) only, meaning if ASR is enabled, the standard self refresh current specifica-
tions do not apply (see “Extended Temperature Usage” on page 150).
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[7] is used to disable/ enable the SRT function. When SRT is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (sometimes
referred to as 1X refresh rate). In the disabled mode, SRT requires the user to ensure the
DRAM never exceeds a T of 85°C while in self refresh mode unless the user enables ASR.
C
When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regard-
less of the case temperature. This enables the user to operate the DRAM beyond the
standard 85°C limit up to the optional extended temperature range of 95°C while in self
refresh mode. The standard self refresh current test specifies test conditions to normal
case temperature (85°C) only, meaning if SRT is enabled, the standard self refresh
current specifications do not apply (see “Extended Temperature Usage” on page 150).
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Op e ra t io n s
SRT vs. ASR
If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR is
required, and both can be disabled throughout operation. However, if the extended
temperature option of 95°C is needed, the user is required to provide a 2X refresh rate
during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is
performed at the 2X rate.
SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is
performed at the 2X refresh rate regardless of the case temperature.
ASR automatically switches the DRAM’s internal self refresh rate from 1X to 2X. However,
while in self refresh mode, ASR enables the refresh rate to automatically adjust between
1X to 2X over the supported temperature range. One other disadvantage with ASR is the
DRAM cannot always switch from a 1X to a 2X refresh rate at an exact case temperature
of 85°C. Although the DRAM will support data integrity when it switches from a 1X to a
2X refresh rate, it may switch at a lower temperature than 85°C.
Since only one mode is neccesary, SRT and ASR cannot be enabled at the same time.
DYNAMIC ODT
The dynamic ODT (RTT_WR) feature is defined by MR2[10, 9]. Dynamic ODT is enabled
when a value is selected. This new DDR3 SDRAM feature enables the ODT termination
value to change without issuing an MRS command, essentially changing the ODT termi-
nation “on-the-fly.”
With dynamic ODT (RTT_WR) enabled, the DRAM switches from normal ODT (RTT_NOM)
to dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches
back to ODT (RTT_NOM) at the completion of the WRITE burst. If RTT_NOM is disabled,
the RTT_NOM value will be High-Z. Special timing parameters must be adhered to when
dynamic ODT (RTT_WR) is enabled: ODTLCNW, ODTLCNW4, ODTLCNW8, ODTH4,
t
ODTH8, and ADC.
Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT_NOM) is disabled,
dynamic ODT (RTT_WR) is still permitted. RTT_NOM and RTT_WR can be used indepen-
dent of one other. Dynamic ODT is not available during write leveling mode, regardless
of the state of ODT (RTT_NOM). For details on dynamic ODT operation, refer to “On-Die
Termination (ODT)” on page 160.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Mo d e Re g ist e r 3 (MR3)
The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
This function is controlled via the bits shown in Figure 60. The MR3 is programmed via
the LOAD MODE command and retains the stored information until it is programmed
again or until the device loses power. Reprogramming the MR3 register will not alter the
contents of the memory array, provided it is performed correctly. The MR3 register must
be loaded when all banks are idle and no data bursts are in progress, and the controller
t
t
must wait the specified time MRD and MOD before initiating a subsequent operation.
Fig u re 60: Mo d e Re g ist e r 3 (MR3) De fin it io n
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
16 15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
0
Mode register 3 (MR3)
MPR READ Function
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
MPR MPR_RF
0
Mode Register
M2
MPR Enable
M15 M14
M1 M0
2
3
Mode register set (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
1
Normal DRAM operations
Dataflow from MPR
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Predefined pattern
Reserved
Reserved
Reserved
Notes: 1. MR3[16 and 13:4] are reserved for future use and must all be programmed to “0.”
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 61 on page 120.
If MR3[2] is a “0,” then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a “1,” then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to “00,” then a
predefined read pattern for system calibration is selected.
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1 (see Table 69
on page 120). Prior to issuing the MRS command, all banks must be in the idle state (all
t
banks are precharged, and RP is met). When the MPR is enabled, any subsequent READ
or RDAP commands are redirected to the multipurpose register. The resulting operation
when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the
MPR is enabled (see Table 70 on page 121). When the MPR is enabled, only READ or
RDAP commands are allowed until a subsequent MRS command is issued with the MPR
disabled (MR3[2] = 0). Power-down mode, self refresh, and any other nonREAD/ RDAP
command is not allowed during MPR enable mode. The RESET function is supported
during MPR enable mode.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 61: Mu lt ip u rp o se Re g ist e r (MPR) Blo ck Dia g ra m
Memory core
MR3[2] = 0 (MPR off)
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
DQ, DM, DQS, DQS#
Notes: 1. A predefined data pattern can be read out of the MPR with an external READ command.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the
data flow is defined, the MPR contents can be read out continuously with a regular READ or
RDAP command.
Ta b le 69:
MR3[2]
MPR Fu n ct io n a l De scrip t io n o f MR3 Bit s
MR3[1:0]
MPR
MPR READ Fu n ct io n
Fu n ct io n
0
“Don’t Care”
Normal operation, no MPR transaction
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
1
A[1:0]
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2
(see Table 70 on page 121)
MPR Fu n ct io n a l De scrip t io n
The MPR is a 1-bit-wide logical interface via all DQ balls during a READ command. DQ0
on a x4 and a x8 is the prime DQ and outputs the MPR data while the remaining DQ are
driven LOW. Similarly, for the x16, DQ0 (lower byte) and DQ8 (upper byte) are the prime
DQ and output the MPR data while the remaining DQ drive LOW. The MPR readout
supports fixed READ burst and READ burst chop (MRS and OTF via A12/ BC#) with
regular READ latencies and AC timings applicable, provided the DLL is locked as
required.
MPR addressing for a valid MPR read is as follows:
• A[1:0] must be set to “00” as the burst order is fixed per nibble
• A2 selects the burst order:
– BL8, A2 is set to “0,” and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7
• For burst chop 4 cases, the burst order is switched on the nibble base and:
– A2 = 0; burst order = 0, 1, 2, 3
– A2 = 1; burst order = 4, 5, 6, 7
• Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is
assigned to MSB
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
• A[9:3] are a “Don’t Care”
• A10 is a “Don’t Care”
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0
• A13 is a “Don’t Care”
• BA[2:0] are a “Don’t Care”
MPR Re g ist e r Ad d re ss De fin it io n s a n d Bu rst in g Ord e r
The MPR currently supports a single data form at. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating 0–1 bit
pattern.
Examples of the different types of predefined READ pattern bursts are shown in
Figure 62 on page 122, Figure 63 on page 123, Figure 64 on page 124, and Figure 65 on
page 125.
Ta b le 70:
MPR Re a d o u t s a n d Bu rst Ord e r Bit Ma p p in g
Bu rst
Le n g t h
Re a d
A[2:0]
MR3[2]
MR3[1:0]
Fu n ct io n
Bu rst Ord e r a n d Da t a Pa t t e rn
1
00
READ predefined
pattern for system
calibration
BL8
BC4
BC4
000
Burst order: 0, 1, 2, 3, 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
000
100
Burst order: 0, 1, 2, 3
Predefined pattern: 0, 1, 0, 1
Burst order: 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1
1
1
1
01
10
11
RFU
RFU
RFU
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Notes: 1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected
MPR agent.
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121
Fig u re 62: MPR Syst e m Re a d Ca lib ra t io n w it h BL8: Fixe d Bu rst Ord e r Sin g le Re a d o u t
T0
Ta0
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
CK#
CK
1
Command
PREA
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Valid
READ
t
t
MOD
t
t
MOD
MPRR
RP
Bank address
A[1:0]
3
0
Valid
3
2
0
Valid
2
0
A2
1
0
00
0
A[9:3]
00
0
Valid
Valid
Valid
A10/AP
A11
1
0
0
1
A12/BC#
A[15:13]
0
0
Valid
0
Valid
0
RL
DQS, DQS#
DQ
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].
Fig u re 63: MPR Syst e m Re a d Ca lib ra t io n w it h BL8: Fixe d Bu rst Ord e r, Ba ck-t o -Ba ck Re a d o u t
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
MRS
Td
CK#
CK
1
1
Command
PREA
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Valid
READ
READ
t
t
t
MPRR
t
t
MOD
CCD
RP
MOD
Bank address
A[1:0]
3
0
Valid
Valid
3
2
0
2
0
Valid
2
0
2
1
A2
1
0
00
0
A[9:3]
00
0
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A10/AP
A11
1
0
0
1
A12/BC#
A[15:13]
0
0
Valid
0
Valid
0
RL
DQS, DQS#
RL
DQ
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].
Fig u re 64: MPR Syst e m Re a d Ca lib ra t io n w it h BC4: Lo w e r Nib b le , Th e n Up p e r Nib b le
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
CK#
CK
1
1
Command
PREA
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Valid
READ
READ
t
t
MOD
t
t
CCD
t
MPRR
RF
MOD
Bank address
A[1:0]
3
0
1
Valid
Valid
3
Valid
0
2
0
2
0
3
0
4
1
A2
A[9:3]
A10/AP
A11
00
0
Valid
Valid
Valid
Valid
Valid
Valid
00
0
1
0
0
1
1
A12/BC#
0
0
Valid
Valid
Valid
A[15:13]
0
Valid
0
RL
DQS, DQS#
RL
DQ
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
4. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
Fig u re 65: MPR Syst e m Re a d Ca lib ra t io n w it h BC4: Up p e r Nib b le , Th e n Lo w e r Nib b le
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
T0
Ta
Tb
CK#
CK
1
1
Command
PREA
MRS
READ
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Valid
t
t
t
t
MOD
t
RF
CCD
MPRR
MOD
Bank address
3
0
Valid
Valid
3
2
0
2
0
A[1:0]
Valid
3
1
4
0
A2
1
0
A[9:3]
A10/AP
A11
00
0
Valid
Valid
Valid
Valid
Valid
Valid
00
0
1
0
0
1
1
A12/BC#
0
0
0
0
Valid
Valid
A[15:13]
Valid
Valid
RL
DQS, DQS#
RL
DQ
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
4. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
MPR Re a d Pre d e fin e d Pa t t e rn
The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The
following is an example of using the read out predetermined read calibration pattern.
The example is to perform multiple reads from the multipurpose register in order to do
system level read timing calibration based on the predetermined and standardized
pattern.
The following protocol outlines the steps used to perform the read calibration:
• Precharge all banks
t
• After RP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all subse-
t
quent reads and loads the predefined pattern into the MPR. As soon as MRD and
t
MOD are satisfied, the MPR is available
• Data WRITE operations are not allowed until the MPR returns to the normal DRAM
state
• Issue a read with burst order information (all other address pins are “Don’t Care”):
– A[1:0] = 00 (data burst order is fixed starting at nibble)
– A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7)
– A12 = 1 (use BL8)
• After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern
(0, 1, 0, 1, 0, 1, 0, 1)
• The memory controller repeats the calibration reads until read data capture at
memory controller is optimized
t
• After the last MPR READ burst and after MPRR has been satisfied, issue MRS,
MR3[2] = 0, and MR3[1:0] = “Don’t Care” to the normal DRAM state. All subsequent
read and write accesses will be regular reads and writes from/ to the DRAM array
t
t
• When MRD and MOD are satisfied from the last MRS, the regular DRAM commands
(such as activate a memory bank for regular read or write access) are permitted
MODE REGISTER SET (MRS)
The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode
register is programmed:
• BA2 = 0, BA1 = 0, BA0 = 0 for MR0
• BA2 = 0, BA1 = 0, BA0 = 1 for MR1
• BA2 = 0, BA1 = 1, BA0 = 0 for MR2
• BA2 = 0, BA1 = 1, BA0 = 1 for MR3
The MRS command can only be issued (or reissued) when all banks are idle and in the
t
precharged state ( RP is satisfied and no data bursts are in progress). The controller must
t
wait the specified time MRD before initiating a subsequent operation such as an ACTI-
VATE command (see Figure 52 on page 108). There is also a restriction after issuing an
MRS command with regard to when the updated functions become available. This
t
t
t
parameter is specified by MOD. Both MRD and MOD parameters are shown in
Figure 52 on page 108 and Figure 53 on page 109. Violating either of these requirements
will result in unspecified operation.
ZQ CALIBRATION
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON)
and ODT values (RTT) over process, voltage, and temperature, provided a dedicated
240Ω (±1 percent) external resistor is connected from the DRAM’s ZQ ball to VSSQ.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
DDR3 SDRAM need a longer tim e to calibrate RON and ODT at power-up initialization
and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3
SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL)
and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ calibration timing is shown in
Figure 66.
t
All banks must be precharged and RP must be met before ZQCL or ZQCS commands
can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS
command may be issued to another DRAM) can be performed on the DRAM channel by
t
t
the controller for the duration of ZQINIT or ZQOPER . The quiet time on the DRAM
channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved,
the DRAM should disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must not
t
t
t
allow overlap of ZQINIT, ZQOPER, or ZQCS between ranks.
Fig u re 66: ZQ Ca lib ra t io n Tim in g (ZQCL a n d ZQCS)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
CK#
CK
Command
Address
A10
ZQCL
NOP
NOP
NOP
Valid
Valid
Valid
Valid
Valid
Valid
ZQCS
NOP
NOP
NOP
Valid
Valid
Valid
CKE
1
2
Valid
Valid
Valid
Valid
Valid
Valid
1
2
ODT
Activ-
ities
DQ
3
High-Z
Activities
3
High-Z
t
t
t
ZQINIT or ZQOPER
ZQCS
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.
ACTIVATE
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE
command, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may be
t
issued to that row, subject to the RCD specification. However, if the additive latency is
t
programmed correctly, a READ or WRITE command may be issued prior to RCD (MIN).
In this operation, the DRAM enables a READ or WRITE command to be issued after the
t
ACTIVATE command for that bank, but prior to RCD (MIN) with the requirement that
t
(ACTIVATE-to-READ/ WRITE) + AL ≥ RCD (MIN) (see "POSTED CAS ADDITIVE Latency
t
(AL)" on page 115). RCD (MIN) should be divided by the clock period and rounded up
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127
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
to the next whole number to determine the earliest clock edge after the ACTIVATE
command on which a READ or WRITE command can be entered. The same procedure is
used to convert other specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command delay or WRITE-to-
t
WRITE command delay is restricted to CCD (MIN).
A subsequent ACTIVATE command to a different row in the same bank can only be
issued after the previous active row has been closed (precharged). The minimum time
t
interval between successive ACTIVATE commands to the same bank is defined by RC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVATE commands to different banks is defined by
t
RRD. No more than four bank ACTIVATE commands may be issued in a given
t
t
t
FAW (MIN) period, and the RRD (MIN) restriction still applies. The FAW (MIN) param-
eter applies, regardless of the number of banks already opened or closed.
t
t
Fig u re 67: Exa m p le : Me e t in g RRD (MIN) a n d RCD (MIN)
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
CK#
CK
Command
Address
BA[2:0]
ACT
Row
NOP
NOP
ACT
Row
NOP
NOP
NOP
NOP
NOP
RD/WR
Col
Bank x
Bank y
Bank y
t
t
RCD
RRD
Indicates A Break in
Time Scale
Don’t Care
t
Fig u re 68: Exa m p le : FAW
T0
T1
T4
T5
T8
T9
T10
T11
T19
T20
CK#
CK
Command
Address
ACT
Row
NOP
ACT
Row
NOP
ACT
NOP
ACT
Row
NOP
NOP
ACT
Row
Row
BA[2:0]
Bank a
Bank b
Bank c
Bank d
Bank e
t
RRD
t
FAW
Indicates A Break in
Time Scale
Don’t Care
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128
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
READ
READ bursts are initiated with a READ command. The starting column and bank
addresses are provided with the READ command and auto precharge is either enabled
or disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of POSTED CAS ADDI-
TIVE latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is
programmable in the mode register via the MRS command. Each subsequent data-out
element will be valid nominally at the next positive or negative clock edge (that is, at the
next crossing of CK and CK#). Figure 69 shows an example of RL based on a CL setting of
8 and an AL setting of 0.
Fig u re 69: READ La t e n cy
T0
T7
T8
T9
T10
T11
T12
T12
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank a,
Col n
Address
CL = 8, AL = 0
DQS, DQS#
DO
n
DQ
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. DO n = data-out from column n.
2. Subsequent elements of data-out appear in the programmed order following DO n.
DQS, DQS# is driven by the DRAM along with the output data. The initial low state on
t
DQS and HIGH state on DQS# is known as the READ preamble ( RPRE). The low state on
DQS and the HIGH state on DQS#, coincident with the last data-out element, is known
t
as the READ postamble ( RPST). Upon completion of a burst, assuming no other
t
commands have been initiated, the DQ will go High-Z. A detailed explanation of DQSQ
t
(valid data-out skew), QH (data-out window hold), and the valid data window are
t
depicted in Figure 80 on page 137. A detailed explanation of DQSCK (DQS transition
skew to CK) is also depicted in Figure 80 on page 137.
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
t
issued CCD cycles after the first READ command. This is shown for BL8 in Figure 70 on
t
page 131. If BC4 is enabled, CCD must still be met which will cause a gap in the data
output, as shown in Figure 71 on page 131. Nonconsecutive read data is reflected in
Figure 72 on page 132. DDR3 SDRAM do not allow interrupting or truncating any READ
burst.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in
Figure 73 on page 132 (BC4 is shown in Figure 74 on page 133). To ensure the read data
is completed before the write data is on the bus, the minimum READ-to-WRITE timing
t
t
is RL + CCD - WL + 2 CK.
A READ burst may be followed by a PRECHARGE command to the same bank provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank is four clocks and must also satisfy a minimum analog time
t
t
from the READ command. This time is called RTP (READ-to-PRECHARGE). RTP starts
AL cycles later than the READ command. Examples for BL8 are shown in Figure 75 on
page 133 and BC4 in Figure 76 on page 134. Following the PRECHARGE command, a
t
subsequent command to the same bank cannot be issued until RP is met. The
PRECHARGE command followed by another PRECHARGE command to the same bank
is allowed. However, the precharge period will be determined by the last PRECHARGE
command issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DRAM starts an auto precharge operation on the rising edge which is AL
t
t
+ RTP cycles after the READ command. DRAM support a RAS lockout feature (see
t
Figure 78 on page 134). If RAS (MIN) is not satisfied at the edge, the starting point of the
auto precharge operation will be delayed until RAS (MIN) is satisfied. If RTP (MIN) is
not satisfied at the edge, the starting point of the auto precharge operation will be
delayed until RTP (MIN) is satisfied. In case the internal precharge is pushed out by
RTP, RP starts at the point at which the internal precharge happens (not at the next
rising clock edge after this event). The time from READ with auto precharge to the next
ACTIVATE command to the same bank is AL + ( RTP + RP)*, where “*” means rounded
up to the next integer. In any event, internal precharge does not start earlier than four
clocks after the last 8n-bit prefetch.
t
t
t
t
t
t
t
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Fig u re 70: Co n se cu t ive READ Bu rst s (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
1
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
CCD
Bank,
Bank,
2
Address
Col n
Col b
t
t
RPRE
RPST
DQS, DQS#
DO
DO
+ 1
DO
+ 2
DO
+ 3
DO
+ 4
DO
+ 5
DO
+ 6
DO
+ 7
DO
DO
+ 1
DO
+ 2
DO
+ 3
DO
+ 4
DO
+ 5
DO
+ 6
DO
b + 7
3
DQ
n
n
n
n
n
n
n
n
b
b
b
b
b
b
b
RL = 5
RL = 5
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BL8, RL = 5 (CL = 5, AL = 0).
Fig u re 71: Co n se cu t ive READ Bu rst s (BC4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
1
Command
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
CCD
Bank,
Col n
Bank,
Col b
2
Address
t
t
t
t
RPST
RPRE
RPST
RPRE
DQS, DQS#
3
DO
DO
DO
DO
DO
DO
b + 1
DO
DO
DQ
n
n + 1
n + 2
n + 3
b
b + 2
b + 3
RL = 5
RL = 5
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BC4, RL = 5 (CL = 5, AL = 0).
Fig u re 72: No n co n se cu t ive READ Bu rst s
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank a,
Bank a,
Address
Col n
Col b
CL = 8
CL = 8
DQS, DQS#
DO
DO
DQ
n
b
Transitioning Data
Don’t Care
Notes: 1. AL = 0, RL = 8.
2. DO n (or b) = data-out from column n (or column b).
3. Seven subsequent elements of data-out appear in the programmed order following DO n.
4. Seven subsequent elements of data-out appear in the programmed order following DO b.
Fig u re 73: READ (BL8) t o WRITE (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
1
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
WR
t
t
t
BL = 4 clocks
READ-to-WRITE command delay = RL + CCD + 2 CK - WL
t
WTR
Bank,
Bank,
2
Address
Col n
Col b
t
t
t
WPRE
t
RPRE
RPST
WPST
DQS, DQS#
DO
DO
n + 1
DO
DO
n + 3
DO
DO
n + 5
DO
DO
DI
DI
DI
DI
DI
DI
DI
DI
n + 7
3
DQ
n
n + 2
n + 4
n + 6
n + 7
n
n + 1
n + 2 n + 3
n + 4
n + 5
n + 6
RL = 5
WL = 5
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and
the WRITE command at T6.
3. DO n = data-out from column, DI b = data-in for column b.
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Fig u re 74: READ (BC4) t o WRITE (BC4) OTF
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
1
READ
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
WR
t
t
t
BL = 4 clocks
READ-to-WRITE command delay = RL + CCD/2 + 2 CK - WL
t
WTR
Bank,
Col n
Bank,
2
Address
Col b
t
t
t
t
RPRE
RPST
WPRE
WPST
DQS, DQS#
DO
DO
n + 1
DO
DO
DI
DI
DI
DI
3
DQ
n
n + 2
n + 3
n
n + 1
n + 2
n + 3
RL = 5
WL = 5
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4.
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Fig u re 75: READ t o PRECHARGE (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
PRE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
NOP
NOP
NOP
NOP
Bank a,
Col n
Bank a,
Bank a,
Address
(or all)
Row b
t
t
RTP
RP
DQS, DQS#
DO
DO
+ 1
DO
+ 2
DO
+ 3
DO
+ 4
DO
+ 5
DO
+ 6
DO
+ 7
DQ
n
n
n
n
n
n
n
n
t
RAS
Transitioning Data
Don’t Care
Fig u re 76: READ t o PRECHARGE (BC4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
PRE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
NOP
NOP
NOP
NOP
Bank a,
Bank a,
(or all)
Bank a,
Address
Col n
Row b
t
RP
t
RTP
DQS, DQS#
DO
DO
+ 1
DO
+ 2
DO
+ 3
DQ
n
n
n
n
t
RAS
Transitioning Data
Don’t Care
Fig u re 77: READ t o PRECHARGE (AL = 5, CL = 6)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
PRE
NOP
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
Bank a,
Col n
Bank a,
(or all)
Bank a,
Row b
Address
t
t
AL = 5
RTP
RP
DQS, DQS#
DO
n
DO
+ 1
DO
+ 2
DO
+ 3
DQ
n
n
n
CL = 6
t
RAS
Transitioning Data
Don’t Care
Fig u re 78: READ w it h Au t o Pre ch a rg e (AL = 4, CL = 6)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Ta0
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
Bank a,
Col n
Bank a,
Address
Row
b
t
AL = 4
RTP (MIN)
DQS, DQS#
DO
DO
DO
DO
+ 3
DQ
n
n
+ 1
n
+ 2
n
CL = 6
t
t
RAS (MIN)
RP
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
A DQS to DQ output timing is shown in Figure 79 on page 136. The DQ transitions
t
between valid data outputs must be within DQSQ of the crossing point of DQS, DQS#.
t
t
DQS must also maintain a minimum HIGH and LOW time of QSH and QSL. Prior to the
READ preamble, the DQ balls will either be floating or terminated depending on the
status of the ODT signal.
Figure 80 on page 137 shows the strobe-to-clock timing during a READ. The crossing
t
point DQS, DQS# must transition within ± DQSCK of the clock crossing point. The data
out has no timing relationship to clock, only to DQS, as shown in Figure 80 on page 137.
Figure 80 on page 137 also shows the READ preamble and postamble. Normally, both
DQS and DQS# are High-Z to save power (VDDQ). Prior to data output from the DRAM,
t
DQS is driven LOW and DQS# is HIGH for RPRE. This is known as the READ preamble.
t
The READ postamble, RPST, is one half clock from the last DQS, DQS# transition.
During the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete,
the DQ will either be disabled or will continue terminating depending on the state of the
t
ODT signal. Figure 85 on page 140 demonstrates how to measure RPST.
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t
Fig u re 79: Da t a Ou t p u t Tim in g – DQSQ a n d Da t a Va lid Win d o w
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
1
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
RL = AL + CL
Bank,
2
Address
Col n
t
DQSQ (MAX)
t
RPST
t
DQSQ (MAX)
t
t
HZ (DQ) MAX
LZ (DQ) MIN
DQS, DQS#
t
t
t
RPRE
QH
DO
QH
DO
3
DO
n + 1
DO
n + 2
DO
n + 4
DO
n + 5
DO
DO
n + 7
DQ (last data valid)
n + 3
n + 6
n
3
DO
DO
DO
DO
DO
DO
DO
DO
DQ (first data no longer valid)
All DQ collectively
n
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
DO
DO
DO
DO
DO
DO
DO
DO
n + 7
n
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
Data valid
Data valid
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0.
3. DO n = data-out from column n.
4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to VDDQ/2 and DLL on and locked.
6. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late)
within a burst.
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
t
t
HZ and LZ transitions occur in the same access time as valid data transitions. These
parameters are referenced to a specific voltage level which specifies when the device
t
t
t
output is no longer driving HZ (DQS) and HZ (DQ) or begins driving LZ (DQS),
t
LZ (DQ). Figure 81 shows a method to calculate the point when the device is no longer
driving HZ (DQS) and HZ (DQ) or begins driving LZ (DQS), LZ (DQ) by measuring the
signal at two different voltages. The actual voltage measurement points are not critical
as long as the calculation is consistent. The parameters LZ (DQS), LZ (DQ), HZ (DQS),
and HZ (DQ) are defined as single-ended.
t
t
t
t
t
t
t
t
Fig u re 80: Da t a St ro b e Tim in g – READs
RL measured
to this point
T0
T1
T2
T3
T4
T5
T6
CK
CK#
t
t
t
t
t
HZ (DQS) MIN
DQSCK (MIN)
DQSCK (MIN)
DQSCK (MIN)
DQSCK (MIN)
t
LZ (DQS) MIN
t
t
t
t
QSL
QSH
QSL
QSH
DQS, DQS#
early strobe
t
t
RPST
RPRE
Bit 0
Bit 1
DQSCK (MAX)
Bit 2
Bit 3
DQSCK (MAX)
Bit 4
Bit 5
DQSCK (MAX)
Bit 6
Bit 7
DQSCK (MAX)
t
HZ (DQS) MAX
t
t
t
t
t
LZ (DQS) MAX
t
RPST
DQS, DQS#
late strobe
t
t
t
t
QSL
QSH
QSL
QSH
t
RPRE
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
t
t
Fig u re 81: Me t h o d fo r Ca lcu la t in g LZ a n d HZ
VOH - xmV
VTT + 2xmV
VTT + xmV
VOH - 2xmV
t
t
t
t
LZ (DQS), LZ (DQ)
HZ (DQS), HZ (DQ)
VTT - xmV
VOL + 2xmV
VOL + xmV
T1
T2
VTT - 2xmV
T1
T2
t
t
t
t
LZ (DQS), LZ (DQ) begin point = 2 × T1 - T2
HZ (DQS), HZ (DQ) end point = 2 × T1 - T2
t
t
Notes: 1. Within a burst, the rising strobe edge is not necessarily fixed at DQSCK (MIN) or DQSCK
t
t
(MAX). Instead, the rising strobe edge can vary between DQSCK (MIN) and DQSCK (MAX).
2. The DQS high pulse width is defined by tQSH, and the DQS low pulse width is defined by
t
t
tQSL. Likewise, tLZ (DQS) MIN and HZ (DQS) MIN are not tied to DQSCK (MIN) (early strobe
t
t
t
case) and LZ (DQS) MAX and HZ (DQS) MAX are not tied to DQSCK (MAX) (late strobe
case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The minimum
pulse width of the READ postamble is defined by tRPST (MIN).
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
t
Fig u re 82: RPRE Tim in g
CK
VTT
VTT
CK#
t
t
B
A
DQS
Single-ended signal provided
as background information
t
t
C
D
VTT
DQS#
Single-ended signal provided
as background information
T1
t
RPRE begins
t
RPRE
DQS - DQS#
0V
T2
Resulting differential
signal relevant for
RPRE specification
t
RPRE ends
t
t
Fig u re 83: RPST Tim in g
CK
VTT
CK#
t
A
DQS
VTT
t
Single-ended signal, provided
as background information
B
t
C
t
D
DQS#
VTT
Single-ended signal, provided
as background information
t
RPST
DQS - DQS#
0V
Resulting differential
signal relevant for
RPST specification
T1
t
RPST begins
T2
t
t
RPST ends
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138
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
WRITE
WRITE bursts are initiated with a WRITE command. The starting column and bank
addresses are provided with the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in
Figure 86 on page 141 through Figure 94 on page 146, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered on a rising edge of DQS
following the WRITE latency (WL) clocks later and subsequent data elements will be
registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
POSTED CAS ADDITIVE latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL.
The values of AL and CWL are programmed in the MR0 and MR2 registers, respectively.
Prior to the first valid DQS edge, a full cycle is needed (including a dummy crossover of
DQS, DQS#) and specified as the WRITE preamble shown in Figure 86 on page 141. The
half cycle on DQS following the last data-in element is known as the WRITE postamble.
The time between the WRITE command and the first valid edge of DQS is WL clocks
t
± DQSS. Figure 87 on page 142 through Figure 94 on page 146 show the nominal case
t
t
where DQSS = 0ns; however, Figure 86 on page 141 includes DQSS (MIN) and
t
DQSS (MAX) cases.
Data may be masked from completing a WRITE using data mask. The mask occurs on
the DM ball aligned to the write data. If DM is LOW, the write completes normally. If DM
is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
t
provide a continuous flow of input data. The new WRITE command can be CCD clocks
following the previous WRITE command. The first data element from the new burst is
applied after the last element of a completed burst. Figures 87 and 88 on page 142 show
concatenated bursts. An example of nonconsecutive WRITEs is shown in Figure 89 on
page 143.
t
Data for any WRITE burst may be followed by a subsequent READ command after WTR
has been met (see Figures 90 and 91 on page 144 and Figure 92 on page 145).
Data for any WRITE burst may be followed by a subsequent PRECHARGE command
t
providing WR has been met, as shown in Figure 93 on page 146 and Figure 94 on
page 146.
t
t
Both WTR and WR starting time may vary depending on the mode register settings
(fixed BC4, BL8 vs. OTF).
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
t
Fig u re 84: WPRE Tim in g
CK
VTT
CK#
T1
t
WPRE begins
0V
DQS - DQS#
t
WPRE
T2
Resulting differential
signal relevant for
t
WPRE ends
t
WPRE specification
t
Fig u re 85: WPST Tim in g
CK
VTT
CK#
t
WPST
DQS - DQS#
0V
T1
Resulting differential
signal relevant for
WPST specification
t
WPST begins
t
T2
t
WPST ends
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140
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 86: Writ e Bu rst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
WL = AL + CWL
Bank,
2
Address
Col n
t
t
t
t
t
DQSS
DSH
DSH
DSH
DSH
t
t
t
WPRE
t
WPST
DQSL
t
DQSS (MIN)
DQS, DQS#
t
t
t
t
t
t
t
t
DQSL
DQSH
DQSH
DQSL DQSH
DQSL DQSH
DQSL DQSH
DI
DI
n + 1
DI
DI
DI
DI
DI
DI
n + 7
3
DQ
n
n + 2
n + 3
n + 4
n + 5
n + 6
t
t
t
t
DSH
DSH
DSH
DSH
t
t
t
WPRE
t
WPST
t
DQSS (NOM)
DQS, DQS#
t
t
t
t
t
t
t t
DQSL DQSH
DQSL
DQSH
DQSL
DQSH
DQSL DQSH
DQSL DQSH
t
t
t
t
t
DSS
DSS
DSS
DSS
DSS
DI
DI
DI
n + 2
DI
n + 3
DI
n + 4
DI
n + 5
DI
DI
n + 7
3
DQ
n
n + 1
n + 6
t
DQSS
t
t
WPRE
t
t
WPST
DQSS (MAX)
DQS, DQS#
t
t
t
t
t
t
t
t
t
t
t
t
DQSL
DQSH
DQSL
DQSH
DQSL DQSH
DQSL DQSH
DQSL DQSH
t
t
DSS
DSS
DSS
DSS
DSS
DI
DI
n + 1
DI
DI
n + 3
DI
DI
n + 5
DI
DI
3
DQ
n
n + 2
n + 4
n + 6
n + 7
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the
WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5. tDQSS must be met at each rising clock edge.
t
6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, WPST actually
ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
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141
Fig u re 87: Co n se cu t ive WRITE (BL8) t o WRITE (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
Command
t
t
t
t
BL = 4 clocks
WR
WTR
CCD
2
Valid
Valid
Address
t
WPST
t
WPRE
DQS, DQS#
DI
DI
+ 1
DI
DI
+ 3
DI
DI
+ 5
DI
DI
+ 7
DI
DI
+ 1
DI
DI
+ 3
DI
+ 4
DI
+ 5
DI
DI
+ 7
3
DQ
n
n
n
n
+ 4
n
n
+ 6
n
b
b
b
+ 2
b
b
b
b
+ 6
b
n
+ 2
WL = 5
WL = 5
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at
T0 and T4.
3. DI n (or b) = data-in for column n (or column b).
4. BL8, WL = 5 (AL = 0, CWL = 5).
Fig u re 88: Co n se cu t ive WRITE (BC4) t o WRITE (BC4) via MRS o r OTF
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
1
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
t
t
t
CCD
BL = 4 clocks
WR
WTR
2
Valid
Valid
Address
t
t
t
t
WPST
WPRE
WPST
WPRE
DQS, DQS#
DI
DI
+ 1
DI
DI
+ 3
DI
DI
+ 1
DI
DI
+ 3
3
DQ
n
n
n
+ 2
n
b
b
b
+ 2
b
WL = 5
WL = 5
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. BC4, WL = 5 (AL = 0, CWL = 5).
3. DI n (or b) = data-in for column n (or column b).
4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
Fig u re 89: No n co n se cu t ive WRITE t o WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
WRITE
NOP
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Valid
Valid
WL = CWL + AL = 7
WL = CWL + AL = 7
DQS, DQS#
DI
DI
+ 1
DI
+ 2
DI
+ 3
DI
+ 4
DI
+ 5
DI
DI
+ 7
DI
DI
+ 1
DI
DI
+ 3
DI
DI
+ 5
DI
DI
+ 7
DQ
n
n
n
n
n
n
n
+ 6
n
b
b
b
+ 2
b
b
+ 4
b
b
+ 6
b
DM
Transitioning Data
Don't Care
Notes: 1. DI n (or b) = data-in for column n (or column b).
2. Seven subsequent elements of data-in are applied in the programmed order following DO n.
3. Each WRITE command may be to any bank.
4. Shown for WL = 7 (CWL = 7, AL = 0).
Fig u re 90: WRITE (BL8) t o READ (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Ta0
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
Command
t
2
WTR
3
Valid
Valid
Address
t
t
WPST
WPRE
DQS, DQS#
DI
DI
n + 1
DI
DI
n + 3
DI
DI
n + 5
DI
DI
n + 7
4
DQ
n
n + 2
n + 4
n + 6
WL = 5
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write
data shown at T9.
3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0.
The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.
4. DI n = data-in for column n.
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Fig u re 91: WRITE t o READ (BC4 Mo d e Re g ist e r Se t t in g )
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
Command
t
2
WTR
Valid
3
Valid
Address
t
t
WPST
WPRE
DQS, DQS#
DI
DI
n + 1
DI
DI
n + 3
4
DQ
n
n + 2
WL = 5
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write
data shown at T7.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
Fig u re 92: WRITE (BC4 OTF) t o READ (BC4 OTF)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Tn
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
Command
t
t
WTR
2
BL = 4 clocks
3
Valid
Valid
Address
t
t
WPST
WPRE
DQS, DQS#
DI
DI
n + 1
DI
DI
n + 3
4
DQ
n
n + 2
WL = 5
RL = 5
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
t
2. tWTR controls the WRITE-to-READ delay to the same device and starts after BL.
3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ command
at Tn.
4. DI n = data-in for column n.
5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 93: WRITE (BL8) t o PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
CK#
CK
Command
Address
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Valid
Valid
t
WR
WL = AL + CWL
DQS, DQS#
DI
DI
DI
DI
DI
DI
DI
DI
DQ BL8
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. DI n = data-in from column n.
2. Seven subsequent elements of data-in are applied in the programmed order following
DO n.
3. Shown for WL = 7 (AL = 0, CWL = 7).
Fig u re 94: WRITE (BC4 Mo d e Re g ist e r Se t t in g ) t o PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
CK#
CK
Command
Address
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Valid
Valid
t
WR
WL = AL + CWL
DQS, DQS#
DQ BC4
DI
DI
DI
DI
n
n + 1 n + 2 n + 3
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. The write recovery time (tWR) is referenced from the first rising clock edge after the last
t
write data is shown at T7. WR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
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146
1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 95: WRITE (BC4 OTF) t o PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Command
t
2
WR
Bank,
3
Valid
Address
Col n
t
t
WPST
WPRE
DQS, DQS#
DI
DI
n + 1
DI
DI
n + 3
4
DQ
n
n + 2
WL = 5
Indicates A Break In
Time Scale
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
t
2. The write recovery time (tWR) is referenced from the rising clock edge at T9. WR specifies
the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
DQ In p u t Tim in g
Figure 86 on page 141 shows the strobe to clock timing during a WRITE. DQS, DQS#
t
t
must transition within 0.25 CK of the clock transitions as limited by DQSS. All data and
data mask setup and hold timings are measured relative to the DQS, DQS# crossing, not
the clock crossing.
The WRITE preamble and postamble are also shown. One clock prior to data input to the
DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is driven
t
LOW (DQS# is driven HIGH) during the WRITE preamble, WPRE. Likewise, DQS must
be kept LOW by the controller after the last data is written to the DRAM during the
t
WRITE postamble, WPST.
Data setup and hold times are shown in Figure 96 on page 148. All setup and hold times
are measured from the crossing points of DQS and DQS#. These setup and hold values
pertain to data input and data mask input.
t
t
Additionally, the half period of the data input strobe is specified by DQSH and DQSL.
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Op e ra t io n s
Fig u re 96: Da t a In p u t Tim in g
DQS, DQS#
t
t
t
t
WPRE
DQSH
DQSL
WPST
DI
b
DQ
DM
t
DS
t
DH
Transitioning Data
Don’t Care
PRECHARGE
Input A10 determines whether one bank or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
SELF REFRESH
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.
t
The DRAM must be idle with all banks in the precharge state ( RP is satisfied and no
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see “On-Die Termination (ODT)” on page 160 for timing
requirem ents). If RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a
“Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW
to keep the DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, become “Don’t Care.” The DRAM initiates a minimum of one REFRESH
t
command internally within the CKE period when it enters self refresh mode.
The requirements for entering and exiting self refresh mode depend on the state of the
t
clock during self refresh mode. First and foremost, the clock must be stable (meeting CK
specifications) when self refresh mode is entered. If the clock remains stable and the
frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self
t
t
refresh mode after CKESR is satisfied (CKE is allowed to transition HIGH CKESR later
than when CKE was registered LOW). Since the clock remains stable in self refresh mode
t
t
(no frequency change), CKSRE and CKSRX are not required. However, if the clock is
altered during self refresh mode (turned-off or frequency change), then CKSRE and
CKSRX must be satisfied. When entering self refresh mode, CKSRE must be satisfied
prior to altering the clock's frequency. Prior to exiting self refresh mode, CKSRX must be
satisfied prior to registering CKE HIGH.
t
t
t
t
t
t
When CKE is HIGH during self refresh exit, NOP or DES must be issued for XS time. XS
is required for the completion of any internal refresh that is already in progress and must
be satisfied before a valid command not requiring a locked DLL can be issued to the
t
device. XS is also the earliest time self refresh reentry may occur (see Figure 97 on
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Op e ra t io n s
page 149). Before a command requiring a locked DLL can be applied, a ZQCL command
t
t
must be issued, ZQOPER timing must be met, and XSDLL must be satisfied. ODT must
t
be off during XSDLL.
Fig u re 97: Se lf Re fre sh En t ry/Exit Tim in g
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf0
CK#
CK
t
1
CKSRX
t
1
CKSRE
t
t
t
t
IS
IS
IH
CPDED
CKE
Valid
Valid
Valid
t
1
CKESR (MIN)
t
IS
2
ODT
ODTL
NOP
2
RESET#
5
3
4
6
7
Command
Address
NOP
SRX (NOP)
SRE (REF)
NOP
Valid
Valid
Valid
Valid
t
t
6, 9
XS
8
t
RP
7, 9
XSDLL
Enter self refresh mode
(synchronous)
Exit self refresh mode
(asynchronous)
Indicates A Break in
Time Scale
Don’t Care
t
t
Notes: 1. The clock must be valid and stable meeting CK specifications at least CKSRE after entering
t
self refresh mode, and at least CKSRX prior to exiting self refresh mode, if the clock is
stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged
t
t
from entry and during self refresh mode, then CKSRE and CKSRX do not apply; however,
tCKESR must be satisfied prior to exiting at SRX.
2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both RTT_NOM
and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care.”
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
inputs becoming “Don’t Care.”
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6. tXS is required before any commands not requiring a locked DLL.
7. tXSDLL is required before any commands requiring a locked DLL.
8. The device must be in the all banks idle state prior to entering self refresh mode. For exam-
t
ple, all banks must be precharged, RP must be met, and no data bursts can be in progress.
t
t
9. Self refresh exit is asynchronous; however, XS and XSDLL timings start at the first rising
t
clock edge where CKE HIGH satisfies tISXR at Tc1. CKSRX timing is also measured so that
tISXR is satisfied at Tc1.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Ext e n d e d Te m p e ra t u re Usa g e
Micron’s DDR3 SDRAM support the optional extended temperature range of 0°C to 95°C,
T . Thus, the SRT and ASR options must be used at a minimum.
C
The extended temperature range DRAM must be refreshed externally at 2X (double
refresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The
external refreshing requirement is accomplished by reducing the refresh period from
64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the
extended temperature. Thus either ASR or SRT must be enabled when T is above 85°C
C
or self refresh cannot be used until the case temperature is at or below 85°C. Table 71
summarizes the two extended temperature options and Table 72 summarizes how the
two extended temperature options relate to one another.
Ta b le 71:
Fie ld
Se lf Re fre sh Te m p e ra t u re a n d Au t o Se lf Re fre sh De scrip t io n
MR2 Bit s
De scrip t io n
Self Refresh Temperature (SRT)
SRT
7
If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh:
*MR2[7] = 0: Normal operating temperature range (0°C to 85°C)
*MR2[7] = 1: Extended operating temperature range (0°C to 95°C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is
supported
*MR2[7] = 0: SRT is disabled
Auto Self Refresh (ASR)
ASR
6
When ASR is enabled, the DRAM automatically provides SELF REFRESH power management
functions, (refresh rate for all supported operating temperature values)
* MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH
operation
* MR2[6] = 0: ASR is disabled, must use manual self refresh temperature (SRT)
Ta b le 72:
Se lf Re fre sh Mo d e Su m m a ry
MR2[6] MR2[7]
Pe rm it t e d Op e ra t in g Te m p e ra t u re
Ra n g e fo r Se lf Re fre sh Mo d e
(ASR)
(SRT) SELF REFRESH Op e ra t io n
0
0
0
1
Self refresh mode is supported in the normal temperature range Normal (0°C to 85°C)
Self refresh mode is supported in normal and extended
temperature ranges; When SRT is enabled, it increases self
refresh power consumption
Normal and extended (0°C to 95°C)
1
1
0
1
Self refresh mode is supported in normal and extended
temperature ranges; Self refresh power consumption may be
temperature-dependent
Normal and extended (0°C to 95°C)
Illegal
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Op e ra t io n s
Po w e r-Do w n Mo d e
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR,
ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of
the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or
REFRESH) are in progress. However, the power-down IDD specifications are not appli-
cable until such operations have been completed. Depending on the previous DRAM
state and the command issued prior to CKE going LOW, certain timing constraints must
be satisfied (as noted in Table 73). Timing diagrams detailing the different power-down
mode entry and exits are shown in Figure 98 on page 152 through Figure 107 on
page 157.
Ta b le 73:
Co m m a n d t o Po w e r-Do w n En t ry Pa ra m e t e rs
La st Co m m a n d Prio r t o
CKE LOW1
DRAM St a t u s
Pa ra m e t e r (Min )
Pa ra m e t e r Va lu e
Fig u re
Idle or active
Idle or active
Active
ACTIVATE
PRECHARGE
tACTPDEN
tPRPDEN
tRDPDEN
tWRPDEN
1tCK
1tCK
RL + 4tCK + 1tCK
Figure 105 on page 156
Figure 106 on page 156
Figure 101 on page 154
Figure 102 on page 154
READ or READAP
t
Active
WRITE: BL8OTF, BL8MRS,
BC4OTF
WL + 4tCK + WR/tCK
t
Active
Active
WRITE: BC4MRS
WL + 2tCK + WR/tCK
Figure 102 on page 154
Figure 103 on page 155
WRITEAP: BL8OTF, BL8MRS,
BC4OTF
tWRAPDEN
WL + 4tCK + WR + 1tCK
Active
Idle
WRITEAP: BC4MRS
REFRESH
WL + 2tCK + WR + 1tCK
1tCK
Greater of 10tCK or 24ns
tMOD
Figure 103 on page 155
Figure 104 on page 155
Figure 108 on page 157
Figure 107 on page 157
tREFPDEN
tXPDLL
tMRSPDEN
Power-down
Idle
REFRESH
MODE REGISTER SET
Notes: 1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchro-
t
nous tANPD prior to CKE going LOW and remains asynchronous until tANPD + XPDLL after
CKE goes HIGH.
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
t
CKE, and RESET#. NOP or DES commands are required until CPDED has been satisfied,
at which time all specified input/ output buffers will be disabled. The DLL should be in a
locked state when power-down is entered for the fastest power-down exit timing. If the
DLL is not locked during power-down entry, the DLL must be reset after exiting power-
down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down mode.
Precharge power-down mode must be programmed to exit with either a slow exit mode
or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in
slow exit mode or kept on in fast exit mode.
The DLL remains on when entering active power-down as well. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to “Asynchronous ODT Mode” on page 172 for detailed ODT usage requirements in slow
exit mode precharge power-down. A summary of the two power-down modes is listed in
Table 74 on page 152.
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Op e ra t io n s
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are a “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
t
remain LOW until PD (MIN) has been satisfied. The maximum time allowed for power-
t
t
down duration is PD (MAX) (9 × REFI).
The power-down states are synchronously exited when CKE is registered HIGH (with a
t
required NOP or DES command). CKE must be maintained HIGH until CKE has been
satisfied. A valid, executable command may be applied after power-down exit latency,
t
t
XP XPDLL have been satisfied. A summary of the power-down modes is listed in
Table 74.
For certain CKE-intensive operations, for example, repeating a power-down exit to
refresh to power-down entry sequence, the number of clock cycles between power-down
exit and power-down entry may not be sufficient enough to keep the DLL properly
t
updated. In addition to meeting PD when the REFRESH command is used in between
t
power-down exit and power-down entry, two other conditions must be met. First, XP
t
must be satisfied before issuing the REFRESH command. Second, XPDLL must be satis-
fied before the next power-down may be entered. An example is shown in Figure 108 on
page 157.
Ta b le 74:
Po w e r-Do w n Mo d e s
Po w e r-Do w n
Exit
DRAM St a t e
MR1[12] DLL St a t e
Re le va n t Pa ra m e t e rs
tXP to any other valid command
Active (any bank open)
“Don’t
Care”
On
Fast
Precharged
(all banks precharged)
1
0
On
Fast
tXP to any other valid command
Off
Slow
tXPDLL to commands that require the DLL to be locked
(READ, RDAP, or ODT on)
tXP to any other valid command
Fig u re 98: Act ive Po w e r-Do w n En t ry a n d Exit
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
t
t
t
CK
CH
CL
Command
Valid
NOP
NOP
NOP
NOP
NOP
Valid
t
PD
t
IS
t
IH
CKE
t
t
t
CKE (MIN)
IH
IS
Address
Valid
Valid
t
t
CPDED
XP
Enter power-down
mode
Exit power-down
mode
Indicates A Break in
Time Scale
Don’t Care
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Op e ra t io n s
Fig u re 99: Pre ch a rg e Po w e r-Do w n (Fa st -Exit Mo d e ) En t ry a n d Exit
T0
T1
T2
T3
T4
T5
Ta0
Ta1
CK#
CK
t
t
t
CK
CH
CL
Command
NOP
NOP
NOP
NOP
NOP
Valid
t
t
CPDED
CKE (MIN)
t
IH
t
IS
CKE
t
IS
t
t
XP
PD
Enter power-down
mode
Exit power-down
mode
Indicates A Break in
Time Scale
Don’t Care
Fig u re 100: Pre ch a rg e Po w e r-Do w n (Slo w -Exit Mo d e ) En t ry a n d Exit
T0
T1
T2
T3
T4
Ta
Ta1
Tb
CK#
CK
t
t
t
CK
CH
CL
1
2
NOP
Command
PRE
NOP
NOP
NOP
Valid
Valid
t
t
CKE (MIN)
CPDED
t
XP
t
t
IH
IS
CKE
t
t
XPDLL
IS
t
PD
Enter power-down
mode
Exit power-down
mode
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Any valid command not requiring a locked DLL.
2. Any valid command requiring a locked DLL.
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Op e ra t io n s
Fig u re 101: Po w e r-Do w n En t ry Aft e r READ o r READ w it h Au t o Pre ch a rg e (RDAP)
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
Ta11
Ta12
CK#
CK
READ/
RDAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
t
CPDED
IS
CKE
Address
Valid
t
RL = AL + CL
PD
DQS, DQS#
DI
DI
DI
DI
DI
DI
DI
DI
DQ BL8
n
n + 1 n + 2 n + 3 n + 4 n+ 5 n + 6 n + 7
DI
DI
DI
DI
DQ BC4
n
n + 1 n + 2 n + 3
t
RDPDEN
Power-down or
self refresh entry
Indicates A Break In
Time Scale
Transitioning Data
Don’t Care
Fig u re 102: Po w e r-Do w n En t ry Aft e r WRITE
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
Tb3
Tb4
CK#
CK
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
t
CPDED
IS
CKE
Valid
Address
t
t
PD
WL = AL + CWL
WR
DQS, DQS#
DQ BL8
DI
n + 7
DI
DI
DI
DI
DI
DI
DI
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6
DI
DI
DI
DI
DQ BC4
n
n + 1 n + 2 n + 3
t
WRPDEN
Power-down or
self refresh entry
1
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. CKE can go LOW 2tCK earlier if BC4MRS.
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Op e ra t io n s
Fig u re 103: Po w e r-Do w n En t ry Aft e r WRITE w it h Au t o Pre ch a rg e (WRAP)
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
Tb3
Tb4
CK#
CK
WRAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
t
CPDED
IS
CKE
Address
Valid
A10
1
t
PD
WL = AL + CWL
WR
DQS, DQS#
DQ BL8
DI
n + 7
DI
DI
DI
DI
DI
DI
DI
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6
DI
DI
DI
DI
DQ BC4
n
n + 1 n + 2 n + 3
t
WRAPDEN
Start internal
precharge
Power-down or
self refresh entry
2
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
Notes: 1. tWR is programmed through MR0[11:9] and represents tWR (MIN)ns/tCK rounded up to the
t
next integer CK.
2. CKE can go LOW 2tCK earlier if BC4MRS.
Fig u re 104: REFRESH t o Po w e r-Do w n En t ry
T0
T1
T2
T3
Ta0
Ta1
Ta2
Tb0
CK#
CK
t
t
t
CL
CK
CH
NOP
Command
REFRESH
NOP
NOP
NOP
Valid
t
t
CPDED
CKE (MIN)
t
t
PD
IS
CKE
t
t
XP (MIN)
REFPDEN
t
1
RFC (MIN)
Indicates A Break In
Time Scale
Don’t Care
t
Notes: 1. After CKE goes HIGH during RFC, CKE must remain HIGH until tRFC is satisfied.
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Op e ra t io n s
Fig u re 105: ACTIVATE t o Po w e r-Do w n En t ry
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
t
t
t
CL
CK
CH
Command
Address
ACTIVE
Valid
NOP
NOP
t
CPDED
t
t
PD
IS
CKE
t
ACTPDEN
Don’t Care
Fig u re 106: PRECHARGE t o Po w e r-Do w n En t ry
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
t
t
t
CL
CK
CH
Command
Address
PRE
NOP
NOP
All/single
bank
t
CPDED
t
t
PD
IS
CKE
t
PREPDEN
Don’t Care
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Op e ra t io n s
Fig u re 107: MRS Co m m a n d t o Po w e r-Do w n En t ry
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
t
t
t
CL
t
CK
CH
CPDED
Command
Address
MRS
Valid
NOP
NOP
NOP
NOP
NOP
t
t
PD
MRSPDEN
t
IS
CKE
Indicates A Break in
Time Scale
Don’t Care
Fig u re 108: Po w e r-Do w n Exit t o Re fre sh t o Po w e r-Do w n En t ry
T0
T1
T2
T3
T4
Ta0
Ta1
Tb0
CK#
CK
t
t
t
CK
CH
CL
Command
NOP
NOP
NOP
NOP
REFRESH
NOP
NOP
t
t
1
CPDED
XP
t
IH
t
IS
CKE
t
IS
t
t
2
PD
XPDLL
Enter power-down
mode
Enter power-down
mode
Exit power-down
mode
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. tXP must be satisfied before issuing the command.
2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the
next power-down can be entered.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
RESET
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it
must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns
off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RESET#
being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though
a normal power up were executed (see Figure 109 on page 159). All refresh counters on
the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET#
has gone LOW.
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1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 109: RESET Se q u e n ce
System RESET
(warm boot)
Stable and
valid clock
Tc0
Td0
Tb0
T1
T0
Ta0
t
CK
CK#
CK
t
t
T (MIN) =
MAX (10ns, 5 CK)
CL
CL
t
T = 100ns (MIN)
t
IOZ
RESET#
t
IS
T=10ns (MIN)
Valid
Valid
CKE
Valid
MRS
Valid
MRS
Valid
ZQCL
ODT
t
IS
Valid
Command
MRS
MRS
NOP
DM
Address
A10
Code
Code
Code
Code
Code
Code
Code
Code
Valid
Valid
Valid
A10 = H
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
BA[2:0]
High-Z
High-Z
DQS
DQ
High-Z
RTT
t
t
MRD
t
t
t
MOD
T = 500µs (MIN)
MRD
XPR
MRD
MR0 with
DLL RESET
MR1 with
DLL ENABLE
MR2
MR3
ZQ CAL
t
All voltage
ZQINIT
supplies valid
and stable
DRAM ready
for external
commands
t
DLLK
Normal
operation
Don’t Care
Indicates A Break in
Time Scale
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1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
On -Die Te rm in a t io n (ODT)
ODT is a feature that enables the DRAM to enable/ disable and turn on/ off termination
resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and
TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ,
UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration.
The ODT feature is designed to improve signal integrity of the memory channel by
enabling the DRAM controller to independently turn on/ off the DRAM’s internal termi-
nation resistance for any grouping of DRAM devices. The ODT feature is not supported
during DLL disable mode. A simple functional representation of the DRAM ODT feature
is shown in Figure 110. The switch is enabled by the internal ODT control logic, which
uses the external ODT ball and other control information.
Fig u re 110: On -Die Te rm in a t io n
ODT
VDDQ/2
To other
circuitry
such as
RCV,
R
TT
Switch
DQ, DQS, DQS#,
DM, TDQS, TDQS#
. . .
Fu n ct io n a l Re p re se n t a t io n o f ODT
The value of RTT (ODT termination value) is determined by the settings of several mode
register bits (see Table 78 on page 163). The ODT ball is ignored while in self refresh
mode (must be turned off prior to self refresh entry) or if mode registers MR1 and MR2
are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT
modes and either of these can function in synchronous or asynchronous mode (when
the DLL is off during precharge power-down or when the DLL is synchronizing).
Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic
ODT is applied only during writes and provides OTF switching from no RTT or RTT_NOM
to RTT_WR.
The actual effective termination, RTT_EFF, may be different from the RTT targeted due to
nonlinearity of the termination. For RTT_EFF values and calculations, see "ODT Charac-
teristics" on page 49.
No m in a l ODT
ODT (NOM) is the base termination resistance for each applicable ball, it is enabled or
disabled via MR1[9, 6, 2] (see Figure 47 on page 61), and it is turned on or off via the ODT
ball (see Table 75 on page 161).
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1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Ta b le 75:
Tru t h Ta b le – ODT (No m in a l)
Note 1 applies to the entire table
MR1[9, 6, 2]
000
ODT Pin
DRAM Te rm in a t io n St a t e
DRAM St a t e
No t e s
0
1
RTT_NOM disabled, ODT off
RTT_NOM disabled, ODT on
RTT_NOM enabled, ODT off
RTT_NOM enabled, ODT on
RTT_NOM reserved, ODT on or off
Any valid
Any valid except self refresh, read
Any valid
2
3
2
3
000
000–101
0
000–101
1
Any valid except self refresh, read
Illegal
110 and 111
X
Notes: 1. Assumes dynamic ODT is disabled (see "Dynamic ODT" on page 162 when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal to
have it off during writes.
3. ODT must be disabled during reads. The RTT_NOM value is restricted during writes. Dynamic
ODT is applicable if enabled.
Nominal ODT resistance RTT_NOM is defined by MR1[9, 6, 2], as shown in Figure 47 on
page 61. The RTT_NOM termination value applies to the output pins previously
mentioned. DDR3 SDRAM supports multiple RTT_NOM values based on RZQ/ n where n
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. RTT_NOM termination is allowed any time after
the DRAM is initialized, calibrated, and not performing read access or when it is not in
self refresh mode.
Write accesses use RTT_NOM if dynamic ODT (RTT_WR) is disabled. If RTT_NOM is used
during writes, only RZQ/ 2, RZQ/ 4, and RZQ/ 6 are allowed (see Table 78 on page 163).
ODT timings are summarized in Table 76, as well as listed in Table 53 on page 67.
Examples of nominal ODT timing are shown in conjunction with the synchronous mode
of operation in “Synchronous ODT Mode” on page 167.
Ta b le 76:
ODT Pa ra m e t e r
De fin it io n fo r All
DDR3 Sp e e d Bin s
Sym b o l
De scrip t io n
Be g in s a t
De fin e d t o
Un it s
ODTL on
ODTL off
tAONPD
tAOFPD
ODTH4
ODT synchronous turn on delay
ODT synchronous turn off delay
ODT asynchronous turn on delay
ODT asynchronous turn off delay
ODT registered HIGH RTT_ON ±tAON
ODT registered HIGH RTT_OFF ±tAOF
CWL + AL - 2
CWL + AL - 2
1–9
tCK
tCK
ns
ODT registered HIGH
ODT registered HIGH
RTT_ON
RTT_OFF
1–9
4tCK
ns
tCK
ODT minimum HIGH time after ODT ODT registered HIGH ODTregistered
assertion or write (BC4)
or write registration
with ODT HIGH
LOW
ODTH8
tAON
tAOF
ODT minimum HIGH time after
write (BL8)
Write registration
with ODT HIGH
ODTregistered
LOW
6tCK
tCK
ps
ODT turn-on relative to ODTL on
completion
Completion of
ODTL on
RTT_ON
See Table 53 on
page 67
0.5tCK ± 0.2tCK
ODT turn-off relative to ODTL off
completion
Completion of
ODTL off
RTT_OFF
tCK
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161
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Dyn a m ic ODT
In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT (RTT_WR) enabled, the DRAM switches from nominal ODT (RTT_NOM) to
dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back
to nominal ODT (RTT_NOM) at the completion of the WRITE burst. This requirement is
supported by the dynamic ODT feature, as described below:
Fu n ct io n a l De scrip t io n
The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to “1.” Dynamic
ODT is not supported during DLL disable mode so RTT_WR must be disabled. The
dynamic ODT function is described, as follows:
• Two RTT values are available—RTT_NOM and RTT_WR:
– The value for RTT_NOM is preselected via MR1[9, 6, 2]
– The value for RTT_WR is preselected via MR2[10, 9]
• During DRAM operation without READ or WRITE commands, the termination is
controlled as follows:
– Nominal termination strength RTT_NOM is used
– Termination on/ off timing is controlled via the ODT ball and latencies ODTL on
and ODTL off
• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,
and if dynamic ODT is enabled, the ODT termination is controlled as follows:
– Alatency of ODTLCNW after the WRITE command: termination strength RTT_NOM
switches to RTT_WR
– Alatency of ODTLCWN8 (for BL8, fixed or OTF) or ODTLCWN4 (for BC4, fixed or
OTF) after the WRITE command: termination strength RTT_WR switches back to
RTT_NOM
– On/ off termination timing is controlled via the ODT ball and determined by ODTL
on, ODTL off, ODTH4, and ODTH8
t
– During the ADC transition window, the value of RTT is undefined
ODT is constrained during writes and when dynamic ODT is enabled (see Table 77).
ODT timings listed in Table 76 on page 161 also apply to dynamic ODT mode.
Ta b le 77:
Dyn a m ic ODT Sp e cific Pa ra m e t e rs
De fin it io n fo r All
DDR3 Sp e e d Bin s Un it s
Sym b o l
De scrip t io n
Be g in s a t
De fin e d t o
ODTLCNW
Change from RTT_NOM to
RTT_WR
Write registration
RTT switched from
RTT_NOM to RTT_WR
WL - 2
tCK
tCK
tCK
tCK
ODTLCWN4
ODTLCWN8
tADC
Change from RTT_WR to
RTT_NOM (BC4)
Write registration
Write registration
RTT switched from RTT_WR
to RTT_NOM
4tCK + ODTL off
6tCK + ODTL off
0.5tCK ± 0.2tCK
Change from RTT_WR to
RTT_NOM (BL8)
RTT switched from RTT_WR
to RTT_NOM
RTT change skew
ODTLCNW completed RTT transition complete
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162
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Ta b le 78:
M9
Mo d e Re g ist e rs fo r RTT_NOM
MR1 (RTT_NOM)
RTT_NOM
(RZQ)
RTT_NOM
(Oh m s)
RTT_NOM
Mo d e Re st rict io n
M6
M2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Off
Off
60
n/a
RZQ/4
Self refresh
RZQ/2
120
40
RZQ/6
RZQ/12
RZQ/8
20
Self refresh, write
30
Reserved
Reserved
Reserved
Reserved
n/a
n/a
Notes: 1. RZQ = 240Ω. If RTT_NOM is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
Ta b le 79:
Mo d e Re g ist e rs fo r RTT_WR
MR2 (RTT_WR)
RTT_WR
(RZQ)
RTT_WR
(Oh m s)
M10
M9
0
0
0
1
Dynamic ODT off: WRITE does not affect RTT_NOM
RZQ/4
RZQ/2
Reserved
n/a
60
120
1
0
1
1
Reserved
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Ta b le 80:
Tim in g Dia g ra m s fo r Dyn a m ic ODT
Fig u re a n d Pa g e
Tit le
Figure 111 on page 164
Figure 112 on page 164
Figure 113 on page 165
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Dynamic ODT: Without WRITE Command
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles,
BL8
Figure 114 on page 166
Figure 115 on page 166
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
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Fig u re 111: Dyn a m ic ODT: ODT Asse rt e d Be fo re a n d Aft e r t h e WRITE, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
NOP
NOP
NOP
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
ODTH4
ODTL off
ODTH4
ODT
ODTL on
ODTLCWN4
t
t
t
AOF (MIN)
t
ADC (MIN)
ADC (MIN)
AON (MIN)
t
RTT
R
TT_NOM
R
TT
_
WR
RTT_NOM
t
t
AOF (MAX)
t
AON (MAX)
ADC (MAX)
ADC (MAX)
ODTLCNW
DQS, DQS#
DI
DI
DI
DI
DQ
n
n + 1
n + 2
n + 3
WL
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled.
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
Fig u re 112: Dyn a m ic ODT: Wit h o u t WRITE Co m m a n d
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
Command
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
ODTH4
ODTL off
ODTL on
ODT
t
t
AON (MAX)
AOF (MIN)
t
RTT_NOM
RTT
t
AON (MIN)
AOF (MAX)
DQS, DQS#
DQ
Transitioning
Don’t Care
Notes: 1. AL = 0, CWL = 5. RTT_NOM is enabled and RTT_WR is either enabled or disabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered
LOW at T5 is also legal.
Fig u re 113: Dyn a m ic ODT: ODT Pin Asse rt e d To g e t h e r w it h WRITE Co m m a n d fo r 6 Clo ck Cycle s, BL8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
NOP
WRS8
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
Address
ODTLCNW
ODTH8
ODTLOFF
ODTLON
ODT
t
t
ADC (MAX)
AOF (MIN)
RTT_WR
RTT
t
AON (MIN)
t
AOF (MAX)
ODTLCWN
8
DQS, DQS#
WL
DI
DI
b + 1
DI
b + 2
DI
b + 3
DI
DI
DI
DI
b + 7
DQ
b
b + 4
b + 5
b + 6
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF; AL = 0, CWL = 5. If RTT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled.
2. In this example, ODTH8 = 6 is satisfied exactly.
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Fig u re 114: Dyn a m ic ODT: ODT Pin Asse rt e d w it h WRITE Co m m a n d fo r 6 Clo ck Cycle s, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
Command
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLCNW
Address
ODTH4
ODTL off
ODT
ODTL on
t
t
AOF (MIN)
t
ADC (MAX)
ADC (MIN)
RTT
RTT_WR
RTT_NOM
t
t
t
AOF (MAX)
AON (MIN)
ADC (MAX)
ODTLCWN
4
DQS, DQS#
DI
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
WL
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Fig u re 115: Dyn a m ic ODT: ODT Pin Asse rt e d w it h WRITE Co m m a n d fo r 4 Clo ck Cycle s, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
Command
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLCNW
Address
ODTL off
ODTH4
ODT
t
t
t
AOF (MIN)
AOF (MAX)
ADC (MAX)
ODTL on
RTT
R
TT
_
WR
t
AON (MIN)
ODTLCWN
4
DQS, DQS#
WL
DI
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM can be either enabled or disabled. If disabled,
ODT can remain HIGH. RTT_WR is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
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1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Syn ch ro n o u s ODT Mo d e
Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either RTT_NOM or RTT_WR is enabled. Based on the power-down definition, these
modes are:
• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled during precharge power-down by
MR0[12]
ODT La t e n cy a n d Po st e d ODT
In synchronous ODT mode, RTT turns on ODTL on clock cycles after ODT is sampled
HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered
t
t
LOW by a rising clock edge. The actual on/ off times varies by AON and AOF around
each clock edge (see Table 81 on page 168). The ODT latency is tied to the WRITE latency
(WL) by ODTL on = WL - 2 and ODTL off = WL - 2.
Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency (AL),
the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal.
The DRAM’s internal ODT signal is delayed a number of clock cycles defined by the AL
relative to the external ODT signal. Thus ODTL on = CWL + AL - 2 and ODTL
off = CWL + AL - 2.
Tim in g Pa ra m e t e rs
Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off,
t
ODTH4, ODTH8, tAON, and AOF (see Table 81 and Figure 116 on page 168). The
t
minimum RTT turn-on time ( AON [MIN]) is the point at which the device leaves High-Z
t
and ODT resistance begins to turn on. Maximum RTT turn-on time ( AON [MAX]) is the
point at which ODT resistance is fully on. Both are measured relative to ODTL on. The
t
minimum RTT turn-off time ( AOF [MIN]) is the point at which the device starts to turn
t
off ODT resistance. Maximum RTT turn off time ( AOF [MAX]) is the point at which ODT
has reached High-Z. Both are measured from ODTL off.
When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE
command is registered by the DRAM with ODT HIGH, then ODT must remain HIGH
until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 117 on
page 169). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT regis-
tered LOW or from the registration of a WRITE command until ODT is registered LOW.
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Ta b le 81:
Sym b o l
Syn ch ro n o u s ODT Pa ra m e t e rs
De scrip t io n
De fin it io n fo r All DDR3
Sp e e d Bin s
Be g in s a t
De fin e d t o
Un it s
ODTL on
ODTL off
ODTH4
ODT synchronous turn-on delay
ODT synchronous turn-off delay
ODT registered HIGH
ODT registered HIGH
RTT_ON ±tAON
RTT_OFF ±tAOF
CWL + AL - 2
CWL + AL - 2
4tCK
tCK
tCK
tCK
ODT minimum HIGH time after ODT
assertion or WRITE (BC4)
ODT registered HIGH, or
write registration with ODT
HIGH
ODT registered LOW
ODTH8
tAON
tAOF
ODT minimum HIGH time after
WRITE (BL8)
Write registration with ODT
HIGH
ODT registered LOW
RTT_ON
6tCK
tCK
ps
ODT turn-on relative to ODTL on
completion
Completion of ODTL on
See Table 53 on page 67
0.5tCK ± 0.2tCK
ODT turn-off relative to ODTL off
completion
Completion of ODTL off
RTT_OFF
tCK
Fig u re 116: Syn ch ro n o u s ODT
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
CKE
AL = 3
AL = 3
CWL - 2
ODT
ODTH4 (MIN)
ODTL off = CWL + AL - 2
ODTL on = CWL + AL - 2
t
t
AON (MIN)
t
AOF (MIN)
t
RTT
RTT_NOM
AON (MAX)
AOF (MAX)
Transitioning
Don’t Care
Notes: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. RTT_NOM is enabled.
Fig u re 117: Syn ch ro n o u s ODT (BC4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
CKE
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTH4 (MIN)
ODTH4
ODTH4
ODT
ODTL off = WL - 2
ODTLoff = WL - 2
ODTL on = WL - 2
ODTL on = WL - 2
t
t
t
t
AON (MAX)
AON (MIN)
AOF (MIN)
AOF (MIN)
RTT
RTT_NOM
RTT_NOM
t
t
t
t
AOF (MAX)
AOF (MAX)
AON (MAX)
AON (MIN)
Transitioning
Don’t Care
Notes: 1. WL = 7. RTT_NOM is enabled. RTT_WR is disabled.
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE
command with ODT HIGH to ODT registered LOW.
5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be
satisfied from the registration of the WRITE command at T7.
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
ODT Off Du rin g READs
As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled
at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if
either RTT_NOM or RTT_WR is enabled). RTT may not be enabled until the end of the post-
amble as shown in the example in Figure 118 on page 171.
Note:
ODT may be disabled earlier and enabled later than shown in Figure 118 on page 171.
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Fig u re 118: ODT Du rin g READs
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Valid
ODTL on = CWL + AL - 2
ODTL off = CWL + AL - 2
ODT
t
AOF (MIN)
RTT
R
TT
_
NOM
RTT_NOM
t
t
AOF (MAX)
AON (MAX)
RL = AL + CL
DQS, DQS#
DQ
DI
DI
DI
DI
DI
DI
DI
DI
b
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
Transitioning
Don’t Care
Notes: 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL +
CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. RTT_WR is a “Don’t Care.”
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Asyn ch ro n o u s ODT Mo d e
Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when
either RTT_NOM or RTT_WR is enabled; however, the DLL is temporarily turned off in
precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchro-
nously when the DLL is synchronizing after being reset. See "Power-Down Mode" on
page 151 for definition and guidance over power-down details.
In asynchronous ODT timing mode, the internal ODT command is not delayed by AL
relative to the external ODT command. In asynchronous ODT mode, ODT controls RTT
t
t
by analog time. The timing parameters AONPD and AOFPD (see Table 82 on page 173)
t
t
replace ODTL on/ AON and ODTL off/ AOF, respectively, when ODT operates asyn-
chronously (see Figure 119 on page 173).
t
The minimum RTT turn-on time ( AONPD [MIN]) is the point at which the device termi-
nation circuit leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn-
t
t
on time ( AONPD [MAX]) is the point at which ODT resistance is fully on. AONPD (MIN)
t
and AONPD (MAX) are measured from ODT being sampled HIGH.
t
The minimum RTT turn-off time ( AOFPD [MIN]) is the point at which the device termi-
t
nation circuit starts to turn off ODT resistance. Maximum RTT turn-off time ( AOFPD
t
t
[MAX]) is the point at which ODT has reached High-Z. AOFPD (MIN) and AOFPD
(MAX) are measured from ODT being sampled LOW.
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Fig u re 119: Asyn ch ro n o u s ODT Tim in g w it h Fa st ODT Tra n sit io n
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
CKE
t
t
t
t
IS
IH
IS
IH
ODT
t
t
AOFPD (MIN)
t
AONPD (MIN)
t
RTT
RTT_NOM
AONPD (MAX)
AOFPD (MAX)
Transitioning
Don’t Care
Notes: 1. AL is ignored.
Ta b le 82:
Sym b o l
Asyn ch ro n o u s ODT Tim in g Pa ra m e t e rs fo r All Sp e e d Bin s
De scrip t io n
Min
Ma x
Un it s
tAONPD
tAOFPD
Asynchronous RTT turn-on delay (power-down with DLL off)
Asynchronous RTT turn-off delay (power-down with DLL off)
1
1
9
9
ns
ns
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Syn ch ro n o u s t o Asyn ch ro n o u s ODT Mo d e Tra n sit io n (Po w e r-Do w n En t ry)
There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period
occurs if the DLL is selected to be off when in precharge power-down mode by the
t
setting MR0[12] = 0. Power-down entry begins ANPD prior to CKE first being registered
t
LOW, and it ends when CKE is first registered LOW. ANPD is equal to the greater of
t
t
ODTL off + 1 CK or ODTL on + 1 CK. If a REFRESH command has been issued, and it is
t
in progress when CKE goes LOW, power-down entry will end RFC after the REFRESH
command rather than when CKE is first registered LOW. Power-down entry will then
t
t
become the greater of ANPD and RFC - REFRESH command to CKE registered LOW.
ODT assertion during power-down entry results in an RTT change as early as the lesser of
t
t
t
t
AONPD (MIN) and ODTL on × CK + AON (MIN) or as late as the greater of AONPD
t
t
(MAX) and ODTL on × CK + AON (MAX). ODT de-assertion during power-down entry
may result in an RTT change as early as the lesser of AOFPD (MIN) and ODTL
off × CK + AOF (MIN) or as late as the greater of AOFPD (MAX) and ODTL
off × CK + AOF (MAX). Table 83 on page 175 summarizes these parameters.
t
t
t
t
t
t
If the AL has a large value, the uncertainty of the state of RTT becomes quite large. This is
because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL.
Figure 120 on page 175 shows three different cases:
t
• ODT_A: Synchronous behavior before ANPD
t
• ODT_B: ODT state changes during the transition period with AONPD (MIN) less than
t
t
t
ODTL on × CK + AON (MIN) and AONPD (MAX) greater than
t
t
ODTL on × CK + AON (MAX)
• ODT_C: ODT state changes after the transition period with asynchronous behavior
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Ta b le 83:
ODT Pa ra m e t e rs fo r Po w e r-Do w n (DLL Off) En t ry a n d Exit Tra n sit io n Pe rio d
De scrip t io n
Min
Ma x
t
Power-down entry transition period (power-down entry)
Power-down exit transition period (power-down exit)
ODT to RTT turn-on delay (ODTL on = WL - 2)
Greater of: tANPD or RFC - refresh to CKE LOW
tANPD + XPDLL
t
Lesser of: tAONPD (MIN) (1ns) or
Greater of: tAONPD (MAX) (9ns) or
t
t
ODTL on × tCK + AON (MIN)
ODTL on × tCK + AON (MAX)
ODT to RTT turn-off delay (ODTL off = WL - 2)
tANPD
Lesser of: tAOFPD (MIN) (1ns) or
Greater of: tAOFPD (MAX) (9ns) or
t
t
ODTL off × tCK + AOF (MIN)
ODTL off × tCK + AOF (MAX)
WL - 1 (greater of ODTL off + 1 or ODTL on + 1)
Fig u re 120: Syn ch ro n o u s t o Asyn ch ro n o u s Tra n sit io n Du rin g Pre ch a rg e Po w e r-Do w n (DLL Off) En t ry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Ta0
Ta1
Ta2
Ta3
CK#
CK
CKE
Command
NOP
REF
NOP
NOP
NOP
NOP
NOP
NOP
t
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
RFC (MIN)
t
ANPD
PDE transition period
ODT A
synchronous
t
AOF (MIN)
DRAM RTT
A
RTT_NOM
synchronous
t
ODTL off + AOFPD (MIN)
ODTL off
t
AOF (MAX)
t
AOFPD (MAX)
ODT B
asynchronous
or synchronous
t
AOFPD (MIN)
DRAM RTT
B
RTT_NOM
asynchronous
t
or synchronous
ODTL off + AOFPD (MAX)
ODT C
asynchronous
t
AOFPD (MIN)
DRAM RTT
C
RTT_NOM
asynchronous
t
AOFPD (MAX)
Indicates A Break In
Time Scale
Transitioning
Don’t Care
Notes: 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3.
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Asyn ch ro n o u s t o Syn ch ro n o u s ODT Mo d e Tra n sit io n (Po w e r-Do w n Exit )
The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to “0.” Power-down exit
t
t
begins ANPD prior to CKE first being registered HIGH, and it ends XPDLL after CKE is
t
t
first registered HIGH. ANPD is equal to the greater of ODTL off + 1 CK or ODTL
on + 1 CK. The transition period is ANPD plus XPDLL.
t
t
t
ODT assertion during power-down exit results in an RTT change as early as the lesser of
t
t
t
t
AONPD (MIN) and ODTL on × CK + AON (MIN) or as late as the greater of
t
t
AONPD (MAX) and ODTL on × CK + AON (MAX). ODT de-assertion during power-
t
down exit may result in an RTT change as early as the lesser of AOFPD (MIN) and
ODTL off × CK + AOF (MIN) or as late as the greater of AOFPD (MAX) and
ODTL off × CK + AOF (MAX). Table 83 on page 175 summarizes these parameters.
t
t
t
t
t
If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is
because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL.
Figure 121 on page 177 shows three different cases:
t
• ODT C: asynchronous behavior before ANPD
t
• ODT B: ODT state changes during the transition period, with AOFPD (MIN) less than
t
t
t
t
ODTL off × CK + AOF (MIN) and ODTL off × CK + AOF (MAX) greater than
t
AOFPD (MAX)
• ODT A: ODT state changes after the transition period with synchronous response
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Fig u re 121: Asyn ch ro n o u s t o Syn ch ro n o u s Tra n sit io n Du rin g Pre ch a rg e Po w e r-Do w n (DLL Off) Exit
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Td0
Td1
CK#
CK
CKE
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
t
XPDLL
ANPD
PDX transition period
ODT A
asynchronous
t
AOFPD (MIN)
DRAM RTT
asynchronous
A
RTT_NOM
t
ODTL off + AOF (MIN)
t
AOFPD (MAX)
t
AOFPD (MAX)
ODT B
asynchronous
or synchronous
t
RTT B
AOFPD (MIN)
asynchronous
or synchronous
RTT_NOM
t
t
AOF (MAX)
ODTL off
ODTL off + AOF (MAX)
ODT C
synchronous
t
AOF (MIN)
DRAM RTT
synchronous
C
RTT_NOM
Indicates A Break in
Time Scale
Transitioning
Don’t Care
Notes: 1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8.
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Asyn ch ro n o u s t o Syn ch ro n o u s ODT Mo d e Tra n sit io n (Sh o rt CKE Pu lse )
If the time in the precharge power down or idle states is very short (short CKE LOW
pulse), the power-down entry and power-down exit transition periods will overlap.
When overlap occurs, the response of the DRAM’s RTT to a change in the ODT state may
be synchronous or asynchronous from the start of the power-down entry transition
period to the end of the power-down exit transition period even if the entry period ends
later than the exit period (see Figure 122 on page 179).
If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit
and power-down entry transition periods overlap. When this overlap occurs, the
response of the DRAM’s RTT to a change in the ODT state may be synchronous or asyn-
chronous from the start of power-down exit transition period to the end of the power-
down entry transition period (see Figure 122 on page 179).
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Fig u re 122: Tra n sit io n Pe rio d fo r Sh o rt CKE LOW Cycle s w it h En t ry a n d Exit Pe rio d Ove rla p p in g
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
Command
CKE
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PDE transition period
t
ANPD
t
RFC (MIN)
PDX transition period
t
t
XPDLL
ANPD
Short CKE LOW transition period (RTT change asynchronous or synchronous)
Indicates A Break in
Time Scale
Transitioning
Don’t Care
Notes: 1. AL = 0, WL = 5, tANPD = 4.
Fig u re 123: Tra n sit io n Pe rio d fo r Sh o rt CKE HIGH Cycle s w it h En t ry a n d Exit Pe rio d Ove rla p p in g
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
Command
CKE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
t
ANPD
XPDLL
t
ANPD
Short CKE HIGH transition period (RTT change asynchronous or synchonous)
Indicates A Break in
Time Scale
Transitioning
Don’t Care
Notes: 1. AL = 0, WL = 5, tANPD = 4.
1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respec-
tive owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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