MG82FX564AD [MEGAWIN]
Dual data pointer;
| 型号： | MG82FX564AD |
| 厂家： | 
MEGAWIN TECHNOLOGY CO., LTD |
| 描述： | Dual data pointer |
| 文件： | 总151页 (文件大小：2621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8051-Based MCU
MG82FE/L564
Data Sheet
Version: A1.01
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
Megawin Technology Co., Ltd. 2012 All rights reserved.
2015/09 version A1.01
2
MG82FEL564 Data Sheet
MEGAWIN
Features
Enhanced 80C51 Central Processing Unit
64K bytes of MG82Fx564 on-chip flash memory with ISP/IAP capability
━
━
━
ISP memory zone as 1.5KB(default)
Flexible IAP size. 2.5KB(default)
Code protection for flash memory access
Part No.
MG82Fx564 60KB (Max.)
AP Flash ROM size IAP size
2.5KB (Min.)
256 bytes scratch-pad RAM and 1024 bytes expanded RAM (XRAM)
Dual data pointer.
Variable length MOVX for slow SRAM or peripherals.
Three 16-bit timer/counter, Timer 0, Timer 1 and Timer 2.
━
━
T0CKO on P34, T1CKO on P35 and T2CKO on P10
X12 mode enabled for T0/T1/T2.
Programmable 16-bit counter/timer Array (PCA) with 6 compare/capture modules
━
━
━
━
Capture mode
16-bit software timer mode
High speed output mode
8/10/12/16-bit PWM (Pulse Width Modulator) mode with phase shift function
Enhanced UART (S0)
━
━
━
Framing Error Detection
Automatic Address Recognition
a speed improvement mechanism (X2/X4 mode)
Secondary UART (S1)
━
━
Dedicated Baud Rate Generator
S1 shares baud rate generator with S0.
Interrupt controller
━
━
━
━
14 sources, four-level-priority interrupt capability
Four external interrupt inputs, nINT0, nINT1, nINT2 and nINT3.
nINT0/nINT1 trigger type: Low Level or Falling Edge
nINT2/nINT3: Low Level, Falling Edge, High Level or Rising Edge
10-Bit ADC
━
━
Programmable throughput up to 200ksps
Up to 8 external inputs (Single-ended)
Master/Slave SPI serial interface
Keypad Interrupt on Port 2
Programmable Watchdog Timer
━
━
one time enabled by CPU or power-on.
WDT operating option in MCU power-down.
Maximum 45 GPIOs in LQFP48 package.
━
P0, P1, P2, P3, P4, P5 can be configured to quasi-bidirectional, push-pull output, open-drain output
and input only
━
━
P6.0 and P6.1 serve quasi-bidirectional mode only and shared with XTAL2 and XTAL1
Maximum 41 GPIOs in PQFP44 package.
Two power control modes: idle mode and power-down mode.
━
━
All interrupts can wake up IDLE mode.
Four external interrupt and keypad interrupt can wake up Power-Down mode.
Brown-Out Detector: 4.2V for E-series VDD=5V and 2.4V for L-series VDD=3V
━
━
Option to reset CPU
Option to interrupt CPU.
MEGAWIN
MG82FEL564 Data Sheet
3
Operating Voltage:
━
━
4.5V~5.5V for MG82Fx564
2.4V~3.6V for MG82Fx564, minimum 2.7V requirement in flash write operation (ISP/IAP)
Operating Temperature:
Industrial (-40℃ to +85℃)*
Maximum Operation frequency : 24MHz(External crystal)
━
━
━
External crystal mode
Internal High frequency RC oscillator (22.1184MHz) (Default)
+/- 1% frequency drift @ 25℃,
+/- 2% frequency drift @ -20 ~ 50℃,
+/- 4% frequency drift @ -40 ~ 85℃,.
━
━
━
Internal High frequency RC Oscillator output on XTAL2/P6.0.
External clock input on XTAL2/P6.0.
Internal Low frequency RC Oscillator support.
Package Types:
━
━
━
LQFP48: MG82Fx564AD
PQFP44: MG82Fx564AF
PDIP40: MG82Fx564AE
*: Tested by sampling.
4
MG82FEL564 Data Sheet
MEGAWIN
Content
Features............................................................................................................. 3
Content.............................................................................................................. 5
1. Description..................................................................................................... 9
2. Order information........................................................................................... 9
3. Pin Description ............................................................................................ 10
3.1.
3.2.
Pin Definition ................................................................................................................10
Package Configuration .................................................................................................13
4. Block Diagram ............................................................................................. 15
5. Special Function Register............................................................................ 16
5.1.
5.2.
SFR Map ......................................................................................................................16
SFR Bit Assignment .....................................................................................................17
6. Memory Organization .................................................................................. 19
6.1.
6.2.
6.3.
6.4.
On-Chip Program Flash................................................................................................19
On-Chip Data RAM.......................................................................................................20
On-chip expanded RAM (XRAM)..................................................................................24
External Data Memory access......................................................................................25
Multiplexed Mode for 8-bit MOVX.........................................................................................26
Multiplexed Mode for 16-bit MOVX.......................................................................................27
No Address Phase Mode for MOVX .....................................................................................28
6.4.1.
6.4.2.
6.4.3.
7. 8051 CPU Description ................................................................................. 29
7.1.
7.2.
7.3.
7.4.
CPU Register ...............................................................................................................29
CPU Timing..................................................................................................................30
CPU Addressing Mode .................................................................................................30
Declaration Identifiers in a C51-Compiler .....................................................................31
8. Dual Data Pointer Register (DPTR) ............................................................. 32
9. Configurable I/O Ports ................................................................................. 33
9.1.
IO Structure..................................................................................................................33
Quasi-Bidirectional IO Structure ...........................................................................................33
Push-Pull Output Structure ...................................................................................................34
Input-Only (High Impedance Input) Structure.......................................................................34
Open-Drain Output Structure................................................................................................35
I/O Port Register...........................................................................................................35
Port 0 Register ......................................................................................................................36
Port 1 Register ......................................................................................................................36
Port 2 Register ......................................................................................................................36
Port 3 Register ......................................................................................................................37
Port 4 Register ......................................................................................................................37
Port 5 Register ......................................................................................................................38
Port 6 Register ......................................................................................................................38
Alternate Function Redirection......................................................................................38
GPIO Sample Code......................................................................................................40
9.1.1.
9.1.2.
9.1.3.
9.1.4.
9.2.
9.2.1.
9.2.2.
9.2.3.
9.2.4.
9.2.5.
9.2.6.
9.2.7.
9.3.
9.4.
10.Interrupt....................................................................................................... 41
10.1.
10.2.
10.1.
Interrupt Structure.........................................................................................................41
Interrupt Register..........................................................................................................43
Interrupt Sample Code..................................................................................................48
11.Timers/Counters .......................................................................................... 49
11.1.
Timer0 and Timer1 .......................................................................................................49
Mode 0 Structure ..................................................................................................................49
Mode 1 Structure ..................................................................................................................50
Mode 2 Structure ..................................................................................................................50
Mode 3 Structure ..................................................................................................................51
Timer Clock-Out Structure ....................................................................................................51
11.1.1.
11.1.2.
11.1.3.
11.1.4.
11.1.5.
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MG82FEL564 Data Sheet
5
11.1.6.
11.2.
Timer0/1 Register .................................................................................................................52
Timer2..........................................................................................................................54
Capture Mode (CP) Structure ...............................................................................................54
Auto-Reload Mode (AR) Structure........................................................................................55
Baud-Rate Generator Mode (BRG) Structure.......................................................................56
Programmable Clock Output from Timer 2 Structure ...........................................................57
Timer2 Register ....................................................................................................................57
Timer0/1 Sample Code.................................................................................................60
11.2.1.
11.2.2.
11.2.3.
11.2.4.
11.2.5.
11.3.
12.Serial Port 0 (UART0).................................................................................. 62
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
12.7.
Serial Port 0 Mode 0.....................................................................................................62
Serial Port 0 Mode 1.....................................................................................................65
Serial Port 0 Mode 2 and Mode 3 .................................................................................66
Frame Error Detection ..................................................................................................66
Multiprocessor Communications...................................................................................67
Automatic Address Recognition....................................................................................67
Baud Rate Setting ........................................................................................................68
Baud Rate in Mode 0 ............................................................................................................69
Baud Rate in Mode 2 ............................................................................................................69
Baud Rate in Mode 1 & 3......................................................................................................69
Serial Port 0 Register ...................................................................................................70
12.7.1.
12.7.2.
12.7.3.
12.8.
13.Serial Port 1 (UART1).................................................................................. 73
13.1.
Serial Port 1 Baud Rates ..............................................................................................73
Baud Rate in Mode 0 ............................................................................................................73
Baud Rate in Mode 2 ............................................................................................................73
Baud Rate in Mode 2 ............................................................................................................73
UART1 Baud Rate Timer used for UART0....................................................................73
Serial Port 1 Register ...................................................................................................74
Serial Port Sample Code ..............................................................................................76
13.1.1.
13.1.2.
13.1.3.
13.2.
13.3.
13.4.
14.Programmable Counter Array (PCA) ........................................................... 78
14.1.
14.2.
14.3.
14.4.
PCA Overview..............................................................................................................78
PCA Timer/Counter ......................................................................................................79
Compare/Capture Modules...........................................................................................82
Operation Modes of the PCA........................................................................................84
Capture Mode .......................................................................................................................84
16-bit Software Timer Mode..................................................................................................84
High Speed Output Mode .....................................................................................................85
PWM Mode ...........................................................................................................................85
Enhance PWM Mode............................................................................................................86
PCA Sample Code .......................................................................................................89
14.4.1.
14.4.2.
14.4.3.
14.4.4.
14.4.5.
14.5.
15.Serial Peripheral Interface (SPI) .................................................................. 90
15.1.
Typical SPI Configurations ...........................................................................................90
Single Master & Single Slave................................................................................................90
Dual Device, where either can be a Master or a Slave ........................................................91
Single Master & Multiple Slaves ...........................................................................................91
Configuring the SPI ......................................................................................................93
Additional Considerations for a Slave...................................................................................93
Additional Considerations for a Master.................................................................................93
Mode Change on nSS-pin.....................................................................................................94
Write Collision .......................................................................................................................94
SPI Clock Rate Select...........................................................................................................94
Data Mode....................................................................................................................95
SPI Register .................................................................................................................97
SPI Sample Code.........................................................................................................99
15.1.1.
15.1.2.
15.1.3.
15.2.
15.2.1.
15.2.2.
15.2.3.
15.2.4.
15.2.5.
15.3.
15.4.
15.5.
16.Keypad Interrupt (KBI)............................................................................... 103
16.1.
16.2.
Keypad Register.........................................................................................................103
Keypad Interrupt Sample Code...................................................................................105
17.10-Bit ADC................................................................................................. 106
6
MG82FEL564 Data Sheet
MEGAWIN
17.1.
17.2.
ADC Structure ............................................................................................................106
ADC Operation...........................................................................................................106
ADC Input Channels ...........................................................................................................106
Starting a Conversion .........................................................................................................107
Sample Code for ADC ........................................................................................................107
ADC Conversion Time ........................................................................................................107
I/O Pins Used with ADC Function.......................................................................................107
Idle and Power-Down Mode................................................................................................107
ADC Register .............................................................................................................108
ADC Sample Code .....................................................................................................110
17.2.1.
17.2.2.
17.2.3.
17.2.4.
17.2.5.
17.2.6.
17.3.
17.4.
18.Watch Dog Timer (WDT) ........................................................................... 112
18.1.
18.2.
18.3.
18.4.
WDT Structure............................................................................................................112
WDT Register.............................................................................................................112
WDT Hardware Option ...............................................................................................113
WDT Sample Code.....................................................................................................114
19.Reset......................................................................................................... 115
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
Reset Source..............................................................................................................115
Power-On Reset.........................................................................................................115
WDT Reset.................................................................................................................116
Software Reset...........................................................................................................116
External Reset............................................................................................................117
Brown-Out Reset........................................................................................................117
Illegal Address Reset..................................................................................................118
Reset Sample Code ...................................................................................................119
20.Power Management................................................................................... 120
20.1.
Power Saving Mode ...................................................................................................120
Idle Mode ............................................................................................................................120
Power-down Mode..............................................................................................................120
Interrupt Recovery from Power-down .................................................................................120
Reset Recovery from Power-down .....................................................................................120
KBI wakeup Recovery from Power-down ...........................................................................121
Power Monitor Module................................................................................................121
Power Control Register...............................................................................................121
Power Control Sample Code ......................................................................................123
20.1.1.
20.1.2.
20.1.3.
20.1.4.
20.1.5.
20.2.
20.3.
20.4.
21.System Clock............................................................................................. 124
21.1.
21.2.
21.3.
Clock Structure...........................................................................................................124
Clock Control Register................................................................................................125
Sample code for switching internal RC-OSC Clock to External XTAL.........................127
22.In System Programming (ISP) ................................................................... 128
22.1.
ISP (IAP) Control Register..........................................................................................128
23.In Application Programming (IAP).............................................................. 131
23.1.
ISP/IAP Sample Code ................................................................................................132
24.Auxiliary SFRs ........................................................................................... 135
25.Hardware Option........................................................................................ 139
26.Absolute Maximum Rating......................................................................... 141
27.Electrical Characteristics............................................................................ 142
27.1.
27.2.
DC Characteristics......................................................................................................142
AC Characteristics......................................................................................................143
28.Instruction Set............................................................................................ 144
29.Package Dimension................................................................................... 147
30.Revision History......................................................................................... 150
MEGAWIN
MG82FEL564 Data Sheet
7
8
MG82FEL564 Data Sheet
MEGAWIN
1. Description
The MG82Fx564 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that
executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051
compatible instruction set. Therefore at the same performance as the standard 8051, the MG82Fx564 can
operate at a much lower speed and thereby greatly reduce the power consumption.
The MG82Fx564 has 64K bytes of embedded Flash memory for code and data. The Flash memory can be
programmed in ISP (In-System Programming) mode. And, it also provides the In-Application Programming (IAP)
capability. ISP allow the user to download new code without removing the microcontroller from the actual end
product; IAP means that the device can write non-volatile data in the Flash memory while the application program
is running. There needs no external high voltage for programming due to its built-in charge-pumping circuitry.
The MG82Fx564 retains all features of the standard 80C52 with 256 bytes of scratch-pad RAM, four 8bit I/O
ports, two external interrupts, a multi-source 4-level interrupt controller and three timer/counters. In addition, the
MG82Fx564 has two extra I/O ports (P4, P5[4:0]), one on-chip XRAM of 1024 bytes, two extra external interrupts
with High/low trigger option, 10-btis ADC, a 6-channel PCA, SPI, secondary UART, keypad interrupt, a one-time
enabled Watchdog Timer, a Brown-out Detector, an on-chip crystal oscillator(shared with P6.0 and P6.1), a high
precision internal oscillator, a more versatile serial channel that facilitates multiprocessor communication (EUART)
and a speed improvement mechanism (X2/X4 mode).
The MG82Fx564 has two power-saving modes and an 8-bit system clock pre-scaler to reduce the power
consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating.
In the Power-Down mode the RAM and SFRs‘ value are saved and all other functions are inoperative; most
importantly, in the Power-down mode the device can be waked up by the external interrupts. And, the user can
further reduce the power consumption by using the 8-bit system clock pre-scaler to slow down the operating
speed.
Additionally, the MG82Fx564 is equipped with the Megawin proprietary On-Chip Debug (OCD) interface for In-
Circuit Emulator (ICE). The OCD interface provides on-chip and in-system non-intrusive debugging without any
target resource occupied. Several operations necessary for an ICE are supported such as Reset, Run, Stop,
Step, Run to Cursor and Breakpoint Setting. The user has no need to prepare any development board during
firmware developing or the socket adapter used in the traditional ICE probe head. All the thing the user needs to
do is to prepare a 4-pin connector for the dedicated OCD interface. This powerful feature makes the developing
very easy for any user.
2. Order information
Part Number
MG82Fx564AE
MG82Fx564AF
MG82Fx564AD
Package
PDIP-40
PQFP-44
LQFP-48
Operation Voltage
x=L: 3V / E: 5V
x=L: 3V / E: 5V
x=L: 3V / E: 5V
MEGAWIN
MG82FEL564 Data Sheet
9
3. Pin Description
3.1. Pin Definition
PIN NUMBER
44-Pin 48-Pin
I/O
TYPE
MNEMONIC
DESCRIPTION
40-Pin
DIP
PQFP
LQFP
P0.0
(AD0)
39
38
37
36
35
34
33
32
1
37
40
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
* Port 0.0.
* AD0: multiplexed A0/D0 during external data
memory access.
* Port 0.1.
* AD1: multiplexed A1/D1 during external data
memory access.
* Port 0.2.
* AD2: multiplexed A2/D2 during external data
memory access.
* Port 0.3.
* AD3: multiplexed A3/D3 during external data
memory access.
* Port 0.4.
* AD4: multiplexed A4/D4 during external data
memory access.
* Port 0.5.
* AD5: multiplexed A5/D5 during external data
memory access.
* Port 0.6.
* AD6: multiplexed A6/D6 during external data
memory access.
* Port 0.7.
* AD7: multiplexed A7/D7 during external data
memory access.
* Port 1.0.
P0.1
(AD1)
36
35
34
33
32
31
30
40
39
38
37
36
35
34
33
44
P0.2
(AD2)
P0.3
(AD3)
P0.4
(AD4)
P0.5
(AD5)
P0.6
(AD6)
P0.7
(AD7)
P1.0
(T2)
* T2: Timer/Counter 2 external input.
* AIN0: ADC channel-0 analog input.
* T2CKO: programmable clock-out from Timer 2.
* Port 1.1.
(AIN0)
(T2CKO)
P1.1
2
41
45
I/O
(T2EX)
(AIN1)
(ECI)
* T2EX: Timer/Counter 2
Reload/Capture/Direction control.
* AIN1: ADC channel-1 analog input.
* ECI: PCA external clock input.
* Port 1.2.
* AIN2: ADC channel-2 analog input.
* RXD1: UART1 serial input port.
* CEX0: PCA module-0 external I/O.
* Port 1.3.
* AIN3: ADC channel-3 analog input.
* TXD1: UART1 serial output port.
* CEX1: PCA module-1 external I/O.
* Port 1.4.
* AIN4: ADC channel-4 analog input.
* nSS: SPI Slave select.
P1.2
3
4
5
6
7
8
42
43
44
1
46
47
48
1
I/O
I/O
I/O
I/O
I/O
I/O
(AIN2)
(RXD1)
(CEX0)
P1.3
(AIN3)
(TXD1)
(CEX1)
P1.4
(AIN4)
(nSS)
(CEX2)
* CEX2: PCA module-2 external I/O.
* Port 1.5.
P1.5
(AIN5)
(MOSI)
(CEX3)
P1.6
(AIN6)
(MISO)
(CEX4)
P1.7
* AIN5: ADC channel-5 analog input.
* MOSI: SPI master out & slave in.
* CEX3: PCA module-3 external I/O.
* Port 1.6.
* AIN6: ADC channel-6 analog input.
* MISO: SPI master in & slave out.
* CEX4: PCA module-4 external I/O.
* Port 1.7.
2
2
3
3
(AIN7)
(SPICLK)
(CEX5)
* AIN7: ADC channel-7 analog input.
* SPICLK: SPI clock, output for master and input for
slave.
* CEX5: PCA module-5 external I/O.
10
MG82FEL564 Data Sheet
MEGAWIN
P2.0
(A8)
(KBI0)
P2.1
(A9)
(KBI1)
P2.2
21
22
23
18
19
20
20
21
22
I/O
I/O
I/O
* Port 2.0.
* A8: A8 output during external data memory access.
* KBI0: keypad input 0.
* Port 2.1.
* A9: A9 output during external data memory access.
* KBI1: keypad input 1.
* Port 2.2.
(A10)
(KBI2)
* A10: A10 output during external data memory
access.
* KBI2: keypad input 2.
P2.3
(A11)
(KBI3)
24
25
26
27
28
21
22
23
24
25
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
* Port 2.3.
* A11: A11 output during external data memory
access.
* KBI3: keypad input 3.
* Port 2.4.
* A12: A12 output during external data memory
access.
* KBI4: keypad input 4.
* Port 2.5.
* A13: A13 output during external data memory
access.
* KBI5: keypad input 5.
* Port 2.6.
* A14: A14 output during external data memory
access.
* KBI6: keypad input 6.
* Port 2.7.
P2.4
(A12)
(KBI4)
P2.5
(A13)
(KBI5)
P2.6
(A14)
(KBI6)
P2.7
(A15)
(KBI7)
* A15: A15 output during external data memory
access.
* KBI7: keypad input 7.
P3.0
(RXD0)
P3.1
(TXD0)
P3.2
(nINT0)
P3.3
(nINT1)
P3.4
10
11
12
13
14
5
7
6
8
I/O
I/O
I/O
I/O
I/O
* Port 3.0.
* RXD0: UART0 serial input port.
* Port 3.1.
* TXD0: UART0 serial output port.
* Port 3.2.
* nINT0: external interrupt 0 input.
* Port 3.3.
* nINT1: external interrupt 1 input.
* Port 3.4.
8
9
9
10
11
10
(T0)
(T0CKO)
P3.5
* T0: Timer/Counter 0 external input.
* T0CKO: programmable clock-out from Timer 0.
* Port 3.5.
15
11
12
I/O
(T1)
(T1CKO)
P3.6
(nWR)
P3.7
* T1: Timer/Counter 1 external input.
* T1CKO: programmable clock-out from Timer 1.
* Port 3.6.
* nWR: external data memory write strobe.
* Port 3 bit-7.
16
17
12
13
13
14
I/O
I/O
(nRD)
* nRD: external data memory read strobe.
P4.0
P4.1
P4.2
-
-
-
17
28
39
19
31
43
I/O
I/O
I/O
* Port 4.0.
* Port 4.1.
* Port 4.2.
(nINT3)
* nINT3: external interrupt 3 input.
P4.3
(nINT2)
P4.4
(OCD_SCL)
P4.5
-
6
7
I/O
I/O
I/O
I/O
* Port 4.3.
* nINT2: external interrupt 2 input.
* Port 4.4.
* OCD_SCL: OCD interface, serial clock.
* Port 4.5.
29
31
30
26
29
27
28
32
30
* OCD_SDA: OCD interface, serial data.
* Port 4.6.
P4.6
(ALE)
* ALE: Address Latch Enable, output pulse for latching
the low byte of the address during an access cycle to
external data memory.
P5.0
P5.1
P5.2
P5.3
P6.0
--
--
--
--
18
--
--
--
--
14
15
29
41
4
I/O
I/O
I/O
I/O
I/O
* Port 5.0.
* Port 5.1.
* Port 5.2
* Port 5.3
* Port 6.0. It is only accessed in SFR page ―F‖.
16
MEGAWIN
MG82FEL564 Data Sheet
11
(CKO)
(ECKI)
(XTAL2)
O
I
O
* CKO: Enable internal High frequency RC-Oscillator
output.
* ECKI: In external clock input mode, this is clock input
pin.
*XTAL2: Output of on-chip crystal oscillating circuit.
* Port 6.1. It is only accessed in SFR page ―F‖.
*XTAL1: Input of on-chip crystal oscillating circuit.
P6.1
(XTAL1)
19
15
17
I/O
I
RST
VDD
9
40
4
38
5
42
I
I
*RST: External RESET input, high active.
Power supply.
Connect to 5V for E-series device and connect to 3.3V
for L-series device.
VSS
20
16
18
I
Ground, 0 V reference.
12
MG82FEL564 Data Sheet
MEGAWIN
3.2. Package Configuration
44 43 42 41 40 39 38 37 36 35 34
1
33
32
31
30
29
28
27
26
25
24
23
(CEX3/MOSI/AIN5) P1.5
P0.4 (AD4)
2
(CEX4/MISO/AIN6) P1.6
(CEX5/SPICLK/AIN7)P1.7
RST
P0.5 (AD5)
3
P0.6 (AD6)
4
P0.7 (AD7)
5
(RXD0) P3.0
P4.5 (OCD_SDA)
P4.1
6
(nINT2) P4.3
PQFP44
7
(TXD0) P3.1
P4.6 (ALE)
8
(nINT0) P3.2
P4.4 (OCD_SCL)
P2.7 (A15/KBI7)
P2.6 (A14/KBI6)
P2.5 (A13/KBI5)
9
(nINT1) P3.3
10
11
(T0CKO/T0) P3.4
(T1CKO/T1) P3.5
12 13 14 15 16 17 18 19 20 21 22
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
(CEX3/MOSI/AIN5) P1.5
(CEX4/MISO/AIN6) P1.6
(CEX5/SPICLK/AIN7) P1.7
P5.3
P0.4 (AD4)
2
P0.5 (AD5)
3
P0.6 (AD6)
4
P0.7 (AD7)
5
RST
P4.5 (OCD_SDA)
P4.1
6
(RXD0) P3.0
LQFP48
7
(nINT2) P4.3
P4.6 (ALE)
8
(TXD0) P3.1
P5.1
9
(nINT0) P3.2
P4.4 (OCD_SCL)
P2.7 (A15/KBI7)
P2.6( A14/KBI6)
P2.5 (A13/KBI5)
10
11
12
(nINT1) P3.3
(T0CKO/T0) P3.4
(T1CKO/T1) P3.5
13 14 15 16 17 18 19 20 21 22 23 24
MEGAWIN
MG82FEL564 Data Sheet
13
(T2CKO/AIN0/T2) P1.0
(ECI/AIN1/T2EX) P1.1
(CEX0/RXD1/AIN2) P1.2
(CEX1/TXD1/AIN3) P1.3
(CEX2/nSS/AIN4) P1.4
(CEX3/MOSI/AIN5) P1.5
(CEX4/MISO/AIN6) P1.6
(CEX5/SPICLK/AIN7)P1.7
RST
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
2
P0.0 (AD0)
3
P0.1 (AD1)
4
P0.2 (AD2)
5
P0.3 (AD3)
6
P0.4 (AD4)
7
P0.5 (AD5)
8
P0.6 (AD6)
9
P0.7 (AD7)
(RXD0) P3.0
10
11
12
13
14
15
16
17
18
19
20
P4.5 (OCD_SDA)
P4.6 (ALE)
PDIP40
(TXD0) P3.1
(nINT0) P3.2
P4.4 (OCD_SCL)
P2.7 (A15/KBI7)
P2.6 (A14/KBI6)
P2.5 (A13/KBI5)
P2.4 (A12/KBI4)
P2.3 (A11/KBI3)
P2.2 (A10/KBI2)
P2.1 (A9/KBI1)
P2.0 (A8/KBI0)
(nINT1) P3.3
(T0CKO/T0) P3.4
(T1CKO/T1) P3.5
(nWR) P3.6
(nRD) P3.7
(CKO/P6.0) XTAL2
(P6.1) XTAL1
VSS
14
MG82FEL564 Data Sheet
MEGAWIN
4. Block Diagram
XTAL1(P6.1)
RST
XTAL
OSC
Internal
OSC
Ctrl
Block
XTAL2/CKO(P6.0)
ALE(P4.6)
nWR(P3.6)
nRD(P3.7)
8051 CPU (1T)
nINT0(P3.2)
nINT1(P3.3)
nINT2(P4.3)
nINT3(P4.2)
OCD_SCL(P4.4)
OCD_SDA(P4.5)
OCD
Interface
Ext. INT
Flash
64K X 8
RXD0(P3.0)
TXD0(P3.1)
UART0
UART1
RAM
256 X 8
RXD1(P1.2)
TXD1(P1.3)
XRAM
1024 X 8
T0/T0CKO(P3.4)
T1/T1CKO(P3.5)
Timer0
Timer1
ISP/IAP
Port0
Port1
Port2
Port3
Port4
Port5
Port6
T2/T2CKO(P1.0)
T2EX(P1.1)
Timer2
P0.0~P0.7
P1.0~P1.7
P2.0~P2.7
P3.0~P3.7
P4.0~P4.6
P5.0~P5.3
P6.0~P6.1
ECI(P1.1)
CEX0~CEX5
(P1.2~P1.7)
PCA
Timer
AIN0~AIN7
(P1.0~P1.7)
10-bit ADC
Keypad Int.
KBI0~KBI7
(P2.0~P2.7)
nSS(P1.4)
MOSI(P1.5)
MISO(P1.6)
SPICLK(P1.7)
SPI
WDT
BOD
4.2V/2.4V
MEGAWIN
MG82FEL564 Data Sheet
15
5. Special Function Register
5.1. SFR Map
P
a
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
g
e
0
F
0
F
0
F
0
F
F8
F0
E8
E0
P5
B
CH
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
CCAP5H
--
PCAPWM0 PCAPWM1 PCAPWM2 PCAPWM3 PCAPWM4 PCAPWM5
P4
ACC
CL
CCAP0L
IFD
CCAP1L
IFADRH
CCAPM1
--
CCAP2L
IFADRL
CCAPM2
--
CCAP3L
IFMT
CCAP4L
SCMD
CCAP5L
ISPCR
WDTCR
0
F
D8
D0
C8
CCON
PSW
CMOD
--
CCAPM0
--
CCAPM3
KBPATN
CCAPM4
KBCON
CCAPM5
KBMASK
0
F
0
T2CON*
P6*
T2MOD
RCAP2L
RCAP2H
TL2
TH2
--
--
F
0
F
0
F
0
F
0
F
0
F
0
1
0
F
0
F
0
F
C0
B8
B0
A8
A0
98
90
88
80
XICON
IP0L
P3
--
--
--
--
ADCON
--
ADCV
ADCVL
P5M1
EIP1L
AUXR2
--
PCON2
--
SADEN
P3M0
SADDR
--
--
--
--
P3M1
--
P4M0
--
P4M1
SFRPI*
--
P5M0
EIE1
--
IP0H
EIP1H
--
IE
P2
AUXR1
--
S0CON* S0BUF*
S1CON* S1BUF*
SCFG*
S1BRT*
--
--
--
--
P1
P1M0
P1M1
TL0
P0M0
TL1
P0M1
TH0
P2M0
TH1
P2M1
AUXR0
PCON1
STRETCH
TCON
TMOD
P0
SP
DPL
DPH
SPSTAT
SPCON
SPDAT
PCON0
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
*: User needs to set SFRPI as SFRPI=0x00, or SFRPI=0x01 for SFR page access.
（MCU will not keep SFRPI value in interrupt. User need to keep SFRPI value in software flow.）
16
MG82FEL564 Data Sheet
MEGAWIN
5.2. SFR Bit Assignment
BIT ADDRESS AND SYMBOL
RESET
VALUE
SYMBOL DESCRIPTION
ADDR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
P0
SP
DPL
DPH
Port 0
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
11111111B
00000111B
00000000B
00000000B
00xxxxxxB
00000100B
00000000B
00010000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0000000xB
0x000000B
11111111B
Stack Pointer
Data Pointer Low
Data Pointer High
SPSTAT SPI Status Register
SPIF
SSIG
WCOL
SPEN
--
--
--
--
--
SPR1
--
SPR0
SPCON
SPDAT
PCON0
TCON
TMOD
TL0
TL1
TH0
TH1
AUXR0
SPI Control Register
SPI Data Register
Power Control 0
Timer Control
Timer Mode
Timer Low 0
Timer Low 1
Timer High 0
Timer High 1
Auxiliary Register 0
DORD MSTR
CPOL
CPHA
SMOD1 SMOD0 GF
TF1
GATE
POF
TR0
M0
GF1
IE1
GATE
GF0
IT1
C/T
PD
IE0
M1
IDL
IT0
M0
TR1
C/T
TF0
M1
8EH P60OC1 P60OC0 P60FD P34FD MOVXFD ADRJ
8FH EMAI1
EXTRAM --
RWS1
P1.1
STRETCH MOVX Timing Stretch
P1
--
P1.6
ALES1 ALES0 RWSH
P1.5 P1.4 P1.3
RWS2
P1.2
RWS0
P1.0
Port 1
90H
91H
92H
93H
94H
95H
96H
97H
P1.7
P1M0
P1M1
P0M0
P0M1
P2M0
P2M1
PCON1
P1 Mode Register 0
P1 Mode Register 1
P0 Mode Register 0
P0 Mode Register 1
P2 Mode Register 0
P2 Mode Register 1
Power Control 1
P1M0.7 P1M0.6 P1M0.5 P1M0.4 P1M0.3 P1M0.2 P1M0.1 P1M0.0 00000000B
P1M1.7 P1M1.6 P1M1.5 P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0 00000000B
P0M0.7 P0M0.6 P0M0.5 P0M0.4 P0M0.3 P0M0.2 P0M0.1 P0M0.0 00000000B
P0M1.7 P0M1.6 P0M1.5 P0M1.4 P0M1.3 P0M1.2 P0M1.1 P0M1.0 00000000B
P2M0.7 P2M0.6 P2M0.5 P2M0.4 P2M0.3 P2M0.2 P2M0.1 P2M0.0 00000000B
P2M1.7 P2M1.6 P2M1.5 P2M1.4 P2M1.3 P2M1.2 P2M1.1 P2M1.0 00000000B
SWRF
SM00
/FE
EXRF
SM10
SM11
BORF
SM20
SM21
IARF
--
--
--
BOF
0000xxx0B
SCON0
Serial 0 Control
98H
REN0
REN1
TB80
TB81
RB80
RB81
TI0
TI1
RI0
00000000B
SCON1
SBUF0
SBUF1
SCFG
S1BRT
P2
AUXR1
AUXR2
IE
SADDR
SFRPI
EIE1
EIP1L
EIP1H
P3
Serial 1 Control
Serial 0 Buffer
Serial 1 Buffer
98H
99H
99H
SM01
RI1
00000000B
xxxxxxxxB
xxxxxxxxB
000000xxB
9AH URTS
SMOD2 URM0X6 S1TR
S1MOD1 S1X12
--
--
S1 Baud-Rate Timer
Port 2
Auxiliary Register 1
Auxiliary Register 2
Interrupt Enable
Slave Address
9AH S1BRT.7 S1BRT.6 S1BRT.5 S1BRT.4 S1BRT.3 S1BRT.2 S1BRT.1 S1BRT.0 00000000B
A0H P2.7
A2H P4KBI
A6H T0X12
A8H EA
A9H
P2.6
P4PCA P5SPI
T1X12
--
P2.5
P2.4
P4S1
--
P2.3
--
--
P2.2
--
--
P2.1
--
P2.0
DPS
11111111B
0000xxx0B
--
ET2
T1CKOE T0CKOE 00xxxx00B
ET0
ES0
ET1
EX1
EX0
0x000000B
00000000B
xxxx0000B
xx000000B
xx000000B
xx000000B
11111111B
SFR Page Index
ACH --
--
--
--
--
--
--
IDX3
EBD
PBDL
PBDH
P3.3
IDX2
EPCA
IDX1
EADC
IDX0
ESPI
Extended INT Enable 1 ADH --
Ext. INT Priority 1 Low AEH --
Ext. INT Priority 1 High AFH --
EKB
PKBL
PKBH
P3.5
ES1
PS1L
PS1H
P3.4
PPCAL PADCL PSPIL
PPCAH PADCH PSPIH
P3.2
Port 3
B0H P3.7
P3.6
P3.1
P3.0
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
IP0H
P3 Mode Register 0
P3 Mode Register 1
P4 Mode Register 0
P4 Mode Register 1
P5 Mode Register 0
P5 Mode Register 1
B1H P3M0.7 P3M0.6 P3M0.5 P3M0.4 P3M0.3 P3M0.2 P3M0.1 P3M0.0 00000000B
B2H P3M1.7 P3M1.6 P3M1.5 P3M1.4 P3M1.3 P3M1.2 P3M1.1 P3M1.0 00000000B
B3H --
B4H --
B5H --
B6H --
P4M0.6 P4M0.5 P4M0.4 P4M0.3 P4M0.2 P4M0.1 P4M0.0 x0000000B
P4M1.6 P4M1.5 P4M1.4 P4M1.3 P4M1.2 P4M1.1 P4M1.0 x0000000B
--
--
--
P5M0.3 P5M0.2 P5M0.1 P5M0.0 xxxx0000B
P5M1.3 P5M1.2 P5M1.1 P5M1.0 xxxx0000B
--
--
--
Interrupt Priority 0 High B7H PX3H
PX2H
PX2L
PT2H
PT2L
PSH
PSL
PT1H
PT1L
PX1H
PX1L
PT0H
PT0L
PX0H
PX0L
00000000B
00000000B
00000000B
IP0L
Interrupt Priority Low
Slave Address Mask
ADC result Low
External INT Control
ADC Control
B8H PX3L
B9H
SADEN
ADCVL
XICON
ADCON
ADCV
PCON2
T2CON
P6
BEH --
C0H IT3H
C5H ADCEN SPEED1 SPEED0 ADCI
--
EX3
--
IE3
--
IT3
--
--
ADCV.1 ADCV.0 xx001010B
IT2H
ADCS
EX2
CHS2
IE2
IT2
00000000B
00000000B
CHS1
CHS0
ADC result
C6H ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 00000000B
Clock Control 0
Timer 2 Control
Port 6
C7H OSCDR --
--
--
--
SCKS2 SCKS1 SCKS0 xxxxx000B
C8H TF2
C8H --
C9H --
CAH
CBH
CCH
CDH
D0H CY
D5H
D6H
D7H
EXF2
--
--
RCLK
--
--
TCLK
--
T2X12 --
EXEN2 TR2
C/T2
P6.1
T2OE
CP/RL
P6.0
DCEN
00000000B
xxxxxx11B
xxx0xx00B
00000000B
00000000B
00000000B
00000000B
00000000B
11111111B
xxxxxx00B
00000000B
--
--
T2MOD
Timer2 mode
--
RCAP2L Timer2 Capture Low
RCAP2H Timer2 Capture High
TL2
TH2
PSW
KBPATN Keypad Pattern
KBCON Keypad Control
KBMASK Keypad Int. Mask
Timer Low 2
Timer High 2
Program Status Word
AC
F0
RS1
RS0
OV
F1
P
PATNS KBIF
MEGAWIN
MG82FEL564 Data Sheet
17
CCON
CMOD
PCA Control Reg.
PCA Mode Reg.
D8H CF
D9H CIDL
DAH --
DBH --
DCH --
DDH --
DEH --
DFH --
E0H ACC.7
CR
FEOV
CCF5
--
CCF4
--
CCF3
--
CCF2
CPS1
TOG0
TOG1
TOG2
TOG3
TOG4
TOG5
ACC.2
CCF1
CPS0
CCF0
ECF
00000000B
00xxx000B
CCAPM0 PCA Module0 Mode
CCAPM1 PCA Module1 Mode
CCAPM2 PCA Module2 Mode
CCAPM3 PCA Module3 Mode
CCAPM4 PCA Module4 Mode
CCAPM5 PCA Module5 Mode
ECOM0 CAPP0 CAPN0 MAT0
ECOM1 CAPP1 CAPN1 MAT1
ECOM2 CAPP2 CAPN2 MAT2
ECOM3 CAPP3 CAPN3 MAT3
ECOM4 CAPP4 CAPN4 MAT4
ECOM5 CAPP5 CAPN5 MAT5
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
ACC.1
ECCF0 x0000000B
ECCF1 x0000000B
ECCF2 x0000000B
ECCF3 x0000000B
ECCF4 x0000000B
ECCF5 x0000000B
ACC
Accumulator
ACC.6
ACC.5 ACC.4 ACC.3
ACC.0
00000000B
Watch-dog-timer Control
register
0x000000B
WDTCR
E1H WRF
--
ENW
CLW
WIDL
PS2
PS1
PS0
IFD
ISP Flash data
ISP Flash address High E3H
ISP Flash Address Low E4H
E2H
11111111B
00000000B
00000000B
xxxx0000B
IFR7
IFADRH
IFADRL
IFMT
IAPLB
AUXRA
AUXRB
SCMD
ISPCR
P4
ISP Mode Table
IAP Low Boundary
Auxiliary Register A
Auxiliary Register A
ISP Serial Command
ISP Control Register
Port 4
PCA base timer Low
PCA module0 Capture
Low
PCA module1 capture
Low
PCA module2 capture
Low
PCA module3 capture
Low
PCA module4 capture
Low
E5H --
--
--
MS4
MS3
MS2
MS1
MS0
Note 1 IAPLB6 IAPLB5 IAPLB4 IAPLB3 IAPLB2 IAPLB1 IAPLB0 --
Note 1 DBOD
Note 1 --
E6H
E7H ISPEN
E8H --
E9H
BORE
--
OCDE
--
ILRCOE XTALE IHRCOE OSCS1 OSCS0 00100100B
IAPO
LPM3
LPM2
--
LPM0
xxx000x0B
xxxxxxxxB
PCKS2 PCKS1 PCKS0 0000x000B
BS
P4.6
SRST
P4.5
CFAIL
P4.4
--
P4.3
P4.2
P4.1
P4.0
x1111111B
00000000B
CL
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAH
EBH
ECH
EDH
EEH
00000000B
00000000B
00000000B
00000000B
00000000B
PCA module5 capture
Low
CCAP5L
EFH
00000000B
B
B Register
F0H F7H
F6H
F5H
F4H
F3H
F2H
F1H
F0H
00000000B
PCAPWM0 PCA PWM0 Mode
PCAPWM1 PCA PWM1 Mode
PCAPWM2 PCA PWM2 Mode
PCAPWM3 PCA PWM3 Mode
PCAPWM4 PCA PWM4 Mode
PCAPWM5 PCA PWM5 Mode
F2H P0RS1 P0RS0 P0PS2 P0PS1 P0PS0 P0INV
F3H P1RS1 P1RS0 P1PS2 P1PS1 P1PS0 P1INV
F4H P2RS1 P2RS0 P2PS2 P2PS1 P2PS0 P2INV
F5H P3RS1 P3RS0 P3PS2 P3PS1 P3PS0 P3INV
F6H P4RS1 P4RS0 P4PS2 P4PS1 P4PS0 P4INV
F7H P5RS1 P5RS0 P5PS2 P5PS1 P5PS0 P5INV
EPC0H EPC0L 00000000B
EPC1H EPC1L 00000000B
EPC2H EPC2L 00000000B
EPC3H EPC3L 00000000B
EPC4H EPC4L 00000000B
EPC5H EPC5L 00000000B
P5
Port 5
F8H
P5.3
P5.2
P5.1
P5.0
xxxx1111B
CH
PCA base timer High
PCA Module0 capture
High
PCA Module1 capture
High
PCA Module2 capture
High
PCA Module3 capture
High
PCA Module4 capture
High
PCA Module5 capture
High
F9H
00000000B
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
CCAP5H
FAH
FBH
FCH
FDH
FEH
FFH
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Note1: The registers are addressed by IFMT and SCMD. Please refer the IFMT register description for more
detail information.
18
MG82FEL564 Data Sheet
MEGAWIN
6. Memory Organization
Like all 80C51 devices, the MG82Fx564 has separate address spaces for program and data memory. The logical
separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can
be quickly stored and manipulated by the 8-bit CPU.
Program memory (ROM) can only be read, not written to. There can be up to 64K bytes of program memory. In
the MG82Fx564, all the program memory are on-chip Flash memory, and without the capability of accessing
external program memory because of no External Access Enable (/EA) and Program Store Enable (/PSEN)
signals designed.
Data memory occupies a separate address space from program memory. In the MG82Fx564, there are 256
bytes of internal scratch-pad RAM and 1024 bytes of on-chip expanded RAM (XRAM).
6.1. On-Chip Program Flash
Program memory is the memory which stores the program codes for the CPU to execute, as shown in Figure 7-1.
After reset, the CPU begins execution from location 0000H, where should be the starting of the user‘s application
code. To service the interrupts, the interrupt service locations (called interrupt vectors) should be located in the
program memory. Each interrupt is assigned a fixed location in the program memory. The interrupt causes the
CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for
example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must begin
at location 0003H. If the interrupt is not going to be used, its service location is available as general purpose
program memory.
The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for
Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as
is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines
can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.
Figure 7-1 Program Memory
Program
Memory
FFFFH
Interrupt
Locations
001BH
0013H
000BH
0003H
0000H
8 bytes
Reset
MEGAWIN
MG82FEL564 Data Sheet
19
6.2. On-Chip Data RAM
Figure 7-2 shows the internal and external data memory spaces available to the MG82Fx564 user. Internal data
memory can be divided into three blocks, which are generally referred to as the lower 128 bytes of RAM, the
upper 128 bytes of RAM, and the 128 bytes of SFR space. Internal data memory addresses are always 8-bit wide,
which implies an address space of only 256 bytes. Direct addresses higher than 7FH access the SFR space; and
indirect addresses higher than 7FH access the upper 128 bytes of RAM. Thus the SFR space and the upper 128
bytes of RAM occupy the same block of addresses, 80H through FFH, although they are physically separate
entities.
The lower 128 bytes of RAM are present in all 80C51 devices as mapped in Figure 7-3. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in
the Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes
above the register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a
wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these
instructions. The bit addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128 can
only be accessed by indirect addressing.
Figure 7-4 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers,
peripheral controls, etc. These registers can only be accessed by direct addressing. Sixteen addresses in SFR
space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H.
To access the external data memory, the EXTRAM bit should be set to 1. Accesses to external data memory can
use either a 16-bit address (using ‗MOVX @DPTR‘) or an 8-bit address (using ‗MOVX @Ri‘), as described below.
Accessing by an 8-bit address
8-bit addresses are often used in conjunction with one or more other I/O lines to page the RAM. If an 8-bit
address is being used, the contents of the Port 2 SFR remain at the Port 2 pins throughout the external
memory cycle. This will facilitate paging access. Figure 7-5 shows an example of a hardware configuration for
accessing up to 2K bytes of external RAM. In multiplexed mode, Port 0 serves as a multiplexed address/data
bus to the RAM, and 3 lines of Port 2 are being used to page the RAM. The CPU generates nRD and nWR
(alternate functions of P3.7 and P3.6) to strobe the memory. Of course, the user may use any other I/O lines
instead of P2 to page the RAM.
Accessing by a 16-bit address
16-bit addresses are often used to access up to 64k bytes of external data memory. Figure 7-6 shows the
hardware configuration for accessing 64K bytes of external RAM. Whenever a 16-bit address is used, in
addition to the functioning of P0, nRD and nWR, the high byte of the address comes out on Port 2 and it is
held during the read or write cycle.
In multiplexed case, the low byte of the address is time-multiplexed with the data byte on Port 0. ALE (Address
Latch Enable) should be used to capture the address byte into an external latch. The address byte is valid at the
negative transition of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just before nWR is
activated, and remains there until after nWR is deactivated. In a read cycle, the incoming byte is accepted at Port
0 just before the read strobe is deactivated. During any access to external memory, the CPU writes 0FFH to the
Port 0 latch (the Special Function Register), thus obliterating whatever information the Port 0 SFR may have
been holding.
To access the on-chip expanded RAM (XRAM), the EXTRAM bit should be cleared to 0. Refer to Figure 7-2, the
1024 bytes of XRAM (0000H to 03FFH) are indirectly accessed by move external instruction, MOVX. An access
to XRAM will have not any outputting of address, address latch enable and read/write strobe. That means P0, P2,
P4.6 (ALE), P3.6 (nWR) and P3.7 (nRD) will keep unchanged during access of on-chip XRAM.
20
MG82FEL564 Data Sheet
MEGAWIN
Figure 7-2 Data Memory
External Data Memory
FFFFH
Addressable by
Indirect External
Addressing
Using MOVX
without
EXTRAM case
On-chip expanded
1024 Bytes RAM
(XRAM)
0400H
03FFH
03FFH
Internal 256 Bytes
SFRs
SRAM
Addressable by
Indirect External
Addressing
Addressable by
Indirect External
Addressing
FFH
FFH
80H
Addressable by
Indirect Addressing Direct Addressing
Only
Addressable by
Upper 128
Bytes
(SFRs)
Using MOVX
with
EXTRAM = 0
Using MOVX
with
EXTRAM = 1
80H
7FH
Addressable by
Direct and Indirect
Addressing
Lower 128
Bytes
0000H
0000H
00H
Figure 7-3 Lower 128 Bytes of Internal RAM
Lower 128 Bytes of
internal SRAM
7FH
2FH
30H
Bit Addressable
20H
18H
10H
08H
00H
1FH
17H
0FH
07H
Bank 3
Bank 2
Bank 1
Bank 0
Four banks of 8
registers R0~R7
Reset value of
Stack Pointer
MEGAWIN
MG82FEL564 Data Sheet
21
Figure 7-4 SFR Space
FFH
E0H
1. I/O ports are register mapping
2. Addresses that end in 0H or
8H are also bit-addressable
- I/O ports
- PSW
- Accumulator
ACC
PSW
D0H
(etc.)
B0H
A0H
90H
80H
Port 3
Port 2
Port 1
Port 0
Figure 7-5 External RAM Accessing by an 8-Bit Address (Using ‗MOVX @ Ri‘ and Page Bits)
MG82FE/L5xx
SRAM
(P0) AD[7:0]
Data I/O[7:0]
Latch
(P4.6) ALE
P2
ADDR
Page Bits
I/O
(P3.6) nWR
(P3.7) nRD
nWE
nOE
Note that in this case, the other bits of P2 are available as general I/O pins.
22
MG82FEL564 Data Sheet
MEGAWIN
Figure 7-6 External RAM Accessing by a 16-Bit Address (Using ‗MOVX @ DPTR‘)
MG82FE/L5xx
SRAM
(P0) AD[7:0]
Data I/O[7:0]
Latch
(P4.6) ALE
(P2) A[15:8]
ADDR
(P3.6) nWR
(P3.7) nRD
nWE
nOE
Figure 7-7 External RAM Accessing by I/O configured Address
Peripheral
Controller
MG82FE/L5xx
(P0) D[7:0]
Data I/O[7:0]
Addr/Cmd
Port I/O
Control Lines
I/O
(P3.6) nWR
(P3.7) nRD
nWE
nOE
Note: It also fits the FIFO Architecture Accessing, such as a NAND type flash application.
MEGAWIN
MG82FEL564 Data Sheet
23
6.3. On-chip expanded RAM (XRAM)
To access the on-chip expanded RAM (XRAM), refer to Figure 7-2, the 1024 bytes of XRAM (0000H to 03FFH)
are indirectly accessed by move external instruction, ―MOVX @Ri‖ and ―MOVX @DPTR‖. For KEIL-C51 compiler,
to assign the variables to be located at XRAM, the ―pdata‖ or ―xdata‖ definition should be used. After being
compiled, the variables declared by ―pdata‖ and ―xdata‖ will become the memories accessed by ―MOVX @Ri‖
and ―MOVX @DPTR‖, respectively. Thus the MG82Fx564 hardware can access them correctly.
24
MG82FEL564 Data Sheet
MEGAWIN
6.4. External Data Memory access
AUXR0: Auxiliary Register 0
SFR Page
= All
SFR Address = 0x8E
RESET = 0000-0X0X
7
6
5
4
3
2
1
0
P60OC1
P60OC0
P60FD
R/W
P34FD
R/W
MOVXFD
ADRJ
R/W
EXTRAM
--
R
R/W
R/W
R/W
R/W
Bit 3: MOVXFD, Fast Driving enabled for MOVX output signals.
0: MOVX output signals with default driving.
1: MOVX output signals with fast driving. If there is an off-chip memory access, MOVX@DPTR or MOVX@Ri, the
MOVX output signals require fast driving for stretched ALE/RD/WR pulse frequency more than 12MHz @5V or
6MHz @3.3V.
Bit 1: EXTRAM, External data RAM enable.
0: Enable on-chip expanded data RAM (XRAM 1024 bytes)
1: Disable on-chip expanded data RAM.
Stretch: MOVX Stretch Register
SFR Page
= All
SFR Address = 0x8F
RESET = 0X00-0000
7
6
5
4
3
2
1
0
EMAI1
R/W
--
R
ALES1
R/W
ALES0
R/W
RWSH
R/W
RWS2
R/W
RWS1
R/W
RWS0
R/W
Bit 7: EMAI1, EMAI1 configures the External data Memory Access Interface mode as following:
0: Multiplexed address/data.
1: No Address phase access
Bit 6: Reserved. Software must write ―0‖ on this bit when STRETCH is written.
Bit 5~4: ALES[1:0], EMAI ALE pulse width select bits. It only has effect when EMAI in Multiplexed mode.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycle.
10: ALE high and ALE low pulse width = 3 SYSCLK cycle.
11: ALE high and ALE low pulse width = 4 SYSCLK cycle.
Bit 3: RWSH, EMAI Read/Write pulse Setup/Hold time control.
0: /RD and /WR command Setup/Hold Time = 1 SYSCLK cycle.
1: /RD and /WR command Setup/Hold Time = 2 SYSCLK cycle.
Bit 2~0: RWS[2:0], EMAI Read/Write command pulse width select bits.
000: /RD and /WR pulse width = 1 SYSCLK cycle.
001: /RD and /WR pulse width = 2 SYSCLK cycle.
010: /RD and /WR pulse width = 3 SYSCLK cycle.
011: /RD and /WR pulse width = 4 SYSCLK cycle.
100: /RD and /WR pulse width = 5 SYSCLK cycle.
101: /RD and /WR pulse width = 6 SYSCLK cycle.
110: /RD and /WR pulse width = 7 SYSCLK cycle.
111: /RD and /WR pulse width = 8 SYSCLK cycle.
MEGAWIN
MG82FEL564 Data Sheet
25
6.4.1. Multiplexed Mode for 8-bit MOVX
Muxed 8-bit Write
ADDR[15:8]
P2
8-bit Low Address from R0 or R1
Write Data
AD[7:0]
ALE
P0
P0
ALES[1:0]
ALES[1:0]
P4.6
P3.6
P3.7
P4.6
P3.6
P3.7
RWSH
RWS[2:0]
RWSH
nWR
nRD
MOVX Cycle
Muxed 8-bit Read
ADDR[15:8]
AD[7:0]
ALE
P2
8-bit Low Address from R0 or R1
Read Data
P0
P0
ALES[1:0]
ALES[1:0]
P4.6
P3.7
P3.6
P4.6
P3.7
P3.6
RWSH
RWS[2:0]
RWSH
nRD
nWR
MOVX Cycle
26
MG82FEL564 Data Sheet
MEGAWIN
6.4.2. Multiplexed Mode for 16-bit MOVX
Muxed 16-bit Write
8-bit High Address from DPH
ADDR[15:8]
AD[7:0]
ALE
P2
P0
P2
P0
8-bit Low Address from DPL
Write Data
ALES[1:0]
ALES[1:0]
P4.6
P3.6
P3.7
P4.6
P3.6
P3.7
RWSH
RWS[2:0]
RWSH
nWR
nRD
MOVX Cycle
Muxed 16-bit Read
8-bit High Address from DPH
ADDR[15:8]
AD[7:0]
ALE
P2
P0
P2
P0
8-bit Low Address from DPL
Read Data
ALES[1:0]
ALES[1:0]
P4.6
P3.7
P3.6
P4.6
P3.7
P3.6
RWSH
RWS[2:0]
RWSH
nRD
nWR
MOVX Cycle
MEGAWIN
MG82FEL564 Data Sheet
27
6.4.3. No Address Phase Mode for MOVX
No Address Phase Write
ADDR[15:8]
DATA[7:0]
nWR
P2
Write Data
RWS[2:0]
P0
P0
RWSH
RWSH
P3.6
P3.7
P3.6
P3.7
nRD
MOVX Cycle
No Address Phase Read
ADDR[15:8]
DATA[7:0]
nRD
P2
Read Data
P0
P0
RWSH
RWS[2:0]
RWSH
P3.7
P3.6
P3.7
P3.6
nWR
MOVX Cycle
28
MG82FEL564 Data Sheet
MEGAWIN
7. 8051 CPU Description
7.1. CPU Register
PSW: Program Status Word
SFR Page
= All
SFR Address = 0xD0
RESET = 0000-0000
7
6
5
4
3
2
1
0
CY
R/W
AC
R/W
F0
R/W
RS1
R/W
RS0
R/W
OV
R/W
F1
R/W
P
R/W
CY: Carry bit.
AC: Auxiliary carry bit.
F0: General purpose flag 0.
RS1: Register bank select bit 1.
RS0: Register bank select bit 0.
OV: Overflow flag.
F1: General purpose flag 1.
P: Parity bit.
The program status word (PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown above, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two
register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the
―Accumulator‖ for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in the on-chip-data-RAM section.
A number of instructions refer to these RAM locations as R0 through R7.
The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s
and otherwise P=0.
SP: Stack Pointer
SFR Page
= All
SFR Address = 0x81
RESET = 0000-0111
7
6
5
4
3
2
1
0
SP[7]
R/W
SP[6]
R/W
SP[5]
R/W
SP[4]
R/W
SP[3]
R/W
SP[2]
R/W
SP[1]
R/W
SP[0]
R/W
DPL: Data Pointer Low
SFR Page
= All
SFR Address = 0x82
RESET = 0000-0000
7
6
5
4
3
2
1
0
DPL[7]
R/W
DPL[6]
R/W
DPL[5]
R/W
DPL[4]
R/W
DPL[3]
R/W
DPL[2]
R/W
DPL[1]
R/W
DPL[0]
R/W
DPH: Data Pointer High
SFR Page
= All
SFR Address = 0x83
RESET = 0000-0000
7
6
5
4
3
2
1
0
DPH[7]
R/W
DPH[6]
R/W
DPH[5]
R/W
DPH[4]
R/W
DPH[3]
R/W
DPH[2]
R/W
DPH[1]
R/W
DPH[0]
R/W
B: B Register
SFR Page
= All
SFR Address = 0xF0
RESET = 0000-0000
7
6
5
4
3
2
1
0
B[7]
R/W
B[6]
R/W
B[5]
R/W
B[4]
R/W
B[3]
R/W
B[2]
R/W
B[1]
R/W
B[0]
R/W
MEGAWIN
MG82FEL564 Data Sheet
29
7.2. CPU Timing
The MG82Fx564 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that
has an 8051 compatible instruction set, and executes instructions in 1~7 clock cycles (about 6~7 times the rate of
a standard 8051 device). It employs a pipelined architecture that greatly increases its instruction throughput over
the standard 8051 architecture. The instruction timing is different than that of the standard 8051.
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine
cycles varying from 2 to 12 clock cycles in length. However, the 1T-80C51 implementation is based solely on
clock cycle timing. All instruction timings are specified in terms of clock cycles. For more detailed information
about the 1T-80C51 instructions, please refer section ―Instruction Set‖ which includes the mnemonic, number of
bytes, and number of clock cycles for each instruction.
7.3. CPU Addressing Mode
Direct Addressing (DIR)
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal data RAM
and SFRs can be direct addressed.
Indirect Addressing (IND)
In indirect addressing the instruction specified a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit data pointer register – DPTR.
Register Instruction (REG)
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-
bit register specification within the op-code of the instruction. Instructions that access the registers this way are
code efficient because this mode eliminates the need of an extra address byte. When such instruction is
executed, one of the eight registers in the selected bank is accessed.
Register-Specific Instruction
Some instructions are specific to a certain register. For example, some instructions always operate on the
accumulator or data pointer, etc. No address byte is needed for such instructions. The op-code itself does it.
Immediate Constant (IMM)
The value of a constant can follow the op-code in the program memory.
Index Addressing
Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode
is intended for reading look-up tables in program memory. A 16-bit base register (either DPTR or PC) points to
the base of the table, and the accumulator is set up with the table entry number. Another type of indexed
addressing is used in the conditional jump instruction.
In conditional jump, the destination address is computed as the sum of the base pointer and the accumulator.
30
MG82FEL564 Data Sheet
MEGAWIN
7.4. Declaration Identifiers in a C51-Compiler
The declaration identifiers in a C51-compiler for the various MG82Fx564memory spaces are as follows:
data
128 bytes of internal data memory space (00h~7Fh); accessed via direct or indirect addressing, using instructions
other than MOVX and MOVC. All or part of the Stack may be in this area.
idata
Indirect data; 256 bytes of internal data memory space (00h~FFh) accessed via indirect addressing using
instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the data
area and the 128 bytes immediately above it.
sfr
Special Function Registers; CPU registers and peripheral control/status registers, accessible only via direct
addressing.
xdata
External data or on-chip expanded RAM (XRAM); duplicates the classic 80C51 64KB memory space addressed
via the ―MOVX @DPTR‖ instruction. The MG82Fx564 has 1024 bytes of on-chip xdata memory.
pdata
Paged (256 bytes) external data or on-chip expanded RAM; duplicates the classic 80C51 256 bytes memory
space addressed via the ―MOVX @Ri‖ instruction. The MG82Fx564 has 256 bytes of on-chip pdata memory
which is shared with on-chip xdata memory.
code
64K bytes of program memory space; accessed as part of program execution and via the ―MOVC @A+DTPR‖
instruction. The MG82Fx564 has 64K bytes of on-chip code memory.
MEGAWIN
MG82FEL564 Data Sheet
31
8. Dual Data Pointer Register (DPTR)
The dual DPTR structure as shown in Figure 8-1 is a way by which the chip can specify the address of an
external data memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called DPS (AUXR1.0) that allows the program code to switch between them.
Figure 8-1 Dual DPTR
External Data Memory
(83h)
DPH
DPH
(82h)
DPL
DPL
DPTR1
DPTR0
DPS=1
DPS=0
DPS
AUXR1(A2H)
DPTR Instructions
The six instructions that refer to DPTR currently selected using the DPS bit are as follows:
INC DPTR ; Increments the data pointer by 1
MOV DPTR,#data16 ; Loads the DPTR with a 16-bit constant
MOV A,@A+DPTR ; Move code byte relative to DPTR to ACC
MOVX A,@DPTR
MOVX @DPTR,A
JMP @A+DPTR
; Move external RAM (16-bit address) to ACC
; Move ACC to external RAM (16-bit address)
; Jump indirect relative to DPTR
Note: User should add a NOP when you access internal and external XRAM switching or access XRAM
over 1KB address.
AUXR1: Auxiliary Control Register 1
SFR Page
= All
SFR Address = 0xA2
RESET = 0000-XXX0
7
6
5
4
3
2
1
0
P4KBI
R/W
P4PCA
R/W
P5SPI
R/W
P4S1
R/W
--
R
--
R
--
R
DPS
R/W
Bit 0: DPTR select bit, used to switch between DPTR0 and DPTR1.
0: Select DPTR0.
1: Select DPTR1.
DPS
0
1
Selected DPTR
DPTR0
DPTR1
32
MG82FEL564 Data Sheet
MEGAWIN
9. Configurable I/O Ports
The MG82Fx564 has following I/O ports: P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7, P4.0~P4.6 and
P5.0~P5.3. ALE pin has a swapped function for P4.6. If select internal oscillator as system clock input, XTAL2
and XTAL1 are configured to Port 6.0 and Port 6.1. The exact number of I/O pins available depends upon the
package types. See Table 9-1.
Table 9-1 Number of I/O Pins Available
Package Type
I/O Pins
Number of I/O ports
39 or
41 (INTOSC enabled)
P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7,
P4.0~P4.6, XTAL2(P6.0), XTAL1(P6.1)
P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7,
P4.0~P4.6, P5.0~P5.3,XTAL2(P6.0), XTAL1(P6.1)
44-pin PQFP
43 or
48-pin LQFP
45 (INTOSC enabled)
9.1. IO Structure
Except P6.0 and P6.1, all I/O port pins can be configured to one of four operating modes. These are: quasi-
bidirectional (standard 8051 I/O port), push-pull output, input-only (high-impedance input) and open-drain output.
P6.0 and P6.1 are only one I/O mode for quasi-bidirectional ports.
Followings describe the configuration of the four types I/O mode.
9.1.1. Quasi-Bidirectional IO Structure
Port pins in quasi-bidirectional mode are similar to the standard 8051 port pins. A quasi-bidirectional port can be
used as an input and output without the need to reconfigure the port. This is possible because when the port
outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin outputs low,
it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional
output that serve different purposes.
One of these pull-ups, called the ―very weak‖ pull-up, is turned on whenever the port register for the pin contains
a logic ―1‖. This very weak pull-up sources a very small current that will pull the pin high if it is left floating. A
second pull-up, called the ―weak‖ pull-up, is turned on when the port register for the pin contains a logic ―1‖ and
the pin itself is also at a logic ―1‖ level. This pull-up provides the primary source current for a quasi-bidirectional
pin that is outputting a 1. If this pin is pulled low by the external device, this weak pull-up turns off, and only the
very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink
enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage. The third
pull-up is referred to as the ―strong‖ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-
bidirectional port pin when the port register changes from a logic ―0‖ to a logic ―1‖. When this occurs, the strong
pull-up turns on for one CPU clocks, quickly pulling the port pin high.
The quasi-bidirectional port configuration is shown in Figure 9-1.
MEGAWIN
MG82FEL564 Data Sheet
33
Figure 9-1 Quasi-Bidirectional I/O
VDD
VDD
VDD
2 clock
delay
Very
weak
Strong
Weak
Port
Pin
Port latch data
Input data
9.1.2. Push-Pull Output Structure
The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-
bidirectional output modes, but provides a continuous strong pull-up when the port register contains a logic ―1‖.
The push-pull mode may be used when more source current is needed from a port output. In addition, the input
path of the port pin in this configuration is also the same as quasi-bidirectional mode.
The push-pull port configuration is shown in Figure 9-2.
Figure 9-2 Push-Pull Output
VDD
Strong
Port
Pin
Port latch data
Input data
9.1.3. Input-Only (High Impedance Input) Structure
The input-only configuration is a input without any pull-up resistors on the pin, as shown in Figure 9-3.
Figure 9-3 Input-Only
Port
Pin
Input data
34
MG82FEL564 Data Sheet
MEGAWIN
9.1.4. Open-Drain Output Structure
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin
when the port register contains a logic ―0‖. To use this configuration in application, a port pin must have an
external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-
bidirectional mode. In addition, the input path of the port pin in this configuration is also the same as quasi-
bidirectional mode.
The open-drain port configuration is shown in Figure 9-4.
Figure 9-4 Open-Drain Output
Port
Pin
Port latch data
Input data
9.2. I/O Port Register
All I/O port pins on the MG82Fx564 may be individually and independently configured by software to one of four
types on a bit-by-bit basis, as shown in Table 9-2. Two mode registers for each port select the output type for
each port pin.
Table 9-2 Port Configuration Settings
PxM0.y
PxM1.y
Port Mode
0
0
1
1
0
1
0
1
Quasi-Bidirectional
Push-Pull Output
Input Only (High Impedance Input)
Open-Drain Output
Where x=0~4 (port number), and y=0~7 (port pin). The registers PxM0 and PxM1 are listed in each port
description.
MEGAWIN
MG82FEL564 Data Sheet
35
9.2.1. Port 0 Register
P0: Port 0 Register
SFR Page
= All
SFR Address = 0x80
RESET = 1111-1111
7
6
5
4
3
2
1
0
P0.7
R/W
P0.6
R/W
P0.5
R/W
P0.4
R/W
P0.3
R/W
P0.2
R/W
P0.1
R/W
P0.0
R/W
Bit 7~0: P0.7~P0.0 could be set/cleared by CPU.
P0M0: Port 0 Mode Register 0
SFR Address = 0x93
SFR Page
= All
RESET = 0000-0000
7
6
5
4
3
2
1
0
P0M0.7
R/W
P0M0.6
R/W
P0M0.5
R/W
P0M0.4
R/W
P0M0.3
R/W
P0M0.2
R/W
P0M0.1
R/W
P0M0.0
R/W
P0M1: Port 0 Mode Register 1
SFR Page
= All
SFR Address = 0x94
RESET = 0000-0000
7
6
5
4
3
2
1
0
P0M1.7
R/W
P0M1.6
R/W
P0M1.5
R/W
P0M1.4
R/W
P0M1.3
R/W
P0M1.2
R/W
P0M1.1
R/W
P0M1.0
R/W
9.2.2. Port 1 Register
P1: Port 1 Register
SFR Page
= All
SFR Address = 0x90
RESET = 1111-1111
7
6
5
4
3
2
1
0
P1.7
R/W
P1.6
R/W
P1.5
R/W
P1.4
R/W
P1.3
R/W
P1.2
R/W
P1.1
R/W
P1.0
R/W
Bit 7~0: P1.7~P1.0 could be only set/cleared by CPU.
P1M0: Port 1 Mode Register 0
SFR Page
= All
SFR Address = 0x91
POR+RESET = 0000-0000
7
6
5
4
3
2
1
0
P1M0.7
R/W
P1M0.6
R/W
P1M0.5
R/W
P1M0.4
R/W
P1M0.3
R/W
P1M0.2
R/W
P1M0.1
R/W
P1M0.0
R/W
P1M1: Port 1 Mode Register 1
SFR Page
= All
SFR Address = 0x92
POR+RESET = 0000-0000
7
6
5
4
3
2
1
0
P1M1.7
R/W
P1M1.6
R/W
P1M1.5
R/W
P1M1.4
R/W
P1M1.3
R/W
P1M1.2
R/W
P1M1.1
R/W
P1M1.0
R/W
9.2.3. Port 2 Register
P2: Port 2 Register
SFR Page
= All
SFR Address = 0xA0
RESET = 1111-1111
7
6
5
4
3
2
1
0
P2.7
R/W
P2.6
R/W
P2.5
R/W
P2.4
R/W
P2.3
R/W
P2.2
R/W
P2.1
R/W
P2.0
R/W
Bit 7~0: P2.7~P2.0 could be only set/cleared by CPU.
36
MG82FEL564 Data Sheet
MEGAWIN
P2M0: Port 2 Mode Register 0
SFR Page
= All
SFR Address = 0x95
RESET = 0000-0000
7
6
5
4
3
2
1
0
P2M0.7
R/W
P2M0.6
R/W
P2M0.5
R/W
P2M0.4
R/W
P2M0.3
R/W
P2M0.2
R/W
P2M0.1
R/W
P2M0.0
R/W
P2M1: Port 2 Mode Register 1
SFR Page
= All
SFR Address = 0x96
RESET = 0000-0000
7
6
5
4
3
2
1
0
P2M1.7
R/W
P2M1.6
R/W
P2M1.5
R/W
P2M1.4
R/W
P2M1.3
R/W
P2M1.2
R/W
P2M1.1
R/W
P2M1.0
R/W
9.2.4. Port 3 Register
P3: Port 3 Register
SFR Page
= All
SFR Address = 0xB0
RESET = 1111-1111
7
6
5
4
3
2
1
0
P3.7
R/W
P3.6
R/W
P3.5
R/W
P3.4
R/W
P3.3
R/W
P3.2
R/W
P3.1
R/W
P3.0
R/W
Bit 7~0: P3.7~P3.0 could be only set/cleared by CPU.
P3M0: Port 3 Mode Register 0
SFR Address = 0xB1
SFR Page
= All
RESET = 0000-0000
7
6
5
4
3
2
1
0
P3M0.7
R/W
P3M0.6
R/W
P3M0.5
R/W
P3M0.4
R/W
P3M0.3
R/W
P3M0.2
R/W
P3M0.1
R/W
P3M0.0
R/W
P3M1: Port 3 Mode Register 1
SFR Page
= All
SFR Address = 0xB2
RESET = 0000-0000
7
6
5
4
3
2
1
0
P3M1.7
R/W
P3M1.6
R/W
P3M1.5
R/W
P3M1.4
R/W
P3M1.3
R/W
P3M1.2
R/W
P3M1.1
R/W
P3M1.0
R/W
9.2.5. Port 4 Register
P4: Port 4 Register
SFR Page
= All
SFR Address = 0xE8
RESET = x111-1111
7
6
5
4
3
2
1
0
--
R
P4.6
R/W
P4.5
R/W
P4.4
R/W
P4.3
R/W
P4.2
R/W
P4.1
R/W
P4.0
R/W
Bit 6~0: P4.6~P4.0 could be only set/cleared by CPU.
P4.6 is an alternated function on ALE pin. When CPU executes off-chip memory access, MOVX, this pin is ALE
function in MOVX cycle.
P4M0: Port 4 Mode Register 0
SFR Page
= All
SFR Address = 0xB3
RESET = x000-0000
7
6
5
4
3
2
1
0
--
R
P4M0.6
R/W
P4M0.5
R/W
P4M0.4
R/W
P4M0.3
R/W
P4M0.2
R/W
P4M0.1
R/W
P4M0.0
R/W
MEGAWIN
MG82FEL564 Data Sheet
37
P4M1: Port 4 Mode Register 1
SFR Page
= All
SFR Address = 0xB4
RESET = x000-0000
7
6
5
4
3
2
1
0
--
R
P4M1.6
R/W
P4M1.5
R/W
P4M1.4
R/W
P4M1.3
R/W
P4M1.2
R/W
P4M1.1
R/W
P4M1.0
R/W
9.2.6. Port 5 Register
P5: Port 5 Register
SFR Page
= All
SFR Address = 0xF8
RESET = xxxx-1111
7
6
5
4
3
2
1
0
--
R
--
R
--
R
--
R
P5.3
R/W
P5.2
R/W
P5.1
R/W
P5.0
R/W
Bit 7~0: P5.3~P5.0 could be only set/cleared by CPU.
P5M0: Port 5 Mode Register 0
SFR Page
= All
SFR Address = 0xB5
RESET = xxxx-0000
7
6
5
4
3
2
1
0
--
R
--
R
--
R
--
R
P5M0.3
R/W
P5M0.2
R/W
P5M0.1
R/W
P5M0.0
R/W
P5M1: Port 5 Mode Register 1
SFR Page
= All
SFR Address = 0xB6
RESET = 0000-0000
7
6
5
4
3
2
1
0
--
R
--
R
--
R
--
R
P5M1.3
R/W
P5M1.2
R/W
P5M1.1
R/W
P5M1.0
R/W
9.2.7. Port 6 Register
P6: Port 6 Register
SFR Page
= F only
SFR Address = 0xC8
RESET = xxxx-xx11
7
6
5
4
3
2
1
0
--
R
--
R
--
R
--
R
--
R
--
R
P6.1
R/W
P6.0
R/W
Bit 7~2: Reserved.
Bit 1~0: P6.1~P6.0 could be only set/cleared by CPU. These two I/Os are active when Internal Oscillator is
enabled for system clock. Then, XTAL1 and XTAL2 behave P6.1 and P6.0. They only support one I/O mode,
quasi-bidirectional mode.
9.3. Alternate Function Redirection
Many I/O pins, in addition to their normal I/O function, also serve the alternate function for internal peripherals.
For the peripherals Keypad interrupt, PCA, SPI and UART1, Port 2 and Port 1 serve the alternate function in the
default state. However, the user may select Port 4 and Port 5 to serve their alternate function by setting the
corresponding control bits P4KB, P4PCA, P5SPI and P4S1 in AUXR1 register. It is especially useful when the
packages more than 40 pins are adopted. Note that only one of the four control bits can be set at any time.
38
MG82FEL564 Data Sheet
MEGAWIN
AUXR1: Auxiliary Control Register 1
SFR Page
= All
SFR Address = 0xA2
RESET = 0000-XXX0
7
6
5
4
3
2
1
0
P4KBI
R/W
P4PCA
R/W
P5SPI
R/W
P4S1
R/W
--
R
--
R
--
R
DPS
R/W
Bit 7: P4KBI, KBI function on P4/P5.
0: Disable KBI function moved to P4/P5.
1: Set KBI function on P4/P5 as following definition.
‗KBI0‘ function in P2.0 is moved to P4.0.
‗KBI1‘ function in P2.1 is moved to P4.1.
‗KBI2‘ function in P2.2 is moved to P4.2.
‗KBI3‘ function in P2.3 is moved to P4.3.
‗KBI5‘ function in P2.5 is moved to P5.1.
‗KBI4‘ function in P2.4 is moved to P5.0.
‗KBI6‘ function in P2.6 is moved to P5.2.
‗KBI7‘ function in P2.7 is moved to P5.3.
Bit 6: P4PCA, PCA function on P4/P5.
0: Disable PCA function moved to P4/P5.
1: Set PCA function on P4/P5 as following definition.
‗ECI‘ function in P1.1 is moved to P4.2.
‗CEX0‘ function in P1.2 is moved to P4.0.
‗CEX1‘ function in P1.3 is moved to P4.1.
‗CEX2‘ function in P1.4 is moved to P5.0.
‗CEX3‘ function in P1.5 is moved to P5.1
‗CEX4‘ function in P1.6 is moved to P5.2.
‗CEX5‘ function in P1.7 is moved to P5.3.
Bit 5: P5SPI, SPI interface on P5.3~P5.0.
0: Disable SPI function moved to P5.
1: Set SPI function on P5 as following definition.
‗nSS‘ function in P1.4 is moved to P5.0.
‗MOSI‘ function in P1.5 is moved to P5.1.
‗MISO‘ function in P1.6 is moved to P5.2.
‗SPICLK‘ function in P1.7 is moved to P5.3.
Bit 4: P4S1, Serial Port 1 (UART1) on P4.0/P4.1.
0: Disable UART1 function moved to P4.
1: Set UART1 RXD1/TXD1 on P4.0/P4.1 following definition.
‗RXD1‘ function in P1.2 is moved to P4.0.
‗TXD1‘ function in P1.3 is moved to P4.1.
MEGAWIN
MG82FEL564 Data Sheet
39
9.4. GPIO Sample Code
(1). Required Function: Set P1.0 to input-only mode
Assembly Code Example:
P1Mn0
EQU
01h
ORL P1M0, #P1Mn0
ANL P1M1, #(0FFh + P1Mn0)
; Configure P1.0 to input only mode
SETB P1.0
; Set P1.0 data latch to ―1‖ to enable input mode
C Code Example:
#define P1Mn0
0x01
P1M0 |= P1Mn0;
P1M1 &= ~P1Mn0;
P10 = 1;
// Configure P1.0 to input only mode
// Set P1.0 data latch to ―1‖ to enable input mode
(2). Required Function: Set P1.0 to push-pull output mode
Assembly Code Example:
P1Mn0
EQU
01h
ANL P1M0, #(0FFh - P1Mn0)
ORL P1M1, #P1Mn0
SETB P1.0
; Configure P1.0 to push pull mode
C Code Example:
#define P1Mn0
0x01
P1M0 &= ~P1Mn0;
P1M1 |= P1Mn0;
P10 = 1;
// Configure P1.0 to push pull mode
// Set P1.0 data latch to ―1‖ to enable push pull mode
(3). Required Function: Set P1.0 to open-drain output mode
Assembly Code Example:
P1Mn0
EQU
01h
ORL P1M0, #P1Mn0
ORL P1M1, #P1Mn0
SETB P1.0
; Configure P1.0 to open drain mode
; Set P1.0 data latch to ―1‖ to enable open drain mode
C Code Example:
#define P1Mn0
0x01
P1M0 |= P1Mn0;
P1M1 |= P1Mn0;
P10 = 1;
// Configure P1.0 to open drain mode
// Set P1.0 data latch to ―1‖ to enable open drain mode
40
MG82FEL564 Data Sheet
MEGAWIN
10. Interrupt
The MG82Fx564 has 14 interrupt sources with a four-level interrupt structure. There are several SFRs associated
with the four-level interrupt. They are the IE, IP0L, IP0H, EIE1, EIP1L, EIP1H and XICON. The IP0H (Interrupt
Priority 0 High) and EIP1H (Extended Interrupt Priority 1 High) registers make the four-level interrupt structure
possible. The four priority level interrupt structure allows great flexibility in handling these interrupt sources.
10.1. Interrupt Structure
Table 10-1 lists all the interrupt sources. The ‗Request Bits‘ are the interrupt flags that will generate an interrupt if
it is enabled by setting the ‗Enable Bit‘. Of course, the global enable bit EA (in IE0 register) should have been set
previously. The ‗Request Bits‘ can be set or cleared by software, with the same result as though it had been set
or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software.
The ‗Priority Bits‘ determine the priority level for each interrupt. The ‗Priority within Level‘ is the polling sequence
used to resolve simultaneous requests of the same priority level. The ‗Vector Address‘ is the entry point of an
interrupt service routine in the program memory.
Figure 10-1 shows the interrupt system. Each of these interrupts will be briefly described in the following sections.
Table 10-1. Interrupt Sources
Enable Request
Priority
Bits
Priority
Within Level
Vector
Address
C51
Vector No.
No
Source Name
Bit
Bits
IE0
TF0
IE1
External Interrupt,
nINT0
Timer 0
External Interrupt,
nINT1
#1
#2
#3
EX0
ET0
EX1
PX0H, PX0L
PT0H, PT0L
PX1H, PX1L
(Highest)
0003H
000Bh
0013H
0
1
2
…
…
#4
#5
Timer 1
Serial Port 0
ET1
ES0
TF1
RI0, TI0
TF2,
PT1H, PT1L
PS0H, PS0L
…
…
001BH
0023H
3
4
#6
#7
Timer 2
ET2
EX2
PT2H, PT2L
PX2H, PX2L
PX3H, PX3L
…
…
002Bh
0033H
5
6
EXF2
External Interrupt,
nINT2
External Interrupt,
nINT3
IE2
#8
#9
EX3
IE3
…
…
…
003BH
0043H
004Bh
7
8
9
SPI
ESPI
EADC
SPIF
ADCI
PSPIH, PSPIL
PADCH,
PADCL
#10 ADC
#11 PCA
CF, CCFn PPCAH,
(n=0~5)
EPCA
…
0053H
10
PPCAL
#12 Brownout Detection EBD
BOF
RI1, TI1
KBIF
PBDH, PBDL
PS1H, PS1L
PKBH, PKBL
…
…
(Lowest)
005BH
0063H
006BH
11
12
13
#13 Serial Port 1
ES1
EKB
#14 Keypad Interrupt
MEGAWIN
MG82FEL564 Data Sheet
41
Figure 10-1 Interrupt System
Highest Priority Level
Interrupt
Global Enable
(IE.EA)
IP0L,IP0H,EIP1L,EIP1H
Registers
Interrupt Polling
Sequence
TCON.IT0
IE.EX0
IE.ET0
IE.EX1
IE.ET1
IE.ES0
IE.ET2
nINT0
IE0
IE1
TCON.TF0
TCON.IT1
nINT1
TCON.TF1
SCON 0.RI0
SCON 0.TI0
TF2
EXF2
XICON.IT2
XICON.EX2
XICON.EX3
nINT2
nINT3
0
1
IE2
IE3
XICON.INT2H
XICON.IT3
0
1
XICON.INT3H
EIE1.ESPI
SPSTAT .SPIF
ADCON .ADCI
EIE1.EADC
CCON .CF
CMOD .ECF
CCON .CCF0
CCAPM 0.ECCF 0
CCON .CCF1
CCAPM 1.ECCF 1
EIE1.EPCA
CCON .CCF2
CCAPM 2.ECCF 2
CCON .CCF3
CCAPM 3.ECCF 3
CCON .CCF4
CCAPM 4.ECCF 4
CCON .CCF5
CCAPM 5.ECCF 5
EIE1_EBD
PCON 1.BOF
EIE1.ES1
EIE1.EKB
SCON 1.RI1
SCON 1.TI1
KBCON .KBIF
Lowest Priority
Level Interrupt
42
MG82FEL564 Data Sheet
MEGAWIN
10.2. Interrupt Register
IE: Interrupt Enable Register
SFR Page
= All
SFR Address = 0xE8
RESET = 0X00-0000
7
6
5
4
3
2
1
0
EA
R/W
--
R
ET2
R/W
ES0
R/W
ET1
R/W
EX1
R/W
ET0
R/W
EX0
R/W
Bit 7: EA, All interrupts enable register.
0: Global disables all interrupts.
1: Global enables all interrupts.
Bit 6: Reserved. Software must write ―0‖ on this bit when IE is written.
Bit 5: ET2, Timer 2 interrupt enable register.
0: Disable Timer 2 interrupt.
1: Enable Timer 2 interrupt.
Bit 4: ES, Serial port 0 interrupt enable register.
0: Disable serial port 0 interrupt.
1: Enable serial port 0 interrupt.
Bit 3: ET1, Timer 1 interrupt enable register.
0: Disable Timer 1 interrupt.
1: Enable Timer 1 interrupt.
Bit 2: EX1, External interrupt 1 enable register.
0: Disable external interrupt 1.
1: Enable external interrupt 1.
Bit 1: ET0, Timer 0 interrupt enable register.
0: Disable Timer 0 interrupt.
1: Enable Timer 1 interrupt.
Bit 0: EX0, External interrupt 0 enable register.
0: Disable external interrupt 0.
1: Enable external interrupt 1.
XICON: External Interrupt Control Register
SFR Page
= All
SFR Address = 0xC0
RESET = 0000-0000
7
6
5
4
3
2
1
0
INT3H
R/W
EX3
R/W
IE3
R/W
IT3
R/W
INT2H
R/W
EX2
R/W
IE2
R/W
IT2
R/W
Bit 7: INT3H, nINT3 High/Rising trigger enable.
0: Maintain nINT3 triggered on low level or falling edge on P4.2.
1: Set nINT3 triggered on high level or rising edge on P4.2.
Bit 6: EX3, external interrupt 3 enable register.
0: Disable external interrupt 3.
1: Enable external interrupt 3.
Bit 5: IE3, External interrupt 3 Edge flag.
0: Cleared by hardware when the interrupt is starting to be serviced. It also could be cleared by CPU.
1: Set by hardware when external interrupt edge detected. It also could be set by CPU.
MEGAWIN
MG82FEL564 Data Sheet
43
Bit 4: IT3, Interrupt 3 type control bit.
0: Cleared by CPU to specify low level triggered on nINT3. If INT3H is set, this bit specifies high level triggered
on nINT3.
1: Set by CPU to specify falling edge triggered on nINT3. If INT3H is set, this bit specifies rising edge triggered on
nINT3.
Bit 3: INT2H, nINT2 High/Rising trigger enable.
0: Maintain nINT2 triggered on low level or falling edge on P4.3.
1: Set nINT2 triggered on high level or rising edge on P4.3.
Bit 2: EX2, external interrupt 2 enable register.
0: Disable external interrupt 2.
1: Enable external interrupt 2.
Bit 1: IE2, External interrupt 2 Edge flag.
0: Cleared by hardware when the interrupt is starting to be serviced. It also could be cleared by CPU.
1: Set by hardware when external interrupt edge detected. It also could be set by CPU.
Bit 0: IT2, Interrupt 2 type control bit.
0: Cleared by CPU to specify low level triggered on nINT2. If INT2H is set, this bit specifies high level triggered
on nINT2.
1: Set by CPU to specify falling edge triggered on nINT2. If INT2H is set, this bit specifies rising edge triggered on
nINT2.
EIE1: Extended Interrupt Enable 1 Register
SFR Page
= All
SFR Address = 0xAD
RESET = XX00-0000
7
6
5
4
3
2
1
0
--
R
--
R
EKBI
R/W
ES1
R/W
EBD
R/W
EPCA
R/W
EADC
R/W
ESPI
R/W
Bit 7~6: Reserved. Software must write ‖0‖s on these bits when IEI1 is written.
Bit 5: EKBI, Enable Keypad Interrupt.
0: Disable the interrupt when KBCON.KBIF is set in Keypad control module.
1: Enable the interrupt when KBCON.KBIF is set in Keypad control module.
Bit 4: ES1, Enable Serial Port 1 (UART1) interrupt.
0: Disable Serial Port 1 interrupt.
1: Enable Serial Port 1 interrupt.
Bit 3: EBD, Enable Brown-out Detection interrupt.
0: Disable the interrupt when PCON1.BOF is set in brown-out detection module.
1: Enable the interrupt when PCON1.BOF is set in brown-out detection module.
Bit 2: EPCA, Enable PCA interrupt.
0: Disable PCA interrupt.
1: Enable PCA interrupt.
Bit 1: EACI, Enable ADC Interrupt.
0: Disable the interrupt when ADCON.ADCI is set in ADC module.
1: Enable the interrupt when ACCON.ADCI is set in ADC module.
Bit 0: ESPI, Enable SPI Interrupt.
0: Disable the interrupt when SPSTAT.SPIF is set in SPI module.
1: Enable the interrupt when SPSTAT.SPIF is set in SPI module.
44
MG82FEL564 Data Sheet
MEGAWIN
IP0L: Interrupt Priority 0 Low Register
SFR Page
= All
SFR Address = 0xB8
RESET = 0000-0000
7
6
5
4
3
2
1
0
PX3L
R/W
PX2L
R/W
PT2L
R/W
PSL
R/W
PT1L
R/W
PX1L
R/W
PT0L
R/W
PX0L
R/W
Bit 7: PX3L, external interrupt 3 priority-L register.
Bit 6: PX2L, external interrupt 2 priority-L register.
Bit 5: PT2L, Timer 2 interrupt priority-L register.
Bit 4: PSL, Serial port interrupt priority-L register.
Bit 3: PT1L, Timer 1 interrupt priority-L register.
Bit 2: PX1L, external interrupt 1 priority-L register.
Bit 1: PT0L, Timer 0 interrupt priority-L register.
Bit 0: PX0L, external interrupt 0 priority-L register.
IP0H: Interrupt Priority 0 High Register
SFR Page
= All
SFR Address = 0xB7
RESET = 0000-0000
7
6
5
4
3
2
1
0
PX3H
R/W
PX2H
R/W
PT2H
R/W
PSH
R/W
PT1H
R/W
PX1H
R/W
PT0H
R/W
PX0H
R/W
Bit 7: PX3H, external interrupt 3 priority-H register.
Bit 6: PX2H, external interrupt 2 priority-H register.
Bit 5: PT2H, Timer 2 interrupt priority-H register.
Bit 4: PSH, Serial port interrupt priority-H register.
Bit 3: PT1H, Timer 1 interrupt priority-H register.
Bit 2: PX1H, external interrupt 1 priority-H register.
Bit 1: PT0H, Timer 0 interrupt priority-H register.
Bit 0: PX0H, external interrupt 0 priority-H register.
EIP1L: Extended Interrupt Priority 1 Low Register
SFR Page
= All
SFR Address = 0xAE
RESET = XX00-0000
7
6
5
4
3
2
1
0
--
R
--
R
PKBL
R/W
PS1L
R/W
PBDL
R/W
PPCAL
R/W
PADCL
R/W
PSPIL
R/W
Bit 7~6: Reserved. Software must write ―0‖s on these bits when EIP1L is written.
Bit 5: PKBL, keypad interrupt priority-L register.
Bit 4: PS1L, UART1 interrupt priority-L register.
Bit 3: PBDL, brown-out detection interrupt priority-L register.
Bit 2: PPCAL, PCA interrupt priority-L register.
Bit 1: PADCL, ADC interrupt priority-L register.
Bit 0: PSPIL, SPI interrupt 0 priority-L register.
EIP1H: Extended Interrupt Priority 1 High Register
SFR Page
= All
SFR Address = 0xAF
RESET = XX00-0000
7
6
5
4
3
2
1
0
--
R
--
R
PKBH
R/W
PS1H
R/W
PBDH
R/W
PPCAH
R/W
PADCH
R/W
PSPIH
R/W
Bit 7~6: Reserved. Software must write ―0‖s on these bits when EIP1H is written.
Bit 5: PKBH, keypad interrupt priority-H register.
Bit 4: PS1H, UART1 interrupt priority-H register.
Bit 3: PBDH, brown-out detection interrupt priority-H register.
Bit 2: PPCAH, PCA interrupt priority-H register.
Bit 1: PADCH, ADC interrupt priority-H register.
Bit 0: PSPIH, SPI interrupt 0 priority-H register.
MEGAWIN
MG82FEL564 Data Sheet
45
IP0L, IP0H, EIP1L and EIP1H are combined to 4-level priority interrupt as the following table.
{IPH.x , IPL.x}
Priority Level
11
10
01
00
1 (highest)
2
3
4
There are 14 interrupt sources available in MG82Fx564. Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in the SFRs named IE, EIE1, and XICON. This register also contains a global
disable bit(EA), which can be cleared to disable all interrupts at once.
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPxH and
the other in IPxL register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two
interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced.
If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine
which request is serviced. The following table shows the internal polling sequence in the same priority level and
the interrupt vector address.
Source
External interrupt 0
Timer 0
External interrupt 1
Timer1
Serial Port 0
Timer2
External interrupt 2
External interrupt 3
SPI
Vector address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
Priority within level
1
(highest)
2
3
4
5
6
7
8
9
003BH
0043H
ADC
004BH
0053H
005BH
0063H
10
11
12
13
14
PCA Counter
Brown-out Detection
Serial Port 1
Keypad Interrupt
006BH
The external interrupt nINT0, nINT1, nINT2 and nINT3 can each be either level-activated or transition-activated,
depending on bits IT0 and IT1 in register TCON, IT2 and IT3 in register XICON. The flags that actually generate
these interrupts are bits IE0 and IE1 in TCON, IE2 and IE3 in XICON. When an external interrupt is generated,
the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt
was transition –activated, then the external requesting source is what controls the request flag, rather than the
on-chip hardware.
The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared
by the on-chip hardware when the service routine is vectored to.
The serial port 0 interrupt is generated by the logical OR of RI0 and TI0. Neither of these flags is cleared by
hardware when the service routine is vectored to. The service routine should poll RI0 and TI0 to determine which
one to request service and it will be cleared by software.
The timer2 interrupt is generated by the logical OR of TF2 and EXF2. Just the same as serial port, neither of
these flags is cleared by hardware when the service routine is vectored to.
SPI interrupt is generated by
The ADC interrupt is generated by ADCI in ADCON. It will not be cleared by hardware when the service routine is
vectored to.
46
MG82FEL564 Data Sheet
MEGAWIN
The PCA interrupt is generated by the logical OR of CF, CCF5, CCF4, CCF3, CCF2, CCF1 and CCF0 in CCON.
Neither of these flags is cleared by hardware when the service routine is vectored to. The service routine should
poll these flags to determine which one to request service and it will be cleared by software.
The BOD interrupt is generated by BOD in PCON1, which is set by on chip Brownout-Detector meets the low
voltage event. It will not be cleared by hardware when the service routine is vectored to.
The serial port 1 interrupt is generated by the logical OR of RI1 and TI1. Neither of these flags is cleared by
hardware when the service routine is vectored to. The service routine should poll RI1 and TI1 to determine which
one to request service and it will be cleared by software.
The keypad interrupt is generated by KBCON.KBIF, which is set by Keypad module meets the input pattern. It
will not be cleared by hardware when the service routine is vectored to.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had
been set or cleared by hardware. In other words, interrupts can be generated or pending interrupts can be
canceled in software.
How hardware see the interrupts
Each interrupt flag is sampled at every system clock cycle. The samples are polled during the next system clock.
If one of the flags was in a set condition at first cycle, the second cycle(polling cycle) will find it and the interrupt
system will generate an hardware LCALL to the appropriate service routine as long as it is not blocked by any of
the following conditions.
Block conditions:
An interrupt of equal or higher priority level is already in progress.
The current cycle (polling cycle) is not the final cycle in the execution of the instruction in progress.
The instruction in progress is RETI or any write to the IE, IP0L, IPH, XICON, EIE1, EIP1L and EIP1H
registers.
Any of these three conditions will block the generation of the hardware LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.
Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one or more
instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with each system clock cycle, and the values polled are the values that were
present at the previous system clock cycle. Note that if an interrupt flag is active but not being responded to for
one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied
interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not being
responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed,
the denied interrupt will not be serviced. The interrupt flag was once active but not serviced is not kept in memory.
Each polling cycle is new.
MEGAWIN
MG82FEL564 Data Sheet
47
10.1. Interrupt Sample Code
(1). Required Function: Set INT0 wake-up MCU in power-down mode
Assembly Code Example:
PX0
PX0H
PD
EQU
EQU
EQU
01h
01h
02h
ORG 0000h
JMP main
ORG 00003h
ext_int0_isr:
to do.....
RETI
main:
SETB P3.2
;
ORL IP,#PX0
ORL IPH,#PX0H
; Select INT0 interrupt priority
;
JB
P3.2, $
; Confirm P3.2 input low?????
SETB EX0
CLR IE0
SETB EA
; Enable INT0 interrupt
; Clear INT0 flag
; Enable global interrupt
ORL PCON,#PD
; Set MCU into Power Down mode
JMP
$
C Code Example:
#define PX0
#define PX0H
#define PD
0x01
0x01
0x02
void ext_int0_isr(void) interrupt 0
{
To do……
}
void main(void)
{
P32 = 1;
IP |= PX0;
IPH |= PX0H;
// Select INT0 interrupt priority
// Confirm P3.2 input low??????
while(P32);
EX0 = 1;
IE0 = 0;
EA = 1;
// Enable INT0 interrupt
// Clear INT0 flag
// Enable global interrupt
PCON |= PD;
// Set MCU into Power Down mode
while(1);
}
48
MG82FEL564 Data Sheet
MEGAWIN
11. Timers/Counters
MG82Fx564 has three 16-bit Timers/Counters: Timer 0, Timer 1 and Timer 2. All of them can be configured as
timers or event counters.
In the ―timer‖ function, the timer rate is prescaled by 12 clock cycle to increment register value. In other words, it
is to count the standard C51 machine cycle. AUXR2.T0X12, AUXR2.T1X12 and T2MOD.T2X12 are the function
for Timer 0/1/2 to set the timer rate on every clock cycle. It behaves X12 times speed than standard C51 timer
function.
In the ―counter‖ function, the register is incremented in response to a 1-to-0 transition at its corresponding
external input pin, T0, T1 or T2. In this function, the external input is sampled by every timer rate cycle. When the
samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value
appears in the register at the end of the cycle following the one in which the transition was detected.
11.1. Timer0 and Timer1
11.1.1. Mode 0 Structure
The timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer
interrupt flag TFx. The counted input is enabled to the timer when TRx = 1 and either GATE=0 or INTx = 1. Mode
0 operation is the same for Timer0 and Timer1.
SYSCLK
¸ 12
AUXR2.TxX12=0
AUXR2.TxX12=1
SYSCLK
C/T=0
Overflow
TLx[4:0]
THx[7:0]
TFx
Interrupt
C/T=1
Tx Pin
TRx
x = 0 or 1
GATE
nINTx Pin
MEGAWIN
MG82FEL564 Data Sheet
49
11.1.2. Mode 1 Structure
Mode1 is the same as Mode0, except that the timer register is being run with all 16 bits.
SYSCLK
¸ 12
AUXR2.TxX12=0
AUXR2.TxX12=1
SYSCLK
C/T=0
Overflow
TLx[7:0]
THx[7:0]
TFx
Interrupt
C/T=1
Tx Pin
TRx
x = 0 or 1
GATE
nINTx Pin
11.1.3. Mode 2 Structure
Mode 2 configures the timer register as an 8-bit counter(TLx) with automatic reload. Overflow from TLx not only
set TFx, but also reload TLx with the content of THx, which is determined by software. The reload leaves THx
unchanged. Mode 2 operation is the same for Timer0 and Timer1.
SYSCLK
¸ 12
AUXR2.TxX12=0
AUXR2.TxX12=1
SYSCLK
C/T=0
Overflow
TLx[7:0]
THx[7:0]
TFx
Interrupt
C/T=1
Tx Pin
Reload
TRx
x = 0 or 1
GATE
nINTx Pin
50
MG82FEL564 Data Sheet
MEGAWIN
11.1.4. Mode 3 Structure
Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0
and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such like C/T, GATE, TR0, INT0 and
TF0. TH0 is locked into a timer function (can not be external event counter) and take over the use of TR1, TF1
from Timer1. TH0 now controls the Timer1 interrupt.
SYSCLK
¸ 12
AUXR2.T0X12=0
AUXR2.T0X12=1
SYSCLK
C/T=0
Overflow
TL0[7:0]
TF0
Interrupt
C/T=1
T0 Pin
TR0
GATE
nINT0 Pin
SYSCLK
¸ 12
AUXR2.T0X12=0
AUXR2.T0X12=1
Overflow
SYSCLK
TH0[7:0]
TF1
Interrupt
TR1
11.1.5. Timer Clock-Out Structure
SYSCLK
D
CK
Q
Q
TxCKO
¸ 12
AUXR2.TxX12=0
Overflow
TLx[7:0]
AUXR2.TxX12=1
SYSCLK
C/T=0
Reload
TRx
AUXR2.TxCKOE = 1
GATE=0
THx[7:0]
x = 0 or 1
nINTx Pin
; n=24, if TxX12=0
; n=2, if TxX12=1
; x = 0 or 1 & C/T = 0
SYSCLK Frequency
n X (256 – THx)
T0/T1 Clock-out Frequency =
MEGAWIN
MG82FEL564 Data Sheet
51
11.1.6. Timer0/1 Register
TMOD: Timer/Counter Mode Control Register
SFR Page
= All
SFR Address = 0x89
RESET = 0000-0000
7
6
5
4
3
2
1
0
GATE
R/W
C/T
R/W
M1
R/W
M0
R/W
GATE
R/W
C/T
R/W
M1
R/W
M0
R/W
|----------------------- Timer1 -------------------------|--------------------------Timer0 ------------------------|
Bit 7/3: Gate, Gating control for Timer1/0.
0: Disable gating control for Timer1/0.
1: Enable gating control for Timer1/0. When set, Timer1/0 or Counter1/0 is enabled only when /INT1 or /INT0 pin
is high and TR1 or TR0 control bit is set.
Bit 6/2: C/T, Timer for Counter function selector.
0: Clear for Timer operation, input from internal system clock.
1: Set for Counter operation, input form T1 input pin.
Bit 5~4/1~0: Operating mode selection.
M1 M0
Operating Mode
0
0
1
1
1
0
1
0
13-bit timer/counter for Timer0 and Timer1
16-bit timer/counter for Timer0 and Timer1
8-bit timer/counter with automatic reload for Timer0 and Timer1
1 (Timer0) TL0 is 8-bit timer/counter, TH0 is locked into 8-bit timer
1 (Timer1) Timer/Counter1 Stopped
TCON: Timer/Counter Control Register
SFR Page
= All
SFR Address = 0x88
RESET = 0000-0000
7
6
5
4
3
2
1
0
TF1
R/W
TR1
R/W
TF0
R/W
TR0
R/W
IE1
R/W
IT1
R/W
IE0
R/W
IT0
R/W
Bit 7: TF1, Timer 1 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 1 overflow, or set by software.
Bit 6: TR1, Timer 1 Run control bit.
0: Cleared by software to turn Timer/Counter 1 off.
1: Set by software to turn Timer/Counter 1 on.
Bit 5: TF0, Timer 0 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 0 overflow, or set by software.
Bit 4: TR0, Timer 0 Run control bit.
0: Cleared by software to turn Timer/Counter 0 off.
1: Set by software to turn Timer/Counter 0 on.
Bit 3: IE1, Interrupt 1 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated).
Bit 2: IT1: Interrupt 1 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 1.
1: Set by software to specify falling edge triggered external interrupt 1.
Bit 1: IE0, Interrupt 0 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 0 edge is detected (transmitted or level-activated).
52
MG82FEL564 Data Sheet
MEGAWIN
Bit 0: IT0: Interrupt 0 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 0.
1: Set by software to specify falling edge triggered external interrupt 0.
TL0: Timer Low 0 Register
SFR Page
= All
SFR Address = 0x8A
RESET = 0000-0000
7
6
5
4
3
2
1
0
TL0[7]
R/W
TL0[6]
R/W
TL0[5]
R/W
TL0[4]
R/W
TL0[3]
R/W
TL0[2]
R/W
TL0[1]
R/W
TL0[0]
R/W
TH0: Timer High 0 Register
SFR Page
= All
SFR Address = 0x8C
RESET = 0000-0000
7
6
5
4
3
2
1
0
TH0[7]
R/W
TH0[6]
R/W
TH0[5]
R/W
TH0[4]
R/W
TH0[3]
R/W
TH0[2]
R/W
TH0[1]
R/W
TH0[0]
R/W
TL1: Timer Low 1 Register
SFR Page
= All
SFR Address = 0x8B
RESET = 0000-0000
7
6
5
4
3
2
1
0
TL1[7]
R/W
TL1[6]
R/W
TL1[5]
R/W
TL1[4]
R/W
TL1[3]
R/W
TL1[2]
R/W
TL1[1]
R/W
TL1[0]
R/W
TH1: Timer High 1 Register
SFR Page
= All
SFR Address = 0x8D
RESET = 0000-0000
7
6
5
4
3
2
1
0
TH1[7]
R/W
TH1[6]
R/W
TH1[5]
R/W
TH1[4]
R/W
TH1[3]
R/W
TH1[2]
R/W
TH1[1]
R/W
TH1[0]
R/W
AUXR2: Auxiliary Register 2
SFR Page
= All
SFR Address = 0xA6
RESET = 00XX-XX00
7
6
5
4
3
2
1
0
T0X12
R/W
T1X12
R/W
--
R
--
R
--
R
--
R
T1CKOE
T0CKOE
R/W
R/W
Bit 7: T0X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 6: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 1: T1CKOE, Timer 1 Clock Output Enable.
0: Disable Timer 1 clock output.
1: Enable Timer 1 clock output on P3.5.
Bit 0: T0CKOE, Timer 0 Clock Output Enable.
0: Disable Timer 0 clock output.
1: Enable Timer 0 clock output on P3.4.
MEGAWIN
MG82FEL564 Data Sheet
53
11.2. Timer2
Timer 2 is a 16-bit Timer/Counter which can operate either as a timer or an event counter, as selected by C/T2 in
T2CON register. Timer 2 has four operating modes: Capture, Auto-Reload (up or down counting), Baud Rate
Generator and Programmable Clock-Out, which are selected by bits in the T2CON and T2MOD registers.
11.2.1. Capture Mode (CP) Structure
In the capture mode there are two options selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit
timer or counter which, upon overflow, sets bit TF2 (Timer 2 overflow flag). This bit can then be used to generate
an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2=1, Timer 2 still does the above, but
with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2
registers, TH2 and TL2, to be captured into registers RCAP2H and RCAP2L, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set, and the EXF2 bit (like TF2) can generate an interrupt
which vectors to the same location as Timer 2 overflow interrupt. The capture mode is illustrated in Figure 11-5.
Figure 11-5 Timer 2 in Capture Mode
SYSCLK
¸ 12
T2MOD.T2X12=0
T2MOD.T2X12=1
Overflow
C/T2=0
C/T2=1
SYSCLK
TL2
(8 Bits)
TH2
(8 Bits)
TF2
T2 Pin
Capture
TR2
Timer2 Interrupt
RCAP2L
RCAP2H
Transition
Detection
T2EX Pin
EXF2
EXEN2
54
MG82FEL564 Data Sheet
MEGAWIN
11.2.2. Auto-Reload Mode (AR) Structure
Figure 11-6 shows DCEN=0, which enables Timer 2 to count up automatically. In this mode there are two options
selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2
(Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in
RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by firmware. If EXEN2=1, then a 16-bit
reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the
EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.
Figure 11-6 Timer 2 in Auto-Reload Mode (DCEN=0)
SYSCLK
¸ 12
T2MOD.T2X12=0
Overflow
T2MOD.T2X12=1
C/T2=0
SYSCLK
TL2
(8 Bits)
TH2
(8 Bits)
TF2
C/T2=1
T2 Pin
TR2
Reload
Timer2 Interrupt
RCAP2L
RCAP2H
Transition
Detection
T2EX Pin
EXF2
EXEN2
Fig 11-7 shows DCEN=1, which enables Timer 2 to count up or down. This mode allows pin T2EX to control the
counting direction. When a logic 1 is applied at pin T2EX, Timer 2 will count up. Timer 2 will overflow at 0FFFFH
and set the TF2 flag, which can then generate an interrupt if the interrupt is enabled. This overflow also causes
the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. A logic 0 applied
to pin T2EX causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the
value stored in RCAP2L and RCAP2H. This underflow sets the TF2 flag and causes 0FFFFH to be reloaded into
the timer registers TL2 and TH2.
The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of
resolution if needed. The EXF2 flag does not generate an interrupt in this mode.
Fig 11-7 Timer 2 in Auto-Reload Mode (DCEN=1)
(Down Counting Reload Value)
Toggle
FFH
FFH
EXF2
SYSCLK
¸ 12
T2MOD.T2X12=0
T2MOD.T2X12=1
C/T2=0
C/T2=1
SYSCLK
Overflow
Timer2 Interrupt
TL2
(8 Bits)
TH2
(8 Bits)
TF2
T2 Pin
Count Direction
TR2
1 = UP
0 = DOWN
RCAP2L
RCAP2H
(Up Counting Reload Value)
T2EX Pin
MEGAWIN
MG82FEL564 Data Sheet
55
11.2.3. Baud-Rate Generator Mode (BRG) Structure
Bits TCLK and/or RCLK in T2CON register allow the serial port transmit and receive baud rates to be derived
from either Timer 1 or Timer 2. When TCLK=0, Timer 1 is used as the serial port transmit baud rate generator.
When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud
rates – one generated by Timer 1, the other by Timer 2.
Fig 11-8 shows the Timer 2 in baud rate generation mode to generate RX Clock and TX Clock into UART engine
(See Fig 12 6 ). The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the
Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by
firmware.
The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK=1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to
be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable bit) is set, a
1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload
from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be
used as an additional external interrupt, if needed.
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud
rate generator, Timer 2 is incremented at 1/2 the system clock or asynchronously from pin T2; under these
conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not
be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be
turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
Note:
Refer to 12.7.3 Baud Rate in Mode 1 & 3 to get baud rate setting value when using Timer 2 as the baud rate
generator.
Fig 11-8 Timer 2 in Baud-Rate Generator Mode
Timer 1
Overflow
¸
2
“0”
“1”
SMOD1
RCLK
SYSCLK
T2 Pin
¸
2
C/T2=0
C/T2=1
“1”
“1”
“0”
“0”
TL2
(8 Bits)
TH2
(8 Bits)
RX Clock
Reload
TR2
TCLK
RCAP2L
RCAP2H
EXF2
TX Clock
Transition
Detection
T2EX Pin
Timer2 Interrupt
EXEN2
56
MG82FEL564 Data Sheet
MEGAWIN
11.2.4. Programmable Clock Output from Timer 2 Structure
Timer 2 has a Clock-Out Mode (while CP/RL2=0 & T2OE=1). In this mode, Timer 2 operates as a programmable
clock generator with 50% duty-cycle. The generated clocks come out on P1.0. The input clock, SYSCLK/2,
increments the 16-bit timer (TH2, TL2). The timer repeatedly counts to overflow from a loaded value. Once
overflows occur, the contents of (RCAP2H, RCAP2L) are loaded into (TH2, TL2) for the consecutive counting.
The following formula gives the clock-out frequency:
SYSCLK Frequency
T2 Clock-out Frequency =
4 x (65536 – (RCAP2H, RCAP2L))
Note:
(1) Timer 2 overflow flag, TF2, will always not be set in this mode.
(2) For SYSCLK=12MHz, Timer 2 has a programmable output frequency range from 45.7Hz to 3MHz.
How to Program Timer 2 in Clock-out Mode
• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in the RCAP2H and RCAP2L registers.
• Enter the same reload value as the initial value in the TH2 and TL2 registers.
• Set TR2 bit in T2CON register to start the Timer 2.
In the Clock-Out mode, Timer 2 rollovers will not generate an interrupt. This is similar to when Timer 2 is used as
a baud-rate generator. It is possible to use Timer 2 as a baud rate generator and a clock generator
simultaneously. Note, however, that the baud-rate and the clock-out frequency depend on the same overflow rate
of Timer 2.
11.2.5. Timer2 Register
T2MOD: Timer/Counter 2 Mode Control Register
SFR Page
= All
SFR Address = 0xC9
RESET= XXX0-XX00
7
6
5
4
3
2
1
0
--
R
--
R
--
R
T2X12
R/W
--
R
--
R
T2OE
R/W
DCEN
R/W
Bit 7~5: Reserved. Software must write ―0‖ on these bits when T2MOD is written.
Bit 4: T2X12, Timer 2 clock source selector.
0: Select SYSCLK/12 as Timer 2 clock source while T2CON.C/T2 = 0 in Capture Mode and Auto-Reload Mode.
1: Select SYSCLK as Timer 2 clock source while T2CON.C/T2 = 0 in Capture Mode and Auto-Reload
Bit 3~2: Reserved. Software must write ―0‖ on these bits when T2MOD is written.
Bit 1: T2OE, Timer 2 clock-out enable bit.
0: Disable Timer 2 clock output.
1: Enable Timer 2 clock output.
Bit 0: DCEN, Timer 2 down-counting enable bit.
0: Timer 2 always keeps up-counting.
1: Enable Timer 2 down-counting ability.
T2CON: Timer/Counter 2 Mode Control Register
SFR Page
= 0 Only
SFR Address = 0xC8
RESET = 0000-0000
7
6
5
4
3
2
1
0
TF2
R/W
EXF2
R/W
RCLK
R/W
TCLK
R/W
EXEN2
R/W
TR2
R/W
C/T2
R/W
CP/RL2
R/W
MEGAWIN
MG82FEL564 Data Sheet
57
Bit 7: TF2, Timer 2 overflow flag.
0: TF2 must be cleared by software.
1: TF2 is set by a Timer 2 overflow happens. TF2 will not be set when either RCLK=1 or TCLK=1.
Bit 6: EXF2, Timer 2 external flag.
0: EXF2 must be cleared by software.
1: Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX pin and
EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 does not cause an interrupt in up/down mode (DCEN = 1).
Bit 5: RCLK, Receive clock flag.
0: Causes Timer 1 overflow to be used for the receive clock.
1: Causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3.
Bit 4: TCLK, Transmit clock flag.
0: Causes Timer 1 overflows to be used for the transmit clock.
1: Causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3.
Bit 3: EXEN2, Timer 2 external enable flag.
0: Cause Timer 2 to ignore events at T2EX pin.
1: Allows a capture or reload to occur as a result of a negative transition on T2EX pin if Timer 2 is not being used
to clock the serial port.
Bit 2: TR2, Timer 2 Run control bit.
0: Stop the Timer 2.
1: Start the Timer 2.
Bit 1: C/T2, Timer or counter selector.
0: Select Timer 2 as internal timer function.
1: Select Timer 2 as external event counter (falling edge triggered).
Bit 0: CP/-RL2, Capture/Reload flag.
0: Auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX pin when EXEN2=1.
1: Captures will occur on negative transitions at T2EX pin if EXEN2=1.
When either RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
When the DCEN is cleared, which makes the function of Timer 2 as the same as the standard 8052 (always
counts up). When DCEN is set, Timer 2 can count up or count down according to the logic level of the T2EX pin
(P1.1). The following Table shows the operation modes of Timer 2.
RCLK + TCLK CP/-RL2
TR2
0
DCEN
T2OE Mode
X
1
0
0
0
0
x
x
1
0
0
0
x
0
0
0
1
0
0
0
0
0
0
1
(off)
1
Baud-rate generator
1
16-bit capture
1
16-bit auto-reload (counting-up only)
16-bit auto-reload (counting-up or counting-down)
Clock output
1
1
TL2: Timer Low 2 Register
SFR Page
= All
SFR Address = 0xCC
RESET = 0000-0000
7
6
5
4
3
2
1
0
TL2.7
R/W
TL2.6
R/W
TL2.5
R/W
TL2.4
R/W
TL2.3
R/W
TL2.2
R/W
TL2.1
R/W
TL2.0
R/W
58
MG82FEL564 Data Sheet
MEGAWIN
TH2: Timer High 2 Register
SFR Page
= All
SFR Address = 0xCD
RESET = 0000-0000
7
6
5
4
3
2
1
0
TH2[7]
R/W
TH2[6]
R/W
TH2[5]
R/W
TH2[4]
R/W
TH2[3]
R/W
TH2[2]
R/W
TH2[1]
R/W
TH2[0]
R/W
RCAP2L: Timer 2 Capture Low Register
SFR Page
= All
SFR Address = 0xCA
RESET = 0000-0000
7
6
5
4
3
2
1
0
RCAP2L[7] RCAP2L[6] RCAP2L[5] RCAP2L[4] RCAP2L[3] RCAP2L[2] RCAP2L[1] RCAP2L[1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RCAP2H: Timer 2 Capture High Register
SFR Page
= All
SFR Address = 0xCB
RESET = 0000-0000
7
6
5
4
3
2
1
0
RCAP2H[7] RCAP2H[6] RCAP2H[5] RCAP2H[4] RCAP2H[3] RCAP2H[2] RCAP2H[1] RCAP2H[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MEGAWIN
MG82FEL564 Data Sheet
59
11.3.Timer0/1 Sample Code
(1). Required Function: IDLE mode with T0 wake-up frequency 10KHz, SYSCLK = 12MHz Crystal
Assembly Code Example:
T0M0
T0M1
PT0
PT0H
IDL
EQU
EQU
EQU
EQU
EQU
01h
02h
02h
02h
01h
ORG 0000h
JMP main
ORG 0000Bh
time0_isr:
to do…
RETI
main:
; (unsigned short value)
MOV TH0,#(256-100)
MOV TL0,#(256-100)
ANL TMOD,#0F0h
ORL TMOD,#T0M1
CLR TF0
; Set Timer 0 overflow rate = SYSCLK x 100
;
; Set Timer 0 to Mode 2
;
; Clear Timer 0 Flag
ORL IP,#PT0
ORL IPH,#PT0H
; Select Timer 0 interrupt priority
;
SETB ET0
SETB EA
; Enable Timer 0 interrupt
; Enable global interrupt
SETB TR0
; Start Timer 0 running
ORL PCON,#IDL
; Set MCU into IDLE mode
JMP
$
C Code Example:
#define T0M0
#define T0M1
#define PT0
#define PT0H
#define IDL
0x01
0x02
0x02
0x02
0x01
void time0_isr(void) interrupt 1
{
To do…
}
void main(void)
{
TH0 = TL0 = (256-100);
TMOD &= 0xF0;
TMOD |= T0M1;
TF0 = 0;
// Set Timer 0 overflow rate = SYSCLK x 100
// Set Timer 0 to Mode 2
// Clear Timer 0 Flag
IP |= PT0;
// Select Timer 0 interrupt priority
IPH |= PT0H;
ET0 = 1;
EA = 1;
// Enable Timer 0 interrupt
// Enable global interrupt
TR0 = 1;
// Start Timer 0 running
PCON=IDL;
// Set MCU into IDLE mode
while(1);
}
60
MG82FEL564 Data Sheet
MEGAWIN
(2). Required Function: Select Timer 0 clock source from SYSCLK (enable T0X12)
Assembly Code Example:
T0M0
T0M1
PT0
PT0H
T0X12
EQU
EQU
EQU
EQU
EQU
01h
02h
02h
02h
80h
ORG 0000h
JMP main
ORG 0000Bh
time0_isr:
to do…
RETI
main:
ORL AUXR, #T0X12
CLR TF0
; Select SYSCLK/1 for Timer 0 clock input
; Clear Timer 0 Flag
ORL IP,#PT0
ORL IPH,#PT0H
; Select Timer 0 interrupt priority
;
SETB ET0
SETB EA
; Enable Timer 0 interrupt
; Enable global interrupt
MOV TH0, #(256 - 240)
MOV TL0, #(256 - 240)
;interrupt interval 20us
;
ANL TMOD,#0F0h
ORL TMOD,#T0M1
; Set Timer 0 to Mode 2
;
SETB TR0
; Start Timer 0 running
JMP
$
C Code Example:
#define T0M0
#define T0M1
#define PT0
#define PT0H
#define T0X12
0x01
0x02
0x02
0x02
0x80
AUXR |= T0X12
TF0 = 0;
IP |= PT0;
// Select Timer 0 interrupt priority
IPH |= PT0H;
ET0 = 1;
EA = 1;
// Enable Timer 0 interrupt
// Enable global interrupt
TH0 = TL0 = (256 - 240);
TMOD &= 0xF0;
TMOD |= T0M1;
// Set Timer 0 to Mode 2
// Start Timer 0 running
TR0 = 1;
MEGAWIN
MG82FEL564 Data Sheet
61
12. Serial Port 0 (UART0)
The serial port 0 of MG82Fx564 supports full-duplex transmission, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a
previously received byte has been read from the register. However, if the first byte still hasn‘t been read by the
time reception of the second byte is complete, one of the bytes will be lost. The serial port receive and transmit
registers are both accessed at special function register SBUF0. Writing to SBUF0 loads the transmit register, and
reading from SBUF0 accesses a physically separate receive register.
The serial port can operate in 4 modes: Mode 0 provides synchronous communication while Modes 1, 2, and 3
provide asynchronous communication. The asynchronous communication operates as a full-duplex Universal
Asynchronous Receiver and Transmitter (UART), which can transmit and receive simultaneously and at different
baud rates.
Mode 0: 8 data bits (LSB first) are transmitted or received through RXD0(P3.0). TXD0(P3.1) always outputs the
shift clock. The baud rate can be selected to 1/12 or 1/2 the system clock frequency by URM0X6 setting in SCFG
register.
Mode 1: 10 bits are transmitted through TXD0 or received through RXD0. The frame data includes a start bit (0),
8 data bits (LSB first), and a stop bit (1), as shown in 292H Figure 132-1 . On receive, the stop bit would be loaded into
RB80 in SCON0 register. The baud rate is variable.
Figure 12-1 Mode 1 Data Frame
Mode 1
8-bit data
Start D0
D1
D2
D3
D4
D5
D6
D7
Stop
Mode 2: 11 bits are transmitted through TXD0 or received through RXD0. The frame data includes a start bit (0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1), as shown in 293HFigure 13-2. On Transmit, the
9th data bit comes from TB80 in SCON0 register can be assigned the value of 0 or 1. On receive, the 9th data bit
would be loaded into RB80 in SCON0 register, while the stop bit is ignored. The baud rate can be configured to
1/32 or 1/64 the system clock frequency.
Figure 12-2 Mode 2, 3 Data Frame
Mode 2, 3
9-bit data
Start D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
Mode 3: Mode 3 is the same as Mode 2 except the baud rate is variable.
In all four modes, transmission is initiated by any instruction that uses SBUF0 as a destination register. In Mode 0,
reception is initiated by the condition RI0=0 and REN0=1. In the other modes, reception is initiated by the
incoming start bit with 1-to-0 transition if REN0=1.
In addition to the standard operation, the UART0 can perform framing error detection by looking for missing stop
bits, and automatic address recognition.
12.1. Serial Port 0 Mode 0
Serial data enters and exits through RXD0. TXD0 outputs the shift clock. 8 bits are transmitted/received: 8 data
bits (LSB first). The shift clock source can be selected to 1/12 or 1/2 the system clock frequency by URM0X6
setting in SCFG register. 294HFigure 13-3 shows a simplified functional diagram of the serial port 0 in Mode 0.
62
MG82FEL564 Data Sheet
MEGAWIN
Transmission is initiated by any instruction that uses SBUF0 as a destination register. The ―write to SBUF0‖
signal triggers the UART0 engine to start the transmission. The data in the SBUF0 would be shifted into the
RXD0(P3.0) pin by each raising edge shift clock on the TXD0(P3.1) pin. After eight raising edge of shift clocks
passing, TI would be asserted by hardware to indicate the end of transmission. 295HFigure 13-4 shows the
transmission waveform in Mode 0.
Reception is initiated by the condition REN0=1 and RI0=0. At the next instruction cycle, the Serial Port 0
Controller writes the bits 11111110 to the receive shift register, and in the next clock phase activates Receive.
Receive enables Shift Clock which directly comes from RX Clock to the alternate output function of P3.1 pin.
When Receive is active, the contents on the RXD0(P3.0) pin would be sampled and shifted into shift register by
falling edge of shift clock. After eight falling edge of shift clock, RI0 would be asserted by hardware to indicate the
end of reception. 296HFigure 13-5 shows the reception waveform in Mode 0.
Figure 12-3 Serial Port 0 Mode 0
SYSCLK
80C51 Internal BUS
¸
2
¸
“1”
12
Write
SBUF
“0”
URM0X6
RXD Alternated
for Input/output
Function
TXBUF
TX Clock
RX Clock
RXBUF
UART engine
TXD Alternated
for output
Function
Shift-clock
REN
RI
RXSTART
TI
Serial Port Interrupt
RI
Read
SBUF
80C51 Internal BUS
MEGAWIN
MG82FEL564 Data Sheet
63
Figure 12-4 Mode 0 Transmission Waveform
Write to
SBUF
P3.1/TXD
D0
D1
D2
D3
D4
D5
D6
D7
P3.0/RXD
TI
RI
Figure 12-5 Mode 0 Reception Waveform
Write to
Set REN, Clear RI
SCON
P3.1/TXD
D0
D1
D2
D3
D4
D5
D6
D7
P3.0/RXD
TI
RI
64
MG82FEL564 Data Sheet
MEGAWIN
12.2. Serial Port 0 Mode 1
10 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB80 in SCON0. The baud rate is determined by the Timer 1 or Timer 2
overflow rate. 297HFigure 132-1 shows the data frame in Mode 1 and 298HFigure 13-6 shows a simplified functional
diagram of the serial port in Mode 1.
Transmission is initiated by any instruction that uses SBUF0 as a destination register. The ―write to SBUF0‖
signal requests the UART0 engine to start the transmission. After receiving a transmission request, the UART0
engine would start the transmission at the raising edge of TX Clock. The data in the SBUF0 would be serial
output on the TXD0 pin with the data frame as shown in 299HFigure 132-1 and data width depend on TX Clock. After
the end of 8th data transmission, TI0 would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when Serial Port 0 Controller detected 1-to-0 transition at RXD0 sampled by RCK. The data
on the RXD0 pin would be sampled by Bit Detector in Serial Port 0 Controller. After the end of STOP-bit reception,
RI0 would be asserted by hardware to indicate the end of data reception and load STOP-bit into RB80 in SCON0
register.
Figure 12-6 Serial Port Mode 1, 2, 3
Mode 2
Mode 1, 3
clock source
clock source
Timer 2
Overflow
Timer 1
Overflow
80C51 Internal BUS
SYSCLK/2
Write
SBUF
¸
2
¸
2
SM0
SM1
TB8
“0”
“1”
“0”
“1”
TXBUF
RXBUF
TxD
RxD
SMOD1
SMOD2
“1”
“0”
TCLK
1
0
TX Clock
UART engine
¸
¸
16
TI
Serial Port
Interrupt
RI
SM1
“1”
“0”
RCLK
STOP-Bit
9th-Bit
0
1
1
RCK
RX Clock
RB8
16
0
SM0
SM1
Read
SBUF
80C51 Internal BUS
MEGAWIN
MG82FEL564 Data Sheet
65
12.3. Serial Port 0 Mode 2 and Mode 3
11 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB80) can be assigned the value of 0
or 1. On receive, the 9th data bit goes into RB80 in SCON0. The baud rate is programmable to select one of 1/16,
1/32 or 1/64 the system clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer
1 or Timer 2.
300HFigure 13-2 shows the data frame in Mode 2 and Mode 3. 301HFigure 13-6 shows a functional diagram of the serial
port in Mode 2 and Mode 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs
from Mode 1 only in the 9th bit of the transmit shift register.
The ―write to SBUF0‖ signal requests the Serial Port 0 Controller to load TB80 into the 9th bit position of the
transmit shit register and starts the transmission. After receiving a transmission request, the UART0 engine
would start the transmission at the raising edge of TX Clock. The data in the SBUF0 would be serial output on the
TXD0 pin with the data frame as shown in 302HFigure 13-2 and data width depend on TX Clock. After the end of 9th
data transmission, TI0 would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when the UART0 engine detected 1-to-0 transition at RXD0 sampled by RCK. The data on
the RXD0 pin would be sampled by Bit Detector in UART0 engine. After the end of 9th data bit reception, RI0
would be asserted by hardware to indicate the end of data reception and load the 9th data bit into RB80 in
SCON0 register.
In all four modes, transmission is initiated by any instruction that use SBUF0 as a destination register. Reception
is initiated in mode 0 by the condition RI0 = 0 and REN0 = 1. Reception is initiated in the other modes by the
incoming start bit with 1-to-0 transition if REN0=1.
12.4. Frame Error Detection
When used for framing error detection, the UART0 looks for missing stop bits in the communication. A missing
stop bit will set the FE bit in the SCON0 register. The FE bit shares the SCON0.7 bit with SM00 and the function
of SCON0.7 is determined by SMOD0 bit (PCON.6). If SMOD0 is set then SCON0.7 functions as FE. SCON0.7
functions as SM00 when SMOD0 is cleared. When SCON0.7 functions as FE, it can only be cleared by firmware.
Refer to 303HFigure 13-7.
Figure 12-7 UART0 Frame Error Detection
9-bit data
Start D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
SET FE bit if STOP=0
SM0 to UART mode control
PCON.SMOD0
TB8 RB8
SCON
SM0/FE SM1
SM2
REN
TI
RI
66
MG82FEL564 Data Sheet
MEGAWIN
12.5. Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications as shown in 304HFigure 13-8. In these
two modes, 9 data bits are received. The 9th bit goes into RB80. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB80=1. This
feature is enabled by setting bit SM20 (in SCON0 register). A way to use this feature in multiprocessor systems is
as follows:
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an
address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM20=1, no slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can examine the received byte and check if it is being
addressed. The addressed slave will clear its SM20 bit and prepare to receive the data bytes that will be coming.
The slaves that weren‘t being addressed leave their SM20 set and go on about their business, ignoring the
coming data bytes.
SM20 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1
reception, if SM20=1, the receive interrupt will not be activated unless a valid stop bit is received.
Figure 12-8 UART0 Multiprocessor Communications
VCC
Pull-up
R
Slave 3
RX TX
Slave 2
RX TX
Slave 1
RX TX
Master
RX TX
12.6. Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART0 to recognize certain addresses in the serial
bit stream by using hardware to make the comparisons. This feature saves a great deal of firmware overhead by
eliminating the need for the firmware to examine every serial address which passes by the serial port. This
feature is enabled by setting the SM20 bit in SCON0.
In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI0) will be automatically set when the
received byte contains either the ―Given‖ address or the ―Broadcast‖ address. The 9-bit mode requires that the
9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address
recognition is shown in 305HFigure 13-9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM20
is enabled and the information received has a valid stop bit following the 8 address bits and the information is
either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM20 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more
slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the
Broadcast address. Two special Function Registers are used to define the slave‘s address, SADDR, and the
address mask, SADEN.
SADEN is used to define which bits in the SADDR are to be used and which bits are ―don‘t care‖. The SADEN
mask can be logically ANDed with the SADDR to create the ―Given‖ address which the master will use for
addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding
others.
MEGAWIN
MG82FEL564 Data Sheet
67
The following examples will help to show the versatility of this scheme:
Slave 0
Slave 1
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00X0
SADDR = 1100 0000
SADEN = 1111 1110
Given = 1100 000X
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves.
Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique
address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would
be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address
which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
Slave 0
Slave 1
Slave 2
SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that
bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely
addressed by 1110 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this
result are treated as don‘t-cares. In most cases, interpreting the don‘t-cares as ones, the broadcast address will
be FF hexadecimal.
Upon reset SADDR (SFR address 0xA9) and SADEN (SFR address 0xB9) are loaded with 0s. This produces a
given address of all ―don‘t cares‖ as well as a Broadcast address of all ―don‘t cares‖. This effectively disables the
Automatic Addressing mode and allows the micro-controller to use standard 80C51 type UART drivers which do
not make use of this feature.
Figure 12-9 Auto-Address Recognition
9-bit data
Start D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
SCON
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Receive Address D0~D7
Programmed Address
addr_match
Comparator
Note: (1) After address matching(addr_match=1), Clear SM20 to receive data bytes
(2) After all data bytes have been received, Set SM20 to wait for next address.
12.7. Baud Rate Setting
Bits AUXR2.T1X12, URM0X6 and SMOD2 in SCFG register provide a new option for the baud rate setting, as
listed below.
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MG82FEL564 Data Sheet
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12.7.1. Baud Rate in Mode 0
FSYSCLK
; n=12, if URM0X6=0
; n=2, if URM0X6=1
Mode 0 Baud Rate =
Note:
n
If URM0X6=0, the baud rate formula is as same as standard 8051.
12.7.2. Baud Rate in Mode 2
2SMOD1 X 2(SMOD2 X 2)
Mode 2 Baud Rate =
Note:
X FSYSCLK
64
If SMOD2=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an enhanced function
for baud rate setting. Following table defines the Baud Rate setting with SMOD2 factor in Mode 2 baud rate
generator.
SMOD2 SMOD1 Baud Rate
Note
0
0
1
1
0
1
0
1
Default Baud Rate
Double Baud Rate
Double Baud Rate X2
Double Baud Rate X4
Standard function
Standard function
Enhanced function
Enhanced function
12.7.3. Baud Rate in Mode 1 & 3
Using Timer 1 as the Baud Rate Generator
2SMOD1 X 2(SMOD2 X 2)
FSYSCLK
Mode 1, 3 Baud Rate =
32
X
X
; T1X12=0
; T1X12=1
12 x (256 – TH1)
2SMOD1 X 2(SMOD2 X 2)
FSYSCLK
or =
32
1 x (256 – TH1)
Note:
If SMOD2=0, T1X12=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an
enhanced function for baud rate setting. Following table defines the Baud Rate setting with SMOD2 factor in
Timer 1 baud rate generator.
SMOD2 SMOD1 Baud Rate
Note
0
0
1
1
0
1
0
1
Default Baud Rate
Double Baud Rate
Double Baud Rate X2
Double Baud Rate X4
Standard function
Standard function
Enhanced function
Enhanced function
Using Timer 2 as the Baud Rate Generator
When Timer 2 is used as the baud rate generator (either TCLK or RCLK in T2CON is ‗1‘), the baud rate is as
follows.
2(SMOD2 + 1) X SMOD1 x FSYSCLK
Mode 1, 3 Baud Rate =
32 x (65536 – (RCAP2H, RCAP2L))
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MG82FEL564 Data Sheet
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Note:
If SMOD2=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an enhanced function
for baud rate setting. Following table defines the Baud Rate setting with SMOD2 factor in Timer 2 baud rate
generator.
SMOD2 SMOD1 Baud Rate
Note
0
1
1
X
0
1
Default Baud Rate
Double Baud Rate
Double Baud Rate X2
Standard function
Enhanced function
Enhanced function
12.8. Serial Port 0 Register
All the four operation modes of the serial port are the same as those of the standard 8051 except the baud rate
setting. Three registers, PCON, AUXR2 and SCFG, are related to the baud rate setting:
SCON0: Serial port 0 Control Register
SFR Page
= 0 only
SFR Address = 0x98
RESET = 0000-0000
7
6
5
4
3
2
1
0
SM00/FE
SM10
R/W
SM20
R/W
REN0
R/W
TB80
R/W
RB80
R/W
TI0
R/W
RI0
R/W
R/W
Bit 7: FE, Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit.
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit is set by the receiver when an invalid stop bit is detected.
Bit 7: Serial port 0 mode bit 0, (SMOD0 must = 0 to access bit SM00)
Bit 6: Serial port 0 mode bit 1.
SM00
SM10
Mode
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
SYSCLK/12 or /2
variable
SYSCLK/64, /32, /16 or /8
variable
0
0
1
1
0
1
0
1
0
1
2
3
Bit 5: Serial port 0 mode bit 2.
0: Disable SM20 function.
1: Enable the automatic address recognition feature in Modes 2 and 3. If SM20=1, RI0 will not be set unless the
received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In
mode1, if SM20=1 then RI0 will not be set unless a valid stop Bit was received, and the received byte is a
Given or Broadcast address. In Mode 0, SM20 should be 0.
Bit 4: REN0, Enable serial reception.
0: Clear by software to disable reception.
1: Set by software to enable reception.
Bit 3: TB80, The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
Bit 2: RB80, In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM20 = 0, RB80 is the stop bit that
was received. In Mode 0, RB80 is not used.
Bit 1: TI0. Transmit interrupt flag.
0: Must be cleared by software.
1: Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes,
in any serial transmission.
Bit 0: RI0. Receive interrupt flag.
0: Must be cleared by software.
1: Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes,
in any serial reception (except see SM20).
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MG82FEL564 Data Sheet
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SBUF0: Serial port 0 Buffer Register
SFR Page
= 0 only
SFR Address = 0x99
RESET = XXXX-XXXX
7
6
5
4
3
2
1
0
SBUF0[7] SBUF0[6] SBUF0[5] SBUF0[4] SBUF0[3] SBUF0[2] SBUF0[1] SBUF0[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7~0: It is used as the buffer register in transmission and reception.
SADDR: Slave Address Register
SFR Page
= All
SFR Address = 0xA9
RESET = 0000-0000
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SADEN: Slave Address Mask Register
SFR Page
= All
SFR Address = 0xB9
RESET = 0000-0000
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SADDR register is combined with SADEN register to form Given/Broadcast Address for automatic address
recognition. In fact, SADEN functions as the ―mask‖ register for SADDR register. The following is the example for
it.
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00x0
The Given slave address will be checked except
bit 1 is treated as ―don‘t care‖
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zero in this
result is considered as ―don‘t care‖. Upon reset, SADDR and SADEN are loaded with all 0s. This produces a
Given Address of all ―don‘t care‖ and a Broadcast Address of all ―don‘t care‖. This disables the automatic address
detection feature.
PCON0: Power Control Register 0
SFR Page
= All
SFR Address = 0x87
RESET = 00X1-0000
7
6
5
4
3
2
1
0
SMOD1
R/W
SMOD0
R/W
--
R
POF
R/W
GF1
R/W
GF0
R/W
PD
R/W
IDL
R/W
Bit 7: SMOD1, double Baud rate control bit.
0: Disable double Baud rate of the UART.
1: Enable double Baud rate of the UART in mode 1, 2, or 3.
Bit 6: SMOD0, Frame Error select.
0: SCON.7 is SM0 function.
1: SCON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.
SCFG: Serial Port Configuration Register
SFR Page
= 0 only
SFR Address = 0x9A
RESET = 0000-00XX
7
6
5
4
3
2
1
0
URTS
R/W
SMOD2
R/W
URM0X6
S1TR
R/W
S1MOD
R/W
S1TX12
--
R
--
R
R/W
R/W
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Bit 7: URTS, UART0 Timer Selection.
0: Timer 1 or Timer 2 can be used as the Baud Rate Generator in Mode 1 and Mode 3.
1: Timer 1 overflow signal is replaced by the UART1 Baud Rate Timer overflow signal when Timer 1 is selected
as the Baud Rate Generator in Mode1 or Mode 3 of the UART0. (Refer to Section 12-2.)
Bit 6: SMOD2, extra double baud rate selector.
0: Disable extra double baud rate for UART0.
1: Enable extra double baud rate for UART0.
Bit 5: URM0X6, Serial Port mode 0 baud rate selector.
0: Clear to select SYSCLK/12 as the baud rate for UART Mode 0.
1: Set to select SYSCLK/2 as the baud rate for UART Mode 0.
Bit 1~0: Reserved. Software must write ―0‖s on these bits when SCFG is written.
AUXR2: Auxiliary Register 2
SFR Page
= All
SFR Address = 0x87
POR+RESET = 00XX-XX00
7
6
5
4
3
2
1
0
T0X12
R/W
T1X12
R/W
--
R/W
--
R/W
--
R
--
R
T1CKOE
T0CKOE
R/W
R/W
Bit 6: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source. If set, the UART0 baud rate by Timer 1 in Mode 1 and Mode 3 is 12
times than standard 8051 function.
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MG82FEL564 Data Sheet
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13. Serial Port 1 (UART1)
The MG82Fx564 is equipped with a secondary UART (hereafter, called UART1), which also has four operation
modes the same as the first UART except the following differences:
(1) The UART1 has no enhanced functions: Framing Error Detection and Auto Address Recognition.
(2) The UART1 use the dedicated Baud Rate Timer as its Baud Rate Generator.
(3) The UART1 uses port pin P1.3 (TXD1) and P1.2 (RXD1) for transmit and receive, respectively.
These two UARTs can be operated simultaneously in identical or different modes and communication speeds.
13.1. Serial Port 1 Baud Rates
13.1.1. Baud Rate in Mode 0
FSYSCLK
S1 Mode 0 Baud Rate =
12
Note:
If URM0X6=0, the baud rate formula is as same as standard 8051.
13.1.2. Baud Rate in Mode 2
2S1MOD1
S1 Mode 2 Baud Rate =
X FSYSCLK
64
13.1.3. Baud Rate in Mode 2
2S1MOD1
32
FSYSCLK
S1 Mode 1, 3 Baud Rate =
or =
X
; S1X12=0
; S1X12=1
12 x (256 – S1BRT)
2S1MOD1
32
FSYSCLK
X
1 x (256 – S1BRT)
13.2. UART1 Baud Rate Timer used for UART0
In the Mode 1 and Mode 3 operation of the UART0, the user can select Timer 1 as the Baud Rate Generator by
clearing bits TCLK and RCLK in T2CON register. At this time, if URTS bit (in SCFG register) is set, then Timer 1
overflow signal will be replaced by the overflow signal of the UART1 Baud Rate Timer. In other words, the user
can adopt UART1 Baud Rate Timer as the Baud Rate Generator for Mode 1 or Mode 3 of the UART0 as long as
RCLK=0, TCLK=0 and URTS=1. In this condition, Timer 1 is free for other application. Of course, if UART1
(Mode 1 or Mode 3) is also operated at this time, these two UARTs will have the same baud rates.
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MG82FEL564 Data Sheet
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Figure 13-1. Additional Baud Rate Source for the UART0
UART1
Baud Rate Timer
Overflow
Timer 1
Overflow
“0”
“1”
URTS
¸
2
Timer 2
Overflow
“0”
“1”
“0”
“0”
SMOD1
“1”
UART0
Mode1 and Mode3
TCLK
TX Clock
“1”
RCLK
RX Clock
13.3. Serial Port 1 Register
The following special function registers are related to the operation of the UART1:
SCON1: Serial port 1 Control Register
SFR Page
= 1 only
SFR Address = 0x98
POR+RESET = 0000-0000
7
6
5
4
3
2
1
0
SM01
R/W
SM11
R/W
SM21
R/W
REN1
R/W
TB81
R/W
RB81
R/W
TI1
R/W
RI1
R/W
Bit 7: SM01, Serial port 1 mode bit 0.
Bit 6: SM11, Serial port 1 mode bit 1.
SM01
SM11
Mode
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
SYSCLK/12
variable
SYSCLK/64, /32
variable
0
0
1
1
0
1
0
1
0
1
2
3
Bit 5: Serial port 0 mode bit 2.
0: Disable SM21 function.
1: Enable the automatic address recognition feature in Modes 2 and 3. If SM21=1, RI1 will not be set unless the
received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In
mode1, if SM21=1 then RI1 will not be set unless a valid stop Bit was received, and the received byte is a
Given or Broadcast address. In Mode 0, SM21 should be 0.
Bit 4: REN1, Enable serial reception.
0: Clear by software to disable reception.
1: Set by software to enable reception.
Bit 3: TB81, The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
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MG82FEL564 Data Sheet
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Bit 2: RB81, In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM21 = 0, RB81 is the stop bit that
was received. In Mode 0, RB81 is not used.
Bit 1: TI1. Transmit interrupt flag.
0: Must be cleared by software.
1: Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes,
in any serial transmission.
Bit 0: RI1. Receive interrupt flag.
0: Must be cleared by software.
1: Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes,
in any serial reception (except see SM21).
SBUF1: Serial port 1 Buffer Register
SFR Page
= 1 only
SFR Address = 0x99
POR+RESET = XXXX-XXXX
7
6
5
4
3
2
1
0
SBUF1[7] SBUF1[6] SBUF1[5] SBUF1[4] SBUF1[3] SBUF1[2] SBUF1[1] SBUF1[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7~0: It is used as the buffer register in transmission and reception.
S1BRT: Serial port 1 Baud Rate Timer Reload Register
SFR Page
= 1 only
SFR Address = 0x9A
POR+RESET = 0000-0000
7
6
5
4
3
2
1
0
S1BRT[7] S1BRT[6] S1BRT[5] S1BRT[4] S1BRT[3] S1BRT[2] S1BRT[1] S1BRT[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7~0: It is used as the reload value register for baud rate timer generator that works in a similar manner as
Timer 1.
SCFG: Serial Port Configuration Register
SFR Page
= 0 only
SFR Address = 0x9A
POR+RESET = 0000-00XX
7
6
5
4
3
2
1
0
URTS
R/W
SMOD2
R/W
URM0X6
S1TR
R/W
S1MOD
R/W
S1TX12
--
R
--
R
R/W
R/W
Bit 7: UART0 Timer Selection.
0: Timer 1 or Timer 2 can be used as the Baud Rate Generator in Mode 1 and Mode 3.
1: Timer 1 overflow signal is replaced by the UART1 Baud Rate Timer overflow signal when Timer 1 is selected
as the Baud Rate Generator in Mode1 or Mode 3 of the UART0. (Refer to Section 12-2.)
Bit 4: S1TR, UART1 Baud Rate Timer control bit.
0: Clear to turn off the S1BRT.
1: Set to turn on S1BRT.
Bit 3: S1SMOD, UART1 double baud rate enable bit.
0: Disable the double baud rate function for UART1.
1: Enable the double baud rate function for UART1.
Bit 2: S1TX12, UART1 Baud Rate Timer clock source select
0: Clear to select SYSCLK/12 as the clock source for S1BRT.
1: Set to select SYSCLK as the clock source for S1BRT.
Bit 1~0: Reserved. Software must write ―0‖s on these bits when SCFG is written.
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13.4.Serial Port Sample Code
(1). Required Function: IDLE mode with RI wake-up capability
Assembly Code Example:
PS
PSH
EQU
EQU
10h
10h
ORG 00023h
uart_ri_idle_isr:
JB
JB
RETI
RI,RI_ISR
TI,TI_ISR
;
;
;
RI_ISR:
; Process
CLR RI
RETI
;
;
TI_ISR:
; Process
CLR TI
RETI
;
;
main:
CLR TI
CLR RI
SETB SM1
SETB REN
;
;
;
; 8bit Mode2, Receive Enable
CALL UART_Baud_Rate_Setting
;
MOV IP,#PSL
MOV IPH,#PSH
; Select UART interrupt priority
;
SETB ES
SETB EA
; Enable S0 interrupt
; Enable global interrupt
ORL PCON,#IDL;
; Set MCU into IDLE mode
C Code Example:
#define PS
#define PSH
0x10
0x10
void uart_ri_idle_isr(void) interrupt 4
{ if(RI)
{
RI=0;
// to do ...
}
if(TI)
{
TI=0;
// to do ...
}
}
void main(void)
{
TI = RI = 0;
SM1 = REN = 1;
// 8bit Mode2, Receive Enable
UART_Baud_Rate_Setting()
IP = PSL;
//
// Select S0 interrupt priority
IPH = PSH;
//
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MG82FEL564 Data Sheet
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ES = 1;
EA = 1;
// Enable S0 interrupt
// Enable global interrupt
PCON |= IDL;
// Set MCU into IDLE mode
}
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MG82FEL564 Data Sheet
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14. Programmable Counter Array (PCA)
The MG82Fx564 is equipped with a Programmable Counter Array (PCA), which provides more timing capabilities
with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead
and improved accuracy.
14.1. PCA Overview
The PCA consists of a dedicated timer/counter which serves as the time base for an array of six compare/capture
modules. Figure 14-1 shows a block diagram of the PCA. Notice that the PCA timer and modules are all 16-bits.
If an external event is associated with a module, that function is shared with the corresponding Port 1 pin. If the
module is not using the port pin, the pin can still be used for standard I/O.
Each of the six modules can be programmed in any one of the following modes:
- Rising and/or Falling Edge Capture
- Software Timer
- High Speed Output
- Pulse Width Modulator (PWM) Output
All of these modes will be discussed later in detail. However, let's first look at how to set up the PCA timer and
modules.
Figure 14-1. PCA Block Diagram
16 Bits Each
Module 0
Module 1
Module 2
Module 3
Module 4
Module 5
P1.2/CEX0
P1.3/CEX1
P1.4/CEX2
P1.5/CEX3
P1.6/CEX4
P1.7/CEX5
16 Bits
PCA Timer/Counter
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MG82FEL564 Data Sheet
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14.2. PCA Timer/Counter
The timer/counter for the PCA is a free-running 16-bit timer consisting of registers CH and CL (the high and low
bytes of the count values), as shown in Figure 14-2. It is the common time base for all modules and its clock input
can be selected from the following source:
- 1/12 the system clock frequency,
- 1/2 the system clock frequency,
- the Timer 0 overflow, which allows for a range of slower clock inputs to the timer.
- external clock input, 1-to-0 transitions, on ECI pin (P1.1).
Special Function Register CMOD contains the Count Pulse Select bits (CPS1 and CPS0) to specify the PCA
timer input. This register also contains the ECF bit which enables an interrupt when the counter overflows. In
addition, the user has the option of turning off the PCA timer during Idle Mode by setting the Counter Idle bit
(CIDL). This can further reduce power consumption during Idle mode.
Figure 14-2. PCA Timer/Counter
CMOD: PCA Counter Mode Register
SFR Page
= All
SFR Address = 0xD9
RESET = 0xxx-x000
7
6
5
4
3
2
1
0
CIDL
R/W
FEOV
R/W
--
R
--
R
--
R
CPS1
R/W
CPS0
R/W
ECF
R/W
Bit 7: CIDL, PCA counter Idle control.
0: Lets the PCA counter continue functioning during Idle mode.
1: Lets the PCA counter be gated off during Idle mode.
Bit 6: FEOV, Maximum Counter {CL} value on FE.
FEOV=0 Maximum CL counter value on FF.
FEOV=1 Maximum CL counter value on FE.
Bit 5~3: Reserved. Software must write ―0‖s on these bits when CMOD is written.
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Bit 2~1: CPS1-CPS0, PCA counter clock source select bits.
CPS1
CPS0
PCA Clock Source
0
0
1
1
0
1
0
1
Internal clock, (system clock)/12
Internal clock, (system clock)/2
Timer 0 overflow
External clock at the ECI pin
Bit 0: ECF,
Enable PCA counter overflow interrupt.
0: Disables an interrupt when CF bit (in CCON register) is set.
1: Enables an interrupt when CF bit (in CCON register) is set.
The CCON register shown below contains the run control bit for the PCA and the flags for the PCA timer and
each module. To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this
bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit
in the CMOD register is set. The CF bit can only be cleared by software. CCF0 to CCF5 are the interrupt flags for
module 0 to module 5, respectively, and they are set by hardware when either a match or a capture occurs.
These flags also can only be cleared by software. The PCA interrupt system is shown Figure 14-3.
CCON: PCA Counter Control Register
SFR Page
= All
SFR Address = 0xD8
RESET = 0000-0000
7
6
5
4
3
2
1
0
CF
R/W
CR
R/W
CCF5
R/W
CCF4
R/W
CCF3
R/W
CCF2
R/W
CCF1
R/W
CCF0
R/W
Bit 7: CF, PCA Counter Overflow flag.
0: Only be cleared by software.
1: Set by hardware when the counter rolls over. CF flag can generate an interrupt if bit ECF in CMOD is set. CF
may be set by either hardware or software.
Bit 6: CR, PCA Counter Run control bit.
0: Must be cleared by software to turn the PCA counter off.
1: Set by software to turn the PCA counter on.
Bit 5: CCF5, PCA Module 5 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
Bit 4: CCF4, PCA Module 4 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
Bit 3: CCF3, PCA Module 3 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
Bit 2: CCF2, PCA Module 2 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
Bit 1: CCF1, PCA Module 1 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
Bit 0: CCF0, PCA Module 0 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
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MG82FEL564 Data Sheet
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Figure 14-3. PCA Interrupt System
CF
CR
CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
CCON
CMOD.ECF
PCA Timer/Counter
Module 0
Module 1
Module 2
Module 3
Module 4
Module 5
EIE1.EPCA
IE.EA
To Interrupt
Priority Processing
CCAPMn.0 (n=0~5)
ECCF0~ECCF5
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14.3. Compare/Capture Modules
Each of the six compare/capture modules has a mode register called CCAPMn (n e 0,1,2,3,or 4) to select which
function it will perform. Note the ECCFn bit which enables an interrupt to occur when a module's interrupt flag is
set.
CCAPMn: PCA Module Compare/Capture Register, n=0~5
SFR Page
= All
SFR Address = 0xDA~0xDF
RESET = x000-0000
7
6
5
4
3
2
1
0
--
R
ECOMn
R/W
CAPPn
R/W
CAPNn
R/W
MATn
R/W
TOGn
R/W
PWMn
R/W
ECCFn
R/W
Bit 7: Reserved. Software must write ―0‖ on this bit when the CCAPMn is written.
Bit 6: ECOMn, Enable Comparator
0: Disable the digital comparator function.
1: Enables the digital comparator function.
Bit 5: CAPPn, Capture Positive enabled.
0: Disable the PCA capture function on CEXn positive edge detected.
1: Enable the PCA capture function on CEXn positive edge detected.
Bit 4: CAPNn, Capture Negative enabled.
0: Disable the PCA capture function on CEXn positive edge detected.
1: Enable the PCA capture function on CEXn negative edge detected.
Bit 3: MATn, Match control.
0: Disable the digital comparator match event to set CCFn.
1: A match of the PCA counter with this module‘s compare/capture register causes the CCFn bit in CCON to be
set.
Bit 2: TOGn, Toggle control.
0: Disable the digital comparator match event to toggle CEXn.
1: A match of the PCA counter with this module‘s compare/capture register causes the CEXn pin to toggle.
Bit 1: PWMn, PWM control.
0: Disable the PWM mode in PCA module.
1: Enable the PWM function and cause CEXn pin to be used as a pulse width modulated output.
Bit 0: ECCFn, Enable CCFn interrupt.
0: Disable compare/capture flag CCFn in the CCON register to generate an interrupt.
1: Enable compare/capture flag CCFn in the CCON register to generate an interrupt.
Note: The bits CAPNn (CCAPMn.4) and CAPPn (CCAPMn.5) determine the edge on which a capture input will
be active. If both bits are set, both edges will be enabled and a capture will occur for either transition.
Each module also has a pair of 8-bit compare/capture registers (CCAPnH, CCAPnL) associated with it. These
registers are used to store the time when a capture event occurred or when a compare event should occur.
When a module is used in the PWM mode, in addition to the above two registers, an extended register
PCAPWMn is used to improve the range of the duty cycle of the output. The improved range of the duty cycle
starts from 0%, up to 100%, with a step of 1/256.
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MG82FEL564 Data Sheet
MEGAWIN
PCAPWMn: PWM Mode Auxiliary Register, n=0~5
SFR Page = All
SFR Address = 0xF2~0xF7
RESET = 0000-0000
7
6
5
4
3
2
1
0
PnRS1
R/W
PnRS0
R/W
PnPS2
R/W
PnPS1
R/W
PnPS0
R/W
PnINV
R/W
ECAPnH
ECAPnL
R/W
R/W
ECAPnH: Extended 9th bit (MSB bit), associated with CCAPnH to become a 9-bit register used in PWM mode.
ECAPnL: Extended 9th bit (MSB bit), associated with CCAPnL to become a 9-bit register used in PWM mode.
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MG82FEL564 Data Sheet
83
14.4. Operation Modes of the PCA
Table 14-1 shows the CCAPMn register settings for the various PCA functions.
Table 14-1. PCA Module Modes
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Module Function
0
X
X
X
1
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
X
X
X
X
X
0
No operation
16-bit capture by a positive-edge trigger on CEXn
16-bit capture by a negative-edge trigger on CEXn
16-bit capture by a transition on CEXn
16-bit Software Timer
1
16-bit High Speed Output
1
8-bit Pulse Width Modulator (PWM)
14.4.1. Capture Mode
To use one of the PCA modules in the capture mode, either one or both of the bits CAPN and CAPP for that
module must be set. The external CEX input for the module is sampled for a transition. When a valid transition
occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module‘s capture
registers (CCAPnL and CCAPnH). If the CCFn and the ECCFn bits for the module are both set, an interrupt will
be generated.
Figure 14-4. PCA Capture Mode
CF
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
PCA Interrupt
(To CCFn)
Capture
PCA Timer/Counter
CH
CL
CEXn
CCAPnH
CCAPnL
--
ECOMn
0
CAPPn CAPNn
MATn
TOGn
0
PWMn
0
ECCFn
CCAPMn, n= 0 to 5
1
1
0
CAPPn or CAPNn =1
14.4.2. 16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the module‘s
CCAPMn register. The PCA timer will be compared to the module‘s capture registers, and when a match occurs
an interrupt will occur if the CCFn and the ECCFn bits for the module are both set.
84
MG82FEL564 Data Sheet
MEGAWIN
Figure 14-5. PCA Software Timer Mode
CF
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
Write to
CCAPnL
Reset
Write to
CCAPnH
CCAPnH
CCAPnL
(To CCFn)
PCA Interrupt
1
0
Enable
Match
16-Bit Comparator
CH
CL
PCA Timer/Counter
--
ECOMn
CAPPn CAPNn
MATn
1
TOGn
PWMn
0
ECCFn
CCAPMn, n= 0 to 5
0
0
0
14.4.3. High Speed Output Mode
In this mode the CEX output associated with the PCA module will toggle each time a match occurs between the
PCA counter and the module‘s capture registers. To activate this mode, the TOG, MAT and ECOM bits in the
module‘s CCAPMn register must be set.
Figure 14-6. PCA High Speed Output Mode
CF
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
Write to
CCAPnL
Reset
Write to
CCAPnH
CCAPnH
CCAPnL
(To CCFn)
PCA Interrupt
1
0
Enable
Match
16-Bit Comparator
Toggle
CH
CL
CEXn
PCA Timer/Counter
--
ECOMn
CAPPn CAPNn
MATn
1
TOGn
PWMn
0
ECCFn
CCAPMn, n= 0 to 5
0
0
1
14.4.4. PWM Mode
All of the PCA modules can be used as PWM outputs. The frequency of the output depends on the clock source
for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA
timer.
The duty cycle of each module is determined by the module‘s capture register CCAPnL and the extended 9th bit,
ECAPnL. When the 9-bit value of { 0, [CL] } is less than the 9-bit value of { ECAPnL, [CCAPnL] } the output will
be low, and if equal to or greater than the output will be high.
MEGAWIN
MG82FEL564 Data Sheet
85
When CL overflows from 0xFF to 0x00, { ECAPnL, [CCAPnL] } is reloaded with the value of { ECAPnH,
[CCAPnH] }. This allows updating the PWM without glitches. The PWMn and ECOMn bits in the module‘s
CCAPMn register must be set to enable the PWM mode.
Using the 9-bit comparison, the duty cycle of the output can be improved to really start from 0%, and up to 100%.
The formula for the duty cycle is:
Duty Cycle = 1 – { ECAPnH, [CCAPnH] } / 256.
Where, [CCAPnH] is the 8-bit value of the CCAPnH register, and ECAPnH (bit-1 in the PCAPWMn register) is 1-
bit value. So, { ECAPnH, [CCAPnH] } forms a 9-bit value for the 9-bit comparator.
For examples,
a. If ECAPnH=0 & CCAPnH=0x00 (i.e., 0x000), the duty cycle is 100%.
b. If ECAPnH=0 & CCAPnH=0x40 (i.e., 0x040) the duty cycle is 75%.
c. If ECAPnH=0 & CCAPnH=0xC0 (i.e., 0x0C0), the duty cycle is 25%.
d. If ECAPnH=1 & CCAPnH=0x00 (i.e., 0x100), the duty cycle is 0%.
Figure 14-7. PCA PWM Mode
CF
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
9 Bits
(To CCFn)
PCA Interrupt
ECAPnH
ECAPnL
CCAPnH
ECCFn
9 Bits
CCAPnL
MATn
Match
Enable
9-Bit
Comparator
S
R
Q
0
1
CEXn
Q
9 Bits
PnINV
CL
Overflow
(Fixed 0)
CL
PCA Timer/Counter
--
ECOMn
1
CAPPn CAPNn
MATn
0
TOGn
0
PWMn
1
ECCFn
0
CCAPMn, n= 0 to 5
0
0
14.4.5. Enhance PWM Mode
The MG82Fx564 provides the variable PWM mode to enhance the control capability on PWM application. There
are additional 10/12/16 bits PWM can be assigned in each channel and each PWM channel with different
resolution can operate concurrently.
86
MG82FEL564 Data Sheet
MEGAWIN
Figure 14-8. PCA Enhance PWM Mode
CF
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(To CCFn)
PCA Interrupt
ECCFn
10/12/16 Bits
CCAPnL
CCAPnH
MATn
Enable
Match
S
R
Q
10/12/16-Bit Comparator
0
1
CEXn
Overflow
Q
16 Bits
CH
CL
PnINV
PCA Timer/Counter
ECOMn
1
--
CAPPn CAPNn
MATn
0
TOGn
0
PWMn
ECCFn
CCAPMn, n= 0 to 5
0
0
1
0
PCAPWMn: PWM Mode Auxiliary Register, n=0~5
SFR Page = All
SFR Address = 0xF2~0xF7
POR+RESET = 0000-0000
7
6
5
4
3
2
1
0
PnRS1
R/W
PnRS0
R/W
PnPS2
R/W
PnPS1
R/W
PnPS0
R/W
PnINV
R/W
ECAPnH
ECAPnL
R/W
R/W
Bit 7~6: PnRS1~0, PWMn Resolution Setting 1~0.
00: 8 bit PWMn, the overflow is active when {CH,CL} is 0xXXFF 0xXX00.
01: 10 bit PWMn, the overflow is active when {CH,CL} is 0xXx3FF 0xXx[00]00.
10: 12 bit PWMn, the overflow is active when {CH,CL} is 0xXxFFF 0xXx000.
11: 16 bit PWMn, the overflow is active when {CH,CL} is 0xFFFF 0x0000.
Bit 5~3: PnPS2~0, PWMn Start Phase Setting 2~0.
000: The enabled PWM channel starts at 0 degree and ends at digital comparator matched.
001: The enabled PWM channel starts at 90 degree and ends at digital comparator matched.
010: The enabled PWM channel starts at 180 degree and ends at digital comparator matched.
011: The enabled PWM channel starts at 270 degree and ends at digital comparator matched.
100: The enabled PWM channel starts at 120 degree and ends at digital comparator matched.
101: The enabled PWM channel starts at 240 degree and ends at digital comparator matched.
110: The enabled PWM channel starts at 60 degree and ends at digital comparator matched.
111: The enabled PWM channel starts at 300 degree and ends at digital comparator matched.
Bit 2: PnINV, Invert PWM output on CEXn.
0: Non-inverted PWM output.
1: Inverted PWM output.
Bit 1: ECAPnH: Extended MSB bit, associated with CCAPnH to become a 9th-bit register used in 8-bit PWM
mode. As well as for 10/12/16 bit PWM, it will become a 11th/13th/17th bit register.
MEGAWIN
MG82FEL564 Data Sheet
87
Bit 0: ECAPnL: Extended MSB bit, associated with CCAPnL to become a 9th-bit register used in 8-bit PWM
mode. As well as for 10/12/16 bit PWM, it will become a 11th/13th/17th bit register.
CMOD: PCA Counter Mode Register
SFR Page
= All
SFR Address = 0xD9
POR+RESET = 0xxx-x000
7
6
5
4
3
2
1
0
CIDL
R/W
FEOV
R/W
--
R
--
R
--
R
CPS1
R/W
CPS0
R/W
ECF
R/W
FEOV: Maximum Counter {CL} value on FE.
FEOV=0 Maximum CL counter value on FF.
FEOV=1 Maximum CL counter value on FE.
88
MG82FEL564 Data Sheet
MEGAWIN
14.5. PCA Sample Code
(1). Required Function: Set PWM2/PWM3 output with 25% & 75% duty cycle
Assembly Code Example:
PWM2
ECOM2
PWM3
ECOM3
EQU
EQU
EQU
EQU
02h
40h
02h
40h
PWM2_PWM3:
MOV
CCON,#00H
CMOD,#02H
; stop CR
MOV
; PCA clock source = system clock / 2
MOV
MOV
CCAPM2, #(ECOM2 + PWM2)
CCAP2H,#0C0H
; enable PCA module 2 (PWM mode)
; 25%
MOV
MOV
;
CCAPM3, #(ECOM3 + PWM3)
CCAP3H,#40H
; enable PCA module 3 (PWM mode)
; 75%
SETB
CR
; start PCA
C Code Example:
#define PWM2
#define ECOM2
#define PWM3
#define ECOM3
EQU
EQU
EQU
EQU
0x02
0x40
0x02
0x40
void main(void)
{
// set PCA
CCON = 0x00;
CMOD = 0x02;
// disable PCA & clear CCF0, CCF1, CCF2, CCF3, CF flag
// PCA clock source = system clock / 2
CCAPM2 |= (ECOM2 | PWM2);
CCAP2H = 0xC0;
// module 2 (Non-inverted)
// 25%
CCAPM3 |= (ECOM3 | PWM3);
CCAP3H = 0x40;
// module 3
// 75 %
//----------------------------------------------
CR = 1;
// start PCA's PWM output
while (1);
}
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MG82FEL564 Data Sheet
89
15. Serial Peripheral Interface (SPI)
The MG82Fx564 provides a high-speed serial communication interface, the SPI interface. SPI is a full-duplex,
high-speed and synchronous communication bus with two operation modes: Master mode and Slave mode. Up
to 3 Mbps can be supported in either Master or Slave mode under a 12MHz system clock. It has a Transfer
Completion Flag (SPIF) and Write Collision Flag (WCOL) in the SPI status register (SPSTAT).
Figure 15-1. SPI Block Diagram
SPICLK
(P1.7)
Output Shift Register
Input Shift Register
Divider
by
MISO
(P1.6)
SYSCLK
4
I/O
16
64
128
Control
MOSI
(P1.5)
SPI Control
nSS
(P1.4)
SSIG
SPIF
SPEN
DORD
--
MSTR
--
CPOL
--
CPHA
--
SPR1
--
SPR0
--
SPCTL
WCOL
SPSTAT
The SPI interface has four pins: MISO (P1.6), MOSI (P1.5), SPICLK (P1.7) and /SS (P1.4):
• SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master
to slave on the MOSI pin (Master Out / Slave In) and flows from slave to master on the MISO pin (Master In /
Slave Out). The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e., SPEN (SPCTL.6) = 0, these pins function as normal I/O pins.
• /SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to
select one SPI device as the current slave. An SPI slave device uses its /SS pin to determine whether it is
selected. The /SS is ignored if any of the following conditions are true:
- If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value).
- If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and P1.4 (/SS) is configured as an output.
- If the /SS pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port functions.
Note that even if the SPI is configured as a master (MSTR=1), it can still be converted to a slave by driving the
/SS pin low (if SSIG=0). Should this happen, the SPIF bit (SPSTAT.7) will be set. (See Section 15.2.3: Mode
change on /SS-pin)
15.1. Typical SPI Configurations
15.1.1. Single Master & Single Slave
For the master: any port pin, including P1.4 (/SS), can be used to drive the /SS pin of the slave.
For the slave: SSIG is ‗0‘, and /SS pin is used to determine whether it is selected.
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MG82FEL564 Data Sheet
MEGAWIN
Figure 15-2. SPI single master & single slave configuration
SPICLK
MISO
SPICLK
MISO
MOSI
nSS
Master
Slave
MOSI
Port Pin
15.1.2. Dual Device, where either can be a Master or a Slave
Two devices are connected to each other and either device can be a master or a slave. When no SPI operation is
occurring, both can be configured as masters with MSTR=1, SSIG=0 and P1.4 (/SS) configured in quasi-
bidirectional mode. When any device initiates a transfer, it can configure P1.4 as an output and drive it low to
force a ―mode change to slave‖ in the other device. (See Section 15.2.3: Mode change on /SS-pin)
Figure 15-3. SPI dual device configuration, where either can be a master or a slave
SPICLK
MISO
MOSI
nSS
SPICLK
MISO
MOSI
nSS
Master/
Slave
Slave/
Master
15.1.3. Single Master & Multiple Slaves
For the master: any port pin, including P1.4 (/SS), can be used to drive the /SS pins of the slaves.
For all the slaves: SSIG is ‗0‘, and /SS pin are used to determine whether it is selected.
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MG82FEL564 Data Sheet
91
Figure 15-4. SPI single master multiple slaves configuration
SPICLK
MISO
SPICLK
MISO
MOSI
nSS
Slave #1
MOSI
Port Pin 1
Master
SPICLK
MISO
MOSI
nSS
Slave #2
Port Pin 2
92
MG82FEL564 Data Sheet
MEGAWIN
15.2. Configuring the SPI
Table 15-1 shows configuration for the master/slave modes as well as usages and directions for the modes.
Table 15-1. SPI Master and Slave Selection
nSS
-pin
MISO MOSI SPICLK
SPEN
(SPCTL.6) (SPCTL.7)
SSIG
MSTR
(SPCTL.4)
Mode
Remarks
-pin
-pin
-pin
P1.4~P1.7 are used as general
port pins.
0
1
1
X
0
0
X
0
1
X
0
0
SPI disabled input input input
Salve
Selected as slave.
Not selected.
output input input
(selected)
Slave
(not selected)
Hi-Z
input input
Mode change to slave
Slave
(by
change)
if /SS pin is driven low, and MSTR
will be cleared to ‗0‘ by H/W
automatically.
1
1
0
0
0
1
1 0
output input input
mode
MOSI and SPICLK are at high
impedance
to
avoid
bus
Master
(idle)
Hi-Z
Hi-Z
contention when the Master is
idle.
1
input
MOSI and SPICLK are push-pull
when the Master is active.
Master
(active)
output output
1
1
1
1
X
X
0
1
Slave
output input input
input output output
Master
―X‖ means ―don‘t care‖.
15.2.1. Additional Considerations for a Slave
When CPHA is 0, SSIG must be 0 and nSS pin must be negated and reasserted between each successive serial
byte transfer. Note the SPDAT register cannot be written while nSS pin is active (low), and the operation is
undefined if CPHA is 0 and SSIG is 1.
When CPHA is 1, SSIG may be 0 or 1. If SSIG=0, the nSS pin may remain active low between successive
transfers (can be tied low at all times). This format is sometimes preferred for use in systems having a single
fixed master and a single slave configuration.
15.2.2. Additional Considerations for a Master
In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN=1) and selected as master,
writing to the SPI data register (SPDAT) by the master starts the SPI clock generator and data transfer. The data
will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT.
Before starting the transfer, the master may select a slave by driving the nSS pin of the corresponding device low.
Data written to the SPDAT register of the master is shifted out of MOSI pin of the master to the MOSI pin of the
slave. And, at the same time the data in SPDAT register of the selected slave is shifted out on MISO pin to the
MISO pin of the master.
After shifting one byte, the SPI clock generator stops, setting the transfer completion flag (SPIF) and an interrupt
will be created if the SPI interrupt is enabled. The two shift registers in the master CPU and slave CPU can be
considered as one distributed 16-bit circular shift register. When data is shifted from the master to the slave, data
is also shifted in the opposite direction simultaneously. This means that during one shift cycle, data in the master
and the slave are interchanged.
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MG82FEL564 Data Sheet
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15.2.3. Mode Change on nSS-pin
If SPEN=1, SSIG=0, MSTR=1 and nSS pin=1, the SPI is enabled in master mode. In this case, another master
can drive this pin low to select this device as an SPI slave and start sending data to it. To avoid bus contention,
the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be
an input and MISO becomes an output. The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an
SPI interrupt will occur. User software should always check the MSTR bit. If this bit is cleared by a slave select
and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it will
stay in slave mode.
15.2.4. Write Collision
The SPI is single buffered in the transmit direction and double buffered in the receive direction. New data for
transmission can not be written to the shift register until the previous transaction is complete. The WCOL
(SPSTAT.6) bit is set to indicate data collision when the data register is written during transmission. In this case,
the data currently being transmitted will continue to be transmitted, but the new data, i.e., the one causing the
collision, will be lost.
While write collision is detected for both a master or a slave, it is uncommon for a master because the master has
full control of the transfer in progress. The slave, however, has no control over when the master will initiate a
transfer and therefore collision can occur.
For receiving data, received data is transferred into a parallel read data buffer so that the shift register is free to
accept a second character. However, the received character must be read from the Data Register (SPDAT)
before the next character has been completely shifted in. Otherwise, the previous data is lost.
WCOL can be cleared in software by writing ‗1‘ to the bit.
15.2.5. SPI Clock Rate Select
The SPI clock rate selection (in master mode) uses the SPR1 and SPR0 bits in the SPCTL register, as shown in
Table 15-2.
Table 15-2. SPI Serial Clock Rates
SPI
Clock
Rate
@
SPR1
SPR0
SYSCLK divided by
SYSCLK=12MHz
0
0
1
1
0
1
0
1
3 MHz
4
750 KHz
16
64
128
187.5 KHz
93.75 KHz
Where, SYSCLK is the system clock.
94
MG82FEL564 Data Sheet
MEGAWIN
15.3. Data Mode
Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit,
CPOL, allows the user to set the clock polarity. The following figures show the different settings of Clock Phase
Bit, CPHA.
Figure 15-5. SPI Slave Transfer Format with CPHA=0
1
2
3
4
5
6
7
8
Clock Cycle
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit in
MOSI
Slave Intput
DORD=0
DORD=1
MSB
6
5
4
3
2
1
LSB
MSB
LSB
1
2
3
4
5
6
Not
defined
MISO
Slave Output
1st bit out
data sampled
nSS (if SSIG=0)
This edge is used by the slave to shift out the 1st bit
of each data byte while CPHA=0
Figure 15-6. Slave Transfer Format with CPHA=1
1
2
3
4
5
6
7
8
Clock Cycle
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit in
MOSI
Slave Intput
DORD=0
DORD=1
MSB
6
5
4
3
2
1
6
LSB
LSB
1
2
3
4
5
MSB
Not
defined
MISO
Slave Output
1st bit out
Not defined
data sampled
nSS (if SSIG=0)
MEGAWIN
MG82FEL564 Data Sheet
95
Figure 15-7. SPI Master Transfer Format with CPHA=0
1
2
3
4
5
6
7
8
Enable SPI
Clock Cycle
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit out
MOSI
Master Output
DORD=0
DORD=1
MSB
LSB
6
5
4
3
2
1
LSB
MSB
1
2
3
4
5
6
MISO
Master Input
1st bit in
data sampled
nSS (if SSIG=0)
Figure 15-8. SPI Master Transfer Format with CPHA=1
1
2
3
4
5
6
7
8
Clock Cycle
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit out
MOSI
Master Output
DORD=0
DORD=1
MSB
LSB
6
5
4
3
4
2
5
1
6
LSB
1
2
3
MSB
MISO
Master Input
1st bit in
data sampled
nSS (if SSIG=0)
96
MG82FEL564 Data Sheet
MEGAWIN
15.4. SPI Register
The following special function registers are related to the SPI operation:
SPCON: SPI Control Register
SFR Page
= All
SFR Address = 0x85
RESET= 0000-0100
7
6
5
4
3
2
1
0
SSIG
R/W
SPEN
R/W
DORD
R/W
MSTR
R/W
CPOL
R/W
CPHA
R/W
SPR1
R/W
SPR0
R/W
Bit 7: SSIG, nSS is ignored.
0: The nSS pin decides whether the device is a master or slave.
1: MSTR decides whether the device is a master or slave.
Bit 6: SPEN, SPI enable.
0: The SPI interface is disabled and all SPI pins will be general-purpose I/O ports.
1: The SPI is enabled.
Bit 5: DORD, SPI data order.
0: The MSB of the data byte is transmitted first.
1: The LSB of the data byte is transmitted first.
Bit 4: MSTR, Master/Slave mode select
0: Selects slave SPI mode.
1: Selects master SPI mode.
Bit 3: CPOL, SPI clock polarity select
0: SPICLK is low when Idle. The leading edge of SPICLK is the rising edge and the trailing edge is the falling
edge.
1: SPICLK is high when Idle. The leading edge of SPICLK is the falling edge and the trailing edge is the rising
edge.
Bit 2: CPHA, SPI clock phase select
0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is sampled on
the leading edge of SPICLK.
1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
(Note: If SSIG=1, CPHA must not be 1, otherwise the operation is not defined.)
Bit 1~0: SPR1-SPR0, SPI clock rate select (in master mode)
00: SYSCLK/4
01: SYSCLK/16
10: SYSCLK/64
11: SYSCLK/128 (Where, SYSCLK is the system clock.)
SPSTAT: SPI Status Register
SFR Page
= All
SFR Address = 0x84
RESET= 00XX-XXXX
7
6
5
4
3
2
1
0
SPIF
R/W
WCOL
R/W
--
R
--
R
--
R
--
R
--
R
--
R
Bit 7: SPIF, SPI transfer completion flag
0: The SPIF is cleared in software by writing ‘1’ to this bit.
1: When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if SPI interrupt is enabled. If
nSS pin is driven low when SPI is in master mode with SSIG=0, SPIF will also be set to signal the ―mode
change‖.
Bit 6: WCOL, SPI write collision flag.
0: The WCOL flag is cleared in software by writing ‘1’ to this bit.
MEGAWIN
MG82FEL564 Data Sheet
97
1: The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer (see Section 15.2.4:
Write Collision).
Bit 5~0: Reserved.
SPDAT: SPI Data Register
SFR Page
= All
SFR Address = 0x86
RESET= 0000-0000
7
6
5
4
3
2
1
0
(MSB)
R/W
(LSB)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SPDAT has two physical buffers for writing to and reading from during transmit and receive, respectively.
98
MG82FEL564 Data Sheet
MEGAWIN
15.5. SPI Sample Code
(1). Required Function: SPI Master Read and Write, sample data at rising edge and clock leading edge is rising.
Assembly Code Example:
CPHA
CPOL
MSTR
SPEN
SSIG
SPIF
EQU
EQU
EQU
EQU
EQU
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
;initial SPI
ORL SPICTL, #(SSIG + SPEN + MSTR)
RET
;enable SPI and Master mode
SPI_Write:
MOV SPIDAT, R7
wait_write:
;write arg R7
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
;trigger SPI read
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR);
// enable SPI and Master mode
}
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
//write arg
//wait transfer finishes
//clear SPI interrupt flag
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
MEGAWIN
MG82FEL564 Data Sheet
99
(2). Required Function: SPI Master Read and Write, sample data at rising edge and clock leading edge is falling.
Assembly Code Example:
CPHA
CPOL
MSTR
SPEN
SSIG
SPIF
EQU
EQU
EQU
EQU
EQU
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
;initial SPI
ORL SPICTL, #(SSIG + SPEN + MSTR + CPOL)
RET
;enable SPI and Master mode
SPI_Write:
MOV SPIDAT, R7
wait_write:
;write arg R7
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
;trigger SPI read
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR | CPOL);
// enable SPI and Master mode
}
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
//write arg
//wait transfer finishes
//clear SPI interrupt flag
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
100
MG82FEL564 Data Sheet
MEGAWIN
(3). Required Function: SPI Master Read and Write, sample data at falling edge and clock leading edge is rising.
Assembly Code Example:
CPHA
CPOL
MSTR
SPEN
SSIG
SPIF
EQU
EQU
EQU
EQU
EQU
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
;initial SPI
ORL SPICTL, #(SSIG + SPEN + MSTR + CPHA)
RET
;enable SPI and Master mode
SPI_Write:
MOV SPIDAT, R7
wait_write:
;write arg R7
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
;trigger SPI read
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR | CPHA);
// enable SPI and Master mode
}
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
//write arg
//wait transfer finishes
//clear SPI interrupt flag
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
MEGAWIN
MG82FEL564 Data Sheet
101
(4). Required Function: SPI Master Read and Write, sample data at falling edge and clock leading edge is falling.
Assembly Code Example:
CPHA
CPOL
MSTR
SPEN
SSIG
SPIF
EQU
EQU
EQU
EQU
EQU
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
;initial SPI
ORL SPICTL, #(SSIG + SPEN + MSTR + CPOL + CPHA)
RET
;enable SPI and Master mode
SPI_Write:
MOV SPIDAT, R7
wait_write:
;write arg R7
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
;trigger SPI read
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR | CPOL | CPHA);
// enable SPI and Master mode
}
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
//write arg
//wait transfer finishes
//clear SPI interrupt flag
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
102
MG82FEL564 Data Sheet
MEGAWIN
16. Keypad Interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 2 is
equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad
recognition.
There are three SFRs used for this function. The Keypad Interrupt Mask Register (KBMASK) is used to define
which input pins connected to Port 2 are enabled to trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 2. The Keypad Interrupt Flag (KBIF) in the
Keypad Interrupt Control Register (KBCON) is set by hardware when the condition is matched. An interrupt will
be generated if it has been enabled by setting the EKBI bit in EIE1 register and EA=1. The PATN_SEL bit in the
Keypad Interrupt Control Register (KBCON) is used to define ―equal‖ or ―not-equal‖ for the comparison.
In order to use the Keypad Interrupt as the ―Keyboard‖ Interrupt, the user needs to set KBPATN=0xFF and
PATN_SEL=0 (not equal), then any key connected to Port 2 which is enabled by KBMASK register will cause the
hardware to set the interrupt flag KBIF and generate an interrupt if it has been enabled. The interrupt may wake
up the CPU from Idle mode or Power-Down mode. This feature is particularly useful in handheld, battery powered
systems that need to carefully manage power consumption but also need to be convenient to use.
16.1. Keypad Register
The following special function registers are related to the KBI operation:
KBPATN: Keypad Pattern Register
SFR Page
= All
SFR Address = 0xD5
RESET= 1111-1111
7
6
5
4
3
2
1
0
KBPATN.7 KBPATN.6 KBPATN.5 KBPATN.4 KBPATN.3 KBPATN.2 KBPATN.1 KBPATN.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7~0: KBPATN.7~0: The keypad pattern, reset value is 0xFF.
KBCON: Keypad Control Register
SFR Page
= All
SFR Address = 0xD6
RESET= XXXX-XX00
7
6
5
4
3
2
1
0
--
R
--
R
--
R
--
R
--
R
--
R
PATN_SEL
KBIF
R/W
R/W
Bit 7~2: Reserved.
Bit 1: PATN_SEL, Pattern Matching Polarity selection.
0: The keypad input has to be not equal to user-defined keypad pattern in KBPATN to generate the interrupt.
1: The keypad input has to be equal to the user-defined keypad pattern in KBPATN to generate the interrupt.
Bit 0: KBIF, Keypad Interrupt Flag.
0: Must be cleared by software by writing ―0‖.
1: Set when Port 2 matches user defined conditions specified in KBPATN, KBMASK, and PATN_SEL.
KBMASK: Keypad Interrupt Mask Register
SFR Page
= All
SFR Address = 0xD7
RESET= 0000-0000
7
6
5
4
3
2
1
0
KBMASK.7 KBMASK.6 KBMASK.5 KBMASK.4 KBMASK.3 KBMASK.2 KBMASK.1 KBMASK.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MEGAWIN
MG82FEL564 Data Sheet
103
KBMASK.7: When set, enables P2.7 as a cause of a Keypad Interrupt (KBI7).
KBMASK.6: When set, enables P2.6 as a cause of a Keypad Interrupt (KBI6).
KBMASK.5: When set, enables P2.5 as a cause of a Keypad Interrupt (KBI5).
KBMASK.4: When set, enables P2.4 as a cause of a Keypad Interrupt (KBI4).
KBMASK.3: When set, enables P2.3 as a cause of a Keypad Interrupt (KBI3).
KBMASK.2: When set, enables P2.2 as a cause of a Keypad Interrupt (KBI2).
KBMASK.1: When set, enables P2.1 as a cause of a Keypad Interrupt (KBI1).
KBMASK.0: When set, enables P2.0 as a cause of a Keypad Interrupt (KBI0).
104
MG82FEL564 Data Sheet
MEGAWIN
16.2. Keypad Interrupt Sample Code
(1). Required Function: Implement a KBI function on P2.3~P2.0
Assembly Code Example:
Jmp main;
ORG 0006Bh
KBI_ISR:
PUSH ACC
;
;
To do KBI key check……
ANL KBCON,#(0FFh - KBIF)
; Clear KBI flag (write ―0‖)
POP ACC
RETI
;
;
main:
ANL P2M1,#0F0h
ORL P2M0,#00Fh
; Set P2.3~P2.0 to Input mode
; Set P2.3~P2.0 to Input mode
MOV KBMASK,#00Fh
; Enable P2.3~P2.0 KBI function
ANL KBCON,# (0FFh - KBIF)
; Clear KBI flag (write ―0‖)
ORL AUXIE,#EKBI
SETB EA
; Enable KBI interrupt
; Enable global interrupt
Jmp $;
C Code Example:
void KBI_ISR(void) interrupt 13
{
// Do KBI key check
KBCON &= ~KBIF;
// Clear KBI Flag
}
}
void main(void)
{
P2M1 &= 0xF0;
P2M0 |= 0x0F;
// Set P2.3~P2.0 to Input mode
// Set P2.3~P2.0 to Input mode
KBMASK = 0x0F;
KBCON &= ~KBIF;
AUXIE |= EKBI;
// Enable P2.3~P2.0 KBI function
// Clear KBI flag (write ―0‖)
// Enable KBI interrupt
EA = 1;
// Enable global interrupt
While(1);
}
MEGAWIN
MG82FEL564 Data Sheet
105
17. 10-Bit ADC
The ADC subsystem for the MG82Fx564 consists of an analog multiplexer (AMUX), and a 200 ksps, 10-bit
successive-approximation-register ADC. The AMUX can be configured via the Special Function Registers shown
in Figure 17-1. ADC operates in Single-ended modes, and may be configured to measure any of the pins on Port
1. The ADC subsystem is enabled only when the ADEN bit in the ADC Control register (ADCON) is set to logic 1.
The ADC subsystem is in low power shutdown when this bit is logic 0.
Note: Suggest user doing ADC conversion under SYSCLK don‘t over 20MHz in High temperature ( Over 60℃)
environment.
17.1. ADC Structure
Figure 17-1. ADC Block Diagram
B9
--
B8
--
B7
--
B6
--
B5
--
B4
--
B3
B1
B2
B0
AMUX
ADCH
ADCL
(P1.0) AIN0
(P1.1) AIN1
(P1.2) AIN2
(P1.3) AIN3
(P1.4) AIN4
(P1.5) AIN5
(P1.6) AIN6
(P1.7) AIN7
10
10-Bit
ADC
Load
/60
200 ksps (Max.)
/120
/180
/240
SYSCLK
ADCEN
SPEED1
SPEED0
ADCI
ADCS
CH2
CH1
CH0
ADCON
17.2. ADC Operation
ADC has a maximum conversion speed of 200 ksps. The ADC conversion clock is a divided version of the
system clock, determined by the SPEED1, SPEED0 bits in the ADCON register.
Software writes a ―1‖ to ADCS to start the ADC operation. After the conversion is complete (ADCI is high), the
conversion result can be found in the ADC Result Registers (ADCH, ADCL). For the single ended ADC, the
conversion result is:
V
IN 1024
ADC Result =
VDD Voltage
17.2.1. ADC Input Channels
The analog multiplexer (AMUX) selects the inputs to the ADC, allowing any of the pins on Port 1 to be measured
in single-ended mode. The ADC input channels are configured and selected by CHS.2~0 in the ADCON register
as described in Figure 17-1. The selected pin is measured with respect to GND.
106
MG82FEL564 Data Sheet
MEGAWIN
17.2.2. Starting a Conversion
Prior to using the ADC function, the user should:
1) Turn on the ADC hardware by setting the ADCEN bit,
2) Configure the conversion speed by bits SPEED1 and SPEED0,
3) Select the analog input channel by bits CHS2, CHS1 and CHS0,
4) Configure the selected input (shared with P1) to the Input-Only mode by P1M0 and P1M1 registers, and
5) Configure ADC result arrangement using ADRJ bit.
Now, user can set the ADCS bit to start the A-to-D conversion. The conversion time is controlled by bits SPEED1
and SPEED0. Once the conversion is completed, the hardware will automatically clear the ADCS bit, set the
interrupt flag ADCI and load the 10 bits of conversion result into ADCH and ADCL (according to ADRJ bit)
simultaneously.
As described above, the interrupt flag ADCI, when set by hardware, shows a completed conversion. Thus two
ways may be used to check if the conversion is completed: (1) Always polling the interrupt flag ADCI by software;
(2) Enable the ADC interrupt by setting bits EADC (in EXIE1 register) and EA (in IE register), and then the CPU
will jump into its Interrupt Service Routine when the conversion is completed. Regardless of (1) or (2), the ADCI
flag should be cleared by software before next conversion.
17.2.3. Sample Code for ADC
start:
;...
MOV ADCON,#0E2h ;ADCEN=1, turn on ADC hardware
;(SPEED1,SPEED0)=(1,1), Conv. Time= 60 clock cycles
;select AIN0 (P1.2) as analog input
ORL P1M0,#00000100B ;P1M0,bit2=1 ;configure P1.2 as Input-Only Mode
ANL P1M1,#11111011B ;P1M1,bit2=0 ;
ANL AUXR0,#11111011B ;ADRJ=0: ADCH contains B9~B2; ADCL contains B1,B0
;now, suppose the analog input is ready on AIN2 (P1.2)
ORL ADCON,#00001000B ;ADCS=1 Start A-to-D conversion
wait_loop:
MOV ACC,ADCON
JNB ACC.4,wait_loop ;wait until ADCI=1 conversion completed
;now, the 10-bit ADC result is in the ADCH and ADCL.
;...
;...
17.2.4. ADC Conversion Time
The user can select the appropriate conversion speed according to the frequency of the analog input signal. For
example, if SYSCLK =12MHz and a conversion speed of 60 clock cycles is selected, then the frequency of the
analog input should be no more than 200KHz to maintain the conversion accuracy. (Conversion time = 1/12MHz
x 60 = 5us, so the conversion speed = 1/5us = 200KHz.)
17.2.5. I/O Pins Used with ADC Function
The analog input pins used for the A/D converters also have its I/O port ‗s digital input and output function. In
order to give the proper analog performance, a pin that is being used with the ADC should have its digital output
as disabled. It is done by putting the port pin into the input-only mode as described in the Port Configurations
section.
17.2.6. Idle and Power-Down Mode
MEGAWIN
MG82FEL564 Data Sheet
107
In Idle mode and Power-Down mode, the ADC does not function. If the A/D is turned on, it will consume a little
power. So, power consumption can be reduced by turning off the ADC hardware (ADCEN=0) before entering Idle
mode and Power-Down mode.
17.3. ADC Register
ADCON: ADC Control Register
SFR
Page
= All
SFR Address = 0xC5
RESET = 0000-0000
7
6
5
4
3
2
1
0
ADCEN
R/W
SPEED1
SPEED0
ADCI
R/W
ADCS
R/W
CHS2
R/W
CHS1
R/W
CHS0
R/W
R/W
R/W
Bit 7: ADCEN, ADC Enable.
0: Clear to turn off the ADC block..
1: Set to turn on the ADC block.
Bit 6~5: SPEED1 and SPEED0, ADC conversion speed control.
SPEED[1:0]
0 0
Conversion Clock Selection
SYSCLK/60
0 1
SYSCLK/120
1 0
SYSCLK/180
1 1
SYSCLK/240
Bit 4: ADCI, ADC Interrupt Flag.
0: The flag must be cleared by software.
1: This flag is set when an A/D conversion is completed. An interrupt is invoked if it is enabled.
Bit 3: ADCS. ADC Start of conversion.
0: ADCS cannot be cleared by software.
1: Setting this bit by software starts an A/D conversion. On completion of the conversion, the ADC hardware will
clear ADCS and set the ADCI. A new conversion may not be started while either ADCS or ADCI is high.
Bit 2~0: CHS2 ~ CHS1, Input Channel Selection for ADC analog multiplexer.
CHS[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Selected ADC Channel
AIN0 (P1.0)
AIN1 (P1.1)
AIN2 (P1.2)
AIN3 (P1.3)
AIN4 (P1.4)
AIN5 (P1.5)
AIN6 (P1.6)
AIN7 (P1.7)
AUXR0: Auxiliary Register 0
SFR Page
= All
SFR Address = 0x8E
RESET = 0000-000X
7
6
5
4
3
2
1
0
P60OC1
P60OC0
P60FD
R/W
P34FD
R/W
MOVXFD
ADRJ
R/W
EXTRAM
--
R
R/W
R/W
R/W
R/W
Bit 2: ADRJ, ADC result Right-Justified selection.
0: The most significant 8 bits of conversion result are saved in ADCH[7:0], while the least significant 2 bits in
ADCL[1:0].
1: The most significant 2 bits of conversion result are saved in ADCH[1:0], while the least significant 8 bits in
ADCL[7:0].
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MG82FEL564 Data Sheet
MEGAWIN
If ADRJ = 0
ADCH: ADC Result High Byte Register
SFR Page
= All
SFR Address = 0xC6
RESET = xxxx-xxxx
7
6
5
4
3
2
1
0
(B9)
R
(B8)
R
(B7)
R
(B6)
R
(B5)
R
(B4)
R
(B3)
R
(B2)
R
ADCL: ADC Result Low Byte Register
SFR Page
= All
SFR Address = 0xBE
RESET = xxxx-xxxx
7
6
5
4
3
2
1
0
--
R
--
R
--
R
--
R
--
R
--
R
(B1)
R
(B0)
R
If ADRJ = 1
7
6
5
4
3
2
1
0
--
R
--
R
--
R
--
R
--
R
--
R
(B8)
R
(B9)
R
7
6
5
4
3
2
1
0
(B7)
R
(B6)
R
(B5)
R
(B4)
R
(B3)
R
(B2)
R
(B1)
R
(B0)
R
MEGAWIN
MG82FEL564 Data Sheet
109
17.4. ADC Sample Code
(1). Required Function: ADC sample code for SYSCLK=24MHz, transfer analog input on P1.0/P1.1/P1.2 with
SPEED[1:0]=SYSCLK/270 for 88.9KHz conversion rate.
Assembly Code Example:
CHS0
CHS1
ADCS
ADCI
SPEED0
SPEED1
ADCON
EQU
EQU
EQU
EQU
EQU
EQU
EQU
01h
02h
08h
10h
20h
40h
80h
INITIAL_ADC_PIN:
ORL P1M0, #00000111B
; P1.0, P1.1, P1.2 = input only
; Enable ADC block
ANL P1M1,#11111000B
MOV ADCTL,#ADCON
; delay 5us
; call ....
Get_P10:
MOV ADCTL, #(ADCON + SPEED1 + SPEED0)
; Enable ADC block & start conversion
; Speed at 88.9k @ 24MHz, select P1.0 for ADC input pin
CALL delay_5us
ORL ADCTL, #ADCS
MOV A, ADCTL
; check ready?
JNB ACC.4,$-3
ANL ADCTL#(0FFh - ADCI - ADCS)
MOV AIN0_data_V,ADCV
MOV AIN0_data_VL, ADCVL
; to do ...
; clear ADCI & ADCS
; reserve P1.0 ADC data
Get_P11:
MOV ADCTL,#(ADCON + SPEED1 + SPEED0 + CHS0) ; select P1.1
CALL delay_5us
ORL ADCTL, #ADCS
MOV A, ADCTL
; check ready?
JNB ACC.4,$-3
ANL ADCTL,# (0FFh - ADCI - ADCS)
MOV AIN1_data_V,ADCV
MOV AIN1_data_VL, ADCVL
; clear ADCI & ADCS
; to do ...
Get_P12:
MOV ADCTL,#(ADCON + SPEED1 + SPEED0 + CHS1) ; select P1.2
CALL delay_5us
ORL ADCTL, #ADCS
MOV ACC,ADCTL
; check ready?
JNB ACC.4,$-3
ANL ADCTL,# (0FFh - ADCI - ADCS)
MOV AIN2_data_V,ADCV
MOV AIN2_data_VL, ADCVL
; clear ADCI & ADCS
; to do ...
RET
110
MG82FEL564 Data Sheet
MEGAWIN
C Code Example:
#define CHS0
#define CHS1
#define ADCS
#define ADCI
#define SPEED0
#define SPEED1
#define ADCON
0x01
0x02
0x08
0x10
0x20
0x40
0x80
void main(void)
{
unsigned char AIN0_data_V, AIN0_data_VL, AIN1_data_V, AIN1_data_VL, AIN2_data_V, AIN2_data_VL;
P1M0 |= 0x07;
P1M1 &= ~0x07;
// P1.0, P1.1, P1.2 = input only
// Enable ADC block
ADCTL = ADCON;
// delay 5us
// ...
// select P1.0
ADCTL = (ADCON | SPEED1 | SPEED0);
// Enable ADC block & start conversion
// Speed at 88.9k @ 24MHz, select P1.0 for ADC input pin
Delay_5us();
ADCTL |= ADCS;
while ((ADCTL & ADCI) == 0x00);
//wait for complete
ADCTL &= ~(ADCI | ADCS);
AIN0_data_V = ADCV;
AIN0_data_VL = ADCVL;
// to do ...
// select P1.1
ADCTL = (ADCON | SPEED1 | SPEED0 | CHS0); // select P1.1
Delay_5us();
ADCTL |= ADCS;
while ((ADCTL & ADCI) == 0x00);
//wait for complete
ADCTL &= ~(ADCI | ADCS);
AIN1_data_V = ADCV;
AIN1_data_VL = ADCVL;
// to do ...
// select P1.2
ADCTL = (ADCON | SPEED1 | SPEED0 | CHS1);
// select P1.2
Delay_5us();
ADCTL |= ADCS;
while ((ADCTL & ADCI) == 0x00);
//wait for complete
ADCTL &= ~(ADCI | ADCS);
AIN2_data_V = ADCV;
AIN2_data_VL = ADCVL;
// to do ...
while (1);
}
MEGAWIN
MG82FEL564 Data Sheet
111
18. Watch Dog Timer (WDT)
Watchdog Timer (WDT) is intended as a recovery method in situations (such as power noise/glitches and
electrostatic discharge) where the CPU may be subjected to software upset. When software upset happens, the
WDT will protect the system from incorrect code execution by causing a system reset. The WDT consists of a 15-
bit free-running counter, an 8-bit prescaler and a control register (WDTCR). Figure 18-1 shows the WDT block
diagram.
18.1. WDT Structure
Figure 18-1. WDT Block Diagram
SYSCLK
0
PCON0.PD
1/256
1/128
1/64
1/32
1/16
1/8
INT_OSC
1
WDT Reset
15-bits WDT
NSWDT
PCON0.IDL
1/4
1/2
8-bits prescaler
WDTCR WRF
--
ENW CLRW WIDL PS2
PS1
PS0
18.2. WDT Register
WDTCR: Watch-Dog-Timer Control Register
SFR Page
= All
SFR Address = 0xE1
POR = 0X00-0000
3
7
6
5
4
2
1
0
WRF
R/W
--
R
ENW
R/W
CLRW
R/W
WIDL
R/W
PS2
R/W
PS1
R/W
PS0
R/W
Bit 7: WRF, WDT reset flag.
0: This bit should be cleared by software.
1: When WDT overflows, this bit is set by hardware to indicate a WDT reset happened.
Bit 6: Reserved. Software must write ―0‖ on this bit when WDTCR is written.
Bit 5: ENW. Enable WDT.
0: ENW can not be cleared by software.
1: Enable WDT while it is set.
Bit 4: CLRW. Clear WDT counter.
0: Hardware will automatically clear this bit.
1: Clear WDT to recount while it is set.
Bit 3: WIDL. WDT idle control.
0: WDT stops counting while the MCU is in idle mode.
1: WDT keeps counting while the MCU is in idle mode.
112
MG82FEL564 Data Sheet
MEGAWIN
Bit 2~0: PS2 ~ PS0, select prescaler output for WDT time base input.
PS[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Prescaler Value
2
4
8
16
32
64
128
256
18.3. WDT Hardware Option
WDSFWP, disable Software write on WDTCR.
Enable: The software SFR - WDTCR will be write-protected except the bit – CLRW.
Disable: The software SFR – WDTCR is free for writing of software.
NSWDT, Non-Stopped WDT
Enable: Keep WDT running in power down mode and select internal high frequency RC Oscillator for the clock
source of WDT.
Disable: Disable WDT running in power down mode.
HWENW, Hardware loaded for ―ENW‖ of WDTCR.
Enable: Clearing it will enable WDT and load the content of HWWIDL, HWPS2, HWPS1 and HWPS0 to WDTCR
SFR when power-up.
Disable: WDT is not enabled automatically during power-up.
HWWIDL, HWPS2, HWPS1, HWPS0
When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR during power-up.
MEGAWIN
MG82FEL564 Data Sheet
113
18.4. WDT Sample Code
(1) Required function: Enable WDT and select WDT prescalar to 1/32
Assembly Code Example:
PS0
PS1
PS2
WIDL
CLRW
ENW
WRF
EQU
EQU
EQU
EQU
EQU
EQU
EQU
01h
02h
04h
08h
10h
20h
80h
ANL WDTCR,#(0FFh - WRF)
; Clear WRF flag (write ―0‖)
MOV WDTCR,#(ENW + CLRW + PS2) ; Enable WDT counter and set WDT prescaler to 1/32
C Code Example:
#define PS0
#define PS1
#define PS2
#define WIDL
#define CLRW
#define ENW
#define WRF
0x01
0x02
0x04
0x08
0x10
0x20
0x80
WDTCR &= ~WRF;
// Clear WRF flag (write ―0‖)
WDTCR = (ENW | CLRW | PS2);
// Enable WDT counter and set WDT prescaler to 1/32
// PS[2:0] | WDT prescaler selection
//
//
//
//
//
//
//
//
0
1
2
3
4
5
6
7
| 1/2
| 1/4
| 1/8
| 1/16
| 1/32
| 1/64
| 1/128
| 1/256
114
MG82FEL564 Data Sheet
MEGAWIN
19. Reset
During reset, all I/O Registers are set to their initial values, the port pins are weakly pulled to VDD, and the
program starts execution from the Reset Vector, 0000H, or ISP start address by Hardware Option setting. The
MG82Fx564 has six sources of reset: power-on reset, WDT reset, software reset, external reset, brown-out reset
and illegal address reset.
19.1. Reset Source
There are six reset sources in MG82Fx564 to generate an internal reset to initial CPU and registers. Figure 19-1
shows the reset source diagram.
Figure 19-1. Reset Source Diagram
POF
Power-On Reset
BORF
Brown-Out Reset
EXRF
External Reset
WRF
Internal Reset
WDT Reset
SWRF
Software Reset or
Illegal Addr Reset
IARF
Illegal Addr Reset
19.2. Power-On Reset
Power-on reset (POR) is used to internally reset the CPU during power-up. The CPU will keep in reset state and
will not start to work until the VDD power rises above the voltage of Power-On Reset. And, the reset state is
activated again whenever the VDD power falls below the POR voltage. During a power cycle, VDD must fall
below the POR voltage before power is reapplied in order to ensure a power-on reset
PCON0: Power Control Register 0
SFR Page
= All
SFR Address = 0x87
POR = 0001-0000, RESET = 000X-0000
7
6
5
4
3
2
1
0
SMOD1
R/W
SMOD0
R/W
GF
R/W
POF
R/W
GF1
R/W
GF0
R/W
PD
R/W
IDL
R/W
Bit 4: POF, Power-On Flag.
0: The flag must be cleared by software to recognize next reset type.
1: Set by hardware when VDD rises from 0 to its nominal voltage. POF can also be set by software.
The Power-on Flag, POF, is set to ―1‖ by hardware during power up or when VDD power drops below the POR
voltage. It can be clear by firmware and is not affected by any warm reset such as external reset, Brown-Out
reset, software reset (ISPCR.5) and WDT reset. It helps users to check if the running of the CPU begins from
power up or not. Note that the POF must be cleared by firmware.
MEGAWIN
MG82FEL564 Data Sheet
115
19.3. WDT Reset
When WDT overflows, it will cause a system warm reset and set a flag, WRF, to indicate a WDT reset happened.
WDTCR: Watch-Dog-Timer Control Register
SFR Page
= All
SFR Address = 0xE1
POR = 0x00-0000
3
7
6
5
4
2
1
0
WRF
R/W
--
R
ENW
R/W
CLRW
R/W
WIDL
R/W
PS2
R/W
PS1
R/W
PS0
R/W
Bit 7: WRF, WDT reset flag.
0: This bit should be cleared by software.
1: When WDT overflows, this bit is set by hardware to indicate a WDT reset happened.
19.4. Software Reset
Software can trigger a system warm reset by writing a ―1‖ on SWRST of ISPCR. After the software reset
completed, hardware sets a flag, SWRF in PCON1, to indicate a software reset happened.
ISPCR: ISP Control Register
SFR Page
= All
SFR Address = 0xE7
RESET = 0000-xxxx
7
6
5
4
3
2
1
0
ISPEN
R/W
SWBS
R/W
SWRST
CFAIL
R/W
-
R
--
R
--
R
--
R
R/W
Bit 5: SWRST, software reset trigger control.
0: No operation
1: Generate software system reset. It will be cleared by hardware automatically.
PCON1: Power Control Register 1
SFR Page
= All
SFR Address = 0x97
POR = 0000-xxx0
3
7
6
5
4
2
1
0
SWRF
R/W
EXRF
R/W
BORF
R/W
IARF
R/W
--
R
--
R
--
R
BOD
R/W
Bit 7: SWRF, Software Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if a Software Reset occurs.
116
MG82FEL564 Data Sheet
MEGAWIN
19.5. External Reset
A reset is accomplished by holding the RESET pin HIGH for at least 24 oscillator periods while the oscillator is
running. To ensure a reliable power-up reset, the hardware reset from RST pin is necessary. After the external
reset completely, hardware sets a flag, EXRF in PCON1, to indicate a external reset happened.
PCON1: Power Control Register 1
SFR Page
= All
SFR Address = 0x97
POR = 0000-XXX0
3
7
6
5
4
2
1
0
SWRF
R/W
EXRF
R/W
BORF
R/W
IARF
R/W
--
R
--
R
--
R
BOD
R/W
Bit 6: EXRF, External Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if an External Reset occurs.
19.6. Brown-Out Reset
In MG82Fx564, if VDD power drops below 4.2V in E series (2.4V in L series), it sets a flag, BOD in PCON1. If
BORE of AUXRA is enabled, BOD event will triggers a RESET to CPU and set a flag, BORF, to indicate a
Brown-Out Reset happened.
PCON1: Power Control Register 1
SFR Page
= All
SFR Address = 0x97
POR = 0000--xxx0
3
7
6
5
4
2
1
0
SWRF
R/W
EXRF
R/W
BORF
R/W
IARF
R/W
--
R
--
R
--
R
BOD
R/W
Bit 5: BORF, Brown-Out Reset Flag.
0: This bit must be cleared by software.
1: Set for the event flag of brown-out reset.
Bit 0: BOD, Brown-Out Detection flag.
0: This bit must be cleared by software.
1: This bit is set if the operating voltage matches the detection level of Brown-Out Detector.
AUXRA: Auxiliary Register A
SFR Address = IFMT
POR = 0010--0100
3
7
6
5
4
2
1
0
DBOD
R/W
BORE
R/W
OCDE
R/W
ILRCOE
XTALE
R/W
IHRCOE
OSCS1
R/W
OSCS0
R/W
R/W
R/W
Bit 6: BORE, Brown-Out Reset Enable.
0: Disable Reset action if BOD occurs.
1: Enable a Reset action if BOD occurs.
MEGAWIN
MG82FEL564 Data Sheet
117
19.7. Illegal Address Reset
In MG82Fx564, if software program runs to the illegal address such as over program ROM limitation, it triggers a
warm reset to CPU and set a flag, IARF in PCON1, to indicate a illegal address reset happened.
PCON1: Power Control Register 1
SFR Page
= All
SFR Address = 0x97
POR+ = 0000-xxx0
3
7
6
5
4
2
1
0
SWRF
R/W
EXRF
R/W
BORF
R/W
IARF
R/W
--
R
--
R
--
R
BOD
R/W
Bit 4: IARF, Illegal Address Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if a PC illegal address Reset occurs.
118
MG82FEL564 Data Sheet
MEGAWIN
19.8. Reset Sample Code
(1) Required function: Trigger a software reset
Assembly Code Example:
SWRST
EQU
20h
ORL ISPCR,#SWRST
; Trigger Software Reset
C Code Example:
#define SWRST
0x20
// Trigger Software Reset
ISPCR |= SWRST;
MEGAWIN
MG82FEL564 Data Sheet
119
20. Power Management
The MG82Fx564 supports one power monitor module, Brown-Out Detector, and two power-reducing modes: Idle
mode and Power-down mode. These modes are accessed through the PCON0 and PCON1 registers to handle
the chip power event.
20.1. Power Saving Mode
20.1.1. Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is
preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and
accumulator. The Port pins hold the logical states they had at the time that Idle was activated. Idle mode leaves
the peripherals running in order to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer
1, Timer 2, SPI, KBI, ADC, UART0 and the UART1 will continue to function during Idle mode. PCA Timer and
WDT are conditional enabled during Idle mode to wake up CPU. Any enabled interrupt source or reset may
terminate Idle mode. When exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and
following RETI, the next instruction to be executed will be the one following the instruction that put the device into
Idle. There is another Idle existing mechanism by enabled wakeup GPIOs that don‘t builds interrupt capability.
The channel inputs of ADC should be set to ―output 0‖ or ―quasi-bidirectional‖ when ADC is disabled in idle mode
or power-down mode.
20.1.2. Power-down Mode
Setting the PD bit in PCON0 enters Power-down mode. Power-down mode stops the oscillator and powers down
the internal macros in order to minimize power consumption. Only the power-on circuitry will continue to draw
power during Power-down. During Power-down the power supply voltage may be reduced to the RAM keep-alive
voltage. The RAM contents will be retained; however, the SFR contents are not guaranteed once VDD has been
reduced out of chip operating voltage range. Power-down may be exited by external reset, power-on reset,
enabled external interrupts, enabled KBI or enabled Non-Stop WDT.
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 μs until after one of
the following conditions has occurred: Start of code execution (after any type of reset), or Exit from power-down
mode.
20.1.3. Interrupt Recovery from Power-down
Four external interrupts may be configured to terminate Power-down mode. External interrupts nINT0 (P3.2),
nINT1 (P3.3), nINT2 (P4.3) and nINT3 (P4.2) may be used to exit Power-down. To wake up by external interrupt
nINT0, nINT1, nINT2 or nINT3, the interrupt must be enabled and configured for level-sensitive operation.
When terminating Power-down by an interrupt, the wake up period is internally timed. At the recognized level on
the interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The
internal clock will not be allowed to propagate and the CPU will not resume execution until after the timer has
reached internal counter full. After the timeout period, the interrupt service routine will begin. To prevent the
interrupt from re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should be held
low (or high for high level or rising edge selected) until the device has timed out and begun executing.
20.1.4. Reset Recovery from Power-down
Wakeup from Power-down through an external reset is similar to the interrupt. At the rising edge of RST, Power-
down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be
allowed to propagate to the CPU until after the timer has reached internal counter full. The RST pin must be held
high for longer than the timeout period to ensure that the device is reset properly. The device will begin executing
once RST is brought low.
120
MG82FEL564 Data Sheet
MEGAWIN
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program
execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-
chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To
eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a port pin or to external memory.
20.1.5. KBI wakeup Recovery from Power-down
The Keypad Interrupt of MG82Fx564, P2.7 ~ P2.0 have wakeup CPU capability that are enabled by the control
registers in KBI module.
Wakeup from Power-down through an enabled wakeup KBI is same to the interrupt. At the matched condition of
enabled KBI pattern and enabled KBI interrupt (EIE1.5, EKB), Power-down is exited, the oscillator is restarted,
and an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU until after
the timer has reached internal counter full. After the timeout period, CPU will meet a KBI interrupt and execute
the interrupt service routine.
20.2. Power Monitor Module
MG82Fx564 has an On-Chip Brown-Out Detection (BOD) for monitoring the Vcc level during operation by
comparing it to a fixed trigger level. The trigger level is 4.2V in E-series and 2.4V in L-series. When VDD
decreases to a level below the trigger, the BOD of PCON1 is set and requests an interrupt if EBD of EIE1 is
enabled. Software can service the interrupt to respond to the BOD event. Until VDD exits the BOD level,
hardware will block any write operation to on-chip flash memory.
When BORE of AUXRA is enabled, BOD has the capability to reset MCU. When VDD decreases below BOD
level in this case, the Brown-Out Reset is activated. When VDD increases above the trigger level, MCU re-starts
the code execution from program counter: 0000H. And hardware sets a Brown-Out Reset Flag, BORF of
PAOCN1 to indicate the brown-out reset just finished.
20.3. Power Control Register
PCON0: Power Control Register 0
SFR Page
= All
SFR Address = 0x87
POR = 0001-0000, RESET = 000x-0000
7
6
5
4
3
2
1
0
SMOD1
R/W
SMOD0
R/W
--
R/W
POF
R/W
GF1
R/W
GF0
R/W
PD
R/W
IDL
R/W
Bit 1: PD, Power-Down control bit.
0: This bit could be cleared by CPU or any exited power-down event.
1: Setting this bit activates power down operation.
Bit 0: IDL, Idle mode control bit.
0: This bit could be cleared by CPU or any exited Idle mode event.
1: Setting this bit activates idle mode operation.
PCON1: Power Control Register 1
SFR Page
= All
SFR Address = 0x97
POR = 0000-xxx0
3
7
6
5
4
2
1
0
SWRF
R/W
EXRF
R/W
BORF
R/W
IARF
R/W
--
R
--
R
--
R
BOD
R/W
Bit 7: SWRF, Software Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if a Software Reset occurs.
MEGAWIN
MG82FEL564 Data Sheet
121
Bit 6: EXRF, External Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if an External Reset occurs.
Bit 5: BORF, Brown-Out Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if a Brown-Out Reset occurs.
Bit 4: IARF, Illegal Address Reset Flag.
0: This bit must be cleared by software.
1: This bit is set if a PC illegal address Reset occurs.
Bit 3~1: Reserved.
Bit 0: BOD, Brown-Out Detection flag.
0: This bit must be cleared by software.
1: This bit is set if the operating voltage matches the detection level of Brown-Out Detector.
122
MG82FEL564 Data Sheet
MEGAWIN
20.4. Power Control Sample Code
(1) Required function: Select Slow mode with OSCin/128 (default is OSCin/1)
Assembly Code Example:
CKS0
CKS1
CKS2
EQU
EQU
EQU
01h
02h
04h
ORL PCON2,#( CKS2 + CKS1 + CKS0) ; Set CKS[2:0] = ―111‖ to select OSCin/128
C Code Example:
#define CKS0
#define CKS1
#define CKS2
0x01
0x02
0x04
PCON2 |= (CKS2 | CKS1 | CKS0);
// System clock divider /128
// CKS[2:0], system clock divider
//
//
//
//
//
//
//
//
0
1
2
3
4
5
6
7
| OSCin/1
| OSCin/2
| OSCin/4
| OSCin/8
| OSCin/16
| OSCin/32
| OSCin/64
| OSCin/128
MEGAWIN
MG82FEL564 Data Sheet
123
21. System Clock
21.1. Clock Structure
There are four clock sources in MG82Fx564 for the system clock: internal high frequency RC oscillator (IHRCO),
internal low frequency RC oscillator (ILRCO), external clock input and external crystal oscillator. The system
clock, SYSCLK, is obtained from one of these four clock sources through the clock divider, as shown in Figure
21-1. The user can program the divider control bits SCKD2~SCKD0 (in PCON2 register) to get the desired
system clock.
The IHRCO (22.12MHz) is enabled and set as the default system clock source after power-on. Software can
enable other oscillating circuits and switches them on the fly by programming AUXRA. Such as user selected the
external crystal as system clock, software must enable external crystal oscillating circuit first and wait it stable.
Then program the OSCS[1:0] to switch the clock source to external crystal. Before software switches the clock
source selection, user must be careful to confirm the selected clock source is ready and stable. Otherwise it will
cause system fault or CPU hung. After the clock selection, software may disable the un-used oscillating circuit to
reduce the power consumption.
The IHRCO in MG82Fx564 supports internal RC-OSC clock frequencies for user application. The 22.12MHz
frequency in IHRCO for system clock is the default setting in Megawin shipped samples..
Figure 21-1. Block Diagram of System Clock
Enable
IHRCOE
(AUXRA.2)
IHRCO
PCKS[2:0]
ISP/IAP Logic
(ISPCR.2~0)
ILRCOE
(AUXRA.4)
Enable
ILRCO
0
1
2
3
OSCin
SCKS[2:0]
(CKCON0.2~0)
SYSCLK
ECKI (P6.0)
(System Clock)
XTAL1 (P6.1)
XTAL2 (P6.0)
XTAL
Oscillating
Circuit
Enable
XTALE
(AUXRA.3)
OSCS1,0
(AUXRA.1~0)
In IHRCO mode, XTAL2 and XTAL1 are the GPIO function on P6.0 and P6.1. By the way, P6.0 can be
programmed to output the IHRCO clock output with divided 1, 2 or 4 by software selection on P60OC[1:0] of
AUXR1 SFR. Figure 21-2 shows the IHRCO output diagram.
124
MG82FEL564 Data Sheet
MEGAWIN
Figure 21-2. IHRCO Clock Output Diagram
P6.0 SFR
0
1
2
3
Enable
IHRCOE
(AUXRA.2)
XTAL2 (P6.0)
IHRCO
¸2
¸4
Enable
P60OC[1:0]
(AUXR0.7~6)
OSCS[1:0] = 00b
(AUXRA.1~0)
21.2. Clock Control Register
PCON2: Clock Control Register 2
SFR Page
= All
SFR Address = 0xC7
RESET = xxxx-x000
7
6
5
4
3
2
1
0
OSCDR
-
R
-
R
-
R
-
R
SCKS2
R/W
SCKS1
R/W
SCKS0
R/W
R/W
Bit 7: OSCDR, OSC Driving control Register. Default value is load from OSCDN (in hardware option). And it
could be read/written by CPU.
0: The driving of crystal oscillator is enough for oscillation up to 24MHz.
1: The driving of crystal oscillator is reduced. It will helpful in EMI reduction. Regarding application not needing
high frequency clock, it is recommended to do so.
Bit 6~3: Reserved.
Bit 2~0: SCKS2 ~ SCKS0, programmable System Clock Selection.
SCKS[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
System Clock (Fosc)
OSCin (Default)
OSCin /2
OSCin /4
OSCin /8
OSCin /16
OSCin /32
OSCin /64
COSin /128
AUXR0: Auxiliary Register 0
SFR Page
= All
SFR Address = 0x8E
RESET = 0000-000x
7
6
5
4
3
2
1
0
P60OC1
P60OC0
P60FD
R/W
P34FD
R/W
MOVXFD
ADRJ
R/W
EXTRAM
--
R
R/W
R/W
R/W
R/W
Bit 7~6: P60 output configured control bit 1 and 0. The two bits only act when IHRCO is selected for system clock
source. In this condition, XTAL2 and XTAL1 are the alternated function for P60 and P61. P60 provides the
following selections for GPIO or clock source generator. When P60OC[1:0] index to non-P60 function, XTAL2 will
drive the internal high frequency RC oscillator output to provide the clock source for other devices.
P60OC[1:0]
XTAL2 function
P60 (Default)
IHRCO
00
01
10
IHRCO/2
MEGAWIN
MG82FEL564 Data Sheet
125
11
IHRCO/2
Bit 5: P60FD, P6.0 Fast Driving.
0: P6.0 output with default driving.
1: P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when P6.0 output
frequency is more than 12MHz at 5V application or more than 6MHz at 3V application.
AUXRA: Auxiliary Register A
SFR Address = IFMT
RESET = 0010--0100
7
6
5
4
3
2
1
0
DBOD
R/W
BORE
R/W
OCDE
R/W
ILRCOE
XTALE
R/W
IHRCOE
OSCS1
R/W
OSCS0
R/W
R/W
R/W
Bit 4: LIRCOE, Internal Low frequency RC Oscillator Enable.
0: Disable internal low frequency RC oscillator.
1: Enable internal low frequency RC oscillator. It is about 125 KHz. It needs 50 us to have stable output after
ILRCOE is enabled.
Bit 3: XTALE, external Crystal(XTAL) Enable.
0: Disable XTAL oscillating circuit. In this case, XTAL2 and XTAL1 behave as Port 6.0 and Port 6.1.
1: Enable XTAL oscillating circuit. If this bit is set by CPU software, it needs 5 ms to have stable output after
XTALE is enabled.
Bit 3: IHRCOE, Internal High frequency RC Oscillator Enable.
0: Disable internal high frequency RC oscillator.
1: Enable internal low frequency RC oscillator. If this bit is set by CPU software, it needs 50 us to have stable
output after IHRCOE is enabled.
Bit 1~0: OSC input selection.
OSCS[1:0]
OSCin Source
IHRCO (Default)
ILRCO
P6.0 Function
P6.0 or IHRCO output
P6.0
P6.1 Function
P6.1
00
01
10
11
P6.1
P6.1
XTAL1
External Clock Input
Ext. Crystal Oscillating
Clock Input
XTAL2
126
MG82FEL564 Data Sheet
MEGAWIN
21.3. Sample code for switching internal RC-OSC Clock to External XTAL
;******************************************************************************
; Demo code for selecting Megawin MG82Fx564 system clock from internal oscillator to external oscillator.
; If user wants to use External Xtal as system clock source, user should Inserted below demo code in program start
;******************************************************************************
$INCLUDE (REG_MG82Fx564.INC) ;for MG82Fx564 SFR definition
ISP_StandBy
AUXRA_Wr
AUXRA_Rd
EQU
EQU
EQU
00h
06h
07h
;==============================================================================
CSEG AT 0000h
JMP start
;==============================================================================
code_main SEGMENT CODE
USING 0
start:
MOV
SP,#stack_space-1
CLR
ORL
MOV
MOV
CLR
TR0
TMOD, #01h
TH0, #0DCh
TL0, #00h
TF0
;use timer0 to delay 5ms
ORL
MOV
MOV
MOV
MOV
ORL
MOV
MOV
MOV
MOV
ISPCR, #80h
IFMT, #AUXRA_Rd
SCMD, #46h
SCMD, #0B9h
A, IFD
A, #08h
IFD, A
IFMT, #AUXRA_Wr
SCMD, #46h
SCMD, #0B9h
;enable ISP/IAP
;set read AUXRA command
;enable XTALE
;set write AUXRA command
SETB TR0
;timer0 run
JNB
CLR
CLR
TF0, $
TF0
TR0
;delay 5ms here, for external XTAL stable
;timer0 stop
MOV
MOV
MOV
MOV
ORL
MOV
MOV
MOV
MOV
IFMT, #AUXRA_Rd
SCMD, #46h
SCMD, #0B9h
A, IFD
A, #03h
IFD, A
IFMT, #AUXRA_Wr
SCMD, #46h
SCMD, #0B9h
;set read AUXRA command
;select crystal as OSCin
;set write AUXRA command
MOV
MOV
MOV
MOV
ANL
IFMT, #AUXRA_Rd
SCMD, #46h
SCMD, #0B9h
A, IFD
;set read AUXRA command
A, #0FBh
;disable IHRCO
MOV
MOV
MOV
MOV
IFD, A
IFMT, #AUXRA_Wr
SCMD, #46h
SCMD, #0B9h
;set write AUXRA command
;==============================================================================
;
User code start from here …………..
MEGAWIN
MG82FEL564 Data Sheet
127
22. In System Programming (ISP)
The ISP in MG82Fx564 makes it possible to update the user‘s application program (in AP-memory) and non-
volatile application data (in IAP-memory) without removing the MCU chip from the actual end product. This useful
capability makes a wide range of field-update applications possible. (Note ISP needs the loader program pre-
programmed in the ISP-memory.) In general, the user needn‘t know how ISP operates because Megawin has
provided the standard ISP tool and embedded ISP code in Megawin shipped samples.
22.1. ISP (IAP) Control Register
The following special function registers are related to the ISP operation. All these registers can be accessed by
software in the user‘s application program.
IFD: ISP/IAP Flash Data Register
SFR Page
= All
SFR Address = 0xE2
RESET = 1111-1111
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFD is the data port register for ISP/IAP operation. The data in IFD will be written into the desired address in
operating ISP/IAP write and it is the data window of readout in operating ISP/IAP read.
If IMFT is indexed on IAPLB, AUXRA or AUXRB access, read/write IFD through SCMD flow will access the
register content of IAPLB, AUXRA or AUXRB.
IFADRH: ISP/IAP Address for High-byte addressing
SFR Page
= All
SFR Address = 0xE3
RESET = 0000-0000
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFADRH is the high-byte address port for all ISP/IAP modes.
IFADRL: ISP/IAP Address for Low-byte addressing
SFR Page
= All
SFR Address = 0xE4
RESET = 0000-0000
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFADRL is the low byte address port for all ISP/IAP modes. In page erase operation, it is ignored.
IFMT: ISP/IAP Flash Mode Table
SFR Page
= All
SFR Address = 0xE5
RESET = xxx0-0000
7
6
5
4
3
2
1
0
--
R
--
R
--
R
MS[4]
MS[3]
R/W
MS[2]
R/W
MS[1]
R/W
MS[0]
R/W
R
Bit 7~4: Reserved
Bit 4~0: ISP/IAP operating mode selection. IFMT is used to select the flash mode for performing numerous
ISP/IAP function or used to access protected SFRs.
128
MG82FEL564 Data Sheet
MEGAWIN
Bit[4:0]
Mode
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Standby
AP-memory read
AP-memory program
AP-memory page erase
IAPLB write (protected SFR)
IAPLB read (protected SFR)
AUXRA write (protected SFR)
AUXRA read (protected SFR)
AUXRB write (protected SFR)
AUXRB read (protected SFR)
Reserved for test mode. Must not program them.
Others
SCMD: Sequential Command Register
SFR Page
= All
SFR Address = 0xE6
RESET = xxxx-xxxx
7
6
5
4
3
2
1
0
SCMD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCMD is the command port for triggering ISP/IAP activity and protected SFRs access. If SCMD is filled with
sequential 0x46h, 0xB9h and if ISPCR.7 = 1, ISP/IAP activity or protected SFRS access will be triggered.
ISPCR: ISP Control Register
SFR Page
= All
SFR Address = 0xE7
RESET = 0000-x000
7
6
5
4
3
2
1
0
ISPEN
R/W
SWBS
R/W
SWRST
CFAIL
R/W
--
R
PCKS2
R/W
PCKS1
R/W
PCKS0
R/W
R/W
Bit 7: ISPEN, ISP/IAP operation enable.
0: Global disable all ISP/IAP program/erase/read function.
1: Enable ISP/IAP program/erase/read function.
Bit 6: SWBS, software boot selection control.
0: Boot from main-memory after reset.
1: Boot from ISP memory after reset.
Bit 5: SWRST, software reset trigger control.
0: No operation
1: Generate software system reset. It will be cleared by hardware automatically.
Bit 4: CFAIL, Command Fail indication for ISP/IAP operation.
0: The last ISP/IAP command has finished successfully.
1: The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited.
Bit 3: Reserved. Software must write ―0‖ on this bit when ISPCR is written.
Bit 2~0: PCKS2~0, ISP/IAP programming clock source selection.
PCKS[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
OSCin Frequency (MHz)
> 24MHz
20 ~ 24
12 ~ 20
6~ 12
3 ~ 6
2 ~ 3
1 ~ 2
< 1
MEGAWIN
MG82FEL564 Data Sheet
129
IAPLB: IAP Low Boundary
SFR Address=indirect
RESET = 1111-111x
7
6
5
4
3
2
1
0
IAPLB
R/W
--
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7~0: The IAPLB determines the IAP-memory lower boundary. Since a Flash page has 512 bytes, the IAPLB
must be an even number.
To read IAPLB, MCU need to define the IMFT for mode selection on IAPLB Read and set ISPCR.ISPEN. And
then write 0x46h & 0xB9h sequentially into SCMD. The IAPLB content is available in IFD. If write IAPLB, MCU
will put new IAPLB setting value in IFD firstly. And then select IMFT, enable ISPCR.ISPEN and then set SCMD.
The IAPLB content has already finished the updated sequence.
There are 1.5K bytes for IAP space higher than AP boundary address in MG82Fx564. If the IAP size is not
enough for user application and AP region has redundant flash memory more than one page, software can
modify IAPLB to move some AP region flash for IAP application memory.
The range of the IAP-memory is determined by IAPLB and the ISP start address as listed below.
IAP lower boundary = IAPLBx256, and
IAP higher boundary = ISP start address – 1.
For example in MG82FE/L564, if IAPLB=0xE0 and ISP start address is F000H, then the IAP-memory range is
located at E000H ~ EFFFH.
Additional attention point, the IAP low boundary address must not be higher than ISP start address or
other non-device defined space. Otherwise, it may cause to corrupt data content in flash memory.
130
MG82FEL564 Data Sheet
MEGAWIN
23. In Application Programming (IAP)
MG82FE/L564 available program memory size (AP-memory) is restricted to 64K. The flash memory between
IAPLB and ISP start address could be defined as data flash memory and can be accessed by the ISP operation
in field application. The size of IAP flash memory is variable. It is defined by IAPLB.
MEGAWIN
MG82FEL564 Data Sheet
131
23.1. ISP/IAP Sample Code
(1). Required Function: General function call for ISP/IAP flash read
Assembly Code Example:
IxP_Flash_Read EQU
01h
80h
ISPEN
EQU
_ixp_read:
ixp_read:
MOV ISPCR,#ISPEN
MOV IFMT,# IxP_Flash_Read
; Enable Function
; ixp_read=0x01
MOV IFADRH,??
MOV IFADRL,??
; fill [IFADRH,IFADRL] with byte address
MOV SCMD,#046h
MOV SCMD,#0B9h
;
;
MOV A,IFD
; now, the read data exists in IFD
MOV IFMT,#000h
ANL ISPCR,#(0FFh – ISPEN)
; Flash_Standby=0x00
; Disable Function
RET
C Code Example:
#define Flash_Standby
#define IxP_Flash_Read
#define ISPEN
0x00
0x01
0x80
unsigned char ixp_read (void)
{
unsigned char arg;
ISPCR = ISPEN;
IFMT = IxP_Flash_Read;
// Enable Function
// IxP_Read=0x01
IFADRH = ??
IFADRL = ??
SCMD = 0x46;
SCMD = 0xB9;
//
//
arg = IFD;
IFMT = Flash_Standby;
ISPCR &= ~ISPEN;
// Flash_Standby=0x00
return arg;
}
132
MG82FEL564 Data Sheet
MEGAWIN
(2). Required Function: General function call for ISP/IAP flash Erase
Assembly Code Example:
IxP_Flash_ EraseEQU
03h
80h
ISPEN
EQU
_ixp_erase:
ixp_erase:
MOV ISPCR,#ISPEN
MOV IFMT,# IxP_Flash_Erase
; Enable Function
; ixp_erase=0x03
MOV IFADRH,??
MOV IFADRL,??
; fill [IFADRH,IFADRL] with byte address
MOV SCMD,#046h
MOV SCMD,#0B9h
;
;
MOV IFMT,#000h
ANL ISPCR,#(0FFh – ISPEN)
; Flash_Standby=0x00
; Disable Function
RET
C Code Example:
#define Flash_Standby
#define IxP_Flash_Erase
#define ISPEN
0x00
0x03
0x80
void ixp_erase (unsigned char Addr_H, unsigned char Addr_L)
{
ISPCR = ISPEN;
IFMT = IxP_Flash_Erase;
// Enable Function
// IxP_Erase=0x03
IFADRH = Addr_H;
IFADRL = Addr_L;
SCMD = 0x46;
SCMD = 0xB9;
//
//
IFMT = Flash_Standby;
ISPCR &= ~ISPEN;
// Flash_Standby=0x00
}
MEGAWIN
MG82FEL564 Data Sheet
133
(3). Required Function: General function call for ISP/IAP flash program
Assembly Code Example:
IxP_Flash_Program
ISPEN
EQU
EQU
02h
80h
_ixp_program:
ixp_program:
MOV ISPCR,#ISPEN
; Enable Function
MOV IFMT,# IxP_Flash_Program
; ixp_program=0x03
MOV IFADRH,??
MOV IFADRL,??
MOV IFD, A
; fill [IFADRH,IFADRL] with byte address
; now, the program data exists in Accumulator
MOV SCMD,#046h
MOV SCMD,#0B9h
;
;
MOV IFMT,#000h
ANL ISPCR,#(0FFh – ISPEN)
; Flash_Standby=0x00
; Disable Function
RET
C Code Example:
#define Flash_Standby
#define IxP_Flash_Program
#define ISPEN
0x00
0x02
0x80
void ixp_program(unsigned char Addr_H, unsigned char Addr_L, unsigned char dta)
{
ISPCR = ISPEN;
IFMT = IxP_Flash_Program;
// Enable Function
// IxP_Program=0x02
IFADRH = Addr_H;
IFADRL = Addr_L;
IFD = dta;
SCMD = 0x46;
SCMD = 0xB9;
//
//
IFMT = Flash_Standby;
ISPCR &= ~ISPEN;
// Flash_Standby=0x00
}
134
MG82FEL564 Data Sheet
MEGAWIN
24. Auxiliary SFRs
AUXR0: Auxiliary Register 0
SFR Page
= All
SFR Address = 0x8E
RESET = 0000-000x
7
6
5
4
3
2
1
0
P60OC1
P60OC0
P60FD
R/W
P34FD
R/W
MOVXFD
ADRJ
R/W
EXTRAM
--
R
R/W
R/W
R/W
R/W
Bit 7~6: P60 output configured control bit 1 and 0. The two bits only act when IHRCO is selected for system clock
source. In this condition, XTAL2 and XTAL1 are the alternated function for P60 and P61. P60 provides the
following selections for GPIO or clock source generator. When P60OC[1:0] index to non-P60 function, XTAL2 will
drive the internal high frequency RC oscillator output to provide the clock source for other devices.
P60OC[1:0]
XTAL2 function
P60 (Default)
INTOSC
INTOSC/2
INTOSC/4
00
01
10
11
Bit 5: P60FD, P6.0 Fast Driving.
0: P6.0 output with default driving.
1: P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when P6.0 output
frequency is more than 12MHz at 5V application or more than 6MHz at 3V application.
Bit 4: P34FD, P3.4 Fast Driving.
0: P3.4 output with default driving.
1: P3.4 output with fast driving enabled. If P3.4 is configured to T0CKO, enable this bit when P3.4 output
frequency is more than 12MHz at 5V application or more than 6MHz at 3V application.
Bit 3: MOVXFD, Fast Driving enabled for MOVX output signals.
0: MOVX output signals with default driving.
1: MOVX output signals with fast driving. If there is an off-chip memory access, MOVX@DPTR or MOVX@Ri, the
MOVX output signals require fast driving for stretched ALE/RD/WR pulse frequency more than 12MHz @5V or
6MHz @3V.
Bit 2: ADRJ, ADC result Right-Justified selection.
0: The most significant 8 bits of conversion result are saved in ADCH[7:0], while the least significant 2 bits in
ADCL[1:0].
1: The most significant 2 bits of conversion result are saved in ADCH[1:0], while the least significant 8 bits in
ADCL[7:0].
Bit 1: EXTRAM, External data RAM enable.
0: Enable on-chip expanded data RAM (XRAM 1024 bytes)
1: Disable on-chip expanded data RAM.
Bit 0: Reserved. Software must write ―0‖ on this bit when AUXR0 is written.
AUXR1: Auxiliary Control Register 1
SFR Page
= All
SFR Address = 0xA2
RESET = 0000-xxx0
7
6
5
4
3
2
1
0
P4KBI
R/W
P4PCA
R/W
P5SPI
R/W
P4S1
R/W
--
R
--
R
--
R
DPS
R/W
Bit 7: P4KBI, KBI function on P4/P5.
0: Disable KBI function moved to P4/P5.
1: Set KBI function on P4/P5 as following definition.
‗KBI0‘ function in P2.0 is moved to P4.0.
‗KBI1‘ function in P2.1 is moved to P4.1.
MEGAWIN
MG82FEL564 Data Sheet
135
‗KBI2‘ function in P2.2 is moved to P4.2.
‗KBI3‘ function in P2.3 is moved to P4.3.
‗KBI5‘ function in P2.5 is moved to P5.1.
‗KBI4‘ function in P2.4 is moved to P5.0.
‗KBI6‘ function in P2.6 is moved to P5.2.
‗KBI7‘ function in P2.7 is moved to P5.3.
Bit 6: P4PCA, PCA function on P4/P5.
0: Disable PCA function moved to P4/P5.
1: Set PCA function on P4/P5 as following definition.
‗ECI‘ function in P1.1 is moved to P4.2.
‗CEX0‘ function in P1.2 is moved to P4.0.
‗CEX1‘ function in P1.3 is moved to P4.1.
‗CEX2‘ function in P1.4 is moved to P5.0.
‗CEX3‘ function in P1.5 is moved to P5.1
‗CEX4‘ function in P1.6 is moved to P5.2.
‗CEX5‘ function in P1.7 is moved to P5.3.
Bit 5: P5SPI, SPI interface on P5.3~P5.0.
0: Disable SPI function moved to P5.
1: Set SPI function on P5 as following definition.
‗/SS‘ function in P1.4 is moved to P5.0.
‗MOSI‘ function in P1.5 is moved to P5.1.
‗MISO‘ function in P1.6 is moved to P5.2.
‗SPICLK‘ function in P1.7 is moved to P5.3.
Bit 4: P4S1, Serial Port 1 (UART1) on P4.0/P4.1.
0: Disable UART1 function moved to P4.
1: Set UART1 RXD1/TXD1 on P4.0/P4.1 following definition.
‗RXD1‘ function in P1.2 is moved to P4.0.
‗TXD1‘ function in P1.3 is moved to P4.1.
Bit 3~1: Reserved. Software must write ―0‖s on these bits when AUXR1 is written.
Bit 0: DPS, dual DPTR Selector.
0: Select DPTR0.
1: Select DPTR1.
AUXR2: Auxiliary Register 2
SFR Page
= All
SFR Address = 0xA6
RESET = 00xx-xx00
7
6
5
4
3
2
1
0
T0X12
R/W
T1X12
R/W
--
R
--
R
--
R
--
R
T1CKOE
T0CKOE
R/W
R/W
Bit 7: T0X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 6: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 5~2: Reserved.
Bit 1: T1CKOE, Timer 1 Clock Output Enable.
0: Disable Timer 1 clock output.
1: Enable Timer 1 clock output on P3.5.
Bit 0: T0CKOE, Timer 0 Clock Output Enable.
0: Disable Timer 0 clock output.
1: Enable Timer 0 clock output on P3.4.
136
MG82FEL564 Data Sheet
MEGAWIN
SFRPI: SFR Page Index Register
SFR Page
= All
SFR Address = 0xAC
RESET = xxxx-0000
7
6
5
4
3
2
1
0
--
R/W
--
R/W
--
R/W
--
R/W
PIDX3
R/W
PIDX2
R/W
PIDX1
R/W
PIDX0
R/W
Bit 7~4: Reserved. Software must write ―0‖s on these bits when SFRPI is written.
Bit 3~0: SFR Page Index. The available pages are only page ―0‖, ―1‖ and ―F‖.
There are four registers only in Page 0, T2CON(C8H), SCON0(98H), SBUF0(99H) and SCFG(9AH).
Three registers in Page 1, SCON0(98H), SBUF0(99H) and SCFG(9AH).
One register in Page F, P6(C8H).
Other registers are accessed by all pages.
PIDX[3:0]
0000
0001
0010
0011
……
Selected Page
Page 0
Page 1
Page 2
Page 3
……
……
……
……
……
1111
Page F
AUXRA: Auxiliary Register A
SFR Address = IFMT
POR = 0010-0100
3
7
6
5
4
2
1
0
DBOD
R/W
BORE
R/W
OCDE
R/W
ILRCOE
XTALE
R/W
IHRCOE
OSCS1
R/W
OSCS0
R/W
R/W
R/W
Bit 7: DBOD, Disable BOD.
0: Enable BOD in default state.
1: Disable BOD.
If software re-enables BOD in program flow, must wait more than 50us for BOD circuit start-up time. In this
period, software must disable BOD interrupt and BORE to filter the pseudo BOD event.
Bit 6: BORE, Brown-Out Reset Enable
0: Disable Reset action if BOD occurs.
1: Enable a Reset action if BOD occurs.
Bit 5: OCDE, OCD enable. The initial value is loaded from OR and reset by POR.
0: Disable OCD interface on P4.4 and P4.5
1: Enable OCD interface on P4.4 and P4.5.
Bit 4: LIRCOE, Internal Low frequency RC Oscillator Enable.
0: Disable internal low frequency RC oscillator.
1: Enable internal low frequency RC oscillator. It is about 125 KHz. It needs 50us to have stable output after
ILRCOE is enabled.
Bit 3: XTALE, external Crystal(XTAL) Enable. The default value is set by hardware option on clock source
selection.
0: Disable XTAL oscillating circuit. In this case, XTAL2 and XTAL1 behave as Port 6.0 and Port 6.1.
1: Enable XTAL oscillating circuit. If this bit is set by CPU software, it needs 5ms to have stable output after
XTALE is enabled.
Bit 2: IHRCOE, Internal High frequency RC Oscillator Enable. The default value is set by hardware option on
clock source selection.
0: Disable internal high frequency RC oscillator.
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MG82FEL564 Data Sheet
137
1: Enable internal low frequency RC oscillator. If this bit is set by CPU software, it needs 50us to have stable
output after IHRCOE is enabled.
Bit 1~0: OSC input selection.
OSCS[1:0]
OSCin Source
IHRCO (Default)
ILRCO
P6.0 Function
P6.0 or IHRCO output
P6.0
P6.1 Function
P6.1
00
01
10
11
P6.1
P6.1
XTAL1
External Clock Input
Ext. Crystal Oscillating
Clock Input
XTAL2
AUXRB: Auxiliary Register B
SFR Address = IFMT
RESET = xxx0-00x0
7
6
5
4
3
2
1
0
--
R
--
R
--
R
IAPO
R/W
LPM3
R/W
LPM2
R/W
--
R
LPM0
R/W
Bit 7~5: Reserved. Software must write ―0‖ on these bits when AUXRB is written.
Bit 4: IAPO, IAP function Only.
0: Maintain IAP region to service IAP function and code execution when the flash region lower than AP boundary
defined by IAPLB.
1: Disable the code execution in IAP region and the region only service IAP function.
Bit 3, 2, 0: LPM3, 2, 0. Control bits for Low power mode operation.
If the frequency of OSCin and SYSCLK is slower than 6MHz, software can write ―1‖s on this bits to reduce
operating current. Otherwise, software must write ―0‖s on this bit to maintain the high speed performance. Other
values writing on these bits are not permitted.
Bit 1: Reserved. Software must write ―0‖ on this bit when AUXRB is written.
138
MG82FEL564 Data Sheet
MEGAWIN
25. Hardware Option
The MCU‘s Hardware Option defines the device behavior which cannot be programmed or controlled by software.
The hardware options can only be programmed by a Universal Programmer, the ―Megawin 8051 Writer‖ or the
―Megawin 8051 ICP Programmer‖. After whole-chip erased, all the hardware options are left in ―disabled‖ state
and there is no ISP-memory and IAP-memory configured. The MG82FE/L564 has the following Hardware
Options:
LOCK:
[enabled]: Code dumped on a universal Writer or Programmer is locked to 0xFF for security.
[disabled]: Not locked.
ISP-memory Space:
The ISP-memory space is specified by its starting address. And, its higher boundary is limited by the Flash end
address, i.e., 0xFFFF. The following table list the ISP space option in this chip.
ISP-memory Size
ISP Start Address
4K bytes
3.5K bytes
3K bytes
0xF000
0xF200
0xF400
0xF600
0xF800
0xFA00
0xFC00
--
2.5K bytes
2K bytes
1.5K bytes
1K bytes
No ISP Space
HWBS:
[enabled]: When powered up, MCU will boot from ISP-memory if ISP-memory is configured.
[disabled]: MCU always boots from AP-memory.
HWBS2:
[enabled]: Not only power-up but also any reset will cause MCU to boot from ISP-memory if ISP-memory is
configured.
[disabled]: Where MCU boots from is determined by HWBS.
BODRE:
[enabled]: BOD will trigger a RESET event to CPU on AP program start address.(4.2V for E-series and 2.4V for
L-series)
[disabled]: BOD can not trigger a RESET to CPU.
This bit value is mirrored to AUXRA.6, BORE, which can be controlled by software program.
OSCDN:
[enabled]: The gain of crystal oscillator is reduced. It will helpful in EMI reduction. Regarding application not
needing high frequency clock, it is recommended to do so.
[disabled]: The gain of crystal oscillator is enough for oscillation up to 25MHz.
ENRCO:
[enabled]: Enable internal high frequency RC oscillator. If this hardware option is enabled, the IHRCO will be
the source into system clock and power down the crystal oscillating circuit. And XTAL2, XTAL1 will
be switched to alternated function of P6.0 and P6.1.
[disabled] Disable IHRCO and set the external crystal oscillator as system clock source.
WDSFWP:
[enabled]: The software SFR - WDTCR will be write-protected except the bit – CLRW.
[disabled]: The software SFR – WDTCR is free for writing of software.
HWENW: Hardware loaded for ―ENW‖ of WDTCR.
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MG82FEL564 Data Sheet
139
[enabled]: Clearing it will enable WDT and load the content of HWWIDL, HWPS2, HWPS1 and HWPS0 to
WDTCR SFR when power-up.
[disabled]: WDT is not enabled automatically during power-up.
HWWIDL: HWPS2, HWPS1, HWPS0
When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR during power-up.
NSWDT: Non-Stopped WDT
[enabled]: Keep WDT running in power down mode and select internal high frequency RC Oscillator for the
clock source of WDT.
[disabled]: Disable WDT running in power down mode.
140
MG82FEL564 Data Sheet
MEGAWIN
26. Absolute Maximum Rating
For MG82FE564
Parameter
Rating
-40 ~ +85
Unit
°C
°C
V
Ambient temperature under bias
Storage temperature
-65 ~ + 150
-0.5 ~ VDD + 0.5
Voltage on any Port I/O Pin or RESET with respect
to Ground
Voltage on VDD with respect to Ground
Maximum total current through VDD and Ground
Maximum output current sunk by any Port pin
-0.5 ~ +6.0
400
V
mA
mA
40
*Note: stresses above those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
For MG82FL564
Parameter
Rating
-40 ~ +85
Unit
°C
°C
V
Ambient temperature under bias
Storage temperature
-65 ~ + 150
-0.3 ~ VDD + 0.3
Voltage on any Port I/O Pin or RESET with respect
to Ground
Voltage on VDD with respect to Ground
Maximum total current through VDD and Ground
Maximum output current sunk by any Port pin
-0.3 ~ +4.2
400
V
mA
mA
40
*Note: stresses above those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
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MG82FEL564 Data Sheet
141
27. Electrical Characteristics
27.1. DC Characteristics
VSS = 0V, TA = 25 ℃, VDD = 5.0V and execute NOP for each machine cycle, unless otherwise specified
Limits
typ
Test
Condition
Unit
Symbol Parameter
min
2.0
3.5
max
VIH1
VIH2
VIL1
VIL2
IIH
Input High voltage (All I/O Ports)
V
V
V
V
Input High voltage (RESET)
Input Low voltage (All I/O Ports)
Input Low voltage (RESET)
0.8
1.6
Input High Leakage current (All I/O Ports) VPIN = VDD
Logic 0 input current (All quasi-I/O Ports) VPIN = 0.4V
Logic 0 input current (All Input only or VPIN = 0.4V
open-drain Ports)
0
20
0
10 uA
50 uA
10 uA
IIL1
IIL2
IH2L
Logic 1 to 0 input transition current (All VPIN =1.8V
quasi-I/O Ports)
250
220
500 uA
IOH1
IOH2
Output High current (All quasi-I/O Ports)
VPIN =2.4V
150
12
uA
mA
Output High current (All push-pull output VPIN =2.4V
ports)
IOL1
IOP
IIDLE
IPD
Output Low current (All I/O Ports)
Operating current
Idle mode current
VPIN =0.4V
FOSC = 24MHz
FOSC = 20MHz
12
mA
30 mA
20 mA
10 uA
22
12
1
Power down current
RRST Internal reset pull-down resistance
100
Kohm
VSS = 0V, TA = 25 ℃, VDD = 3.3V and execute NOP for each machine cycle, unless otherwise specified
Limits
typ
Test
Condition
Unit
Symbol Parameter
min
2.0
2.8
max
VIH1
VIH2
VIL1
VIL2
IIH
Input High voltage (All I/O Ports)
V
V
V
V
Input High voltage (RESET)
Input Low voltage (All I/O Ports)
Input Low voltage (RESET)
0.8
1.5
Input High Leakage current (All I/O Ports) VPIN = VDD
Logic 0 input current (All quasi-I/O Ports) VPIN = 0.4V
Logic 0 input current (All Input only or VPIN = 0.4V
open-drain Ports)
0
7
0
10 uA
30 uA
10 uA
IIL1
IIL2
IH2L
Logic 1 to 0 input transition current (All VPIN =1.8V
quasi-I/O Ports)
100
70
250 uA
IOH1
IOH2
Output High current (All quasi-I/O Ports)
VPIN =2.4V
40
4
uA
mA
Output High current (All push-pull output VPIN =2.4V
ports)
IOL1
IOP
IIDLE
IPD
Output Low current (All I/O Ports)
Operating current
Idle mode current
VPIN =0.4V
FOSC = 20MHz
FOSC = 20MHz
8
mA
25 mA
15 mA
20
9
1
Power down current
5
uA
RRST Internal reset pull-down resistance
200
Kohm
142
MG82FEL564 Data Sheet
MEGAWIN
27.2. AC Characteristics
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MG82FEL564 Data Sheet
143
28. Instruction Set
MNEMONIC
DESCRIPTION
BYTE EXECUTION
Cycles
DATA TRASFER
MOV A,Rn
Move register to Acc
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
1
2
1
1
1
MOV A,direct
Move direct byte o Acc
2
MOV A,@Ri
Move indirect RAM to Acc
2
MOV A,#data
Move immediate data to Acc
2
MOV Rn,A
Move Acc to register
2
MOV Rn,direct
MOV Rn,#data
MOV direct,A
Move direct byte to register
4
Move immediate data to register
Move Acc to direct byte
2
3
MOV direct,Rn
MOV direct,direct
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
Move register to direct byte
3
Move direct byte to direct byte
4
Move indirect RAM to direct byte
Move immediate data to direct byte
Move Acc to indirect RAM
4
3
3
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load DPTR with a 16-bit constant
Move code byte relative to DPTR to Acc
Move code byte relative to PC to Acc
Move on-chip auxiliary RAM(8-bit address) to Acc
Move on-chip auxiliary RAM(16-bit address) to Acc
Move Acc to on-chip auxiliary RAM(8-bit address)
Move Acc to on-chip auxiliary RAM(16-bit address)
Move external RAM(8-bit address) to Acc
Move external RAM(16-bit address) to Acc
Move Acc to external RAM(8-bit address)
Move Acc to external RAM(16-bit address)
Push direct byte onto Stack
3
3
3
4
4
3
3
3
3
3 ~ 20*Note1
3 ~ 20*Note1
3 ~ 20*Note1
3 ~ 20*Note1
4
3
3
4
4
4
POP direct
Pop direct byte from Stack
XCH A,Rn
Exchange register with Acc
XCH A,direct
Exchange direct byte with Acc
XCH A,@Ri
Exchange indirect RAM with Acc
Exchange low-order digit indirect RAM with Acc
XCHD A,@Ri
ARITHEMATIC OPERATIONS
ADD A,Rn
Add register to Acc
1
2
1
2
1
2
1
2
1
2
1
2
3
3
2
2
3
3
2
2
3
3
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
Add direct byte to Acc
Add indirect RAM to Acc
Add immediate data to Acc
Add register to Acc with Carry
Add direct byte to Acc with Carry
Add indirect RAM to Acc with Carry
Add immediate data to Acc with Carry
Subtract register from Acc with borrow
Subtract direct byte from Acc with borrow
Subtract indirect RAM from Acc with borrow
SUBB A,direct
SUBB A,@Ri
144
MG82FEL564 Data Sheet
MEGAWIN
SUBB A,#data
INC A
Subtract immediate data from Acc with borrow
Increment Acc
2
1
1
2
1
1
1
2
1
1
1
1
1
2
2
3
4
4
2
3
4
4
1
4
5
4
INC Rn
Increment register
INC direct
INC @Ri
DEC A
Increment direct byte
Increment indirect RAM
Decrement Acc
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment DPTR
Multiply A and B
Divide A by B
DA A
Decimal Adjust Acc
LOGIC OPERATION
ANL A,Rn
AND register to Acc
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
2
3
3
2
4
4
2
3
3
2
4
4
2
3
3
2
4
4
1
2
1
1
1
1
1
ANL A,direct
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
ORL A,Rn
AND direct byte to Acc
AND indirect RAM to Acc
AND immediate data to Acc
AND Acc to direct byte
AND immediate data to direct byte
OR register to Acc
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data
XRL A,Rn
OR direct byte to Acc
OR indirect RAM to Acc
OR immediate data to Acc
OR Acc to direct byte
OR immediate data to direct byte
Exclusive-OR register to Acc
Exclusive-OR direct byte to Acc
Exclusive-OR indirect RAM to Acc
Exclusive-OR immediate data to Acc
Exclusive-OR Acc to direct byte
Exclusive-OR immediate data to direct byte
Clear Acc
XRL A,direct
XRL A,@Ri
XRL A,#data
XRL direct,A
XRL direct,#data
CLR A
CPL A
Complement Acc
RL A
Rotate Acc Left
RLC A
Rotate Acc Left through the Carry
Rotate Acc Right
RR A
RRC A
Rotate Acc Right through the Carry
Swap nibbles within the Acc
SWAP A
BOOLEAN VARIABLE MANIPULATION
CLR C
Clear Carry
1
2
1
2
1
2
2
2
2
2
1
4
1
4
1
4
3
3
3
3
CLR bit
Clear direct bit
SETB C
SETB bit
CPL C
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to Carry
OR complement of direct bit to Carry
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MEGAWIN
MG82FEL564 Data Sheet
145
MOV C,bit
MOV bit,C
Move direct bit to Carry
Move Carry to direct bit
2
2
3
4
BOOLEAN VARIABLE MANIPULATION
JC rel
Jump if Carry is set
2
2
3
3
3
3
3
4
4
5
JNC rel
Jump if Carry not set
JB bit,rel
JNB bit,rel
JBC bit,rel
Jump if direct bit is set
Jump if direct bit not set
Jump if direct bit is set and then clear bit
PROAGRAM BRACHING
ACALL addr11
LCALL addr16
RET
Absolute subroutine call
2
3
1
1
2
3
2
1
2
2
3
3
3
3
2
3
1
6
6
4
4
3
4
3
3
3
3
5
4
4
5
4
5
1
Long subroutine call
Return from subroutine
RETI
Return from interrupt subroutine
Absolute jump
AJMP addr11
LJMP addr16
SJMP rel
Long jump
Short jump
JMP @A+DPTR
JZ rel
Jump indirect relative to DPTR
Jump if Acc is zero
JNZ rel
Jump if Acc not zero
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct,rel
NOP
Compare direct byte to Acc and jump if not equal
Compare immediate data to Acc and jump if not equal
Compare immediate data to register and jump if not equal
Compare immediate data to indirect RAM and jump if not equal
Decrement register and jump if not equal
Decrement direct byte and jump if not equal
No Operation
Note 1: The cycle time for access of external auxiliary RAM is:
EMAI[1:0] = 00: 5 + 2 x ALE_Stretch + RW_Stretch + 2 x RWSH; (5~20)
EMAI[1:0] = 01: 3 + RW_Stretch + 2 x RWSH; (3~12)
EMAI[1:0] = 10: 3 + RW_Stretch + 2 x RWSH; (3~12)
EMAI[1:0] = 11: Not Define.
146
MG82FEL564 Data Sheet
MEGAWIN
29.Package Dimension
PQFP-44
MEGAWIN
MG82FEL564 Data Sheet
147
LQFP-48
148
MG82FEL564 Data Sheet
MEGAWIN
PDIP-40
MEGAWIN
MG82FEL564 Data Sheet
149
30. Revision History
Rev Descriptions
Date
1. Initial release
2. Added application note (sample code) for switching default internal RC-OSC to
External XTAL
V1.0
2010/08/19
3. ADC conversion speed note. Suggest user doing ADC conversion under SYSCLK
don‘t over 20MHz in High temperature ( Over 60℃) environment.
V1.1 1. Remove PDIP-40 package
V1.2 2. Remove PLCC-44 package
2010/11/03
2011/05/16
1. Add PDIP-40PLCC-44 package
V1.3 2. PCON2 edit error ( CKCON2)
3. ISPCR edit error (SFR address)
2011/06/20
1. COMD.6 edit error (FEOV bit)
2. PCAPWMn edit error (R, R/W)
V1.4
2011/06/27
V1.5 Remove PLCC-44 package
V1.51 Edit content
2011/12/06
2012/07/03
2014/02/25
2015/09/25
A1.0 New form & added sample code
A1.01 Modify system clock Diagram
150
MG82FEL564 Data Sheet
MEGAWIN
Disclaimers
Herein, Megawin stands for ―Megawin Technology Co., Ltd.‖
Life Support — This product is not designed for use in medical, life-saving or life-sustaining applications, or
systems where malfunction of this product can reasonably be expected to result in personal injury. Customers
using or selling this product for use in such applications do so at their own risk and agree to fully indemnify
Megawin for any damages resulting from such improper use or sale.
Right to Make Changes — Megawin reserves the right to make changes in the products - including circuits,
standard cells, and/or software - described or contained herein in order to improve design and/or performance.
When the product is in mass production, relevant changes will be communicated via an Engineering Change
Notification (ECN).
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