EVB71122A-915-ASK-C
更新时间:2024-09-18 06:46:05
品牌:MELEXIS
描述:300 to 930MHz Receiver Evaluation Board Description
EVB71122A-915-ASK-C 概述
300 to 930MHz Receiver Evaluation Board Description 300〜 930MHz接收器评估板说明
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300 to 930MHz Receiver
Evaluation Board Description
Features
! Programmable PLL synthesizer
! 8-channel preconfigured or fully programmable SPI mode
! Double super-heterodyne receiver architecture with 2nd mixer as image rejection mixer
! Reception of FSK, FM and ASK modulated signals
! Low shut-down and operating currents
! Build-in acceptance of input frequency variations
! On-chip IF filter
! Fully integrated FSK/FM demodulator
! RSSI for level indication and ASK detection
! 2nd order low-pass data filter
! Positive and negative peak detectors
! Data slicer (with averaging or peak-detector adaptive threshold)
! EVB programming software is available on Melexis web site
Ordering Information
Part No. (see paragraph 6)
EVB71122C-315-C
EVB71122C-433-C
EVB71122C-868-C
EVB71122C-915-C
Note: SPI mode is default population, ABC mode according to paragraph 4.2
Application Examples
Evaluation Board Example
! General digital and analog RF receivers
at 300 to 930MHz
! Tire pressure monitoring systems (TPMS)
! Remote keyless entry (RKE)
! Low power telemetry systems
! Alarm and security systems
! Active RFID tags
! Remote controls
! Garage door openers
! Home and building automation
General Description
The MLX71122 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architec-
ture. It is designed to receive FSK and ASK modulated RF signals either in 8 predefined frequency channels
or frequency programmable via a 3-wire serial programming interface (SPI).
The IC is designed for a variety of applications, for example in the European bands at 433MHz and 868MHz
or for the use in North America or Asia, e.g. at 315MHz, 447MHz or 915MHz.
39012 71122 01
Rev. 001
Page 1 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Document Content
1
Theory of Operation...................................................................................................4
1.1
General............................................................................................................................. 4
EVB Data Overview.......................................................................................................... 4
Block Diagram .................................................................................................................. 5
Enable/Disable in ABC Mode ........................................................................................... 6
Demodulation Selection in ABC Mode.............................................................................. 6
Programming Modes ........................................................................................................ 6
Preconfigured Frequencies in ABC Mode ........................................................................ 6
1.2
1.3
1.4
1.5
1.6
1.7
2
Functional Description ..............................................................................................7
2.1
Frequency Planning.......................................................................................................... 7
2.2
Calculation of Counter Settings........................................................................................ 8
2.2.1 Calculation of LO1 and IF1 frequency for Low Frequency Bands............................................... 8
2.2.2 Calculation of LO1 and IF1 frequency for High Frequency Bands.............................................. 9
2.2.3 Counter Setting Examples for SPI Mode..................................................................................... 9
2.2.4 Counter Settings in ABC Mode – 8 Preconfigured Channels.................................................... 10
2.2.5 PLL Counter Ranges ................................................................................................................. 11
2.3
SPI Description............................................................................................................... 11
2.3.1 General ...................................................................................................................................... 11
2.3.2 Read / Write Sequences............................................................................................................ 12
2.3.3 Serial Programming Interface Timing ........................................................................................ 12
3
Register Description ................................................................................................13
3.1
Register Overview .......................................................................................................... 13
3.1.1 Control Word R0 ........................................................................................................................ 15
3.1.2 Control Word R1 ........................................................................................................................ 16
3.1.3 Control Word R2 ........................................................................................................................ 17
3.1.4 Control Word R3 ........................................................................................................................ 17
3.1.5 Control Word R4 ........................................................................................................................ 18
3.1.6 Control Word R5 ........................................................................................................................ 18
3.1.7 Control Word R6 ........................................................................................................................ 18
3.1.8 Control Word R7 (Read-only Register)...................................................................................... 19
4
Application Circuits .................................................................................................20
4.1
Standard FSK & ASK Circuit in SPI Mode...................................................................... 20
4.1.1 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 20
4.1.2 Component Arrangement Top Side for SPI Mode (Averaging Data Slicer) .............................. 21
4.1.3 Peak Detector Data Slicer Configured for NRZ Codes ............................................................. 22
4.1.4 Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer)........................ 23
4.1.5 Board Component Values List (SPI mode)................................................................................ 24
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Rev. 001
Page 2 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2
Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode.......................... 25
4.2.1 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 25
4.2.2 Component Arrangement Top Side for ABC Mode (averaging data slicer) .............................. 26
4.2.3 Board Component Values List (ABC mode).............................................................................. 27
5
6
7
Evaluation Board Layouts.......................................................................................28
Board Variants..........................................................................................................28
Package Description................................................................................................29
7.1
Soldering Information ..................................................................................................... 29
Reliability Information .............................................................................................30
ESD Precautions ......................................................................................................30
8
9
10 Disclaimer.................................................................................................................32
39012 71122 01
Rev. 001
Page 3 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1
Theory of Operation
1.1 General
The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator
with external inductor, a programmable feedback divider chain, a programmable reference divider, a phase-
frequency detector with a charge pump and an external loop filter.
In the receiver’s down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local oscillator
signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first intermedi-
ate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image rejection is
provided even without using an RF front-end filter. At applications asking for very high image rejections,
cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA.
The receiver signal chain is setup by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and
MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an
FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based
ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator.
The data slicer threshold can be generated from the mean-value of the data stream or by means of the posi-
tive and negative peak detectors (PKDET+/-).
In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely turned
off, and to several other operating modes. There are two global operating modes that are selectable via the
logic level at pin SPISEL:
•
•
8-channel preconfigured mode (ABC mode)
fully programmable mode (SPI mode).
In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is
required. In this case the three lines of the serial programming interface (SPI) are used to select one of the
eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are
used to enable/disable the receiver and to select FSK or ASK demodulation, respectively.
SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are config-
ured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the
receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types,
data slicer settings and more. The pin MODSEL has no effect in this mode.
1.2 EVB Data Overview
! Input frequency ranges: 300 to 930MHz
! Power supply range: 3.0 to 5.5V
! Temperature range: -40 to +105°C
! Shutdown current: 50nA
! Operating current: 11mA (typ.)
! Internal IF2: 2MHz with 230kHz 3dB bandwidth
! Maximum data rate: 100kbps NRZ code,
50kbps bi-phase code
! Total image rejection: > 65dB (with external
RF front-end filter)
! FSK/FM deviation range: ±10 to ±50kHz
! Spurious emission: < -70dBm
! Linear RSSI range: > 70dB
! FSK input frequency acceptance range:
170kHz (3dB)
! Crystal reference frequency: 10MHz
! Minimum frequency resolution: 10kHz
! Input Sensitivity: at 4 kbps NRZ, BER = 3·10-3
Frequency
FSK: ±20 kHz deviation
ASK
315 MHZ
-106dBm
-108dBm
433 MHz
-104dBm
-108dBm
868 MHz
915 MHz
-101dBm
-106dBm
-101dBm
-106dBm
39012 71122 01
Rev. 001
Page 4 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1.3 Block Diagram
5
1
2
6
3
4
8
9
28
29
200k
200k
DFO
OA1
27
ASK
FSK
IFF
MIX1
MIX2
SW1
IF1
IF2
IFA
LNAI
25
PKDET+
LNA
31
PDP
FSK
DEMOD
LO1
LO2
_
PDN
PKDET
LO2DIV
26
N / A
counter
R
SLCSEL
PFD
counter
SW2
DTAO
VCO
OA2
Control
Logic
22
BIAS
LF
CP
RO
SLC
32
TNK1
TNK2
11
14
12 13
15
23
24
18
10
16
20
21
30
7
17
19
Fig. 1: MLX71122 block diagram
The MLX71122 receiver IC consists of the following building blocks:
•
PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2,
parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R,
the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator
(RO)
•
•
•
•
•
•
•
•
•
Low-noise amplifier (LNA) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth
IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detector data slicer
•
•
Control logic with 3-wire bus serial programming interface (SPI)
Biasing circuit with modes control
For more detailed information, please refer to the latest MLX71122 data sheet revision.
39012 71122 01
Rev. 001
Page 5 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1.4 Enable/Disable in ABC Mode
ENRX
Description
0
1
Shutdown mode
Receive mode
Pin ENRX is pulled down internally. Device is in shutdown by default, after power supply on.
If ENRX = 0 and SPISEL = 1 then operating modes according to OPMODE bit (refer to control word R0).
If ENRX = 1 then OPMODE bit has no effect (hardwired receive mode).
1.5 Demodulation Selection in ABC Mode
MODSEL
Description
0
1
FSK demodulation
ASK demodulation
Pin MODSEL has no effect in SPI mode (SPISEL = 1). We recommend connecting it to ground to avoid a
floating CMOS gate.
1.6 Programming Modes
SPISEL
Description
0
1
ABC mode (8 channels preconfigured)
SPI mode (programming via 3-wire bus)
1.7 Preconfigured Frequencies in ABC Mode
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
C
0
0
0
0
1
1
1
1
Receive Frequency
FSK1: 369.5 MHz
FSK5: 388.3 MHz
FSK2: 371.1 MHz
FSK4: 376.9 MHz
FSK3: 375.3 MHz
FSK7: 394.3 MHz
FSK6: 391.5 MHz
FSK8: 395.9 MHz
As all pins, pins A, B, and C are equipped with ESD protection diodes that are tied to VCC and to VEE.
Therefore these pins should not be directly connected to positive supply (a logic “1”) before the supply volt-
age is applied to the IC. Otherwise the IC will be supplied through these control lines and it may enter into an
unpredictable mode. In case the user wants to apply a positive supply voltage to these pins before the sup-
ply voltage is applied to the IC, a protection resistor should be inserted in each control line.
39012 71122 01
Rev. 001
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EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2
Functional Description
2.1 Frequency Planning
Because of the double conversion architecture that employs two mixers and two IF signals, there are four
different combinations for injecting the LO1 and LO2 signals:
•
•
•
•
LO1 high side and LO2 high side:
LO1 high side and LO2 low side:
LO1 low side and LO2 high side:
LO1 low side and LO2 low side:
receiving at fRF(high-high)
receiving at fRF(high-low)
receiving at fRF(low-high)
receiving at fRF(low-low)
As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 2
shows this for the case of receiving at fRF(high-high). In the example of Fig. 2, the image signals at fRF(low-
high) and fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The
bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by
the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the
high value of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low).
The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second
mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means
either the upper or lower sideband of IF1 can be selected. In the example of Fig. 2, LO2 high-side injection
has been chosen to select the IF2 signal resulting from fRF(high-high).
fLO2
fLO2
fRF
fRF
fRF
fLO1
fRF
Fig. 2: The four receiving frequencies in a double conversion superhet receiver
It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO1 signal fre-
quency fLO1 and the LO2 signal frequency fLO2
.
fLO1
LO2DIV = NLO2
=
(1)
fLO2
The LO1 signal frequency fLO1 is directly synthesized from the crystal reference oscillator frequency fRO by
means of an integer-N PLL synthesizer. The PLL consists of a dual-modulus prescaler (P/P+1), a program
counter N and a swallow counter A.
fRO
fLO1
=
(N ⋅ P + A) = fPFD (N ⋅ P + A) = fPFD ⋅ Ntot
(2)
R
39012 71122 01
Rev. 001
Page 7 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Due to the double superhet receiver architecture, the channel frequency step size fCH is not equal to the
phase-frequency detector (PFD) frequency fPFD. For high-side injection, the channel step size fCH is given by:
fRO NLO2 −1
NLO2 −1
NLO2
fCH
=
= fPFD
(3)
(4)
R
NLO2
While the following equation is valid for low-side injection:
fRO NLO2 +1
NLO2 +1
NLO2
fCH
=
= fPFD
R
NLO2
2.2 Calculation of Counter Settings
Frequency planning and the selection of the MLX71122’s PLL counter settings are straightforward and can
be laid out on the following procedure.
Usually the receive frequency fRF and the channel step size fCH are given by system requirements. The N
and A counter settings can be derived from Ntot or fLO1 and fPFD by using the following equations.
N
N
N = floor( tot ) = floor( tot ) ; A = Ntot − N ⋅ P = Ntot − N ⋅32
32
(5)
P
2.2.1
Calculation of LO1 and IF1 frequency for Low Frequency Bands
High-high injection must be used for the low frequency bands. First of all choose a PFD frequency fPFD
according to below table. The R counter values are valid for a 10MHz crystal reference frequency fRO. The
PFD frequency is given by fPFD = fRO /R.
Injection Type
fCH [kHz]
10
fPFD [kHz]
13.3
R
h-h
h-h
h-h
h-h
h-h
h-h
h-h
750
600
375
300
150
75
12.5
20
16.7
26.7
25
33.3
50
66.7
100
250
133.3
333.3
30
The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the
NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLO2 = 4 (or 8) and P =32.
NLO2
4
fLO1
=
(fRF − fIF2 )
fLO1 = (fRF − 2MHz)
(6)
(7)
NLO2 −1
3
fRF − NLO2fIF2
NLO2 −1
fRF − 8MHz
fIF1
=
fIF1 =
3
Finally N and A can be calculated with formula (5).
39012 71122 01
Rev. 001
Page 8 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.2
Calculation of LO1 and IF1 frequency for High Frequency Bands
Typical ISM band operating frequencies like 868.3 and 915MHz can be covered without changing the crystal
nor the VCO inductor.
Low-low injection should be used for the high frequency bands. First of all choose a PFD frequency fPFD
according to below table. The R counter values are valid for a 10MHz crystal reference. The PFD frequency
is given by fPFD = fRO /R.
Injection Type
fCH [kHz]
20
fPFD [kHz]
16
R
l-l
l-l
l-l
l-l
l-l
l-l
625
500
250
125
50
25
20
50
40
100
250
500
80
200
400
25
The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the
NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLo2 = 4 (or 8) and P =32.
NLO2
4
fLO1
=
(fRF − fIF2 )
fLO1 = (fRF − 2MHz)
(8)
(9)
NLO2 +1
5
fRF + NLO2fIF2
NLO2 +1
fRF + 8MHz
fIF1
=
fIF1 =
5
Finally N and A can be calculated with formula (5).
2.2.3
Counter Setting Examples for SPI Mode
To provide some examples, the following table shows some counter settings for the reception of the well-
known ISM and SRD frequency bands. The channel spacing is assumed to be fCH = 100kHz. In below table
all frequency units are in MHz.
Inj
h-h
h-h
h-h
h-h
l-l
fRF
fIF1
fLO1
Ntot
N
P
A
4
fPFD
0.133
0.133
0.133
0.133
0.08
R
fREF
10
10
10
10
10
10
10
10
fLO2
99.3
fIF2
2
300
315
434
470
850
868
915
930
97.3 397.3 2980
102.3 417.3 3130
93
32
32
32
32
32
32
32
32
75
97
26
0
75
104.3
144
2
142
154
576
624
4320
4680
135
146
256
270
285
290
75
2
8
75
156
2
171.6 678.4 8480
175.2 692.8 8660
184.6 730.4 9130
187.6 742.4 9280
0
125
125
125
125
169.6
173.2
182.6
185.6
2
l-l
20
10
0
0.08
2
l-l
0.08
2
l-l
0.08
2
39012 71122 01
Rev. 001
Page 9 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.4
Counter Settings in ABC Mode – 8 Preconfigured Channels
In ABC mode (SPISEL=0), the counter settings are hard-wired. In below table all frequency units are in MHz.
FSK
1
fRF
fIF1
fLO1
Ntot
N
P
A
27
11
21
5
fPFD
R
fREF
10
10
10
10
10
10
10
10
fLO2
fIF2
2
369.5 120.5 490.0 3675
371.1 121.0 492.0 3691
375.3 122.4 497.7 3733
376.9 123.0 499.9 3749
388.3 126.8 515.1 3863
391.5 127.8 519.3 3895
394.3 128.8 523.1 3923
395.9 129.3 525.2 3939
114
115
116
117
120
121
122
123
32
32
32
32
32
32
32
32
0.133
0.133
0.133
0.133
0.133
0.133
0.133
0.133
75
75
75
75
75
75
75
75
122.5
123.0
124.4
125.0
128.8
129.8
130.8
131.3
2
2
3
2
4
2
5
23
23
19
3
2
6
2
7
2
8
2
List of Mathematical Acronyms
divider ratio of the swallow counter (part of feedback divider)
frequency at the feedback divider output
A
fFB
The floor function gives the largest integer less than or equal to x.
For example, floor(5.4) gives 5, floor(-6.3) gives -7.
floor (x)
fPFD
PFD frequency in locked state
fRO
= fR
R
reference frequency of the PLL
fRO
frequency of the crystal reference oscillator
fVCO
frequency of the VCO (equals the LO1 signal of the first mixer)
Ntot = N ⋅ P + A
total divider ratio of the PLL feedback path
N
divider ratio of the program counter (part of feedback divider)
LO2DIV divider ratio, to derive the LO2 signal from LO1 (N1 = 4 or 8)
divider ratio of the prescaler (part of feedback divider)
divider ratio of the reference divider R
NLO2
P
R
39012 71122 01
Rev. 001
Page 10 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.5
PLL Counter Ranges
In order to cover the frequency range of about 300 to 930MHz the following counter values are implemented
in the receiver:
PLL Counter Ranges
A
N
R
P
0 to 31 (5bit)
3 to 2047 (11bit)
3 to 2047 (11bit)
32
Therefore the minimum and maximum divider ratios of the PLL feedback divider are given by:
Ntotmin = 32⋅32 = 1024
Ntotmax = 2047⋅32 + 31 = 65535
2.3 SPI Description
2.3.1
General
Serial programming interface (SPI) mode can be activated by choosing SPISEL = 1 (e.g. at positive supply
voltage VCC). In this mode, the input pins 17, 18 and 19 are used as a 3-wire unidirectional serial bus inter-
face (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter
settings, mode bits etc.
In addition the MFO pin can be programmed as an output (see section 4.1.4) in order to read data from the
internal latches and it can be used as an output for different test modes as well.
At each rising edge of the SCLK signal, the logic value at the SDTA terminal is written into a shift register.
The programming information is taken over into internal latches with the rising edge of SDEN. Additional
leading bits are ignored, only the last bits are serially clocked into the shift register. A normal write operation
shifts 16 bits into the SPI, a normal read operation shifts 4 bits into the SPI and reads additional 12 bits from
the MFO pin. If less than 12 data bits are shifted into SDTA during the write operation then the control regis-
ter may contain invalid information.
In general a control word has the following format. Bit 0 is the Read/Write bit that determines whether it is a
read (R/W = 1) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the
corresponding data bits.
Control Word Format
MSB
LSB
MSB
LSB
Bit 0
Data
D6 D5
Latch Address Mode
A2 A2 A0 R/W
D11 D10 D9
D8
D7
D4
D3
D2
D1
D0
There are two control word formats for read and for write operation. Data bits are only needed in write mode.
Read operations require only a latch address and a R/W bit.
Due to the static CMOS design, the serial interface consumes virtually no current. The SPI is a fully separate
building block and can therefore be programmed in every operational mode.
39012 71122 01
Rev. 001
Page 11 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.3.2
Read / Write Sequences
Fig. 6
Typical write sequence diagram
Fig. 7
Typical read sequence diagram
2.3.3
Serial Programming Interface Timing
SDEN
SCLK
tCWH
tCR
tEW
tEH
tCWL
tCF
tES
tCS tCH
tDES
tDSO
SDTA
MFO
Fig. 8
SPI timing diagram
39012 71122 01
Rev. 001
Page 12 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3
Register Description
The following tables are to describe the functionality of the registers.
Sec. 4.1 provides a register overview with all the control words R0 to R7. The subsequent sections. 4.1.1 to
4.1.8 show the content of the control words in more detail.
Programming the registers requires SPI mode (SPISEL = 1). Default settings are for ABC mode.
3.1 Register Overview
DATA
CONTROL
WORD
LATCH
ADDRESS
MSB
11
LSB
Bit No.
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
default
1
0
1
1
1
0
0
0
1
0
0
0
0
0
0
read/
write
R0
MSB
LSB
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
default
1
0
0
0
1
0
1
1
0
1
0
0
0
0
1
read/
write
R1
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
default
1
1
1
0
1
1
1
0
1
1
0
0
0
1
0
read/
write
R2
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
default
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
read/
write
R3
39012 71122 01
Rev. 001
Page 13 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
DATA
CONTROL
WORD
LATCH
ADDRESS
MSB
11
LSB
Bit No.
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
default
0
0
0
0
0
1
0
0
1
0
1
1
1
0
0
read/
write
R4
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
default
0
0
1
0
1
0
0
1
1
0
1
1
1
0
1
read/
write
R5
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
default
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
read/
write
R6
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
default
1
1
1
read-
only
R7
Note:
∗ depends on bit 11 in R4, 0 = RSSIL, 1 = LD
39012 71122 01
Rev. 001
Page 14 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.1
Control Word R0
Name
Bits
Description
operation mode
#default
00
01
10
11
shutdown
receive mode
OPMODE
[1:0]
reference oscillator & BIAS only
synthesizer only
LNA gain
00
01
10
11
lowest gain
low gain
high gain
(-18dB)
(-4dB)
(0dB)
LNAGAIN
[3:2]
#default
highest gain
(+2dB)
gain values are relative to gain at default
1st Mixer gain
(14dB)
(0dB)
2nd Mixer gain
MIX1GAIN
MIX2GAIN
[4]
[5]
#default
#default
0
1
high gain
low gain
0
1
high gain
low gain
(9dB)
(-2dB)
intermediate frequency filter gain
00
01
10
11
lowest gain
low gain
high gain
(-14dB)
(-6dB)
(0dB)
IFFGAIN
[7:6]
#default
highest gain
(+6dB)
demodulator gain
DEMGAIN
SSBSEL
SLCSEL
[8]
[9]
[9]
0
1
low gain
high gain
(~ 4mV/kHz)
(~ 15mV/kHz)
#default
#default
single side band selection
0
1
upper side band LO2 low-side inj. (IF1 = LO2 + IF2)
lower side band
LO2 high-side inj. (IF1 = LO2 – IF2)
Internal IF2 = 2MHz
slicer mode select
#default
#default
0
1
averaging Data Slicer mode
peak detector Data Slicer mode
data output polarity OA2
0
1
inverted
‘1’ for space at ASK or fmin at FSK, ‘0’ for mark at ASK or fmax at FSK
DTAPOL
[11]
normal
‘0’ for space at ASK or fmin at FSK, ‘1’ for mark at ASK or fmax at FSK
39012 71122 01
Rev. 001
Page 15 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.2
Control Word R1
Name
Bits
Description
charge pump current setting
#default
00
01
10
11
100µA
400µA
400µA static down
400µA static up
CPCUR
[1:0]
PFD output polarity
lock detector time error
lock detection time
[2]
[3]
PFDPOL
LDERR
0
1
negative
positive
#default
#default
0
1
15ns
30ns
00
01
10
11
2/fR
4/fR
8/fR
[5:4]
LDTIME
#default
#default
16/fR
minimum time span before lock in
fR is the reference oscillator frequency fRO divided by R, see section 4.1.5 (R4)
lock detector mode
LDMODE
[6]
[7]
0
1
check lock condition permanently
check lock condition until 1st lock in
VCO range
0
1
3V supply
5V supply
VCORANGE
#default
#default
#default
#default
VCO range setting for different VCCs.
VCO core current
VCOCUR
VCOBUF
[8]
[9]
0
1
450µA
520µA
VCO buffer current
0
1
900µA
1040µA
prescaler 32/33 reference current
0
1
20µA
30µA
PRESCUR
SHOWLD
[10]
[11]
30µA may be used for fRF = 868/915MHz
function of LDRSSIL bit
0
1
RSSIL (RSSI low flag)
LD (lock detection flag)
#default
select output data of LDRSSIL, see section 4.1.8 (R7)
39012 71122 01
Rev. 001
Page 16 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.3
Control Word R2
Name
Bits
Description
swallow counter value
#default
value is 12
[4:0]
A
N
01100
swallow counter range: 0 to 31
program counter value (bits 0 – 6)
[11:5]
#default
000 0111 0111 N value is 119
N counter range: 3 to 2047
3.1.4
Control Word R3
program counter range (bits 7 – 10)
000 0111 0111 N value is 119
N
[3:0]
#default
N counter range: 3 to 2047
LO2 divider ratio
AGC enable mode
AGC delay settings
LO2DIV
AGCEN
[4]
[5]
#default
#default
#default
0
1
divide by 4
divide by 8
0
1
disabled
enabled
00
01
10
11
no delay
3/fIFF
15/fIFF
31/fIFF
AGCDEL
[7:6]
fIFF is the reference oscillator frequency fRO divided by RIFF, see section 4.1.6 (R6)
multi functional output
0000 MFO is in Z state
0001 MFO is SPI read-out
0010 MFO = 0
[11:8]
MFO
0011 MFO = 1
#default
0100 MFO is analog RO output
0101 MFO is IFF output
1000 MFO is lock detector output
39012 71122 01
Rev. 001
Page 17 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.5
Control Word R4
Name
Bits
Description
reference divider range
#default
[10:0]
R
000 0100 1011 value is 75
R counter range: 3 to 2047
AGC delay mode
#default
0
1
gain decrease and increase with delay
gain decrease without delay, gain increase with delay
AGCMODE
[11]
selects AGC delay mode in combination with AGCDEL bits, see section 4.1.4 (R3)
3.1.6
Control Word R5
Name
Bits
Description
reference divider value for IFF adjustment
[10:0]
RIFF
#default
#default
010 1001 1011 value is 667
IFF counter range: 4 to 2047
demodulation selection
0
1
FSK demodulation
ASK demodulation
MODSEL
[11]
selects modulation type when chip is controlled via SPI mode
3.1.7
Control Word R6
Name
Bits
Description
IFF preset value
[7:0]
IFFPRES
#default
#default
0110 1100
value is 108
IFF DAC preset at start of automatic tuning
IFF halt
0
1
auto tuning running
auto tuning halted
IFFHLT
[8]
[9]
suspends IFF automatic tuning
IFF tuning
IFFTUNE
0
1
disable and load DAC with IFFPRES
enable
#default
#default
reference Oscillator core current
00
01
10
11
85µA
170µA
270µA
355µA
ROCUR
[11:10]
39012 71122 01
Rev. 001
Page 18 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.8
Control Word R7 (Read-only Register)
Name
Bits
Description
IFF adjustment value
[7:0]
IFFVAL
see also IFFPRES in section 4.1.7 (R6)
IFF automatic tuning state
filter tuned or auto-tuning disabled
tuning up the filter frequency
tuning down the filter frequency
master oscillator of filter deactivated
00
01
10
11
IFFSTATE
[9:8]
lock detector or RSSI low flag
0
1
PLL not locked or RSSI value in lower region
PLL locked or RSSI value above lower region
LDRSSIL
RSSIH
[10]
[11]
depends on SHOWLD in section 4.1.2 (R1)
RSSI high flag
RSSI value below upper region
RSSI value in upper region
0
1
39012 71122 01
Rev. 001
Page 19 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4
Application Circuits
4.1 Standard FSK & ASK Circuit in SPI Mode
4.1.1
Averaging Data Slicer Configured for Bi-Phase Codes
MFO
GND
DTAO
RS1
SCLK
SDTA
SDEN
1 2 3
1 2
CB3
XTAL
CX
16
15
25 PDP
ENRX
LF
CF2
RF
26
PDN
DFO
DF1
CF1
14
13
12
27
28
VCCVCO
TNK2
C8
C9
MLX71122
L0
29 DF2
TNK1
CB2
L1
C1
VEEANA
30
31
32
11
10
9
VEEVCO
RBS
1
3
L2
SAWFIL
RBIAS
LNAI
SLC
C2
4
6
MODSEL
RSSI
GND VCC
1
2
3
7
8
4
5
6
C10
1 2
1 2
L3
C5
C6
C7
CB0
C4
CB1
Fig. 6: Application circuit for SPI Mode (averaging data slicer option)
Note
•
EVB71122 default population is SPI mode
39012 71122 01
Rev. 001
Page 20 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.1.2
Component Arrangement Top Side for SPI Mode (Averaging Data Slicer)
Board size is 49mm x 35.6mm
DFO GND MFO GND DTAO
GND
VCC
1
1
MFO
Melexis
A
GND
RS1
SCLK
B
SDTA
SDEN
RS2
C
CB3
RS3
RF_input
RF
ENRX
L1
0
MODSEL
RBS
FSK/ASK
L2
L3
C4
VCC
GND
CB1
1
EVB71122_002
GND
RSSI
SPI mode selected
39012 71122 01
Rev. 001
Page 21 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.1.3
Peak Detector Data Slicer Configured for NRZ Codes
MFO
GND
DTAO
RS1
SCLK
SDTA
SDEN
1 2 3
1 2
CB3
XTAL
CX
C11
C12
16
15
25 PDP
ENRX
LF
CF2
RF
26
PDN
DFO
DF1
CF1
14
13
12
27
28
VCCVCO
TNK2
C8
C9
MLX71122
L0
29 DF2
TNK1
CB2
L1
C1
VEEANA
30
31
11
10
9
VEEVCO
RBS
1
3
L2
SAWFIL
RBIAS
LNAI
SLC
C2
4
6
MODSEL
RSSI
GND VCC
1
2
3
7
8
4
5
6
1 2
1 2
L3
C5
C6
C7
CB0
C4
CB1
Fig. 7: Application circuit for SPI Mode (peak detector option)
Note
•
EVB71122 default population is SPI mode
39012 71122 01
Rev. 001
Page 22 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.1.4
Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer)
Board size is 49mm x 35.6mm
DFO GND MFO GND DTAO
GND
VCC
1
1
MFO
Melexis
A
GND
RS1
SCLK
B
SDTA
SDEN
RS2
C
CB3
RS3
RF_input
C11
C12
RF
ENRX
L1
0
MODSEL
RBS
FSK/ASK
L2
L3
C4
VCC
GND
CB1
1
EVB71122_002
GND
RSSI
SPI mode selected
39012 71122 01
Rev. 001
Page 23 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.1.5
Board Component Values List (SPI mode)
Below table is for all application circuits show in Figures 6 and 7
Value @
315 MHz
Value @
433.9 MHz 868.3 MHz
Value @
Value @
915 MHz
Part
Size
Tol.
Description
C1
C2
C4
0603
0603
0603
NIP
NIP
NIP
NIP
3.3 pF
NIP
NIP
NIP
matching capacitor
±5%
±5%
±5%
matching capacitor
4.7 pF
3.3 pF
2.7 pF
2.2 pF
LNA output tank capacitor
MIX1 negative input matching
capacitor
C5
C6
0603
0603
100 pF
100 pF
100 pF
100 pF
100 pF
100 pF
100 pF
100 pF
±5%
±5%
MIX1 negative input matching
capacitor
RSSI output low pass capacitor,
this value for data rates 4 kbps
NRZ
C7
C8
C9
0603
0603
0603
1 nF
1 nF
1 nF
1 nF
±10%
±10%
±10%
data low-pass filter capacitor,
this value for data rates 4 kbps
NRZ
330 pF
330 pF
330 pF
330 pF
data low-pass filter capacitor,
this value for data rates 4 kbps
NRZ
150 pF
33 nF
150 pF
33 nF
150 pF
33 nF
150 pF
33 nF
C10
C11
C12
0603
0603
0603
data slicer capacitor
±10%
±10%
±10%
not required in Figure 7
33 nF 33 nF
not required in Figures 6
33 nF 33 nF
not required in Figures 6
33 nF
33 nF
33 nF
33 nF
peak detector positive filtering
capacitor
peak detector negative filtering
capacitor
decoupling capacitor,
low-noise power supply recom-
mended
CB0
1210
10 μF
10 μF
10 μF
10 μF
±10%
CB1
CB2
CB3
CF1
CF2
CX
0603
0603
0603
0603
0603
0603
0603
0603
0603
470 pF
33 nF
33 nF
2.2 nF
220 pF
27 pF
10 Ω
470 pF
33 nF
33 nF
2.2 nF
220 pF
27 pF
10 Ω
470 pF
33 nF
33 nF
2.2 nF
220 pF
27 pF
10 Ω
470 pF
33 nF
33 nF
2.2 nF
220 pF
27 pF
10 Ω
decoupling capacitor
decoupling capacitor
decoupling capacitor
loop filter capacitor
loop filter capacitor
crystal series capacitor
protection resistor
±10%
±10%
±10%
±5%
±5%
±5%
±5%
±5%
±2%
±5%
±5%
±5%
±5%
±5%
RB0
RF
loop filter resistor
27 kΩ
30 kΩ
10 kΩ
33 nH
0 Ω
27 kΩ
30 kΩ
10 kΩ
15 nH
56 nH
82 nH
22 nH
47 kΩ
30 kΩ
10 kΩ
8.2 nH
22 nH
22 nH
5.6 nH
47 kΩ
30 kΩ
10 kΩ
8.2 nH
0 Ω
RBS
RS1…RS3
L0
reference bias resistor
protection resistor
0603
0603
0603
0603
VCO tank inductor
matching inductor
L1
L2
82 nH
33 nH
8.2 nH
5.6 nH
matching inductor
L3
LNA output tank inductor
SMD
5x3.2
XTAL
fundamental-mode crystal
10.00000 MHz / ±20ppm cal., ±30ppm temp.
SAFDC315MS SAFCC433MB SAFCC868MS SAFCH915MA
SAW
FIL
SMD
3x3
low-loss SAW filter from Murata
or equivalent part
M0T00
L0X00
L0X00
L0N00
(315 MHz)
(433.92 MHz)
(868.3 MHz)
(915 MHz)
Note:
- NIP – not in place, may be used optionally
39012 71122 01
Rev. 001
Page 24 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2 Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode
4.2.1
Averaging Data Slicer Configured for Bi-Phase Codes
DFO
DTAO
A
B
C
3
3
3
1 2
1 2
1 2
1 2
1 2
CB3
ENRX
XTAL
CX
1 2
3
MODSEL
16
ENRX
25 PDP
26
CF2
RF
15
LF
PDN
27 DFO
1 2
3
CF1
CB2
14
13
12
VCCVCO
TNK2
C8
C9
DF1
DF2
28
29
MLX71122
L0
TNK1
30 VEEANA
11
10
9
VEEVCO
L1
RBS
C3
31
RBIAS
LNAI
MODSEL
SLC
C1
C2
GND VCC
RSSI
1
2
3
7
8
5
6
4
C10
2
1
2
1
L3
C5
C6
C7
CB0
C4
CB1
Fig. 8: Application circuit for ABC Mode
Note
•
ABC mode population can be easily modified from default SPI mode population by changing the con-
nection at SPISEL from VCC to ground.
39012 71122 01
Rev. 001
Page 25 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2.2
Component Arrangement Top Side for ABC Mode (averaging data slicer)
Board size is 49mm x 35.6mm
DFO GND MFO GND DTAO
GND
VCC
1
1
MFO
GND
SCLK
Melexis
1
A
B
C
1
1
SDTA
SDEN
CB3
RF_input
RF
1
1
ENRX
L1
MODSEL
RBS
FSK/ASK
C3
L3
C4
VCC
GND
CB1
1
EVB71122_002
GND
RSSI
ABC mode selected
39012 71122 01
Rev. 001
Page 26 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2.3
Board Component Values List (ABC mode)
Below table is for all application circuits show in Figures 8
Value @
369 MHz to 396 MHz
Part
Size
Tol.
Description
C1
C2
C3
C4
C5
C6
0603
0603
0603
0603
0603
0603
NIP
matching capacitor
±5%
±5%
±5%
±5%
±5%
±5%
NIP
matching capacitor
100 pF
3.3 pF
100 pF
100 pF
LNA input filtering capacitor
LNA output tank capacitor
MIX1 negative input matching capacitor
MIX1 negative input matching capacitor
RSSI output low pass capacitor,
this value for data rates 4 kbps NRZ
C7
C8
0603
0603
1 nF
±10%
±10%
data low-pass filter capacitor,
this value for data rates 4 kbps NRZ
330 pF
data low-pass filter capacitor,
this value for data rates 4 kbps NRZ
C9
0603
0603
1210
150 pF
33 nF
10 μF
±10%
±10%
±10%
C10
CB0
data slicer capacitor
decoupling capacitor,
low-noise power supply recommended
CB1
CB2
CB3
CF1
CF2
CX
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
470 pF
33 nF
33 nF
2.2 nF
220 pF
27 pF
10 Ω
decoupling capacitor
decoupling capacitor
decoupling capacitor
loop filter capacitor
loop filter capacitor
crystal series capacitor
protection resistor
±10%
±10%
±10%
±5%
±5%
±5%
±5%
±5%
±2%
±5%
±5%
±5%
±5%
RB0
RF
loop filter resistor
27 kΩ
30 kΩ
10 kΩ
18 nH
39 nH
27 nH
RBS
RS1…RS3
L0
reference bias resistor
protection resistor
VCO tank inductor
matching inductor
L1
L3
LNA output tank inductor
SMD
5x3.2
XTAL
fundamental-mode crystal
10.00000 MHz / ±20ppm cal., ±30ppm temp.
Note:
- NIP – not in place, may be used optionally
39012 71122 01
Rev. 001
Page 27 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
5
Evaluation Board Layouts
•
Board layout data in Gerber format is available, board size is 35.6mm x 49mm.
PCB bottom view
PCB top view
6
Board Variants
Type
Regional Code
Frequency/MHz
–315
Modulation
–FSK
Board Execution
antenna version
connector version
world wide
EVB71122
C
A
B
–A
–C
Europe, Asia
USA, Canada
–433
–ASK
–868
–FM
–915
Note:
possible combinations
39012 71122 01
Rev. 001
Page 28 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
7
Package Description
•
The device MLX71122 is RoHS compliant.
D
A3
24
17
25
16
E
32
9
A1
A
8
b
1
e
exposed pad
E2
L
D2
The “exposed pad” is not connected to internal ground,
it should not be connected to the PCB.
Fig 12: 32L QFN 5x5 Quad
all Dimension in mm
D
E
D2
E2
A
A1
A3
L
e
b
min
4.75
5.25
4.75
5.25
3.00
3.25
3.00
3.25
0.80
1.00
0
0.3
0.5
0.18
0.30
0.20
0.50
max
0.05
all Dimension in inch
min
0.187
0.207
0.187
0.207
0.118
0.128
0.118 0.0315
0
0.0118
0.0197
0.0071
0.0118
0.0079
0.0197
max
0.128 0.0393 0.002
7.1 Soldering Information
•
The device MLX71122 is qualified for MSL3 with soldering peak temperature 260 deg C
according to JEDEC J-STD-20
39012 71122 01
Rev. 001
Page 29 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
8
Reliability Information
This Melexis device is classified and qualified regarding soldering technology, solderability and moisture
sensitivity level, as defined in this specification, according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification
reflow profiles according to table 5-2)”
EIA/JEDEC JESD22-A113
“Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according
to table 2)”
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EN60749-20
“Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat”
EIA/JEDEC JESD22-B106 and EN60749-15
“Resistance to soldering temperature for through-hole mounted devices”
Iron Soldering THD’s (Through Hole Devices)
EN60749-15
“Resistance to soldering temperature for through-hole mounted devices”
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EIA/JEDEC JESD22-B102 and EN60749-21
“Solderability”
For all soldering technologies deviating from above mentioned standard conditions (regarding peak tempera-
ture, temperature gradient, temperature profile etc) additional classification and qualification tests have to be
agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more in-
formation on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the
Use of Certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality_leadfree.aspx
9
ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
39012 71122 01
Rev. 001
Page 30 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Your Notes
39012 71122 01
Rev. 001
Page 31 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
10 Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the infor-
mation set forth herein or regarding the freedom of the described devices from patent infringement. Melexis
reserves the right to change specifications and prices at any time and without notice. Therefore, prior to de-
signing this product into a system, it is necessary to check with Melexis for current information. This product
is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or
life-sustaining equipment are specifically not recommended without additional processing by Melexis for
each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential dam-
ages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data
herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of
technical or other services.
© 2006 Melexis NV. All rights reserved.
For the latest version of this document, go to our website at:
www.melexis.com
Or for additional information contact Melexis Direct:
Europe and Japan:
Phone: +32 1367 0495
All other locations:
Phone: +1 603 223 2362
E-mail: sales_europe@melexis.com
E-mail: sales_usa@melexis.com
ISO/TS 16949 and ISO14001 Certified
39012 71122 01
Rev. 001
Page 32 of 32
EVB Description
Sept/06
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