EVB71122C-915-FSK-C中文资料_数据手册_规格书

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

Features

! Programmable PLL synthesizer

! 8-channel preconfigured or fully programmable SPI mode

! Double super-heterodyne receiver architecture with 2^ndmixer as image rejection mixer

! Reception of FSK, FM and ASK modulated signals

! Low shut-down and operating currents

! Build-in acceptance of input frequency variations

! On-chip IF filter

! Fully integrated FSK/FM demodulator

! RSSI for level indication and ASK detection

! 2^ndorder low-pass data filter

! Positive and negative peak detectors

! Data slicer (with averaging or peak-detector adaptive threshold)

! EVB programming software is available on Melexis web site

Ordering Information

Part No. (see paragraph 6)

EVB71122C-315-C

EVB71122C-433-C

EVB71122C-868-C

EVB71122C-915-C

Note: SPI mode is default population, ABC mode according to paragraph 4.2

Application Examples

Evaluation Board Example

! General digital and analog RF receivers

at 300 to 930MHz

! Tire pressure monitoring systems (TPMS)

! Remote keyless entry (RKE)

! Low power telemetry systems

! Alarm and security systems

! Active RFID tags

! Remote controls

! Garage door openers

! Home and building automation

General Description

The MLX71122 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architec-

ture. It is designed to receive FSK and ASK modulated RF signals either in 8 predefined frequency channels

or frequency programmable via a 3-wire serial programming interface (SPI).

The IC is designed for a variety of applications, for example in the European bands at 433MHz and 868MHz

or for the use in North America or Asia, e.g. at 315MHz, 447MHz or 915MHz.

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Rev. 001

Page 1 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

Document Content

1

Theory of Operation...................................................................................................4

1.1

General............................................................................................................................. 4

EVB Data Overview.......................................................................................................... 4

Block Diagram .................................................................................................................. 5

Enable/Disable in ABC Mode ........................................................................................... 6

Demodulation Selection in ABC Mode.............................................................................. 6

Programming Modes ........................................................................................................ 6

Preconfigured Frequencies in ABC Mode ........................................................................ 6

1.2

1.3

1.4

1.5

1.6

1.7

2

Functional Description ..............................................................................................7

2.1

Frequency Planning.......................................................................................................... 7

2.2

Calculation of Counter Settings........................................................................................ 8

2.2.1 Calculation of LO1 and IF1 frequency for Low Frequency Bands............................................... 8

2.2.2 Calculation of LO1 and IF1 frequency for High Frequency Bands.............................................. 9

2.2.3 Counter Setting Examples for SPI Mode..................................................................................... 9

2.2.4 Counter Settings in ABC Mode – 8 Preconfigured Channels.................................................... 10

2.2.5 PLL Counter Ranges ................................................................................................................. 11

2.3

SPI Description............................................................................................................... 11

2.3.1 General ...................................................................................................................................... 11

2.3.2 Read / Write Sequences............................................................................................................ 12

2.3.3 Serial Programming Interface Timing ........................................................................................ 12

3

Register Description ................................................................................................13

3.1

Register Overview .......................................................................................................... 13

3.1.1 Control Word R0 ........................................................................................................................ 15

3.1.2 Control Word R1 ........................................................................................................................ 16

3.1.3 Control Word R2 ........................................................................................................................ 17

3.1.4 Control Word R3 ........................................................................................................................ 17

3.1.5 Control Word R4 ........................................................................................................................ 18

3.1.6 Control Word R5 ........................................................................................................................ 18

3.1.7 Control Word R6 ........................................................................................................................ 18

3.1.8 Control Word R7 (Read-only Register)...................................................................................... 19

4

Application Circuits .................................................................................................20

4.1

Standard FSK & ASK Circuit in SPI Mode...................................................................... 20

4.1.1 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 20

4.1.2 Component Arrangement Top Side for SPI Mode (Averaging Data Slicer) .............................. 21

4.1.3 Peak Detector Data Slicer Configured for NRZ Codes ............................................................. 22

4.1.4 Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer)........................ 23

4.1.5 Board Component Values List (SPI mode)................................................................................ 24

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EVB Description

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EVB71122

300 to 930MHz Receiver

Evaluation Board Description

4.2

Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode.......................... 25

4.2.1 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 25

4.2.2 Component Arrangement Top Side for ABC Mode (averaging data slicer) .............................. 26

4.2.3 Board Component Values List (ABC mode).............................................................................. 27

5

6

7

Evaluation Board Layouts.......................................................................................28

Board Variants..........................................................................................................28

Package Description................................................................................................29

7.1

Soldering Information ..................................................................................................... 29

Reliability Information .............................................................................................30

ESD Precautions ......................................................................................................30

8

9

10 Disclaimer.................................................................................................................32

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Rev. 001

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EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

1

Theory of Operation

1.1 General

The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two

LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency

is derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator

with external inductor, a programmable feedback divider chain, a programmable reference divider, a phase-

frequency detector with a charge pump and an external loop filter.

In the receiver’s down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local oscillator

signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first intermedi-

ate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image rejection is

provided even without using an RF front-end filter. At applications asking for very high image rejections,

cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA.

The receiver signal chain is setup by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and

MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an

FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based

ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator.

The data slicer threshold can be generated from the mean-value of the data stream or by means of the posi-

tive and negative peak detectors (PKDET+/-).

In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely turned

off, and to several other operating modes. There are two global operating modes that are selectable via the

logic level at pin SPISEL:

•

8-channel preconfigured mode (ABC mode)

fully programmable mode (SPI mode).

In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is

required. In this case the three lines of the serial programming interface (SPI) are used to select one of the

eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are

used to enable/disable the receiver and to select FSK or ASK demodulation, respectively.

SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are config-

ured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the

receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types,

data slicer settings and more. The pin MODSEL has no effect in this mode.

1.2 EVB Data Overview

! Input frequency ranges: 300 to 930MHz

! Power supply range: 3.0 to 5.5V

! Temperature range: -40 to +105°C

! Shutdown current: 50nA

! Operating current: 11mA (typ.)

! Internal IF2: 2MHz with 230kHz 3dB bandwidth

! Maximum data rate: 100kbps NRZ code,

50kbps bi-phase code

! Total image rejection: > 65dB (with external

RF front-end filter)

! FSK/FM deviation range: ±10 to ±50kHz

! Spurious emission: < -70dBm

! Linear RSSI range: > 70dB

! FSK input frequency acceptance range:

170kHz (3dB)

! Crystal reference frequency: 10MHz

! Minimum frequency resolution: 10kHz

! Input Sensitivity: at 4 kbps NRZ, BER = 3·10^-3

Frequency

FSK: ±20 kHz deviation

ASK

315 MHZ

-106dBm

-108dBm

433 MHz

-104dBm

-108dBm

868 MHz

915 MHz

-101dBm

-106dBm

-101dBm

-106dBm

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EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

1.3 Block Diagram

5

1

2

6

3

4

8

9

28

29

200k

DFO

OA1

27

ASK

FSK

IFF

MIX1

MIX2

SW1

IF1

IF2

IFA

LNAI

25

PKDET+

LNA

31

PDP

FSK

DEMOD

LO1

LO2

_

PDN

PKDET

LO2DIV

26

N / A

counter

R

SLCSEL

PFD

counter

SW2

DTAO

VCO

OA2

Control

Logic

22

BIAS

LF

CP

RO

SLC

32

TNK1

TNK2

11

14

12 13

15

23

24

18

10

16

20

21

30

7

17

19

Fig. 1: MLX71122 block diagram

The MLX71122 receiver IC consists of the following building blocks:

•

PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2,

parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R,

the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator

(RO)

•

Low-noise amplifier (LNA) for high-sensitivity RF signal reception

First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)

Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF

IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth

IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output

FSK demodulator (FSK DEMOD)

Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively

Positive (PKDET+) and negative (PKDET-) peak detectors

Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak

detector data slicer

•

Control logic with 3-wire bus serial programming interface (SPI)

Biasing circuit with modes control

For more detailed information, please refer to the latest MLX71122 data sheet revision.

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EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

1.4 Enable/Disable in ABC Mode

ENRX

Description

0

1

Shutdown mode

Receive mode

Pin ENRX is pulled down internally. Device is in shutdown by default, after power supply on.

If ENRX = 0 and SPISEL = 1 then operating modes according to OPMODE bit (refer to control word R0).

If ENRX = 1 then OPMODE bit has no effect (hardwired receive mode).

1.5 Demodulation Selection in ABC Mode

MODSEL

Description

0

1

FSK demodulation

ASK demodulation

Pin MODSEL has no effect in SPI mode (SPISEL = 1). We recommend connecting it to ground to avoid a

floating CMOS gate.

1.6 Programming Modes

SPISEL

Description

0

1

ABC mode (8 channels preconfigured)

SPI mode (programming via 3-wire bus)

1.7 Preconfigured Frequencies in ABC Mode

A

0

1

0

1

B

0

1

0

1

0

1

0

1

C

0

1

Receive Frequency

FSK1: 369.5 MHz

FSK5: 388.3 MHz

FSK2: 371.1 MHz

FSK4: 376.9 MHz

FSK3: 375.3 MHz

FSK7: 394.3 MHz

FSK6: 391.5 MHz

FSK8: 395.9 MHz

As all pins, pins A, B, and C are equipped with ESD protection diodes that are tied to VCC and to VEE.

Therefore these pins should not be directly connected to positive supply (a logic “1”) before the supply volt-

age is applied to the IC. Otherwise the IC will be supplied through these control lines and it may enter into an

unpredictable mode. In case the user wants to apply a positive supply voltage to these pins before the sup-

ply voltage is applied to the IC, a protection resistor should be inserted in each control line.

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EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

2

Functional Description

2.1 Frequency Planning

Because of the double conversion architecture that employs two mixers and two IF signals, there are four

different combinations for injecting the LO1 and LO2 signals:

•

LO1 high side and LO2 high side:

LO1 high side and LO2 low side:

LO1 low side and LO2 high side:

LO1 low side and LO2 low side:

receiving at f_RF(high-high)

receiving at f_RF(high-low)

receiving at f_RF(low-high)

receiving at f_RF(low-low)

As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 2

shows this for the case of receiving at f_RF(high-high). In the example of Fig. 2, the image signals at f_RF(low-

high) and f_RF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The

bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by

the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the

high value of the first IF (IF1) helps to suppress the image signals at f_RF(low-high) and f_RF(low-low).

The two remaining signals at IF1 resulting from f_RF(high-high) and f_RF(high-low) are entering the second

mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means

either the upper or lower sideband of IF1 can be selected. In the example of Fig. 2, LO2 high-side injection

has been chosen to select the IF2 signal resulting from f_RF(high-high).

f_LO2

f_RF

f_LO1

f_RF

Fig. 2: The four receiving frequencies in a double conversion superhet receiver

It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO1 signal fre-

quency f_LO1and the LO2 signal frequency f_LO2

.

f_LO1

LO2DIV = N_LO2

=

(1)

f_LO2

The LO1 signal frequency f_LO1is directly synthesized from the crystal reference oscillator frequency f_ROby

means of an integer-N PLL synthesizer. The PLL consists of a dual-modulus prescaler (P/P+1), a program

counter N and a swallow counter A.

f_RO

f_LO1

=

(N ⋅ P + A) = f_PFD(N ⋅ P + A) = f_PFD⋅ N_tot

(2)

R

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Rev. 001

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EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

Due to the double superhet receiver architecture, the channel frequency step size f_CHis not equal to the

phase-frequency detector (PFD) frequency f_PFD. For high-side injection, the channel step size f_CHis given by:

f_RON_LO2−1

N_LO2−1

N_LO2

f_CH

=

= f_PFD

(3)

(4)

R

N_LO2

While the following equation is valid for low-side injection:

f_RON_LO2+1

N_LO2+1

N_LO2

f_CH

=

= f_PFD

R

N_LO2

2.2 Calculation of Counter Settings

Frequency planning and the selection of the MLX71122’s PLL counter settings are straightforward and can

be laid out on the following procedure.

Usually the receive frequency f_RFand the channel step size f_CHare given by system requirements. The N

and A counter settings can be derived from N_totor f_LO1and f_PFDby using the following equations.

N

N = floor( ^tot) = floor( ^tot) ; A = N_tot− N ⋅ P = N_tot− N ⋅32

32

(5)

P

2.2.1

Calculation of LO1 and IF1 frequency for Low Frequency Bands

High-high injection must be used for the low frequency bands. First of all choose a PFD frequency f_PFD

according to below table. The R counter values are valid for a 10MHz crystal reference frequency f_RO. The

PFD frequency is given by f_PFD= f_RO/R.

Injection Type

f_CH[kHz]

10

f_PFD[kHz]

13.3

R

h-h

750

600

375

300

150

75

12.5

20

16.7

26.7

25

33.3

50

66.7

100

250

133.3

333.3

30

The second step is to calculate the missing parameters f_LO1, f_IF1, N_tot, N and A. While the second IF (f_IF2), the

N_LO2divider ratio and the prescaler divider ratio P are bound to f_IF2= 2MHz, N_LO2= 4 (or 8) and P =32.

N_LO2

4

f_LO1

=

(f_RF− f_IF2)

f_LO1= (f_RF− 2MHz)

(6)

(7)

N_LO2−1

3

f_RF− N_LO2f_IF2

N_LO2−1

f_RF− 8MHz

f_IF1

=

f_IF1=

3

Finally N and A can be calculated with formula (5).

39012 71122 01

Rev. 001

Page 8 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

2.2.2

Calculation of LO1 and IF1 frequency for High Frequency Bands

Typical ISM band operating frequencies like 868.3 and 915MHz can be covered without changing the crystal

nor the VCO inductor.

Low-low injection should be used for the high frequency bands. First of all choose a PFD frequency f_PFD

according to below table. The R counter values are valid for a 10MHz crystal reference. The PFD frequency

is given by f_PFD= f_RO/R.

Injection Type

f_CH[kHz]

20

f_PFD[kHz]

16

R

l-l

625

500

250

125

50

25

20

50

40

100

250

500

80

200

400

25

The second step is to calculate the missing parameters f_LO1, f_IF1, N_tot, N and A. While the second IF (f_IF2), the

N_LO2divider ratio and the prescaler divider ratio P are bound to f_IF2= 2MHz, N_Lo2= 4 (or 8) and P =32.

N_LO2

4

f_LO1

=

(f_RF− f_IF2)

f_LO1= (f_RF− 2MHz)

(8)

(9)

N_LO2+1

5

f_RF+ N_LO2f_IF2

N_LO2+1

f_RF+ 8MHz

f_IF1

=

f_IF1=

5

Finally N and A can be calculated with formula (5).

2.2.3

Counter Setting Examples for SPI Mode

To provide some examples, the following table shows some counter settings for the reception of the well-

known ISM and SRD frequency bands. The channel spacing is assumed to be f_CH= 100kHz. In below table

all frequency units are in MHz.

Inj

h-h

l-l

f_RF

f_IF1

f_LO1

N_tot

N

P

A

4

f_PFD

0.133

0.08

R

f_REF

10

f_LO2

99.3

f_IF2

2

300

315

434

470

850

868

915

930

97.3 397.3 2980

102.3 417.3 3130

93

32

75

97

26

0

75

104.3

144

2

142

154

576

624

4320

4680

135

146

256

270

285

290

75

2

8

75

156

2

171.6 678.4 8480

175.2 692.8 8660

184.6 730.4 9130

187.6 742.4 9280

0

125

169.6

173.2

182.6

185.6

2

l-l

20

10

0

0.08

2

l-l

0.08

2

l-l

0.08

2

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Rev. 001

Page 9 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

2.2.4

Counter Settings in ABC Mode – 8 Preconfigured Channels

In ABC mode (SPISEL=0), the counter settings are hard-wired. In below table all frequency units are in MHz.

FSK

1

f_RF

f_IF1

f_LO1

N_tot

N

P

A

27

11

21

5

f_PFD

R

f_REF

10

f_LO2

f_IF2

2

369.5 120.5 490.0 3675

371.1 121.0 492.0 3691

375.3 122.4 497.7 3733

376.9 123.0 499.9 3749

388.3 126.8 515.1 3863

391.5 127.8 519.3 3895

394.3 128.8 523.1 3923

395.9 129.3 525.2 3939

114

115

116

117

120

121

122

123

32

0.133

75

122.5

123.0

124.4

125.0

128.8

129.8

130.8

131.3

2

3

2

4

2

5

23

19

3

2

6

2

7

2

8

2

List of Mathematical Acronyms

divider ratio of the swallow counter (part of feedback divider)

frequency at the feedback divider output

A

f_FB

The floor function gives the largest integer less than or equal to x.

For example, floor(5.4) gives 5, floor(-6.3) gives -7.

floor (x)

f_PFD

PFD frequency in locked state

f_RO

= f_R

R

reference frequency of the PLL

f_RO

frequency of the crystal reference oscillator

f_VCO

frequency of the VCO (equals the LO1 signal of the first mixer)

N_tot= N ⋅ P + A

total divider ratio of the PLL feedback path

N

divider ratio of the program counter (part of feedback divider)

LO2DIV divider ratio, to derive the LO2 signal from LO1 (N₁= 4 or 8)

divider ratio of the prescaler (part of feedback divider)

divider ratio of the reference divider R

N_LO2

P

R

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Rev. 001

Page 10 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

2.2.5

PLL Counter Ranges

In order to cover the frequency range of about 300 to 930MHz the following counter values are implemented

in the receiver:

PLL Counter Ranges

A

N

R

P

0 to 31 (5bit)

3 to 2047 (11bit)

32

Therefore the minimum and maximum divider ratios of the PLL feedback divider are given by:

N_totmin= 32⋅32 = 1024

N_totmax= 2047⋅32 + 31 = 65535

2.3 SPI Description

2.3.1

General

Serial programming interface (SPI) mode can be activated by choosing SPISEL = 1 (e.g. at positive supply

voltage V_CC). In this mode, the input pins 17, 18 and 19 are used as a 3-wire unidirectional serial bus inter-

face (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter

settings, mode bits etc.

In addition the MFO pin can be programmed as an output (see section 4.1.4) in order to read data from the

internal latches and it can be used as an output for different test modes as well.

At each rising edge of the SCLK signal, the logic value at the SDTA terminal is written into a shift register.

The programming information is taken over into internal latches with the rising edge of SDEN. Additional

leading bits are ignored, only the last bits are serially clocked into the shift register. A normal write operation

shifts 16 bits into the SPI, a normal read operation shifts 4 bits into the SPI and reads additional 12 bits from

the MFO pin. If less than 12 data bits are shifted into SDTA during the write operation then the control regis-

ter may contain invalid information.

In general a control word has the following format. Bit 0 is the Read/Write bit that determines whether it is a

read (R/W = 1) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the

corresponding data bits.

Control Word Format

MSB

LSB

MSB

LSB

Bit 0

Data

D6 D5

Latch Address Mode

A2 A2 A0 R/W

D11 D10 D9

D8

D7

D4

D3

D2

D1

D0

There are two control word formats for read and for write operation. Data bits are only needed in write mode.

Read operations require only a latch address and a R/W bit.

Due to the static CMOS design, the serial interface consumes virtually no current. The SPI is a fully separate

building block and can therefore be programmed in every operational mode.

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Rev. 001

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EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

2.3.2

Read / Write Sequences

Fig. 6

Typical write sequence diagram

Fig. 7

Typical read sequence diagram

2.3.3

Serial Programming Interface Timing

SDEN

SCLK

t_CWH

t_CR

t_EW

t_EH

t_CWL

t_CF

t_ES

t_CSt_CH

t_DES

t_DSO

SDTA

MFO

Fig. 8

SPI timing diagram

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Rev. 001

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EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

3

Register Description

The following tables are to describe the functionality of the registers.

Sec. 4.1 provides a register overview with all the control words R0 to R7. The subsequent sections. 4.1.1 to

4.1.8 show the content of the control words in more detail.

Programming the registers requires SPI mode (SPISEL = 1). Default settings are for ABC mode.

3.1 Register Overview

DATA

CONTROL

WORD

LATCH

ADDRESS

MSB

11

LSB

Bit No.

10

9

8

7

6

5

4

3

2

1

0

MSB

LSB

default

1

0

1

0

1

0

read/

write

R0

MSB

LSB

Bit No.

11

10

9

8

7

6

5

4

3

2

1

0

default

1

0

1

0

1

0

1

0

1

read/

write

R1

Bit No.

11

10

9

8

7

6

5

4

3

2

1

0

MSB

LSB

default

1

0

1

0

1

0

1

0

read/

write

R2

Bit No.

11

10

9

8

7

6

5

4

3

2

1

0

MSB

LSB

default

0

1

0

1

read/

write

R3

39012 71122 01

Rev. 001

Page 13 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

DATA

CONTROL

WORD

LATCH

ADDRESS

MSB

11

LSB

Bit No.

10

9

8

7

6

5

4

3

2

1

0

MSB

LSB

default

0

1

0

1

0

1

0

read/

write

R4

Bit No.

11

10

9

8

7

6

5

4

3

2

1

0

MSB

LSB

default

0

1

0

1

0

1

0

1

0

1

read/

write

R5

Bit No.

11

10

9

8

7

6

5

4

3

2

1

0

MSB

LSB

default

1

0

1

0

1

0

1

0

1

0

read/

write

R6

Bit No.

11

10

9

8

7

6

5

4

3

2

1

0

MSB

LSB

default

1

read-

only

R7

Note:

^∗depends on bit 11 in R4, 0 = RSSIL, 1 = LD

39012 71122 01

Rev. 001

Page 14 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

3.1.1

Control Word R0

Name

Bits

Description

operation mode

#default

00

01

10

11

shutdown

receive mode

OPMODE

[1:0]

reference oscillator & BIAS only

synthesizer only

LNA gain

00

01

10

11

lowest gain

low gain

high gain

(-18dB)

(-4dB)

(0dB)

LNAGAIN

[3:2]

#default

highest gain

(+2dB)

gain values are relative to gain at default

1^stMixer gain

(14dB)

(0dB)

2^ndMixer gain

MIX1GAIN

MIX2GAIN

[4]

[5]

#default

0

1

high gain

low gain

0

1

high gain

low gain

(9dB)

(-2dB)

intermediate frequency filter gain

00

01

10

11

lowest gain

low gain

high gain

(-14dB)

(-6dB)

(0dB)

IFFGAIN

[7:6]

#default

highest gain

(+6dB)

demodulator gain

DEMGAIN

SSBSEL

SLCSEL

[8]

[9]

0

1

low gain

high gain

(~ 4mV/kHz)

(~ 15mV/kHz)

#default

single side band selection

0

1

upper side band LO2 low-side inj. (IF1 = LO2 + IF2)

lower side band

LO2 high-side inj. (IF1 = LO2 – IF2)

Internal IF2 = 2MHz

slicer mode select

#default

0

1

averaging Data Slicer mode

peak detector Data Slicer mode

data output polarity OA2

0

1

inverted

‘1’ for space at ASK or f_minat FSK, ‘0’ for mark at ASK or f_maxat FSK

DTAPOL

[11]

normal

‘0’ for space at ASK or f_minat FSK, ‘1’ for mark at ASK or f_maxat FSK

39012 71122 01

Rev. 001

Page 15 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

3.1.2

Control Word R1

Name

Bits

Description

charge pump current setting

#default

00

01

10

11

100µA

400µA

400µA static down

400µA static up

CPCUR

[1:0]

PFD output polarity

lock detector time error

lock detection time

[2]

[3]

PFDPOL

LDERR

0

1

negative

positive

#default

0

1

15ns

30ns

00

01

10

11

2/f_R

4/f_R

8/f_R

[5:4]

LDTIME

#default

16/f_R

minimum time span before lock in

f_Ris the reference oscillator frequency f_ROdivided by R, see section 4.1.5 (R4)

lock detector mode

LDMODE

[6]

[7]

0

1

check lock condition permanently

check lock condition until 1^stlock in

VCO range

0

1

3V supply

5V supply

VCORANGE

#default

VCO range setting for different VCCs.

VCO core current

VCOCUR

VCOBUF

[8]

[9]

0

1

450µA

520µA

VCO buffer current

0

1

900µA

1040µA

prescaler 32/33 reference current

0

1

20µA

30µA

PRESCUR

SHOWLD

[10]

[11]

30µA may be used for f_RF= 868/915MHz

function of LDRSSIL bit

0

1

RSSIL (RSSI low flag)

LD (lock detection flag)

#default

select output data of LDRSSIL, see section 4.1.8 (R7)

39012 71122 01

Rev. 001

Page 16 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

3.1.3

Control Word R2

Name

Bits

Description

swallow counter value

#default

value is 12

[4:0]

A

N

01100

swallow counter range: 0 to 31

program counter value (bits 0 – 6)

[11:5]

#default

000 0111 0111 N value is 119

N counter range: 3 to 2047

3.1.4

Control Word R3

program counter range (bits 7 – 10)

000 0111 0111 N value is 119

N

[3:0]

#default

N counter range: 3 to 2047

LO2 divider ratio

AGC enable mode

AGC delay settings

LO2DIV

AGCEN

[4]

[5]

#default

0

1

divide by 4

divide by 8

0

1

disabled

enabled

00

01

10

11

no delay

3/f_IFF

15/f_IFF

31/f_IFF

AGCDEL

[7:6]

f_IFFis the reference oscillator frequency f_ROdivided by RIFF, see section 4.1.6 (R6)

multi functional output

0000 MFO is in Z state

0001 MFO is SPI read-out

0010 MFO = 0

[11:8]

MFO

0011 MFO = 1

#default

0100 MFO is analog RO output

0101 MFO is IFF output

1000 MFO is lock detector output

39012 71122 01

Rev. 001

Page 17 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

3.1.5

Control Word R4

Name

Bits

Description

reference divider range

#default

[10:0]

R

000 0100 1011 value is 75

R counter range: 3 to 2047

AGC delay mode

#default

0

1

gain decrease and increase with delay

gain decrease without delay, gain increase with delay

AGCMODE

[11]

selects AGC delay mode in combination with AGCDEL bits, see section 4.1.4 (R3)

3.1.6

Control Word R5

Name

Bits

Description

reference divider value for IFF adjustment

[10:0]

RIFF

#default

010 1001 1011 value is 667

IFF counter range: 4 to 2047

demodulation selection

0

1

FSK demodulation

ASK demodulation

MODSEL

[11]

selects modulation type when chip is controlled via SPI mode

3.1.7

Control Word R6

Name

Bits

Description

IFF preset value

[7:0]

IFFPRES

#default

0110 1100

value is 108

IFF DAC preset at start of automatic tuning

IFF halt

0

1

auto tuning running

auto tuning halted

IFFHLT

[8]

[9]

suspends IFF automatic tuning

IFF tuning

IFFTUNE

0

1

disable and load DAC with IFFPRES

enable

#default

reference Oscillator core current

00

01

10

11

85µA

170µA

270µA

355µA

ROCUR

[11:10]

39012 71122 01

Rev. 001

Page 18 of 32

EVB Description

Sept/06

EVB71122

300 to 930MHz Receiver

Evaluation Board Description

3.1.8

Control Word R7 (Read-only Register)

Name

Bits

Description

IFF adjustment value

[7:0]

IFFVAL

型号	制造商	描述	价格	文档
EVB71122_15	MELEXIS	300 to 930MHz Receiver Evaluation Board Description	获取价格
EVB7120	ETC	EVB7120 EValuation Board For TH7120 300 to 930MHz FSK/FM/ASK Transceiver	获取价格
EVB7122	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格
EVB7122-315-ASK-A	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格
EVB7122-315-ASK-C	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格
EVB7122-315-FM-A	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格
EVB7122-315-FM-C	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格
EVB7122-315-FSK-A	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格
EVB7122-315-FSK-C	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格
EVB7122-433-ASK-A	MELEXIS	27 to 930MHz Transceiver Evaluation Board Description	获取价格

EVB71122C-915-FSK-C

EVB71122C-915-FSK-C 概述

EVB71122C-915-FSK-C 数据手册

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