MLX71120KLQAAA-000TU [MELEXIS]
FSK/FM/ASK Receiver;
| 型号： | MLX71120KLQAAA-000TU |
| 厂家： | 
Melexis Microelectronic Systems |
| 描述： | FSK/FM/ASK Receiver |
| 文件： | 总31页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Features
ꢀ Dual RF input for antenna space and frequency diversity, LNA cascading or differential feeding
ꢀ Fully integrated PLL-based synthesizer
ꢀ 2nd mixer with image rejection
ꢀ Reception of ASK or FSK modulated signals
ꢀ Wide operating voltage and temperature ranges
ꢀ Very low standby current consumption
ꢀ Low operating current consumption
ꢀ External IF filter for 455kHz or 10.7MHz
ꢀ Internal FSK demodulator
ꢀ Average or peak detection data slicer mode
ꢀ RSSI output with high dynamic range for RF level indication
ꢀ Output noise cancellation filter
ꢀ MCU clock output
ꢀ High over-all frequency accuracy
ꢀ 32-pin Quad Flat No-Lead Package (QFN)
Ordering Code
Product Code
MLX71120
MLX71120
Temperature Code
Package Code
Option Code
AAA-000
AAA-000
Packing Form Code
K
K
LQ
LQ
RE
TU
Legend:
Temperature Code:
Package Code:
Packing Form:
K for Temperature Range -40°C to 125°C
LQ for QFN
RE for Reel, TU for Tube
Ordering example:
MLX71120KLQ-AAA-000-RE
39010 71120
Rev. 008
Page 1 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Application Examples
Pin Description
bottom
top
ꢀ Tire pressure monitoring systems (TPMS)
ꢀ Remote keyless entry (RKE)
ꢀ Remote controls
ꢀ Home and building automation
ꢀ Alarm and security systems
ꢀ Low power telemetry systems
ꢀ Garage and gate controls
ꢀ General-purpose RF receivers at 300 to
930MHz
LNAI1
VEE
RSSI
CINT
VCC
PDN
LNAO1
MIXP
MLX71120
MIXN
LNAO2
VEE
PDP
SLC
DFO
DF1
LNAI2
General Description
The MLX71120 is a highly-integrated single-channel/dual-band RF receiver based on a double-conversion
super-heterodyne architecture. It can receive FSK and ASK modulated signals. The IC is designed for gen-
eral purpose applications for example in the European bands at 433MHz and 868MHz or for similar applica-
tions in North America or Asia, e.g. at 315MHz or 915MHz. It is also well-suited for narrow-band applications
according to the ARIB STD-T67 standard in the frequency range 426MHz to 470MHz.
The receiver’s extended temperature and supply voltage ranges make the device a perfect fit for automotive
or similar applications where harsh environmental conditions can occur.
39010 71120
Rev. 008
Page 2 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Document Content
1
Theory of Operation...................................................................................................5
1.1 General..............................................................................................................................5
1.2 Technical Data Overview ...................................................................................................5
1.3 Block Diagram....................................................................................................................6
1.4 Operating Modes................................................................................................................7
1.5 LNA Selection ....................................................................................................................7
1.6 Mixer Section .....................................................................................................................8
1.7 IF Amplifier.........................................................................................................................8
1.8 PLL Synthesizer.................................................................................................................8
1.9 Reference Oscillator...........................................................................................................9
1.10 Clock Output...................................................................................................................9
1.11 FSK Demodulator ...........................................................................................................9
1.12 Baseband Data Path.....................................................................................................10
1.13 Data Filter.....................................................................................................................11
1.14 Data Slicer....................................................................................................................11
1.14.1
1.14.2
Averaging Detection Mode..................................................................................................... 12
Peak Detection Mode............................................................................................................. 12
1.15 Data Output and Noise Cancellation Filter ....................................................................13
2
Frequency Planning.................................................................................................14
2.1 Calculation of Frequency Settings....................................................................................15
2.2 Standard Frequency Plans...............................................................................................16
2.3 433/868MHz Frequency Diversity ....................................................................................16
3
4
Pin Definitions and Descriptions............................................................................17
Technical Data..........................................................................................................21
4.1 Absolute Maximum Ratings..............................................................................................21
4.2 Normal Operating Conditions...........................................................................................21
4.3 DC Characteristics ...........................................................................................................22
4.4 AC System Characteristics...............................................................................................23
4.5 External Components.......................................................................................................25
5
Test Circuit ...............................................................................................................26
5.1 Dual-Channel Application Circuit......................................................................................26
5.1.1 Test Circuit Component List for Figure 10................................................................................. 27
39010 71120
Rev. 008
Page 3 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
6
7
Package Description................................................................................................28
6.1 Soldering Information.......................................................................................................28
Standard information regarding manufacturability of Melexis products with
different soldering processes.................................................................................29
8
9
ESD Precautions ......................................................................................................29
Disclaimer.................................................................................................................31
39010 71120
Rev. 008
Page 4 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1
Theory of Operation
1.1 General
The MLX71120 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high
degree of image rejection is provided even without using an RF front-end filter. At applications asking for
very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front
of the LNA. The second mixer MIX2 is an image-reject mixer.
The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion
mixers (MIX1, MIX2) and an external IF filter with an on-chip amplifier (IFA). By choosing the required modu-
lation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the
RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the
demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by
means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data
signal can be performed by a noise cancellation filter (NCF) building block.
The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to
setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the
RF signal differentially.
A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize
power dissipation.
A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a microcon-
troller. The clock output is open drain and gets activated through a load connected to positive supply.
1.2 Technical Data Overview
ꢀ Input frequency ranges: 300 to 470MHz
610 to 930MHz
ꢀ FSK deviation range: 10kHz to 100kHz (WB)
2kHz to 10kHz (NB)
ꢀ Power supply range: 2.1 to 5.5V
ꢀ Temperature range: -40 to +125°C
ꢀ Shutdown current: 50 nA
ꢀ Operating current: 6.5 to 8.1mA
ꢀ FSK input sensitivity: -108dBm* (WB, 433MHz)
-112dBm* (NB, 433MHz)
ꢀ Image rejection:
65dB 1st IF (with external RF front-end filter)
25dB 2nd IF (internal image rejection)
ꢀ Maximum data rate: 50kps RZ (bi-phase) code,
100kps NRZ
ꢀ Spurious emission: < -54dBm
ꢀ Linear RSSI range: > 70dB
ꢀ Crystal reference frequency: 16 to 27MHz
ꢀ MCU clock frequency: 2.0 to 3.4MHz
ꢀ ASK input sensitivity: -113dBm* (WB, 433MHz)
ꢀ Selectable IF2 frequency: 10.7MHz or 455kHz
* at 4kbps NRZ, BER = 3⋅10-3, without SAW front-end-filter loss
WB – wideband (180kHz bandwidth at IF2=10.7MHz)
NB – narrowband (20kHz bandwidth at IF2=455kHz)
39010 71120
Rev. 008
Page 5 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.3 Block Diagram
13
6
4
5
9
10
11
12
27
24
14
17
16
3
VEE
2
100k
100k
DFO
OA1
ASK
FSK
18
LNAI1
1
LNA1
SW1
MIX1
MIX2
IFA
LNASEL
32
PKDET+
20
PDP
FSK
DEMOD
LO1
LO2
LNAI2
8
LNA2
_
PDN
PKDET
VEE
7
21
N1
counter
N2
counter
PFD
SEQ
RFSEL
31
SW2
VCO
RO
DTAO
29
OA2
NCF
BIAS
TEST
26
DIV 8
LF
CP
CINT
23
19
30
25
28
15
22
Fig. 1: MLX71120 block diagram
The MLX71120 receiver IC consists of the following building blocks:
•
PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2.
The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback
divider chain (N1,N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a
crystal-based reference oscillator (RO).
•
•
•
•
•
•
•
•
Two low-noise amplifiers (LNA1, LNA2) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detection mode.
Noise cancellation filter (NCF)
Sequencer circuit (SEQ) and biasing (BIAS) circuit
Clock output (DIV8)
•
•
•
39010 71120
Rev. 008
Page 6 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.4 Operating Modes
The receiver offers two operating modes selectable by setting the corresponding logic level at pin ENRX.
ENRX
Description
Shutdown mode
Receive mode
0
1
Note: ENRX is pulled down internally.
The receiver’s start-up procedure is controlled by a sequencer circuit. It performs the sequential activation of
the different building blocks. It also initiates the pre-charging of the data filter and data slicer capacitors in
order to reduce the overall start-up time and current consumption during the start-up phase.
At ENRX = 0, the receiver is in shutdown mode and draws only a few nA. The bias system and the reference
oscillator are activated after enabling the receiver by a positive edge at pin ENRX. The crystal oscillator (RO)
is turned on first. Then the crystal oscillation amplitude builds up from noise. After reaching a certain ampli-
tude level at pin ROI, the whole IC is activated and draws the full receive mode current consumption ICC. This
event is used to start the pre-charging of the external data path capacitors. Pre-charging is finished after
5504 clock cycles. After that time the data output pin DTAO output is activated.
ENRX
I
CC
RO
I
I
SDN
Hi-Z
valid data
Hi-Z
DTAO
t
t
SEQ
onRO
t
onRX
Fig. 2:
Timing diagram of start-up and shutdown behavior
1.5 LNA Selection
The receiver features two identical LNAs. Each LNA is a cascode amplifier with a voltage gain of approxi-
mately 18dB. The actual gain depends on the antenna matching network at the inputs and the LC tank net-
work between the LNA outputs and mixer input. LNA operation can be controlled by the LNASEL pin.
LNASEL
Description
0
Hi-Z
1
LNA1 active, LNA2 shutdown
LNA1 and LNA2 active
LNA1 shutdown, LNA2 active
Pin LNASEL is internally pulled to VCC/2 during receive mode. Therefore both LNAs are active if LNASEL is
left floating (Hi-Z state).
39010 71120
Rev. 008
Page 7 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.6 Mixer Section
The mixer section consists of two mixers. Both are double-balanced mixers. The second mixer is built as an
image rejection mixer. The first mixer’s inputs (MIXP and MIXN) are functionally the same. For single-ended
drive, the unused input has to be tied to ground via a capacitor. A soft band-pass filter is placed between the
mixers.
RFSEL
Description
0
1
Input frequency range 300 to 470MHz
Input frequency range 610 to 930MHz
Pin RFSEL is used to select the required RF band. The LO frequencies and the proper sidebands for image
suppression will be set accordingly. The mixer output (MIXO) is to drive an external IF filter. This output is set
up by a source follower that can be biased to create a driving impedance of either 1500 Ohms or 330 Ohms,
depending on the logic level at pin IFSEL.
IFSEL
Description
IF2 = 455 kHz
IF2 = 10.7 MHz
0
1
This feature allows to use standard ceramic filters for 455kHz and 10.7MHz. They can be connected directly
without additional matching elements. The overall voltage conversion gain of the mixer section is approxi-
mately 25dB.
1.7 IF Amplifier
After having passed the IF filter, the signal is amplified by a high-gain limiting amplifier. It consists of several
AC-coupled gain stages with a bandwidth of 400kHz to 11MHz. The overall small-signal pass-band gain is
about 80dB. A received-signal-strength indicator (RSSI) signal is generated within the IF amplifier and is
available at pin RSSI.
1.8 PLL Synthesizer
The PLL synthesizer consists of a fully integrated voltage-controlled oscillator running at 400MHz to
640MHz, a distributed feedback divider chain, an edge-triggered phase-frequency detector, a charge pump,
a loop filter and a crystal-based reference oscillator. The PLL is used for generating the LO signals. The LO1
is directly taken from the VCO output, and the LO2 is derived from the LO1 signal passing the N1 counter.
Another counter N2 follows N1. The overall feedback divider ratio Ntot is fixed to 24. The values of N1 and N2
are depending on the selected RF band that can be chosen via pin RFSEL.
fLO1min
[MHz]
fLO1max
[MHz]
fLO2min
[MHz]
fLO2max
[MHz]
RFSEL
N1
N2
Ntot
0
1
400
400
640
640
100
200
160
320
4
2
6
24
24
12
39010 71120
Rev. 008
Page 8 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.9 Reference Oscillator
A Colpitts crystal oscillator with integrated functional capacitors is used as the reference oscillator (RO) of
the PLL synthesizer. The equivalent input capacitance CRO offered to the crystal at pin ROI is about 18pF.
The crystal oscillator features an amplitude control loop. This is to assure a very stable frequency over the
specified supply voltage and temperature range together with a short start-up time. A buffer amplifier with
hysteresis is between RO and PFD. Also a clock divider follows the buffer.
1.10 Clock Output
The clock output pin CKOUT is an open-drain output. For power saving reasons, the circuit is only active if
an external pull-up resistor RCL is applied to the pin. Furthermore, RCL can be used to adjust the clock
waveform. It forms an RC low-pass together with the capacitive load at the pin, the parasitics of the PCB and
the input capacitance of the external circuitry (e.g. a microcontroller).
The clock output feature is disabled if pin CKOUT is connected to ground or left open.
VCC
RCL
CLKO
Control
logic
RO
output
CL
DIV8
Fig. 3: Clock output implementation
1.11 FSK Demodulator
The integrated FSK demodulator is based on a phase-coincidence demodulator principle. An injection-locked
oscillator (ILO) is used as a frequency-dependent phase shifter. This topology features a good linearity of the
frequency-phase relationship over the entire locking range. The type of demodulator has no built-in con-
straints regarding the modulation index. It also offers a wide carrier acceptance range.
In addition, the demodulator provides an AFC loop for correcting the remaining free-running frequency error
and drift effects, and also to remove possible frequency offsets between transmitter and receiver frequen-
cies. The AFC loop features a dead band which means that the AFC loop is only closed if the demodulator
output voltage leaves the linear region of the demodulator. Most of the time, the control loop is open. This
leads to several advantages. The AFC loop bandwidth can be high and therefore the reaction time is short.
Furthermore the demodulator itself has no low-end cut-off frequency.
The FSK demodulator has a negative control slope, this means the output voltage decreases by increasing
the IF2 frequency. This guarantees an overall positive slope because the mixer section converts the receive
frequency to IF2 either with high-low or low-high side injection.
The FSK demodulator is turned off during ASK demodulation.
39010 71120
Rev. 008
Page 9 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.12 Baseband Data Path
The baseband data path can be divided into a data filter section and a data slicer section.
DF1
MODSEL
DF2
data filter
ASK
FSK
100k
100k
OA1
DF0
PDP
SLC
PDN
SW1
data slicer
PKDET+
S4
S1
100k
S2
switches
S3
SLCSEL
VCC
S5
S6
_
PKDET
OA2
Fig. 4: Block diagram of the data path
Control
logic
DTAO
CINT
The data filter input is either connected to the ASK or to the FSK demodulation output. Pin MODSEL can be
used to set the internal switch SW1 accordingly.
MODSEL
Description
0
1
ASK demodulation
FSK demodulation
For ASK demodulation, the RSSI signal of the IFA is used. During FSK demodulation, SW1 is connected to
the FSK demodulator output.
The SLCSEL pin is used to control the internal switches depending on operating and slicer mode.
Pins DF1, DF2, DFO, SLC and DTAO are left floating during shutdown mode. So they are in a high-Z state.
39010 71120
Rev. 008
Page 10 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.13 Data Filter
The data filter is formed by the operational amplifier OA1, two internal 100kΩ resistors and two external ca-
pacitors. It is implemented as a 2nd order Sallen-Key filter. The low pass filter characteristic rejects noise at
higher frequencies and therefore leads to an increased sensitivity.
CF1
DF1
CF2
DF2
data filter
OA1
100k
100k
DF0
Fig. 5: Data filter
The filter’s pole locations can be set by the external capacitors CF1 and CF2. The cut-off frequency fc has to
be adjusted according to the transmission data rate R. It should be set to approximately 1.5 times the fastest
expected data rate. For a Butterworth filter characteristic, the data filter capacitors can be calculated as fol-
lows.
1
CF1
2
CF1 =
CF2 =
2 ⋅ π ⋅100k ⋅ fc
RRZ [kbit/s]
RNRZ [kbit/s]
fc [kHz]
0.9
1.8
2.4
3.6
5
CF1 [pF]
2200
1200
1000
680
CF2 [pF]
1000
680
0.6
1.2
1.6
2.4
3.3
4.8
6.0
1.2
2.4
3.2
4.8
6.6
9.6
12
470
330
470
220
7.2
9
330
150
220
100
1.14 Data Slicer
The purpose of the data slicer is to convert the filtered data signal into a digital output. It can therefore be
considered as an analog-to-digital converter. This is done by using the operational amplifier OA2 as a com-
parator that compares the data filter output with a threshold voltage. The threshold voltage can be derived in
two different ways from the data signal.
SLCSEL
Description
0
1
Averaging detection mode
Peak detection mode
39010 71120
Rev. 008
Page 11 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.14.1 Averaging Detection Mode
The simplest configuration is the averaging or RC inte-
gration method. An on-chip 100kΩ resistor together with
an external slicer capacitor (CSL) set up an RC low-
pass filter. This way the threshold voltage automatically
adjusts to the mean or average value of the analog in-
put voltage.
data slicer
PKDET+
PDP
S4
data
filter
S1
SLC
To create a stable threshold voltage, the cut-off fre-
quency of the low pass has to be lower than the lowest
signal frequency.
100k
S2
switches
S3
SLCSEL
VCC
CSL
S5
_
τAVG
1.5
PKDET
OA2
CSL ≥
τAVG
=
PDN
100k
RRZ
S6
A long string of zeros or ones, like in NRZ codes, can
cause a drift of the threshold. That’s why a Manchester
or other DC-free coding scheme works best.
Control
logic
DTAO
CINT
The peak detectors are disabled during averaging de-
tection mode, and the output pins PDP and PDN are
pulled to ground (S4, S6 are closed).
Fig. 6: Data path in averaging detection mode
1.14.2 Peak Detection Mode
Peak detection mode has a general advantage over
averaging detection mode because of the part attack
and slow release times. Peak detection should be used
for all non DC-free codes like NRZ. In this configuration
the threshold is generated by using the positive and
negative peak detectors. The slicer comparator thresh-
old is set to the midpoint between the high output and
the low output of the data filter by an on-chip resistance
divider. Two external capacitors (CP1, CP2) determine
the release times for the positive and negative enve-
lope. The two on-chip resistors provide a path for the
capacitors to discharge. This allows the peak detectors
to dynamically follow peak changes of the data filter
output voltage. The attack times are very short due to
the high peak detector load currents of about 500uA.
The decay time constant mainly depends on the longest
time period without bit polarity change. This corre-
sponds to the maximum number of consecutive bits with
the same polarity (NMAX).
data slicer
PKDET+
PDP
S4
CP1
data
filter
S1
S3
100k
SLC
PDN
S2
switches
SLCSEL
VCC
CP2
S5
_
PKDET
OA2
S6
Control
logic
DTAO
CINT
Fig. 7: Data path in peak detection mode
τDECAY
100k
NMAX
RNRZ
CP1/2 ≥
τDECAY
=
If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are dis-
abled and the output of the positive peak detector (PDP) is connected to VEE (S4 is closed) and the output
of the negative peak detector (PDN) is connected to VCC (S5 is closed). This guarantees the correct biasing
of CP1 and CP2 during start-up
39010 71120
Rev. 008
Page 12 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.15 Data Output and Noise Cancellation Filter
The data output pin DTAO delivers the demodulated data signal which can be further processed by a noise
cancellation filter (NCF). The NCF can be disabled if pin CINT is connected to ground. In this case the
multiplexer (MUX) connects the receiver output DTAO directly to the data slicer output.
MUX
data slicer
output
DTAO
Fig. 8: Data output and noise filter
NCF
CINT
noise cancellation filter
CF3
The noise cancellation filter can suppress random pulses in the data output which are shorter than tmin
.
15⋅10−6 7.5⋅10−6
CF3 = 15⋅10-6 ⋅ tmin
=
=
RNRZ
RRZ
The NCF can also operate as a muting circuit. So if the RF input signal is below sensitivity level (or if no
RF signal is applied) then the data output will go to a constant DC level (either HIGH or LOW). This can be
achieved by setting the bandwidth of the preceding data filter (sec 1.13) about 10 times higher than the
bandwidth of the NCF. Further the data filter cutoff frequency must be higher than the data rate, so the noise
pulses are shorter than the shortest data pulse. Otherwise, the NCF will not be able to distinguish between
noise and data pulses.
Having the NCF activated is a good means for reducing the computing power of the microcontroller that fol-
lows the receiver IC for further data processing.
In contrast to conventional muting (or squelch) circuits, this topology does not need the RSSI signal for level
indication. The filtering process is done by means of an analogue integrator. The cut-off frequency of the
NCF is set by the external capacitor connected to pin CINT. This capacitor CF3 should be set according to
the maximum data rate. Below table provides some recommendations..
During receiver start-up a sequencer checks if pin CINT is connected to a capacitor or to ground. The maxi-
mum value of CF3 should not exceed 12nF. This defines the lowest data rate that can be processed if the
noise cancellation filter is activated.
RRZ [kbit/s]
RNRZ [kbit/s]
CF3[nF]
12
0.6
1.2
1.6
2.4
3.3
4.8
6.0
1.2
2.4
3.2
4.8
6.6
9.6
12
6.8
4.7
3.3
2.2
1.5
1.2
In shutdown mode pin DTAO is set to Hi-Z state.
39010 71120
Rev. 008
Page 13 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
2
Frequency Planning
Because of the double conversion architecture that employs two mixers and two IF signals, there are four
different combinations for injecting the LO1 and LO2 signals:
LO1 high side and LO2 high side: receiving at fRF(high-high)
LO1 high side and LO2 low side: receiving at fRF(high-low)
LO1 low side and LO2 high side: receiving at fRF(low-high)
LO1 low side and LO2 low side:
receiving at fRF(low-low)
As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 9 shows
this for the case of receiving at fRF(high-high). In the example of Fig. 9, the image signals at fRF(low-high) and
fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The bandpass
shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by the tank
circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the high value
of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low).
The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second
mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means
either the upper or lower sideband of IF1 can be selected. In the example of Fig. 9, LO2 high-side injection
has been chosen to select the IF2 signal resulting from fRF(high-high).
Fig. 9: The four receiving frequencies in a double conversion superhet receiver
It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO signal fre-
.
quencies (fLO1 , fLO2) and the reference oscillator frequency fRO
fLO1 = N1 ⋅fLO2
fLO2 = N2 ⋅fRO
The IF2 frequency can be selected to 455kHz or 10.7MHz via the logic level at the IFSEL control pin. At the
same time the output impedance of the 2nd mixer at pin MIXO is set according to the IF2 (please refer to pin
description for details). Of course, also the operating frequency of the FSK demodulator (FSK DEMOD) is set
accordingly.
39010 71120
Rev. 008
Page 14 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
2.1 Calculation of Frequency Settings
The receiver has two predefined receive frequency plans which can be selected by the RFSEL control pin.
Depending on the logic level of RFSEL pin the sideband selection of the second mixer and the counter set-
tings for N1 and N2 are changed accordingly.
RFSEL
Injection
high-low
low-high
fRFmin [MHz]
300
fRFmax [MHz]
470
N1
4
N2
6
0
1
610
930
2
12
The following table shows the relationships of several internal receiver frequencies for the two input fre-
quency ranges.
fRF [MHz]
fIF1
fLO1
fLO2
fRO
fRF + N1fIF2
N1 −1
N1 (fRF + fIF2
N1 −1
)
)
fRF + fIF2
N1 −1
fRF + fIF2
300 to 470
N2 (N1 −1)
fRF − N1fIF2
N1 +1
N1 (fRF + fIF2
N1 +1
fRF + fIF2
N1 +1
fRF + fIF2
610 to 930
N2 (N1 +1)
Given IF2 is selectable at either 455kHz or 10.7MHz and the corresponding N1, N2 counter settings, above
equations can be transferred into the following table.
IF2=455kHz
fRF [MHz]
fIF1
fLO1
fLO2
fRO
fRF + 1.82MHz
4(fRF + 0.455MHz)
fRF + 0.455MHz
300 to 470
3
3
18
fRF + 0.455MHz
3
fRF − 0.91MHz
2(fRF + 0.455MHz)
fRF + 0.455MHz
610 to 930
3
3
36
IF2=10.7MHz
fRF [MHz]
fIF1
fLO1
fLO2
fRO
fRF + 42.8MHz
4(fRF +10.7MHz)
fRF +10.7MHz
300 to 470
610 to 930
3
3
18
fRF + 10.7MHz
3
fRF − 21.4MHz
2(fRF +10.7MHz)
fRF +10.7MHz
3
3
36
39010 71120
Rev. 008
Page 15 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
2.2 Standard Frequency Plans
IF2 = 455kHz
RFSEL
fRF [MHz]
315
fIF1 [MHz]
105.6067
145.2467
289.1300
304.6967
fLO1 [MHz]
420.6067
579.1667
579.1700
610.3033
fLO2 [MHz]
105.1517
144.7917
289.5850
305.1517
fRO [MHz]
17.525278
24.131944
24.132083
25.429306
0
433.92
868.3
915
1
IF2 = 10.7MHz
RFSEL
fRF [MHz]
315
fIF1 [MHz]
119.2667
158.0667
282.3000
297.8667
fLO1 [MHz]
434.2667
592.8267
586.0000
617.1333
fLO2 [MHz]
108.5667
148.2067
293.0000
308.5667
fRO [MHz]
18.094444
24.701111
24.416667
25.713889
0
1
433.92
868.3
915
2.3 433/868MHz Frequency Diversity
The receiver’s multi-band functionality can be used to operate at two different frequency bands just by
changing the logic level at pin RFSEL and without changing the crystal. This feature is applicable for com-
mon use of the 433 and 868MHz bands. Below table shows the corresponding frequency plans.
IF2 = 455kHz
RFSEL
fRF [MHz]
433.9225
868.3
fIF1 [MHz]
145.2483
289.1300
fLO1 [MHz]
579.17
fLO2 [MHz]
144.7925
289.5850
fRO [MHz]
0
1
24.132083
579.17
39010 71120
Rev. 008
Page 16 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
3
Pin Definitions and Descriptions
Pin No.
Name
I/O Type
Functional Schematic
Description
Vbias
LNAO1
3
LNAO1
analog
output
LNA output 1
Vbias
3
VCC
VEE
LNAI1
1
1
LNAI1
analog
input
LNA input 1
VEE
2
4
VEE
ground
negative supply voltage
MIX1 positive input
Vbias
MIXP
analog
input
VCC
VCC
MIXP
4
MIXN
5
5
6
8
MIXN
analog
input
MIX1 negative input
LNA output 2
VEE
VEE
Vbias
Vbias
LNAO2
6
LNAO2
LNAI2
analog
output
VCC
VEE
LNAI2
8
analog
input
LNA input 2
VEE
7
9
VEE
ground
supply
negative supply voltage
positive supply voltage
mixer 2 output,
VCC
MIXO
VCC
VCC
10
analog
output
about 150Ώ at 10.7MHz
and 670 Ώ at 455kHz, resp.
MIXO
150
(670)
10
350µA
(50µA)
VEE
11
12
VEE
ground
negative supply voltage
IF amplifier positive input
VCC
Vbias
VCC
IFAP
analog
input
IFAP
12
IFAN
13
1.5k
13
IFAN
analog
input
IF amplifier negative input
VEE
VEE
39010 71120
Rev. 008
Page 17 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Pin No.
Name
I/O Type
Functional Schematic
Description
VCC
VCC
14
MODSEL CMOS
input
modulation select input
MODSEL
14
400
VEE
VCC
VEE
VCC
15
SLCSEL
CMOS
input
slicer mode select input
SLCSEL
15
400
VEE
VEE
VCC
VCC
16
17
DF2
DF1
analog
I/O
data filter connection 2
DF2
16
400
VEE
VCC
analog
I/O
data filter connection 1
DF1
17
400
VEE
VCC
VCC
18
19
20
DFO
SLC
PDP
analog
output
data filter output
DFO
18
400
VEE
VCC
analog
input
slicer reference input
SLC
19
400
100k
VEE
VCC
VCC
analog
output
peak detector
positive output
PDP
20
400
VEE
39010 71120
Rev. 008
Page 18 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Pin No.
Name
PDN
I/O Type
Functional Schematic
Description
VCC
21
analog
output
peak detector
negative output
PDN
400
21
VEE
22
23
VCC
supply
positive supply voltage
VCC
CINT
analog
input
capacitor for noise cancella-
tion filter
pin must be connected to
ground if noise cancellation
filter is not used
CINT
23
VEE
VCC
24
RSSI
analog
output
receive signal strength
indication
RSSI
400
24
VEE
VEE
VCC
VCC
25
ROI
analog
input
reference oscillator input
ROI
25
VEE
VEE
26
27
TEST
IFSEL
CMOS
input
not used
connect to ground
test pin
VCC
VCC
CMOS
input
IF select input
IFSEL
27
400
VEE
VEE
VCC
28
CLKO
CMOS
output
clock output
connect pull-up resistor
to activate clock
CLKO
28
VEE
39010 71120
Rev. 008
Page 19 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Pin No.
Name
DTAO
I/O Type
Functional Schematic
Description
VCC
VCC
29
CMOS
output
data output
DTAO
29
220
VEE
VCC
VCC
30
31
32
ENRX
CMOS
input
enable RX mode control
ENRX
400
30
VEE
VCC
VEE
VCC
RFSEL
CMOS
input
receive frequency select
input
RFSEL
31
400
VEE
VEE
VCC
LNASEL
CMOS
input
LNA select input
LNASEL
32
400
VEE
39010 71120
Rev. 008
Page 20 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
4
Technical Data
4.1 Absolute Maximum Ratings
Operation beyond absolute maximum ratings may cause permanent damage of the device.
Parameter
Supply voltage
Symbol
Condition
Min
Max
Unit
VCC
VIN
0
7
VCC +0.3
150
V
V
Input voltage
-0.3
-55
Storage temperature
Junction temperature
Thermal Resistance
Power dissipation
TSTG
TJ
°C
°C
K/W
W
150
RthJA
Pdiss
22
0.12
HBM according to MIL STD
833D, method 3015.7
Electrostatic discharge
VESD
1
kV
4.2 Normal Operating Conditions
Parameter
Supply voltage
Symbol
Condition
Min
Max
Unit
VCC
TA
2.1
-40
5.5
125
V
°C
V
Operating temperature
Input low voltage (CMOS)
Input high voltage (CMOS)
VIL
VIH
ENRX, SEL pins
ENRX, SEL pins
RFSEL=0
0.3*VCC
0.7*VCC
300
610
100
200
0.4
V
470
930
170
310
11
Input frequency range
First IF range
fRF
fIF1
MHz
MHz
RFSEL=1
RFSEL=0
RFSEL=1
Second IF range
fIF2
MHz
MHz
LO1 range (VCO frequency)
fLO1
fLO1 = 24*fREF
400
100
200
16
640
160
320
27
RFSEL=0, fLO2 = fLO1 / 4
RFSEL=1, fLO2 = fLO1 / 2
set by the crystal
fCLK = fREF / 8
LO2 range
fLO2
MHz
XOSC frequency
CLKO frequency
fREF
fCLK
MHz
MHz
kHz
2.0
3.375
10
IFSEL=0
2
FSK deviation
Data rate ASK
∆f
IFSEL=1
10
100
50
bi-phase code
RASK
kbps
kbps
NRZ
100
5
bi-phase code, IFSEL=0
NRZ, IFSEL=0
bi-phase code, IFSEL=1
NRZ, IFSEL=1
10
Data rate FSK
RFSK
50
100
39010 71120
Rev. 008
Page 21 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
4.3 DC Characteristics
all parameters under normal operating conditions, unless otherwise stated;
typical values at TA= 23 °C and VCC = 3 V, all parameters based on test circuits as shown Fig. 10
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Operating Currents
ENRX=0, TA = 85°C
ENRX=0, TA = 125°C
50
200
4
nA
µA
Shutdown current
ISDN
Supply current reference
oscillator
IRO
ENRX=1, t < tonRO
1.5
7.0
mA
mA
ENRX=1, MODSEL= 1
IFSEL=0, SLCSEL=0
LNASEL=0 or 1
Supply current, FSK
IF2= 455kHz
IFSK1
IFSK2
IASK1
IASK2
ENRX=1, MODSEL= 1
IFSEL=1, SLCSEL=0
LNASEL=0 or 1
Supply current, FSK
IF2= 10.7MHz
7.5
6.6
7.1
mA
mA
mA
ENRX= 1, MODSEL= 0
IFSEL=0, SLCSEL=0
LNASEL=0 or 1
Supply current, ASK
IF2= 455kHz
ENRX= 1, MODSEL= 0
IFSEL=1, SLCSEL=0
LNASEL=0 or 1
Supply current, ASK
IF2= 10.7MHz
Digital Pin Characteristics (except of LNASEL)
Input low voltage (CMOS)
Input high voltage (CMOS)
Pull down current ENRX pin
VIL
VIH
ENRX, SEL pins
ENRX, SEL pins
ENRX=1
0.3*VCC
V
V
0.7*VCC
2
IPDEN
8
30
1
µA
Low level input current
ENRX pin
IINLEN
ENRX=0
µA
High level input current
IINHSEL
IINLSEL
SEL pins
SEL pins
1
1
µA
µA
Low level input current
LNASEL Pin Characteristics
Input voltage LNA1 active
Input voltage LNA2 active
DTAO Pin Characteristics
VLNASEL1 ENRX=1
VLNASEL2 ENRX=1
0.1*VCC
0.3*VCC
V
V
0.9*VCC
DTAO pin,
VOL
Output low voltage
Output high voltage
V
V
ISINK = 600µA
DTAO pin,
VOH
0.7*VCC
ISOURCE = 600µA
39010 71120
Rev. 008
Page 22 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
4.4 AC System Characteristics
all parameters under normal operating conditions, unless otherwise stated;
typical values at TA= 23 °C and VCC = 3 V, all parameters based on test circuits as shown Fig. 11
Parameter
Sym-
bol
Condition
Min
Typ
Max
Unit
Receive Characteristics
Input Sensitivity 1)
MODSEL IFSEL
RFSEL
315MHz
433MHz
868MHz
915MHz
315MHz
433MHz
868MHz
915MHz
315MHz
433MHz
868MHz
915MHz
Pmin1
Pmin2
Pmin3
Pmin4
Pmin5
Pmin6
Pmin7
Pmin8
Pmin9
Pmin10
Pmin11
Pmin12
-109
-108
-106
-104
-113
-113
-111
-109
-114
-112
-111
-109
0
FSK
1
0
1
1
0
dBm
dBm
dBm
1
0
1
0
1
wide band
180kHz BW
ASK
narrow band
20kHz BW
FSK
1
Pmax,
FSK
Maximum input signal – FSK
Maximum input signal – ASK
MODSEL=1
-10
-10
dBm
dBm
Pmax,
ASK
MODSEL=0, M>60dB
Spurious emission
Image rejection 1st IF
Image rejection 2nd IF
Pspur
-54
dBm
dB
IR1 w/o SAW filter
IR2
20
25
dB
1) at 4kbps NRZ, BER ≤ 3⋅10-3, peak detector data slicer, LNASEL = 0 or 1
WB: ∆f = 20kHz
NB: ∆f = 5kHz
39010 71120
Rev. 008
Page 23 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Parameter
LNA Parameters
Symbol
Condition
Min
Typ
Max
Unit
depends on external
LC tank
Voltage gain
GLNA
18
dB
Mixer Section Parameters
Mixer output impedance
IFSEL=0
IFSEL=1
1500
330
ZMIXO
GMIX
IIP3
Ω
with CERFIL between
MIXO and IFAP
Voltage conversion gain
25
dB
Input referred 3rd order intercept
point
with CERFIL between
MIXO and IFAP
-40
dBm
IF Amplifier / RSSI
Operating frequency
RSSI usable range
RSSI slope
fIFA
0.4
45
11
60
MHz
dB
DRRSSI
SRSSI
usable, non-linear
20
mV/dB
FSK Demodulator
IFSEL=0
IFSEL=1
IFSEL=0
IFSEL=1
IFSEL=0
IFSEL=1
455
10.7
20
kHz
Input frequency range
fDEM
ꢀfDEM
SDEM
MHz
Carrier acceptance range
Demodulator sensitivity
kHz
400
50
mV/
kHz
5
Baseband Data Path
Data filter bandwidth
BDF
IPKD
depending on CF1,
CF2
100
650
kHz
µA
Peak detector load current
500
350
Start-up Parameters
Reference oscillator
start-up time
depending on crystal
parameters
tonRO
µs
Sequencer time
tSEQ
5504 / fREF
tonRO + tSEQ
200
250
0.6
350
1
µs
Receiver start-up time
tonRX
ms
Frequency Stability
Frequency pulling by supply
voltage
dfVCC
3
ppm/V
39010 71120
Rev. 008
Page 24 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
4.5 External Components
Parameter
Symbol
Condition
Min
Max
Unit
Crystal Parameters
Crystal frequency
Load capacitance
Static capacitance
Series resistance
f0
fundamental mode, AT
16
10
27
15
5
MHz
pF
CL
C0
R1
pF
60
Ω
Noise Cancellation Filter
Integrator capacitor
Clock Output
CF3
depends on data rate
12
50
nF
RCL
CL
Pull-up resistor
600
Ω
Load capacitance
pF
39010 71120
Rev. 008
Page 25 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
5
Test Circuit
5.1 Dual-Channel Application Circuit
•
for antenna-diversity applications
Fig. 10: Dual-channel circuit schematic, peak detectors activated
39010 71120
Rev. 008
Page 26 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
5.1.1 Test Circuit Component List for Figure 10
Value @
Value @
Value @
315 MHz 433.92 MHz 868.3 MHz 915 MHz
Value @
Part Size
Tol.
Description
C3
C4
0603
0603
0603
0603
0603
0805
0603
0603
0603
100 pF
4.7 pF
100 pF
100 pF
100 pF
33 nF
100 pF
3.9 pF
100 pF
100 pF
100 pF
33 nF
100 pF
2.2 pF
100 pF
100 pF
100 pF
33 nF
100 pF
1.5 pF
100 pF
100 pF
100 pF
33 nF
5% LNA input filtering capacitor
LNA output tank capacitor
5%
C5
5% MIX1 positive input matching capacitor
5% MIX1 negative input matching capacitor
C6
C9
LNA input filtering capacitor
10% decoupling capacitor
decoupling capacitor
5%
CB0
CB1
CB2
CB3
330 pF
330 pF
330 pF
330 pF
330 pF
330 pF
330 pF
330 pF
330 pF
330 pF
330 pF
330 pF
10%
10% decoupling capacitor
decoupling capacitor
10%
10%
data low-pass filter capacitor,
for data rate of 4 kbps NRZ
CF1
CF2
0603
0603
680 pF
330 pF
680 pF
330 pF
680 pF
330 pF
680 pF
330 pF
data low-pass filter capacitor,
for data rate of 4 kbps NRZ
10%
10%
value according to the data rate
optional capacitor for noise cancellation
filter
CF3
0603
connected to ground if noise filter not used
CIF
0603
0603
1 nF
1 nF
1 nF
1 nF
10% IFA feedback capacitor
positive PKDET capacitor,
10%
CP1
33 nF
33 nF
33 nF
33 nF
for data rate of 4 kbps NRZ
negative PKDET capacitor,
10%
CP2
CRS
0603
0603
33 nF
33 nF
33 nF
33 nF
for data rate of 4 kbps NRZ
1 nF
1 nF
1 nF
1 nF
10% RSSI output low pass capacitor
100 nF
100 nF
100 nF
100 nF
data slicer capacitor,
10%
CSL
0603
for data rate of 4 kbps NRZ
for averaging detection mode only
CX
L1
L2
L3
0603
0603
0603
0603
27 pF
56 nH
27 nH
56 nH
27 pF
27 nH
15 nH
27 nH
27 pF
0 Ω
27 pF
0 Ω
5% crystal series capacitor
matching inductor
5%
3.9 nH
0 Ω
3.9 nH
0 Ω
5% LNA output tank inductor
5% matching inductor
optional CLK output resistor,
5%
RCL
0603
3.3 kΩ
3.3 kΩ
3.3 kΩ
3.3 kΩ
to clock output signal generated
SMD
3.45x3.1
SFECF10M7HA00 1)
B3dB = 180 kHz
IF2=10.7MHz
IF2=455kHz
IF2=10.7MHz
IF2=455kHz
ceramic filter
from Murata,
or equivalent part
CER
FIL
SMD
6.5x6.0
CFUKG455KD4A
B6dB = 20 kHz
18.094444
MHz
24.701111
MHz
24.416667
MHz
25.713889
MHz
fundamental-mode
crystal from Telcona,
or equivalent part
SMD
5x3.2
17.525278
MHz
24.131944
MHz
24.132083
MHz
25.429306
MHz
XTAL
20ppm cal., 30ppm temp.
Note 1): SFECF10M7HA00 for -20 to 80˚C
SFECF10M7HA00S0 for -40 to 125˚C
39010 71120
Rev. 008
Page 27 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
6
Package Description
The device MLX71120 is RoHS compliant.
Fig 11: 32L QFN 5x5 Quad
all Dimension in mm
D
E
D2
E2
A
A1
A3
L
e
b
min
4.75
5.25
4.75
5.25
3.00
3.25
3.00
3.25
0.80
1.00
0
0.3
0.5
0.18
0.30
0.20
0.50
max
0.05
all Dimension in inch
min
0.187
0.207
0.187
0.207
0.118
0.128
0.118 0.0315
0
0.0118
0.0197
0.0071
0.0118
0.0079
0.0197
max
0.128 0.0393 0.002
6.1 Soldering Information
•
The device MLX71120 is qualified for MSL3 with soldering peak temperature 260 deg C
according to JEDEC J-STD-20.
39010 71120
Rev. 008
Page 28 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
7
Standard information regarding manufacturability of Melexis
products with different soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitiv-
ity level according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
•
IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
•
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
•
EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Iron Soldering THD’s (Through Hole Devices)
•
EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
EIA/JEDEC JESD22-B102 and EN60749-21
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak tempera-
ture, temperature gradient, temperature profile etc) additional classification and qualification tests have to be
agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more in-
formation on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of
the use of certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality.aspx
8
ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
39010 71120
Rev. 008
Page 29 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
Your Notes
39010 71120
Rev. 008
Page 30 of 31
Data Sheet
Jun/12
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
9
Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the infor-
mation set forth herein or regarding the freedom of the described devices from patent infringement. Melexis
reserves the right to change specifications and prices at any time and without notice. Therefore, prior to de-
signing this product into a system, it is necessary to check with Melexis for current information. This product
is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or
life-sustaining equipment are specifically not recommended without additional processing by Melexis for
each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical
data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering
of technical or other services.
© 2012 Melexis NV. All rights reserved.
For the latest version of this document, go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe, Africa, Asia:
Phone: +32 1367 0495
E-mail: sales_europe@melexis.com
America:
Phone: +1 248 306 5400
E-mail: sales_usa@melexis.com
ISO/TS 16949 and ISO14001 Certified
39010 71120
Rev. 008
Page 31 of 31
Data Sheet
Jun/12
相关型号：
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