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MLX75123

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品牌：MELEXIS
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MLX75123 概述

MLX75123 数据手册

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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Features & Benefits  
Description  
.
.
.
Combines four high speed ADCs with a  
digital sensor control for Melexis’ TOF  
camera sensors  
Integrated light source control with  
modulation frequencies between  
12-40 MHz  
Programmable modulation frequencies to  
avoid module to module crosstalk  
Up to 8 raw phases per frame  
Pre-processed difference & sum output  
modes to reduce the data bandwidth  
Continuous or triggered operation modes  
Configurable over I2C up to 400kHz  
12-bit parallel camera interface up to  
80Mpix/s  
Region of interest (ROI) selection  
Horizontal & vertical flip/mirror modes  
Per-phase statistics & diagnostics  
Ambient operating temperature ranges  
of -20 +85°C and -40 +105°C  
MLX75123 is a fully integrated companion chip for  
Melexis’ Time-of-Flight (TOF) sensors. It’s perfectly  
suited for automotive and non-automotive  
applications, including, but not limited to, gesture  
recognition, driver monitoring, skeleton tracking,  
people or obstacle detection and traffic monitoring.  
This sensor interface is designed to connect  
instinctively to any Melexis TOF sensor and the  
output can be directly connected to a camera  
parallel port and I2C interface of a microcontroller.  
The chip features a configurable sequencer to  
control the TOF sensor and will sequentially provide  
the 12-bit output data from its four built-in high-  
speed ADCs for an accurate analog to digital  
conversion. Furthermore, MLX75123 synchronously  
provides the control signals for a modulated light  
source (LED or laser based). Combined with a TOF  
sensor like MLX75023, the MLX75123 offers a cost-  
effective, integrated, QVGA (320x240) pixel  
resolution camera solution. This chipset can deliver  
raw TOF data up to 600 frames per second. The  
device is available in a compact 7x7mm AQFN  
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AEC-Q100 qualification available!  
package and offers  
possibilities.  
a
variety of integration  
Figure 1: MLX75123 package  
 
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Contents  
Features & Benefits................................................................................................................................... 1  
Description................................................................................................................................................ 1  
1. Datasheet Changelog............................................................................................................................. 4  
2. Ordering Information ............................................................................................................................ 5  
3. Application System Architecture............................................................................................................ 6  
4. System Block Diagram ........................................................................................................................... 7  
5. Pinout Description................................................................................................................................. 8  
6. Absolute Maximum Ratings1................................................................................................................ 10  
7. Electrical Specifications ....................................................................................................................... 10  
7.1. Crystal Oscillator Requirements.......................................................................................................10  
7.2. Operating Conditions........................................................................................................................11  
7.3. ADC Characteristics...........................................................................................................................13  
8. Power Consumption............................................................................................................................ 14  
8.1. Power Up & Down Sequence ...........................................................................................................14  
9. Output Modes..................................................................................................................................... 15  
9.1. Mode #0 : 11bit (A-B)/4 + 1bit statistics..........................................................................................15  
9.2. Mode #1 : 12bit (A-B)/2....................................................................................................................15  
9.3. Mode #2 : 11bit (A+B)/4 + 1bit statistics.........................................................................................15  
9.4. Mode #3 : 12bit (A+B)/2...................................................................................................................15  
9.5. Mode #4 : 12bit A .............................................................................................................................16  
9.6. Mode #5 : 12bit B .............................................................................................................................16  
10. Parallel Output Sequence & Timing................................................................................................... 17  
11. Distance Calculation .......................................................................................................................... 18  
12. I2C Commands .................................................................................................................................. 19  
12.1. I2C_READ .........................................................................................................................................19  
12.2. I2C_WRITE .......................................................................................................................................19  
12.3. I2C_RESET ........................................................................................................................................20  
12.4. I2C_GLOBAL_RESET.........................................................................................................................20  
12.5. I2C_SAVEREGMAP...........................................................................................................................20  
13. Registers............................................................................................................................................ 21  
13.1. Configuration Parameters Registers..............................................................................................22  
13.2. FrameTable & Phase Registers.......................................................................................................25  
13.2.1. Frame : Tx_SETTINGS ...............................................................................................................26  
Version V1.2  
Page 2 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.2. Frame : Tx_IDLETIME................................................................................................................27  
13.2.3. Frame : Tx_MODE.....................................................................................................................28  
13.2.4. Frame : Tx_FRAMECOUNT .......................................................................................................29  
13.2.5. Frame : Tx_UPPER_LIMIT .........................................................................................................29  
13.2.6. Frame : Tx_LOWER_LIMIT........................................................................................................29  
13.2.7. Frame : Tx_ROI_START & Tx_ROI_SIZE....................................................................................30  
13.2.8. Phase : Tx_Py_SETTINGS ..........................................................................................................31  
13.2.9. Phase : Tx_Py_INTEGRATION...................................................................................................32  
13.2.10. Phase : Tx_Py_PREHEAT.........................................................................................................33  
13.2.11. Phase : Tx_Py_PREMIX ...........................................................................................................34  
13.2.12. Phase : Tx_Py_IDLE.................................................................................................................35  
13.2.13. Phase : Tx_Py_SETUP .............................................................................................................35  
13.3. USER Registers ................................................................................................................................36  
14. MetaData .......................................................................................................................................... 37  
15. Diagnostics ........................................................................................................................................ 42  
16. Sleep Mode(s) ................................................................................................................................... 43  
17. FMOD Generator............................................................................................................................... 44  
18. AQFN Package Dimensions................................................................................................................ 45  
19. Layout & Solder Recommendations................................................................................................... 46  
19.1. PCB Footprint Design.....................................................................................................................46  
19.2. Reflow Solder Profile ......................................................................................................................47  
Disclaimer................................................................................................................................................ 48  
Version V1.2  
Page 3 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
1. Datasheet Changelog  
Version  
Date  
Changes  
1.0  
1.1  
17.01.2017  
11.04.2017  
Initial version  
Updated section 13.3 : USER[0..3] are visible in Metadata1, not MetaData2  
Updated section 7.1 : Clock thresholds depend on VDDD_1V8, not VDD_IO  
Updated section 13.1 : VIDEO_DRIVE has 2 options (low & high), not 16  
Updated default register values in section 13  
Added and updated electrical operating conditions in section 7.2  
Updated the power consumption values in section 8  
Changed BLOCK_ENABLE register to BLOCK_DISABLE in section 16  
1.2  
02.08.2017 Added LEDP specifications for single ended mode  
Updated description of parameters in section 7.2  
Updated default register values in section 13  
Minor updates to register descriptions  
Table 1 : Datasheet changelog  
Version V1.2  
Page 4 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
2. Ordering Information  
Product  
Temperature Code  
Package  
Option Code  
Packing Form  
MLX75123  
MLX75123  
R
S
LA  
LA  
AAA-000  
AAA-000  
RE  
RE  
Table 2 : Order code(s)  
Legend:  
Temperature Code  
R : -40°C to 105°C  
S : -20°C to 85°C  
Package Code  
Option Code  
LA : Array QFN package, 84pins  
AAA-000 : Default product configuration  
RE : Reel  
Packing Form  
Ordering Example  
MLX75123RLA-AAA-000-RE  
Table 3  
Version V1.2  
Page 5 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
3. Application System Architecture  
A complete TOF system or camera module typically includes the following main components :  
.
.
.
.
.
MLX75123 + MLX75023 TOF chipset  
A synchronized high bandwidth near infrared (NIR) active illumination source (LED or laser)  
Beam shaping optics for the light distribution  
A receiving sensor lens, optimized for maximum NIR transmittance  
A microprocessor (like Freescale i.MX6 or equivalent) to calculate and process the data  
S
A
I
B
Y
A
H
R
3
X
I
R
A
Memory  
V
M
3
3
8
V
V
3
CLK  
1
Receiving  
optics  
I2C  
TOF Sensor  
MLX750xx  
TOF CC  
MLX75123  
Digital Control  
Analog Data  
Microcontroller  
or  
DSP  
Digital Data  
LEDP  
Scene  
Illum. Driver  
LEDN  
LED / VCSEL  
Illumination  
Beam shaping  
optics  
Figure 2  
Version V1.2  
Page 6 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
4. System Block Diagram  
1V8  
3V3  
Registers  
Memory  
POR  
I2C  
SDA, SCL  
RSTB  
LEDP, LEDN  
LED Control  
Mix Control  
DMIX[1], DMIX[0]  
Timing  
Generator  
SHUT  
CLK  
FLUSH  
Sequencer  
ARRAY_RST  
QUIET  
TRIGGER  
PIXD [11:0]  
LATCH_EN  
ROW [7:0]  
COL [7:0]  
HSYNC, VSYNC, FSYNC  
PIXCLK  
Delay line  
Data  
process  
A_IN[0]  
A_IN[1]  
A_IN[2]  
A_IN[3]  
ADC  
ADC  
ADC  
ADC  
GND  
Figure 3 : System block diagram  
Version V1.2  
Page 7 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
5. Pinout Description  
Designator  
Pin #  
Function  
Description  
Domain  
PIXCLK 1  
HSYNC 1  
VSYNC 1  
FSYNC 1  
B28  
B29  
A32  
A31  
Digital Out  
Digital Out  
Digital Out  
Digital Out  
Pixel clock  
VDD_IO  
VDD_IO  
VDD_IO  
VDD_IO  
Horizontal sync bit  
Vertical sync bit  
Frame sync bit  
PIXD[11]  
PIXD[10]  
PIXD[9]  
PIXD[8]  
PIXD[7]  
PIXD[6]  
PIXD[5]  
PIXD[4]  
PIXD[3]  
PIXD[2]  
PIXD[1]  
PIXD[0]  
B22  
A25  
B23  
A26  
B24  
A27  
B25  
A28  
B26  
A29  
B27  
A30  
Digital Out  
Pixel data  
VDD_IO  
QUIET  
CLK  
A15  
B13  
A13  
A14  
Digital Out  
Digital In  
Digital In  
Digital In  
Configurable indication output  
Input clock  
VDD_IO  
VDD_IO  
VDD_IO  
VDD_IO  
TRIGGER  
RSTB  
Frame trigger  
Reset pin (= active high)  
SDA  
SCL  
B11  
A12  
Digital Out  
Digital In  
I2C pins  
VDD_I2C  
VDDD_3V3  
VDDD_3V3  
LEDP  
LEDN  
B31  
A34  
Digital Out  
Digital Out  
Single ended or differential LED control signals  
Differential pixel modulation signals  
DMIX[1] 1  
B32  
A35  
DMIX[0] 1  
LATCH_EN  
SHUT  
A4  
B2  
A3  
B3  
Digital Out  
Digital Out  
Digital Out  
Digital Out  
Pixel array latch enable  
Pixel array shutter  
VDDD_3V3  
VDDD_3V3  
VDDD_3V3  
VDDD_3V3  
ARRAY_RST  
FLUSH  
Pixel array reset signal  
Pixel array flush output  
ROW[7]  
ROW[6]  
ROW[5]  
ROW[4]  
ROW[3]  
ROW[2]  
ROW[1]  
ROW[0]  
A2  
B1  
A1  
A44  
B40  
A43  
B39  
A42  
Digital Out  
Digital Out  
Row addressing  
VDDD_3V3  
VDDD_3V3  
COL[7]  
COL[6]  
COL[5]  
COL[4]  
COL[3]  
COL[2]  
COL[1]  
COL[0]  
A37  
B34  
A38  
B35  
A39  
B36  
A40  
B37  
Column addressing  
Table 4.1  
1 can be selected as active high or active low  
Version V1.2  
Page 8 of 48  
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Designator  
Pin #  
Function  
Description  
Domain  
A_IN[3]  
A_IN[2]  
A_IN[1]  
A_IN[0]  
B7  
A7  
A6  
B6  
Analog In  
Analog input of the pixel data  
VDDA_1V8  
B14  
1V8 Supply  
1V8 Supply  
Analog supply in the 1.8V domain for the PLL  
A9  
B5  
Analog supply for the ADC in the 1.8V  
analog domain  
VDDA_ADC_1V8  
Analog supply for the ADC in 1.8V  
analog domain for switched circuitry  
VDDA_ADC_S_1V8  
VDDD_1V8  
A10  
B20  
B4  
1V8 Supply  
1V8 Supply  
3V3 Supply  
Digital supply in 1.8V digital domain  
Analog supply for the ADC in the 3.3V  
analog domain  
VDDA_3V3  
A36  
B17  
B38  
Digital supply in 3.3V digital domain for the interface with  
the 75023  
VDDD_3V3  
3V3 Supply  
B21  
B30  
Supply pin for interface to application processor  
(1.8 or 3.3V)  
VDD_IO  
Supply  
VDD_I2C  
B12  
A16  
Supply  
GND  
1.8 or 3.3V supply for I2C interface  
GNDA_1V8  
Analog ground in the 1.8V domain for the PLL  
A5  
B8  
GNDA_ADC_1V8  
GND  
Analog ADC ground for 1.8V  
Analog ADC ground for the ADC in 1.8V analog domain  
switched  
GNDA_ADC_S_1V8  
GNDD_1V8  
B9  
GND  
GND  
A22  
Digital ground in 1.8V digital domain  
A8  
B15  
A18  
A24  
A33  
B33  
A41  
GND_IO  
GND  
GND  
Digital ground for the interface to application processor  
TEST[6]  
TEST[5]  
TEST[4]  
TEST[3]  
TEST[2]  
TEST[1]  
TEST[0]  
B10  
A11  
B16  
A17  
B18  
B19  
A21  
Test pins reserved for Melexis purposes,  
advised to connect to GND_IO  
A19  
A20  
A23  
n.c.  
not connected  
Table 4.2  
Version V1.2  
Page 9 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
6. Absolute Maximum Ratings1  
Parameter  
Min.  
Typ.  
Max.1  
Unit  
3V3 supply voltage :  
VDDA_3V3, VDDD_3V3, VDD_IO, VDD_I2C  
-0.2  
4
V
1V8 supply voltage :  
VDDA_1V8, VDDA_ADC_1V8,  
VDDA_ADC_S_1V8, VDDD_1V8  
-0.2  
-0.2  
2.3  
V
V
Analog input voltage  
A_IN[3], A_IN[2], A_IN[1], A_IN[0]  
VDDA_3V3 + 0.2  
Digital IO voltage for MLX75023 :  
COL[x], ROW[x], DMIX[x], LATCH_EN,  
SHUT, ARRAY_RST, FLUSH  
-0.2  
-0.2  
-0.2  
VDDD_3V3 + 0.2  
VDD_I2C + 0.2  
VDD_IO + 0.2  
V
V
V
Digital IO voltage I2C  
Digital IO voltage for video Interface :  
HSYNC, VSYNC, FSYNC, PIXCLK, PIXD[x],  
CLK, TRIGGER, RSTB  
Operating junction temperature  
Storage temperature  
-40  
-40  
125  
150  
2
°C  
°C  
kV  
ESD : Human Body Model  
Table 5 : Absolute Maximum Ratings  
Note 1 : Absolute maximum ratings should never be exceeded to avoid permanent hardware failure.  
7. Electrical Specifications  
7.1. Crystal Oscillator Requirements  
The clock input requires an accurate and clean input signal. It’s recommended to use a crystal oscillator with the following  
specifications towards this purpose. The clock input thresholds are determined by VDDD_1V8, however the ESD protection  
circuit limits the amplitude to VDD_IO+0.2V as defined in Table 5. Oscillator drift is a less significant parameter and will not  
impact MLX75123 behaviour because all timing related parameters scale directly with this clock.  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Clock frequency  
Positive clock threshold  
Negative clock threshold  
Jitter  
40  
1
80  
MHz  
V
VTH+  
VTH-  
0.6  
60  
V
30  
ps  
Table 6 : Input clock requirements  
Version V1.2  
Page 10 of 48  
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
7.2. Operating Conditions  
The operation conditions of MLX75123 are highly dependent on the configuration of the device.  
Values listed in the Table 7 are measured at typical application conditions1 :  
.
.
.
.
.
.
80 MHz input clock  
20 MHz modulation frequency  
250 us integration time  
Four phase acquisition  
50 distance FPS (= 200 raw frames)  
± 5pF load on all output buffers  
Typ.  
Typ.  
Typ.  
Max.6  
Parameter  
Min.  
Peak3  
Unit  
-40 °C2 25 °C2 105 °C2  
1V8 analog supply voltage  
VDDA_1V8 supply current  
VDDA_ADC_1V8 supply current 3  
VDDA_ADC_S_1V8 supply current 3  
1.7  
1.8  
4.57  
39.60  
9.58  
1.8  
2
V
4.52  
4.45  
46.39  
11.05  
mA  
mA  
mA  
tbd  
tbd  
tbd  
42.44  
10.25  
221  
58  
1V8 digital supply voltage  
VDDD_1V8 supply current  
1.7  
1.8  
8.5  
1.8  
1.8  
2
V
8.61  
n/A 4  
8.84  
mA  
mA  
mA  
tbd  
tbd  
tbd  
VDDD_I2C supply current @1V8  
VDDD_IO supply current @1V8 3, 5  
16  
16.18  
16.43  
3.3  
39  
3V3 analog supply voltage  
VDDA_3V3 supply current  
3
3
3.3  
3.3  
3.6  
V
0.001  
mA  
tbd  
3V3 digital supply voltage  
VDDD_3V3 supply current 3  
3.3  
3.3  
3.3  
3.6  
tbd  
tbd  
tbd  
V
1.29  
1.28  
n/A 4  
1.29  
7.85  
37  
mA  
mA  
mA  
VDDD_I2C supply current @3V3  
VDDD_IO supply current @3V3 3, 5  
37.09  
36.47  
37.34  
Table 7 : Power requirements  
Note 1 : A power calculator that simulates the power consumption at different application parameters is available on request  
Note 2 : Temperatures listed in Table 7 are ambient temperatures  
Note 3 : Some power domains only work for a specific time (for example during sensor read out). The overall (or average)  
power consumption thus depends on the duty cycle of that domain, but the peak current determines the power supply  
requirements and decouple techniques. Please refer to chapter 14 for more information.  
Note 4 : The power consumption of VDDD_I2C depends on the amount of communication between MLX75123 and the host  
controller. When the device is only initialized once at start up no further power will be consumed.  
Note 5 : The average power consumption of VDDD_IO depends on the actual data content that is being transmitted.  
Values in Table 7 are considered worst case conditions because in our setup the PIXD lines are toggling heavily.  
Note 6 : The max. current consumption measured at the max. supply voltage incl. process & temperature variation for typical  
application conditions.  
Version V1.2  
Page 11 of 48  
 
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Parameter  
VDDD_1V8  
power on reset (POR)  
Min.  
1.3 - 1.45  
100  
Max.  
Unit  
V
1.45 - 1.55  
POR on/off hysteresis  
mV  
Table 8 : Power on reset behaviour  
When VDDD_1V8 drops under its lower threshold the device will reset. To avoid unwanted behaviour on noisy power  
supplies the device will only turn on again when VDDD_1V8 reaches its upper threshold voltage level.  
A hysteresis of min. 100mV over temperature variation is guaranteed.  
Parameter  
Symbol  
JA  
Min.  
Typ.  
22.18  
1.19  
3
Max.  
Unit  
°C/W  
°C/W  
Junction to ambient thermal resistance  
Junction to package resistance 1  
Moisture sensitivity level (MSL) 2  
JC, JB  
Table 9 : Package thermal behaviour  
Note 1 : For an AQFN package incl. thermal pad the thermal resistance junction-board is equal to resistance junction-package  
Note 2 : According to IPC/JEDEC J-STD-020E moisture/reflow sensitivity classification  
Parameter  
Modulation frequency  
Min.  
12  
Typ.  
50  
Max.  
40  
Unit  
MHz  
%
Modulation frequency duty cycle  
Modulation frequency phase accuracy  
Modulation frequency settling time  
12.5  
87.5  
1
%
20  
100  
us  
Table 10 : Modulation frequency parameters  
Parameter  
Min.  
Typ. Max. Unit  
Input frequency clock (FIN)  
Pixel clock frequency (PIXCLK)  
I2C frequency (SCL)  
40  
80  
Fin  
80  
MHz  
MHz  
kHz  
20  
3
400  
I2C sink strength (SDA)  
mA  
VDD_IO buffer sink strength 3  
(measured @ 200mV)  
VDD_IO buffer source strength 3  
(measured @ VDD_IO - 200mV)  
8.2  
17.2  
23.8  
26.9  
17  
118  
40  
mA  
mA  
mA  
mA  
5.03  
16.2  
10.6  
VDDD_3V3 buffer sink strength  
(measured @ 200mV)  
37.2  
24.8  
VDDD_3V3 buffer source strength  
(measured @ VDD_3V3 - 200mV)  
Table 11 : IO interface description  
Note 3 : Measured at VDD_IO = 1V8, the values depend on the selection of VIDEO_DRIVE .  
VIDEO_DRIVE can be selected in register CONFIG (0x1004) as explained in section 13.1.  
Typical values are with VIDEO_DRIVE at low drive strength, max. values are for high VIDEO_DRIVE setting.  
Version V1.2  
Page 12 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Parameter  
LVDS mode : recommended load impedance  
Min.  
Typ.  
100  
3.5  
Max.  
Unit  
Ohm  
mA  
V
LVDS mode : output current  
LVDS mode : common mode voltage  
1.2  
Single ended mode :  
LEDP buffer sink strength  
(measured @ 200mV)  
16.2  
10.6  
26.9  
17  
37.2  
24.8  
mA  
mA  
Single ended mode :  
LEDP buffer source strength  
(measured @ VDD_3V3 - 200mV)  
Table 12 : LED_P & LED_N electrical description  
7.3. ADC Characteristics  
MLX75123 has four single, general purpose analog to digital converters. All ADCs are used in a single ended configuration  
and independently from each other convert one analog output from MLX75023. Each pipelined ADC consists of a  
concurrently operating series of stages, isolated by a sample-hold buffer. For sampling rates > 25 MSPS it is needed to  
optimize the sample point with register ADC_DELAY_FT as explained in section 13.1  
Parameter  
ADC resolution  
Min.  
Typ.  
12  
Max.  
Unit  
bit  
ADC input range  
0.2  
20  
1.9  
40  
V
ADC sampling rate  
Fin/2  
500  
2
MSPS  
uV/LSB  
%
ADC conversion gain  
ADC to ADC gain mismatch  
Analog input capacitance DC  
ADC delay line number of steps  
ADC delay line step size  
5
3
5
pF  
32  
1
ns  
Table 13 : ADC Characteristics  
Version V1.2  
Page 13 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
8. Power Consumption  
MLX75123 requires eight different voltage domains, each to be connected to either 1V8 or 3V3.  
An overview of the different types can be found here:  
Supply Domain  
Voltage (V)  
Power (mW)  
VDDA_1V8  
VDDA_ADC_1V8  
VDDA_ADC_S_1V8  
VDDD_1V8  
1.8  
1.8  
8.12  
77.05  
18.53  
15.57  
29.16  
n/A  
1.8  
1.8  
VDD_IO (at 1V8)  
VDD_I2C  
1.8  
3.3  
VDDA_3V3  
3.3  
0.01  
VDDD_3V3  
3.3  
4.24  
153 mW 1  
TOTAL  
Table 14 : Typical power consumption  
Note 1 : Calculations are based on typical application parameters listed in chapter 11.  
Note 1 : Calculations are based on the average power consumption of each domain incl. temperature variation  
VDD_I2C and VDD_IO can be connected to 1V8 or 3V3 depending on the microprocessor. For EMC performance and a  
reduction in power consumption we suggest to connect both domains to 1V8.  
We recommend to use independent regulators on each supply, however if from system point of view this is not desirable  
one could consider three regulators only. In this scenario we suggest to connect certain domains to each other with good  
decoupling techniques.  
1V8 : VDDD_1V8, VDD_IO, VDD_I2C  
1V8_Clean : VDDA_1V8, VDDA_ADC_1V8, VDDA_ADC_S_1V8  
3V3 : VDDA_3V3, VDDD_3V3  
In combination with MLX75023 or MLX75024 an extra MIXH regulator, 3V3_clean and negative ARRAYBIAS supply is  
required.  
8.1. Power Up & Down Sequence  
To guarantee a proper operation of MLX75123 it’s considered mandatory to apply 1V8 prior to the 3V3 supply voltage.  
Reversely it’s also recommended to disconnect 3V3 before 1V8 on power down. Both conditions are visualized in this graph.  
It’s important to keep both supplies within 500mV (V) range of each other during start-up and power down sequences.  
When 1V8 ramps up too fast, compared to 3V3, a diode will be reversed biased which could lead to HW damage,  
if 3V3 ramps up too fast, compared to 1V8, internal circuitry could be destroyed because of undefined currents.  
VDDD_3V3  
3.3V  
1.8V  
VDDD_1V8  
V  
V  
time  
Figure 4 : Voltage domains startup sequence  
Version V1.2  
Page 14 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
9. Output Modes  
One Depthsensepixel has two outputs, known as tap A and tap B, each in counterphase of one other. To reduce the  
calculation time from raw to depth information the data output already combines the information from both taps, either as  
a sum, or as a subtraction.  
MLX75123 has six different data output modes. The output mode can be changed via register Tx_Py_Settings as described in  
section 13.2.8 and can change per phase.  
Each pixel output A or B is a 12 bit value in range of 0 - 4095. The statistics bit in Mode #0 and Mode #2 is used to indicate if  
this pixel value before the sum or subtraction of A, or B, is between Tx_UPPER_LIMIT and Tx_LOWER_LIMIT thresholds as  
defined in the registers in section 13.2.5 and 13.2.6. If both tap A and tap B are between these limits this statistics bit will be  
high, if one of these outputs fails these criteria it will be set to 0. The MLX75023 test rows and ADC test row are not part of  
these statistics, for these pixels the statistics bit is always 1.  
9.1. Mode #0 : 11bit (A-B)/4 + 1bit statistics  
PIXD[11] PIXD[10] PIXD[9] PIXD[8] PIXD[7] PIXD[6] PIXD[5] PIXD[4] PIXD[3] PIXD[2] PIXD[1] PIXD[0]  
1bit  
11bit (A-B)/4 pixel data  
Statistic  
The 13bit subtraction result of A-B should be truncated to a 11bit value which corresponds to (A-B)/4 in the range of  
-1024 - 1023. This 11bit value is signed.  
9.2. Mode #1 : 12bit (A-B)/2  
PIXD[11] PIXD[10] PIXD[9] PIXD[8] PIXD[7] PIXD[6] PIXD[5] PIXD[4] PIXD[3] PIXD[2] PIXD[1] PIXD[0]  
12bit (A-B)/2 pixel data  
9.3. Mode #2 : 11bit (A+B)/4 + 1bit statistics  
PIXD[11] PIXD[10] PIXD[9] PIXD[8] PIXD[7] PIXD[6] PIXD[5] PIXD[4] PIXD[3] PIXD[2] PIXD[1] PIXD[0]  
1bit  
11bit (A+B)/4 pixel data  
Statistic  
The 13 bit result of this sum should be truncated to a 11bit value which corresponds to (A+B)/4 in range of 0 - 2047.  
9.4. Mode #3 : 12bit (A+B)/2  
PIXD[11] PIXD[10] PIXD[9] PIXD[8] PIXD[7] PIXD[6] PIXD[5] PIXD[4] PIXD[3] PIXD[2] PIXD[1] PIXD[0]  
12bit (A+B)/2 pixel data  
Version V1.2  
Page 15 of 48  
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
9.5. Mode #4 : 12bit A  
PIXD[11] PIXD[10] PIXD[9] PIXD[8] PIXD[7] PIXD[6] PIXD[5] PIXD[4] PIXD[3] PIXD[2] PIXD[1] PIXD[0]  
12bit A pixel data  
9.6. Mode #5 : 12bit B  
PIXD[11] PIXD[10] PIXD[9] PIXD[8] PIXD[7] PIXD[6] PIXD[5] PIXD[4] PIXD[3] PIXD[2] PIXD[1] PIXD[0]  
12bit B pixel data  
Version V1.2  
Page 16 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
10. Parallel Output Sequence & Timing  
The complete output data interface consists out of 16 parallel lines:  
.
.
.
.
.
1 bit PIXCLK uses same frequency as input CLK  
1 bit FSYNC indicates start of a frame (one pulse per frame start)  
1 bit VSYNC indicates start of a phase (one pulse per phase start)  
1 bit HSYNC indicates start of a row (one pulse for each row start)  
12 bit pixel data PIXD[11:0]  
Figure 5: FSYNC, VSYNC & HSYNC timing diagram  
The sequential pixel output per row when used in combination with MLX75023 looks like 0, 8, 1, 9, … 310, 318, 311, 319.  
This means that the pixels should be re-ordered on the microcontroller to reconstruct a presentable distance map.  
This pixel re-ordering can be done on the individual phase data or on the calculated distance map.  
The serial output order can be simulated with this Matlab example code:  
for x = 0:1:159  
y = mod(x,8) + 16*floor(x/8);  
z = mod(x,8) + 16*floor(x/8) + 8;  
fprintf('%d, %d, ', y, z);  
end  
On a timing diagram, without ROI, it would look like :  
md0, md1, md2, md3, … = MetaData  
p0, p8, p1, p9, … , p319 = PixelData / row  
During a phase the maximum # of rows is limited to 251, depending on the features that are enabled or disabled.  
0
46  
83  
0
316 317 318 319  
0 0 0 0 0 0 0  
MetaData1*  
0
1
0
0
0
MLX75023 Row1  
MLX75023 Row2  
MLX75023 Row3  
…
.
.
.
.
.
1x MetaData1 line  
240x Pixel array data  
8x MLX75023 Test Rows  
1x ADC Test Row  
1x MetaData2 line  
240  
241  
MLX75023 Row240  
MLX75023 Test Rows  
248  
249  
250  
ADC Test Row  
MetaData2*  
0
0
0
0
0
0
0
Version V1.2  
Page 17 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
11. Distance Calculation  
The distance data per pixel in mm can be calculated by the following formulas.  
ꢐ
ꢐ
ꢈ
 ꢀꢁꢂꢃꢄꢅꢆꢀꢇꢈꢉꢂꢊꢉꢋꢂꢊꢄꢌꢉꢍꢂꢄꢇꢂꢎꢄꢍꢍꢄꢎꢉꢆꢋꢉ ꢏꢂ  
ꢒ
ꢒ
ꢒ ꢘ ꢒ ꢐꢕꢕꢕ  
ꢑ ꢓꢔꢕ ꢖꢎꢗꢃ  
where  
ꢎ
ꢈ ꢏ ꢅꢊꢉꢉꢃꢂꢗꢙꢂꢍꢄꢚꢛꢆ ꢏ ꢑꢜꢜꢂꢝꢜꢑꢂꢞꢟꢠꢂ  
ꢅ
ꢖꢎꢗꢃ ꢏ ꢡꢗꢃꢢꢍꢀꢆꢄꢗꢇꢂꢙꢋꢉꢣꢢꢉꢇꢈꢤꢂꢄꢇꢂꢥꢦ  
(
)
)
ꢜꢕ ꢒ ꢐ ꢧ ꢌ ꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢄꢙꢂꢤꢂ ꢨ ꢕ  
ꢘ ꢏꢂ{  
(
ꢜꢕ ꢒ ꢓ ꢩ ꢌ ꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢄꢙꢂꢤꢂ ꢪ ꢕ  
and ꢌꢫ ꢤ are averaged quadrature values calculated as  
ꢌ ꢏꢂ  
ꢬꢭꢮ  
ꢬꢭꢰ  
ꢧ
ꢑ ꢒ ꢯꢭꢮ ꢑ ꢒ ꢯꢭꢰ  
ꢱꢭꢮ ꢱꢭꢰ  
ꢤ ꢏꢂ  
ꢧ
ꢑ ꢒ ꢯꢭꢮ ꢑ ꢒ ꢯꢭꢰ  
with  
ꢬꢭꢮ ꢏ ꢲꢥꢐꢭꢮ ꢧ ꢲꢥꢐꢭꢰ  
ꢬꢭꢰ ꢏ ꢲꢥꢓꢭꢮ ꢧ ꢲꢥꢓꢭꢰ  
ꢱꢭꢮ ꢏ ꢲꢥꢞꢭꢮ ꢧ ꢲꢥꢞꢭꢰ  
ꢱꢭꢰ ꢏ ꢲꢥꢑꢭꢮ ꢧ ꢲꢥꢑꢭꢰ  
where ꢲꢥꢌꢭꢮꢂꢳꢂꢲꢥꢌꢭꢰ are the differential output values of output A and output B,  
and ꢌ is the typical phase shift (0,90,180 or 270)  
ꢲꢥꢌꢭꢮ ꢧ ꢲꢥꢌꢭꢰ values are available directly as output in 12bit (A-B) mode.  
|
|
|
|
ꢯꢭꢮ ꢏ ꢬꢭꢮ ꢩ ꢱꢭꢮ  
|
|
|
|
ꢯꢭꢰ ꢏ ꢬꢭꢰ ꢩ ꢱꢭꢰ  
and  
ꢴꢗꢇꢙꢄꢃꢉꢇꢈꢉꢂꢊꢉꢋꢂꢊꢄꢌꢉꢍ ꢏ ꢯꢭꢮꢂ ꢩ ꢂꢯꢭꢰ  
Version V1.2  
Page 18 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
12. I2C Commands  
MLX75123 features a standard (up to 400kHz) inter-integrated circuit communication interface, also known as I2C.  
This device acts as a I2C slave with address 0x0067. This address can be reprogrammed via register I2C_ADDRESS.  
More information on custom I2C addresses can be found in chapter 13.1 .  
The size of both the register addresses & register data is 16bit.  
I2C follows a strict timing sequence, the master device will initiate all communication, it’s in control of the SCL line, data will  
be transmitted via SDA line. Each slave monitors the I2C bus and will respond to the master when needed.  
The following sections describe these timings for each of the individual commands.  
Legend :  
AK  
NK  
R
SDA  
SCL  
SDA  
SCL  
SDA = 0  
SDA = 1  
SDA = 1  
SDA = 0  
S
Sr  
W
P
12.1. I2C_READ  
This command allows you to read the registers listed in chapter 13. Normally it will read 1x register only, but the slave will  
continue to transmit data of sequential register addresses until the master terminates the communication.  
#bit  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27  
Master  
Slave  
S
I2C Slave Address  
W
MSByte Start Address  
LSByte Start Address  
AK  
AK  
AK  
#bit  
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55  
Master  
Slave  
Sr  
I2C Slave Address  
R
AK  
AK  
AK  
NK  
P
AK  
MSByte Data 1  
LSByte Data 1  
MSByte Data x  
Master  
Slave  
AK  
(optional)  
(optional)  
LSByte Data x  
12.2. I2C_WRITE  
This command allows you to write the registers listed in chapter 13. Normally you write 1x register only, but optionally the  
master can continue to transmit data of sequential register addresses to reduce the communication time when a lot of  
registers should be written.  
Master  
Slave  
MSByte Data x  
LSByte Data x  
(optional)  
(optional)  
AK  
AK  
#bit  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45  
Master  
Slave  
S
I2C Slave Address  
W
MSByte Start Address  
LSByte Start Address  
MSByte Data 1  
LSByte Data 1  
P
AK  
AK  
AK  
AK  
AK  
Version V1.2  
Page 19 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
12.3. I2C_RESET  
This command will reset MLX75123.  
#bit  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45  
Master  
Slave  
S
I2CSlave Address  
W
0x00  
0x06  
0x00  
0x06  
P
AK  
AK  
AK  
AK  
AK  
12.4. I2C_GLOBAL_RESET  
This command will reset all I2C devices on the bus which support this standardized, but optional, command.  
#bit  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18  
Master  
Slave  
S
0x00  
W
0x06  
P
AK  
AK  
12.5. I2C_SAVEREGMAP  
On MLX75123 start-up all registers will be copied from the non-volatile EEPROM into the volatile RAM, where they can be  
changed via the I2C communication. When the device is restarted it will load the default values from the EEPROM again. It’s  
possible to save your own custom register map into the EEPROM with the following command sequence :  
#bit  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45  
Master  
Slave  
S
I2CSlave Address  
W
0x00  
0x06  
0x55  
0x4C  
P
AK  
AK  
AK  
AK  
AK  
followed by an I2C_WRITE of register 0x0000 with value 0x0100. This register won’t be writeable while the device is copying  
the data and it will be automatically cleared when the operation is completed. Saving a complete register map will take a  
few milliseconds and it’s advised to wait until register 0x000 is cleared before continuing any communication.  
For long term reliability of the NVRAM there’s a defined maximum of I2C_SAVEREGMAP cycles possible. These limits depend  
on the junction temperature(s) with a guaranteed amount of minimum cycles:  
.
Min.100000 store cycles at 25°C  
.
Min.10000 store cycles at 125°C  
Version V1.2  
Page 20 of 48  
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13. Registers  
MLX75123 has internal memory that is used to store the default register values and that can be used to store customer  
specific parameters like unique module no. identifiers. On startup this EEPROM is loaded into the RAM where it can be  
accessed during normal operation. Commands to read/write custom RAM settings into the EEPROM are available.  
The complete memory map can be found here, it’s strongly linked to values that can be read out from the metadata.  
Memory  
Address  
Memory  
Address  
Description  
Description  
Table 2 Properties  
T2_P0_Settings  
T2_P1_Settings  
T2_P2_Settings  
T2_P3_Settings  
T2_P4_Settings  
T2_P5_Settings  
T2_P6_Settings  
T2_P7_Settings  
0x1000  
…
0x1010  
0x1012  
…
0x1022  
0x1024  
…
0x1030  
0x1032  
…
0x103E  
0x1040  
…
0x104C  
0x104E  
…
0x105A  
0x105C  
…
0x1068  
0x106A  
…
0x1094  
…
0x10A4  
0x10A6  
…
0x10B2  
0x10B4  
…
0x10C0  
0x10C2  
…
0x10CE  
0x10D0  
…
0x10DC  
0x10DE  
…
0x10EA  
0x10EC  
…
0x10F8  
0x10FA  
…
Configuration  
Parameters I  
Table 1 Properties  
T1_P0_Settings  
T1_P1_Settings  
T1_P2_Settings  
T1_P3_Settings  
T1_P4_Settings  
T1_P5_Settings  
T1_P6_Settings  
T1_P7_Settings  
0x1076  
0x1078  
…
0x1084  
0x1086  
…
0x1106  
0x1108  
…
0x1114  
0x1116  
0x1118  
0x111A  
0x111C  
0x111E  
0x1120  
0x1122  
…
Configuration  
Parameters II  
0x1092  
USER DEFINED  
(these can be read out  
in MetaData1)  
USER DEFINED  
0x1198  
Version V1.2  
Page 21 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.1. Configuration Parameters Registers  
General parameters that influence the behaviour of MLX75123 can be changed in the following registers.  
Name : I2C_ADDRESS  
Address : 0x1000  
Default Value : 0x0067  
Bit  
15  
-
14  
-
13  
-
12  
-
11  
-
10  
-
9
-
8
-
7
-
6
5
4
3
2
1
0
I2C_ADDRESS [6:0]  
I2C_ADDRESS : Programmable 7bit I2C slave address.  
A change of this register should be followed by a I2C_SAVEREGMAP operation (section 12.5) and a device reset  
before this new address will be active. Address 0x0032 should not be used.  
Name : START_DELAY  
Address : 0x1002  
Default Value : 0x00FF  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
START_DELAY [8:0]  
START_DELAY : Defines the time between the NVRAM to EEPROM copy and the 3V3_READY signals are available  
and the start of the digital block for the first frame acquisition. It ranges from 0 - 5.12ms at 80MHz input clock, in  
steps of 9 bit.  
Name : CONFIG  
Address : 0x1004  
Default Value : 0x0000  
Bit  
15  
14  
13  
12  
11  
10  
9
8
-
-
-
-
-
-
-
-
Bit  
7
6
5
4
3
2
1
0
VIDEO_  
DRIVE  
-
-
LED_MODE  
-
-
-
-
VIDEO_DRIVE : Select the drive strength of the video output buffers  
0 : low drive strength  
1 : high drive strength  
By default the drive strength is set high for board debug processes, however the low drive strength is  
advised to reduce noise & EMC impact to a minimum in application conditions.  
LED_MODE : Select single ended or differential LED control signals  
0 : Single ended mode (LED_P, LED_N connected to ground)  
1 : LVDS mode (LED_P & LED_N)  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Name : Bx_LATCH  
Address : 0x1006  
Default Value : 0xFF11 (in configuration with sensor MLX75023)  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
BxCOL_LATCH [15:7]  
BxROW_LATCH [7:0]  
BxCOL_LATCH : Pattern to be applied to BxCOL[7:0] bits at initialization/power-up phase of the MLX75023.  
BxROW_LATCH : Pattern to be applied to BxROW[7:0] bits at initialization/power-up phase of the MLX75023  
0x11 : BxROW_LATCH pattern to apply for MLX75023 in application mode  
0x13 : BxROW_LATCH pattern to apply for MLX75023 with 4 test columns enabled  
Note : Bx_LATCH is only applied once during startup, for change(s) during operation the value has to be copied to NVRAM  
(see section 12.5) and a MLX75123 reset has to be applied.  
Note : For a configuration with MLX75024 this register value HAS to change to 0x0000.  
Name : PIXEL1  
Address : 0x1008  
Default Value : 0xF39D  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
PIXEL1_Y [15:7]  
PIXEL1_X [7:0]  
MLX75123 offers the functionality to read out any pixel in addition to the normal read-out sequence. This feature  
can be used to read out single pixels or test structures from the sensor array. This register hold the X & Y  
coordinates of one pixel. This pixel will be read out only once per frame, at the start of each frame and the result  
(available in the metadata) will be constant for all phase frames. PIXEL1_Y and PIXEL2_Y should be from 2  
neighbouring rows  
Name : PIXEL2  
Address : 0x100A  
Default Value : 0xF39C  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
PIXEL2_Y [15:7]  
PIXEL2_X [7:0]  
MLX75123 offers the functionality to read out any pixel in addition to the normal read-out sequence. This feature  
can be used to read out single pixels or test structures from the sensor array. This register hold the X & Y  
coordinates of one pixel. This pixel will be read out only once per frame, at the start of each frame and the result  
(available in the metadata) will be constant for all phase frames. PIXEL1_Y and PIXEL2_Y should be from 2  
neighbouring rows  
Version V1.2  
Page 23 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Name : ADC_DELAY_FT  
Address : 0x1010  
Default Value : 0x0000  
Bit  
15  
14  
13  
12  
11  
10  
9
8
-
-
-
-
-
-
-
-
Bit  
7
6
5
4
3
2
1
0
EN_PROG_  
DELAY  
FRAME_  
TABLE  
-
PROG_DELAY [5:1]  
EN_PROG_DELAY : Automatic calibration procedure  
0 : Disable the delay line sweep  
1 : Enable the delay line sweep, at the beginning of the readout, before the first phase readout.  
Row 'DELAY_LINE_ADDRESS' will be read out while the delay filter is incremented every other pixel (on pins  
PROG_DELAY [5:1], starting from 0 to 31. As there are 32 delay line taps, only the first 64 pixels of the line  
have to be read out. Only the data on ADC channel 'DELAY_LINE_ADC' is taken into account.  
PROG_DELAY : The setting for the delay line that shall be applied during a full frame (0 = default sampling point)  
This setting is not being applied during the automatic delay line sweep.  
This register using GRAY coding : 0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8,  
24, 25, 27, 26, 30, 31, 29, 28, 20, 21, 23, 22, 18, 19, 17, 16 (listed in order of magnitude)  
For increasing values, a delay is added, thus the sample point occurs later in time.  
Note : Operation at non optimized PROG_DELAY settings can cause vertical stripe image artefacts in the image.  
More information on this effect and the optimization procedure is available upon request.  
FRAME_TABLE : Selection of the Frame Table to be used.  
0 : Frame Definition Table 1 is used to generate the frames  
1 : Frame Definition Table 2 is used to generate the frames  
A definition of these tables can be found in registers 0x1012 and 0x1094  
Name : DELAY_CONFIG  
Address : 0x1116  
Default Value : 0x0000  
Bit  
15  
14  
6
13  
5
12  
11  
3
10  
2
9
8
MOD_INV  
ADC_LATENCY [14:10]  
DELAY_LINE_ADC [9:8]  
Bit  
7
4
1
0
DELAY_LINE_ADDRESS [7:0]  
MOD_INV : Inverts the sensor (DMIX0/1) modulation signal  
ADC_LATENCY : Changes the digital sampling point of the ADCs. Results in a full column shift of the image.  
Changes to ADC_LATENCY should be programmed into NVRAM (see section 12.5) and are only  
applied after sensor reset.  
DELAY_LINE_ADC : tbd  
DELAY_LINE_ADDRESS : tbd  
Version V1.2  
Page 24 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Name : BxROW_IDLE  
Address : 0x1118  
Default Value : 0x00F4  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
BxROW_IDLE [7:0]  
BxROW_IDLE : Pattern to be applied to BxROW[7:0] bits during reset, integration & sampling phases  
13.2. FrameTable & Phase Registers  
MLX75123 has two different FrameTable definitions. Each table consists of eight individual configurable phases as indicated  
in Table 15. The FrameTable used to capture the frames can be selected register 0x1010 ADC_DELAY_FT.  
FrameTable Definition  
Phase Definition  
T1_SETTINGS  
T1_IDLETIME  
T1_MODE  
T1_FRAMECOUNT  
T1_UPPER_LIMIT  
T1_LOWER_LIMIT  
T1_ROI_START & T1_ROI_SIZE  
T1_P0_SETTINGS  
T1_P0_INTEGRATION  
T1_P0_PREHEAT  
T1_P0_PREMIX  
T1_P0_IDLE  
T1_P0_SETUP  
… Phase1  
… Phase2  
… Phase3  
… Phase4  
… Phase5  
… Phase6  
… Phase7  
T2_SETTINGS  
T2_IDLETIME  
T2_MODE  
T2_FRAMECOUNT  
T2_UPPER_LIMIT  
T2_LOWER_LIMIT  
T2_ROI_START & T2_ROI_SIZE  
T2_P0_SETTINGS  
T2_P0_INTEGRATION  
T2_P0_PREHEAT  
T2_P0_PREMIX  
T2_P0_IDLE  
T2_P0_SETUP  
… Phase1  
… Phase2  
… Phase3  
… Phase4  
… Phase5  
… Phase6  
… Phase7  
Table 15 : Frametable configuration  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.1. Frame : Tx_SETTINGS  
Memory Address Default Value  
0x1012  
0x1094  
0x0C03  
0x0000  
T1_SETTINGS  
T2_SETTINGS  
Bit  
Bit  
15  
14  
Tx_EN_  
TEST_ADC  
13  
Tx_EN_  
TEST_ROW  
12  
11  
Tx_EN_  
META2  
10  
Tx_EN_  
META1  
9
8
-
-
-
-
7
6
5
4
3
2
1
0
Tx_FLIP_MIRROR [7:6]  
Tx_QUIET [5:4]  
-
Tx_PHASE_COUNT [3:0]  
Tx_EN_TEST_ADC : One additional row of pixel data will connected to a known voltage reference (on/off)  
The data of this row can only be evaluated in Mode #4 or Mode #5 (from section 9)  
This known voltage reference per pixel changes with BxCOL[4:3] column addresses.  
00 : ADC inputs connected to sensor  
01 : ADC inputs connected 0V  
10 : ADC inputs connected to +Vref  
11 : ADC inputs connected to -Vref  
Figure 6 : EN_TEST_ADC row for Mode #4 (12bit A)  
Tx_EN_TEST_ROW : Enable the eight MLX75023 test rows (on/off)  
Tx_EN_META2 : Enable/disable Metadata2 line (on/off)  
Tx_EN_META1 : Enable/disable Metadata1 line (on/off)  
Tx_FLIP_MIRROR : Mirror the image along its horizontal and/or vertical center axis  
00 : default  
01 : Flip (along horizontal axis)  
10 : Mirror (along vertical axis)  
11 : Flip & mirror  
Tx_QUIET : Select behaviour of the quiet pin  
00 : default, QUIET is not used  
01 : QUIET is high in reset + integration phase  
10 : QUIET is high in readout phase  
11 : QUIET is high in reset + integration + readout phase  
Tx_PHASE_COUNT : # phases to be accumulated in one FrameTable (between 0-7)  
Version V1.2  
Page 26 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.2. Frame : Tx_IDLETIME  
After the eight phases it’s possible to define a frame idle time. This time can be used to fix the distance framerate.  
It’s defined in number of Tmix pulses and ranges from 0 - 4 294 967 296.  
Memory Address Default Value  
0x1014  
0x1016  
0x1096  
0x1098  
0x93E0  
0x0004  
0x0000  
0x0000  
T1_IDLETIME0  
T1_IDLETIME1  
T2_IDLETIME0  
T2_IDLETIME1  
Bit  
Bit  
31  
15  
30  
14  
29  
13  
28  
12  
27  
11  
26  
10  
25  
24  
23  
22  
21  
5
20  
19  
3
18  
2
17  
1
16  
0
Tx_IDLETIME1 [31:16]  
9
8
7
6
4
Tx_IDLETIME0 [15:0]  
Tx_IDLETIME in Tmix pulses can be calculated as :  
(
)
ꢵꢊꢢꢍꢅꢉꢅ ꢏ ꢂꢆꢄꢎꢉꢂ ꢎꢅ ꢒ ꢖꢎꢗꢃꢂ(ꢶꢥꢦ)  
For a typical application setup with Tint = 250us, FMOD = 20MHz and a distance framerate of 25 FPS the Tx_IDLETIME is 35ms.  
ꢵꢊꢢꢍꢅꢉꢅ ꢏ ꢂꢓꢟ ꢒ ꢑꢕꢕꢕꢕ ꢏ ꢝꢕꢕꢂꢕꢕꢕ ꢏ 0x 000A AE60 (hexadecimal)  
IDLETIME1  
IDLETIME0  
Note : The default T1_IDLETIME has been set to 0x493E0 (dec. 300 000) which corresponds to 15ms @ FMOD = 20MHz  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.3. Frame : Tx_MODE  
Memory Address Default Value  
0x1018  
0x109A  
0x6E80  
0x0000  
T1_MODE  
T2_MODE  
Bit  
Bit  
15  
14  
13  
12  
-
11  
10  
9
1
8
Tx_MOD_DUTY_CYLE [15:13]  
Tx_RDIV [11:9]  
Tx_NDIV [8]  
7
6
5
4
3
2
0
Tx_NDIV [7:6]  
Tx_VSYNC  
Tx_HSYNC  
Tx_PIXCLK  
Tx_FSYNC  
Tx_TRIGGER [1:0]  
Tx_MOD_DUTY_CYLE : Duty cycle correction for the MOD signal  
0x000 : 12.5%  
0x001 : 25%  
0x010 : 37.5%  
0x011 : 50%  
0x100 : 62.5%  
0x101 : 75%  
0x110 : 87.5%  
Tx_RDIV : PLL RDIV value (see chapter 17)  
Tx_NDIV [8:6] : PLL NDIV value (see chapter 17)  
Tx_VSYNC : 0: default / 1: VSYNC inverted  
Tx_HSYNC : 0: default / 1: HSYNC inverted  
Tx_PIXCLK : 0: default / 1: PIXCLK inverted  
Tx_FSYNC : 0: default / 1: FSYNC inverted  
Tx_TRIGGER :  
0x00 : Continuous Mode :  
Once started, the system will execute the phase measurements according the configured sequence.  
0x01: Triggered Multi Frame Mode:  
In this mode the system will acquire a variable number of frames with a preset number of phases, after  
which time the system will return to idle state. The number of frames to be acquired can be set using  
register Tx_FRAME_COUNT.  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.4. Frame : Tx_FRAMECOUNT  
This register holds the amount of frames to be captured in triggered multi frame mode in the range of 0 - 65535.  
Memory Address Default Value  
0x101A  
0x109C  
0x0000  
0x0000  
T1_FRAMECOUNT  
T2_FRAMECOUNT  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tx_FRAMECOUNT [15:0]  
13.2.5. Frame : Tx_UPPER_LIMIT  
The value of this register is used as high threshold value. The amount of pixels that return a value higher than this threshold  
will be counted and will be available in the statistics. It can be used to indicate low confidence pixels.  
The same threshold is used for the common mode bit in the 11bit + 1 output modes.  
Memory Address Default Value  
0x101C  
0x109E  
0x0CCC  
0x0000  
T1_UPPER_LIMIT  
T2_UPPER_LIMIT  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tx_UPPER_LIMIT [15:0]  
13.2.6. Frame : Tx_LOWER_LIMIT  
The value of this register is used as low threshold value. The amount of pixels that return a value lower than this threshold  
will be counted and will be available in the statistics. It can be used to indicate saturated pixels.  
The same threshold is used for the common mode bit in the 11bit + 1 output modes.  
Memory Address Default Value  
0x101E  
0x10A0  
0x0333  
0x0000  
T1_LOWER_LIMIT  
T2_LOWER_LIMIT  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tx_LOWER_LIMIT [15:0]  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.7. Frame : Tx_ROI_START & Tx_ROI_SIZE  
The ROI registers enable you to read out only part of the complete MLX75023 pixel array.  
This region is defined by its starting location and its size.  
Values in Y (rows) are multipliers of 1, values in X (columns) are multipliers of 16.  
1
1
320  
Memory  
Address  
0x1020  
Default  
Value  
0x0000  
0xF014  
0x0000  
0x0000  
X_START  
T1_ROI_START  
T1_ROI_SIZE  
T2_ROI_START  
T2_ROI_SIZE  
Y_START  
0x1022  
Y_SIZE  
0x10A2  
0x10A4  
X_SIZE  
240  
Bit  
Bit  
15  
15  
14  
13  
12  
11  
10  
9
9
8
8
7
7
6
6
5
5
4
3
2
2
1
1
0
0
Tx_ROI_START [15:8]  
Tx_ROI_START [7:0]  
14  
13  
12  
11  
10  
4
3
Tx_ROI_SIZE [15:8]  
Tx_ROI_SIZE [7:0]  
Tx_ROI_START [15:8] : Start position in Y direction (Y_START on the graph)  
Tx_ROI_START [7:0] : Start position in X direction (X_START on the graph)  
Tx_ROI_SIZE [15:8] : Size in Y direction (Y_SIZE on the graph)  
Tx_ROI_SIZE [7:0] : Size in X direction (X_SIZE on the graph)  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.8. Phase : Tx_Py_SETTINGS  
Each phase frame has its own phase configuration parameters.  
Memory  
Address  
Default  
Value  
Memory  
Address  
Default  
Value  
FRAMETABLE 1  
FRAMETABLE 2  
0x1024  
0x1032  
0x1040  
0x104E  
0x105C  
0x106A  
0x1078  
0x1086  
0x00C0  
0x00C4  
0x00C2  
0x00C6  
0x0000  
0x0000  
0x0000  
0x0000  
T1_P0_SETTINGS  
T1_P1_SETTINGS  
T1_P2_SETTINGS  
T1_P3_SETTINGS  
T1_P4_SETTINGS  
T1_P5_SETTINGS  
T1_P6_SETTINGS  
T1_P7_SETTINGS  
0x10A6  
0x10B4  
0x10C2  
0x10D0  
0x10DE  
0x10EC  
0x10FA  
0x1108  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T2_P0_SETTINGS  
T2_P1_SETTINGS  
T2_P2_SETTINGS  
T2_P3_SETTINGS  
T2_P4_SETTINGS  
T2_P5_SETTINGS  
T2_P6_SETTINGS  
T2_P7_SETTINGS  
Bit  
Bit  
15  
14  
13  
12  
11  
10  
9
8
Tx_Py_  
STATIC  
-
-
-
-
Tx_Py_OUTPUT_MODE [11:9]  
7
6
5
4
3
2
1
0
Tx_Py_  
DMIX  
Tx_Py_  
LIGHT  
-
-
Tx_Py_PHASE_SHIFT [3:0]  
Tx_Py_OUTPUT_MODE : Define the output mode per phase  
0x000 : Mode #0 : 11bit (A-B)/4 data + 1bit statistics  
0x001 : Mode #1 : 12bit (A-B)/2 data  
0x010 : Mode #2 : 11bit (A+B)/4 data + 1bit statistics  
0x011 : Mode #3 : 12bit (A+B)/2 data  
0x100 : Mode #4 : 12bit A  
0x101 : Mode #5 : 12bit B  
Tx_Py_STATIC : Only evaluated if Tx_Py_DMIX = 1  
0x0 : static level on DMIX[1:0] during integration is 2'b10  
0x1 : static level on DMIX[1:0] during integration is 2'b01  
Tx_Py_DMIX : Enable (0) / disable (1) MIX pulses during the integration time  
When disabled DMIX[1] and DMIX[0] signal levels are defined by Tx_Py_STATIC  
Tx_Py_LIGHT : Enable (1) / disable (0) the illumination pulses during the integration time  
Tx_Py_PHASE_SHIFT [3:0] : Selects the phase shift between MOD and DMIX[0] signals.  
DMIX[1] is always 180° shift compared to DMIX[0] (except during reset phase)  
0x000 : 0°  
0x001 : 45°  
0x010 : 90°  
0x011 : 135°  
0x100 : 180°  
0x101 : 225°  
0x110 : 270°  
0x111 : 315°  
Version V1.2  
Page 31 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.9. Phase : Tx_Py_INTEGRATION  
These registers are used to define the integration times for each of the different phases.  
It ranges from 0 - 4 294 967 295 Tmix periods.  
Memory  
Address  
0x1026  
Default  
Value  
0x1388  
Memory  
Address  
0x10A8  
Default  
Value  
0x0000  
FRAMETABLE 1  
FRAMETABLE 2  
T1_P0_INT0  
T1_P0_INT1  
T2_P0_INT0  
T2_P0_INT1  
0x1028  
0x0000  
0x10AA  
0x0000  
0x1034  
0x1036  
0x1388  
0x0000  
T1_P1_INT0  
T1_P1_INT1  
0x10B6  
0x10B8  
0x0000  
0x0000  
T2_P1_INT0  
T2_P1_INT1  
0x1042  
0x1044  
0x1388  
0x0000  
T1_P2_INT0  
T1_P2_INT1  
0x10C4  
0x10C6  
0x0000  
0x0000  
T2_P2_INT0  
T2_P2_INT1  
0x1050  
0x1052  
0x1388  
0x0000  
T1_P3_INT0  
T1_P3_INT1  
0x10D2  
0x10D4  
0x0000  
0x0000  
T2_P3_INT0  
T2_P3_INT1  
0x105E  
0x1060  
0x0000  
0x0000  
T1_P4_INT0  
T1_P4_INT1  
0x10E0  
0x10E2  
0x0000  
0x0000  
T2_P4_INT0  
T2_P4_INT1  
0x106C  
0x106E  
0x0000  
0x0000  
T1_P5_INT0  
T1_P5_INT1  
0x10EE  
0x10F0  
0x0000  
0x0000  
T2_P5_INT0  
T2_P5_INT1  
0x107A  
0x107C  
0x0000  
0x0000  
T1_P6_INT0  
T1_P6_INT1  
0x10FC  
0x10FE  
0x0000  
0x0000  
T2_P6_INT0  
T2_P6_INT1  
0x1088  
0x108A  
0x0000  
0x0000  
T1_P7_INT0  
T1_P7_INT1  
0x110A  
0x110C  
0x0000  
0x0000  
T2_P7_INT0  
T2_P7_INT1  
Bit  
Bit  
31  
15  
30  
14  
29  
13  
28  
12  
27  
11  
26  
10  
25  
9
24  
23  
22  
6
21  
5
20  
19  
3
18  
2
17  
1
16  
0
Tx_Py_INT1 [31:16]  
8
7
4
Tx_Py_INT0 [15:0]  
The integration time can be calculated in a similar way as the Tx_IDLETIME time in section 13.2.2.  
Example : Tint 250us (= 0.25ms) with FMOD 20MHz  
ꢵꢊꢢꢍꢅꢉꢅ ꢏ ꢂꢕꢷꢑꢟ ꢒ ꢑꢕꢕꢕꢕ ꢏ ꢟꢂꢕꢕꢕ ꢏ 0x 0000 1388 (hexadecimal)  
Tx_Py_INT1  
Tx_Py_INT0  
Version V1.2  
Page 32 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.10. Phase : Tx_Py_PREHEAT  
Illumination preheating can be used to avoid IU waveform transients at the beginning of each pulse train.  
It defines the amount of light pulses before the actual integration time is started.  
It ranges from 0 - 65535 Tmix periods.  
Memory  
Address  
Default  
Value  
Memory  
Address  
Default  
Value  
FRAMETABLE 1  
FRAMETABLE 2  
0x102A  
0x1038  
0x1046  
0x1054  
0x1062  
0x1070  
0x107E  
0x108C  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T1_P0_PREHEAT  
T1_P1_PREHEAT  
T1_P2_PREHEAT  
T1_P3_PREHEAT  
T1_P4_PREHEAT  
T1_P5_PREHEAT  
T1_P6_PREHEAT  
T1_P7_PREHEAT  
0x10AC  
0x10BA  
0x10C8  
0x10D6  
0x10E4  
0x10F2  
0x1100  
0x110E  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T2_P0_PREHEAT  
T2_P1_PREHEAT  
T2_P2_PREHEAT  
T2_P3_PREHEAT  
T2_P4_PREHEAT  
T2_P5_PREHEAT  
T2_P6_PREHEAT  
T2_P7_PREHEAT  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tx_Py_PREHEAT [15:0]  
Version V1.2  
Page 33 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.11. Phase : Tx_Py_PREMIX  
Sensor premixing can be used to avoid temperature transients at the beginning of each integration time.  
It ranges from 0 - 65535 Tmix periods.  
Memory  
Address  
Default  
Value  
Memory  
Address  
Default  
Value  
FRAMETABLE 1  
FRAMETABLE 2  
0x102C  
0x103A  
0x1048  
0x1056  
0x1064  
0x1072  
0x1080  
0x108E  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T1_P0_PREMIX  
T1_P1_PREMIX  
T1_P2_PREMIX  
T1_P3_PREMIX  
T1_P4_PREMIX  
T1_P5_PREMIX  
T1_P6_PREMIX  
T1_P7_PREMIX  
0x10AE  
0x10BC  
0x10CA  
0x10D8  
0x10E6  
0x10F4  
0x1102  
0x1110  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T2_P0_PREMIX  
T2_P1_PREMIX  
T2_P2_PREMIX  
T2_P3_PREMIX  
T2_P4_PREMIX  
T2_P5_PREMIX  
T2_P6_PREMIX  
T2_P7_PREMIX  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tx_Py_PREMIX [15:0]  
Version V1.2  
Page 34 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.2.12. Phase : Tx_Py_IDLE  
Increasing PHASE_IDLE time will have impact on motion robustness, ideally keep to 0.  
Memory  
Address  
Default  
Value  
Memory  
Address  
Default  
Value  
FRAMETABLE 1  
FRAMETABLE 1  
0x102E  
0x103C  
0x104A  
0x1058  
0x1066  
0x1074  
0x1082  
0x1090  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T1_P0_IDLE  
T1_P1_IDLE  
T1_P2_IDLE  
T1_P3_IDLE  
T1_P4_IDLE  
T1_P5_IDLE  
T1_P6_IDLE  
T1_P7_IDLE  
0x10B0  
0x10BE  
0x10CC  
0x10DA  
0x10E8  
0x10F6  
0x1104  
0x1112  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T2_P0_IDLE  
T2_P1_IDLE  
T2_P2_IDLE  
T2_P3_IDLE  
T2_P4_IDLE  
T2_P5_IDLE  
T2_P6_IDLE  
T2_P7_IDLE  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tx_Py_IDLE [15:0]  
13.2.13. Phase : Tx_Py_SETUP  
Memory  
Address  
Default  
Value  
Memory  
Address  
Default  
Value  
FRAMETABLE 1  
FRAMETABLE 2  
0x1030  
0x103E  
0x104C  
0x105A  
0x1068  
0x1076  
0x1084  
0x1092  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T1_P0_SETUP  
T1_P1_SETUP  
T1_P2_SETUP  
T1_P3_SETUP  
T1_P4_SETUP  
T1_P5_SETUP  
T1_P6_SETUP  
T1_P7_SETUP  
0x10B2  
0x10C0  
0x10CE  
0x10DC  
0x10EA  
0x10F8  
0x1106  
0x1114  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
T2_P0_SETUP  
T2_P1_SETUP  
T2_P2_SETUP  
T2_P3_SETUP  
T2_P4_SETUP  
T2_P5_SETUP  
T2_P6_SETUP  
T2_P7_SETUP  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Tx_Py_SETUP [15:0]  
Version V1.2  
Page 35 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
13.3. USER Registers  
Memory  
Address  
Default  
Value  
Memory  
Address  
Default  
Value  
0x111A  
0x111C  
0x111E  
0x1120  
0x1122  
0x1124  
0x1126  
0x1128  
0x112A  
0x112C  
0x112E  
0x1130  
0x1132  
0x1134  
0x1136  
0x1138  
0x113A  
0x113C  
0x113E  
0x1140  
0x1142  
0x1144  
0x1146  
0x1148  
0x114A  
0x114C  
0x114E  
0x1150  
0x1152  
0x1154  
0x1156  
0x1158  
0x0000  
0x0001  
0x0002  
0x0003  
0x0004  
0x0005  
0x0006  
0x0007  
0x0008  
0x0009  
0x000A  
0x000B  
0x000C  
0x000D  
0x000E  
0x000F  
0x0010  
0x0011  
0x0012  
0x0013  
0x0014  
0x0015  
0x0016  
0x0017  
0x0018  
0x0019  
0x001A  
0x001B  
0x001C  
0x001D  
0x001E  
0x001F  
USER0  
USER1  
USER2  
USER3  
USER4  
0x115A  
0x115C  
0x115E  
0x1160  
0x1162  
0x1164  
0x1166  
0x1168  
0x116A  
0x116C  
0x116E  
0x1170  
0x1172  
0x1174  
0x1176  
0x1178  
0x117A  
0x117C  
0x117E  
0x1180  
0x1182  
0x1184  
0x1186  
0x1188  
0x118A  
0x118C  
0x118E  
0x1190  
0x1192  
0x1194  
0x1196  
0x1198  
0x0020  
0x0021  
0x0022  
0x0023  
0x0024  
0x0025  
0x0026  
0x0027  
0x0028  
0x0029  
0x002A  
0x002B  
0x002C  
0x002D  
0x002E  
0x002F  
0x0030  
0x0031  
0x0032  
0x0033  
0x0034  
0x0035  
0x0036  
0x0037  
0x0038  
0x0039  
0x003A  
0x003B  
0x003C  
0x003D  
0x003E  
0x003F  
USER32  
USER33  
USER34  
USER35  
USER36  
USER37  
USER38  
USER39  
USER40  
USER41  
USER42  
USER43  
USER44  
USER45  
USER46  
USER47  
USER48  
USER49  
USER50  
USER51  
USER52  
USER53  
USER54  
USER55  
USER56  
USER57  
USER58  
USER59  
USER60  
USER61  
USER62  
USER63  
USER5  
USER6  
USER7  
USER8  
USER9  
USER10  
USER11  
USER12  
USER13  
USER14  
USER15  
USER16  
USER17  
USER18  
USER19  
USER20  
USER21  
USER22  
USER23  
USER24  
USER25  
USER26  
USER27  
USER28  
USER29  
USER30  
USER31  
Bit  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
USER [15:0]  
USER [15:0]: These registers can be used to program any customer specific data.  
USER0, USER1, USER2, USER3 can be read out via MetaData1.  
Typically these registers are used to store module identifiers like production batch no./date, …  
Version V1.2  
Page 36 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
14. MetaData  
PIXD  
[11]  
PIXD  
[10]  
PIXD  
[9]  
PIXD  
[8]  
PIXD  
[7]  
PIXD  
[6]  
PIXD  
[5]  
PIXD  
[4]  
PIXD  
[3:0]  
Description  
Value can change on each phase frame = P  
Value is constant = C  
#
MetaData1  
Value can change on each frame = F  
0
1
2
DIAGNOSTICS [15:8]  
DIAGNOSTICS [7:0]  
FIXED_VALUE  
0000  
0000  
Diagnostics of the PREVIOUS phase  
P
C
0000 FIXED_VALUE : 0x4D = “M”  
in Continuous Mode :  
3
4
5
FRAME_NUMBER [15:8]  
FRAME_NUMBER [7:0]  
PHASE_NUMBER  
0000  
FRAME_NUMBER increments every frame, starting from 0  
F
in Triggered Multi Frame Mode :  
FRAME_NUMBER increments every frame, resets at new trigger  
0000  
0000  
PHASE_NUMBER :  
Phase number from 0 to PHASE_COUNT  
-
-
-
-
-
P
C
PIXEL1_X = column number, PIXEL1_Y = row number  
This pixel will be read out after a full array read out,  
the pixel value can be found in MetaData2  
6
7
8
9
PIXEL1_X  
PIXEL1_Y  
PIXEL2_X  
PIXEL2_Y  
0000  
0000  
0000  
0000  
PIXEL2_X = column number, PIXEL2_Y = row number  
This pixel will be read out after a full array read out,  
the pixel value can be found in MetaData2  
C
F
EN_DELAY : Disabled/enabled ADC delay lines  
EN_  
DELAY  
FRAME  
TABLE  
10  
-
-
PROG_DELAY  
0000 PROG_DELAY : Settings of the ADC delay line  
FRAMETABLE : Selected FrameTable 1 or 2  
EN_TESTADC :  
Disabled/enabled ADC test mode  
EN_TESTROW :  
Disabled/enabled MLX75023 test rows  
0000  
EN_  
TEST  
ADC  
EN_  
TEST  
ROW  
EN_  
EN_  
11  
-
METAD METAD  
ATA2 ATA1  
-
-
F
EN_METADATA2 :  
Disabled/enabled Metadata2  
EN_METADATA1 :  
Disabled/enabled Metadata1  
FLIR_MIRROR :  
- 0x00: no FLIP, no MIRROR  
- 0x01: Vertical FLIP  
- 0x10: Horizontal MIRROR  
- 0x11: FLIP & MIRROR  
FLIP_  
MIRROR  
QUIET_  
DEFINE  
QUIET_DEFINE :  
0000  
12  
PHASE_COUNT  
F
- 00 : QUIET is not used  
- 01 : QUIET is high in reset + integration phase  
- 10 : QUIET is high in readout phase  
- 11 : QUIET is high in reset + integration + readout phase  
PHASE_COUNT :  
Total numbers of phase frames to be captured  
Table 16.1 : MetaData1  
Version V1.2  
Page 37 of 48  
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
PIXD  
[11]  
PIXD  
[10]  
PIXD  
[9]  
PIXD  
[8]  
PIXD  
[7]  
PIXD  
[6]  
PIXD  
[5]  
PIXD  
[4]  
PIXD  
[3:0]  
Description  
Value can change on each phase frame = P  
Value is constant = C  
#
MetaData1  
Value can change on each frame = F  
13  
14  
15  
16  
FRAME_IDLETIME [15:8]  
FRAME_IDLETIME [7:0]  
FRAME_IDLETIME [31:24]  
FRAME_IDLETIME [23:16]  
0000  
0000  
0000  
0000  
FRAME_IDLETIME :  
32 bit value counted in TMIX periods  
F
MOD_DUTY_CYLE :  
- 0x000 : 12.5 %  
- 0x001 : 25 %  
- 0x010 : 37.5 %  
- 0x011 : 50 %  
- 0x100 : 62.5 %  
- 0x101 : 75 %  
- 0x110 : 87.5 %  
PLL_  
NDIV 0000  
17  
MOD_DUTY_CYCLE  
-
PLL_RDIV  
F
[2]  
PLL_RDIV :  
Parameter used to calculate FMOD  
More information can be found in section 17  
PLL_NDIV [2] :  
Parameter used to calculate FMOD  
More information can be found in section 17  
PLL_NDIV [1:0] :  
Parameter used to calculate FMOD  
More information can be found in section 17  
FSYNC : 0x0 (active high) or 0x1 (= active low)  
PIXCLK : 0x0 (active high) or 0x1 (= active low)  
HSYNC : 0x0 (active high) or 0x1 (= active low)  
VSYNC : 0x0 (active high) or 0x1 (= active low)  
P
I
X
C
L
F
S
Y
N
H
S
Y
N
C
V
S
Y
N
C
PLL_NDIV  
[1:0]  
18  
TRIGGER  
0000  
F
F
C
K
TRIGGER :  
- 0x00: Continuous Mode  
- 0x01: Triggered Multi Frame Mode  
19  
20  
FRAME_COUNT [15:8]  
FRAME_COUNT [7:0]  
0000  
0000  
FRAMECOUNT : Total number of frames to be  
captured in triggered multi-frame mode  
ROI_START_Y : Y coordinate of ROI start position  
More information can be found in chapter 13.2.7  
21  
22  
23  
24  
FRAME_ROI_START_Y  
FRAME_ROI_START_X  
FRAME_ROI_SIZE_Y  
FRAME_ROI_SZIE_X  
0000  
0000  
0000  
0000  
F
F
F
F
ROI_START_X : X coordinate of ROI start position  
More information can be found in chapter 13.2.7  
ROI_SIZE_Y : Y size of ROI  
More information can be found in chapter 13.2.7  
ROI_SIZE_X : X size of ROI  
More information can be found in chapter 13.2.7  
OUTPUT_MODE :  
- 0x000 : Mode #0 : 11b (A-B)/4 + 1b  
- 0x001 : Mode #1 : 12b (A-B)/2  
- 0x010 : Mode #2 : 11b (A+B)/4 + 1b  
- 0x011 : Mode #3 : 12b (A+B)/2  
- 0x100 : Mode #4 : 12b A  
EN_  
DMIX  
STATIC  
25  
-
-
-
-
OUTPUT_MODE  
0000  
P
- 0x101 : Mode #5 : 12b B  
EN_DMIXSTATIC :  
(Value is only valid if DMIX_DISABLE = 1)  
- 0x0: Both DMIX pins are LOW during integration  
- 0x1: Both DMIX pins are HIGH during integration  
Table 16.2 : MetaData1  
Version V1.2  
Page 38 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
PIXD  
[11]  
PIXD  
[10]  
PIXD  
[9]  
PIXD  
[8]  
PIXD  
[7]  
PIXD  
[6]  
PIXD  
[5]  
PIXD  
[4]  
PIXD  
[3:0]  
Description  
Value can change on each phase frame = P  
Value is constant = C  
#
MetaData1  
Value can change on each frame = F  
DMIX_DISABLE :  
- 0x0: DMIX pulses are enabled during integration time  
- 0x1: EN_DMIXSTATIC is enabled  
EN_LIGHT :  
- 0x0: LED pulses are disabled during integration time  
- 0x1: LED pulses are enabled during integration time  
PHASE_SHIFT : Shift between MOD and DMIX[0]  
0000 (DMIX[1] is always 180° shifted compared to DMIX[0],  
EN_  
LIGHT  
DMIX_  
DISABLE  
-
26  
-
PHASE_SHIFT  
P
except during reset phase)  
- 0x000: 0°  
- 0x001: 45°  
- 0x010: 90°  
- 0x011: 135°  
- 0x100: 180°  
- 0x101: 225°  
- 0x110: 270°  
- 0x111: 315°  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
PHASE_INTEGRATION [15:8]  
PHASE_INTEGRATION [7:0]  
PHASE_INTEGRATION [31:24]  
PHASE_INTEGRATION [23:16]  
PHASE_PREHEAT [15:8]  
PHASE_PREHEAT [7:0]  
PHASE_PREMIX [15:8]  
PHASE_PREMIX [7:0]  
0000  
0000  
Integration Time (32-bit), in #Tmix periods  
0000  
P
0000  
0000  
Number of LED pulses before sensor integration  
0000  
P
P
P
P
C
C
C
C
0000  
Number of DMIX pulses before sensor integration  
0000  
PHASE_IDLE [15:8]  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
Phase idle time at the end of each phase read out,  
in #Tmix periods  
PHASE_IDLE [7:0]  
PHASE_SETUP [15:8]  
Setup time before integration, in #Tmix periods  
PHASE_SETUP [7:0]  
USER_DEFINED0 [15:8]  
USER_DEFINED0 [7:0]  
USER_DEFINED1 [15:8]  
USER_DEFINED1 [7:0]  
USER_DEFINED2 [15:8]  
USER_DEFINED2 [7:0]  
USER_DEFINED3 [15:8]  
USER_DEFINED3 [7:0]  
Readout of USER_DEFINED0 16bit register value  
This can be used to program unique a device identifier  
Readout of USER_DEFINED1 16bit register value  
This can be used to program unique a device identifier  
Readout of USER_DEFINED2 16bit register value  
This can be used to program unique a device identifier  
Readout of a USER_DEFINED3 16bit register value  
This can be used to program unique a device identifier  
*The length of MetaData1 can be truncated depending on ROI settings  
Table 16.3 : MetaData1  
Version V1.2  
Page 39 of 48  
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
PIXD  
[11]  
PIXD  
[10]  
PIXD  
[9]  
PIXD  
[8]  
PIXD  
[7]  
PIXD  
[6]  
PIXD  
[5]  
PIXD  
[4]  
PIXD  
[3:0]  
Description  
Value can change on each phase frame = P  
Value is constant = C  
#
MetaData2  
Value can change on each frame = F  
0
DIAGNOSTICS [15:8]  
DIAGNOSTICS [7:0]  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
Diagnostics of the CURRENT phase  
P
P
1
2
-
-
-
-
-
NR_PIXELS_ABOVE [20:16]  
NR_PIXELS_ABOVE [15:8]  
NR_PIXELS_ABOVE [7:0]  
NR_PIXELS_BELOW [20:16]  
# ADC readings above the threshold defined in register  
Tx_UPPER_LIMIT, see chapter 13.2.5 for more information  
3
4
5
-
# ADC readings above the threshold defined in register  
Tx_LOWER_LIMIT, see chapter 13.2.6 for more information  
6
NR_PIXELS_BELOW [15:8]  
NR_PIXELS_BELOW [7:0]  
PIXEL1_CH0 [11:4]  
P
P
7
8
Returns the ADC values from PIXEL1 with coordinates defined  
in register 0x1008. See chapter 13.1 for more information.  
9
PIXEL1_CH0 [3:0]  
PIXEL1_CH2 [3:0]  
PIXEL2_CH0 [3:0]  
PIXEL2_CH2 [3:0]  
PIXEL1_CH1 [11:8]  
PIXEL1_CH1 [7:0]  
PIXEL1_CH2 [11:4]  
PIXEL1_CH3 [11:8]  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
PIXEL1_CH0 : 12bit data from tap A  
PIXEL1_CH1 : 12bit data from tap B  
PIXEL1_CH2 : 12bit data from tap A  
PIXEL1_CH3 : 12bit data from tap B  
PIXEL1_CH3 [7:0]  
PIXEL2_CH0 [11:4]  
Returns the ADC values from PIXEL2 with coordinates defined  
in register 0x100A. See chapter 13.1 for more information.  
PIXEL2_CH1 [11:8]  
PIXEL2_CH1 [7:0]  
PIXEL2_CH2 [11:4]  
PIXEL2_CH0 : 12bit data from tap A  
PIXEL2_CH1 : 12bit data from tap B  
PIXEL2_CH2 : 12bit data from tap A  
PIXEL2_CH3 : 12bit data from tap B  
P
PIXEL2_CH3 [11:8]  
PIXEL2_CH3 [7:0]  
DELAY_LINE_PIXEL0  
DELAY_LINE_PIXEL1  
DELAY_LINE_PIXEL2  
DELAY_LINE_PIXEL3  
DELAY_LINE_PIXEL4  
DELAY_LINE_PIXEL5  
DELAY_LINE_PIXEL6  
DELAY_LINE_PIXEL7  
DELAY_LINE_PIXEL8  
DELAY_LINE_PIXEL9  
DELAY_LINE_PIXEL10  
DELAY_LINE_PIXEL11  
DELAY_LINE_PIXEL12  
DELAY_LINE_PIXEL13  
DELAY_LINE_PIXEL14  
DELAY_LINE_PIXEL15  
DELAY_LINE_PIXEL16  
DELAY_LINE_PIXEL17  
DELAY_LINE_PIXEL18  
DELAY_LINE_PIXEL19  
Values of the delay line sweep  
This feature can be used to optimize the ADC sampling point  
P
Table 17.1 : MetaData2  
Version V1.2  
Page 40 of 48  
 
MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
PIXD  
[11]  
PIXD  
[10]  
PIXD  
[9]  
PIXD  
[8]  
PIXD  
[7]  
PIXD  
[6]  
PIXD  
[5]  
PIXD  
[4]  
PIXD  
[3:0]  
Description  
Value can change on each phase frame = P  
Value is constant = C  
#
MetaData2  
Value can change on each frame = F  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
DELAY_LINE_PIXEL20  
DELAY_LINE_PIXEL21  
DELAY_LINE_PIXEL22  
DELAY_LINE_PIXEL23  
DELAY_LINE_PIXEL24  
DELAY_LINE_PIXEL25  
DELAY_LINE_PIXEL26  
DELAY_LINE_PIXEL27  
DELAY_LINE_PIXEL28  
DELAY_LINE_PIXEL29  
DELAY_LINE_PIXEL30  
DELAY_LINE_PIXEL31  
DELAY_LINE_PIXEL32  
DELAY_LINE_PIXEL33  
DELAY_LINE_PIXEL34  
DELAY_LINE_PIXEL35  
DELAY_LINE_PIXEL36  
DELAY_LINE_PIXEL37  
DELAY_LINE_PIXEL38  
DELAY_LINE_PIXEL39  
DELAY_LINE_PIXEL40  
DELAY_LINE_PIXEL41  
DELAY_LINE_PIXEL42  
DELAY_LINE_PIXEL43  
DELAY_LINE_PIXEL44  
DELAY_LINE_PIXEL45  
DELAY_LINE_PIXEL46  
DELAY_LINE_PIXEL47  
DELAY_LINE_PIXEL48  
DELAY_LINE_PIXEL49  
DELAY_LINE_PIXEL50  
DELAY_LINE_PIXEL51  
DELAY_LINE_PIXEL52  
DELAY_LINE_PIXEL53  
DELAY_LINE_PIXEL54  
DELAY_LINE_PIXEL55  
DELAY_LINE_PIXEL56  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
Values of the delay line sweep  
This feature can be used to optimize the ADC sampling point  
P
Table 17.2 : MetaData2  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
PIXD  
[11]  
PIXD  
[10]  
PIXD  
[9]  
PIXD  
[8]  
PIXD  
[7]  
PIXD  
[6]  
PIXD  
[5]  
PIXD  
[4]  
PIXD  
[3:0]  
Description  
Value can change on each phase frame = P  
Value is constant = C  
#
MetaData2  
Value can change on each frame = F  
77  
78  
79  
80  
81  
82  
83  
DELAY_LINE_PIXEL57  
DELAY_LINE_PIXEL58  
DELAY_LINE_PIXEL59  
DELAY_LINE_PIXEL60  
DELAY_LINE_PIXEL61  
DELAY_LINE_PIXEL62  
DELAY_LINE_PIXEL63  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
Values of the delay line sweep  
This feature can be used to optimize the ADC sampling point  
P
Table 17.3 : MetaData2  
15. Diagnostics  
On top of the Metadata lines there’s one extra register that holds information about the device status.  
Name : DIAGNOSTICS  
Address : 0x0002  
Default Value : 0x0005  
Bit  
15  
14  
13  
12  
11  
10  
9
8
ROI_ERROR SEC_ERROR DED_ERROR SEC_LATCH DED_LATCH  
-
-
-
Bit  
7
6
5
4
3
2
1
0
-
-
-
-
-
3V3_READY  
-
PLL_LOCK  
ROI_ERROR : This bit is set high when an incorrect ROI is set via registers Frame : Tx_ROI_START & Tx_ROI_SIZE  
When a ROI error occurs, the video output stops. It can only be corrected by setting a valid ROI.  
SEC_ERROR : Selfclearing bit that indicates single error correction from NVRAM.  
The bit gets cleared as soon as the information is shared via the MetaData.  
DED_ERROR : Selfclearing bit that indicate when a double error is detected inside the NVRAM.  
The bit gets cleared as soon as the information is shared via the MetaData.  
SEC_LATCH : This bit is set high as soon as a SEC occurred, and will stay high until it get’s cleared.  
This bit needs to be actively cleared by the user by writing register 0x0000 with value 0x0004.  
DED_LATCH : This bit is set high as soon as a SEC occurred, and will stay high until it get’s cleared.  
This bit needs to be actively cleared by the user by writing register 0x0000 with value 0x0008.  
3V3_READY : This bit is set high when the VDDD_3V3 voltage level is higher than 2.8V.  
PLL_LOCK : This bit is set high when the PLL is locked at the correct modulation frequency.  
Version V1.2  
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16. Sleep Mode(s)  
MLX75123 features 1 register that can be used to enable/disable some internal blocks to reduce the power consumption.  
In normal operation all blocks are enabled. The I2C communication is always active. This register is not part of the NVRAM  
and it’s not possible to save its value with I2C_SAVEREGMAP as explained in section 12.5. On start-up this register will always  
load it’s default value.  
Name : BLOCK_DISABLE  
Address : 0x0004  
Default Value : 0x0000  
Bit  
15  
14  
13  
12  
11  
10  
9
8
-
-
-
-
-
-
-
-
Bit  
7
6
5
4
3
2
1
0
DIS_VIDEO_ DIS_75023_  
BUFFERS BUFFERS  
DIS_ADC_REF DIS_ADC_BG  
-
-
DIS_PLL  
DIS_BG  
DIS_ADC_REF : Enable/disable the input test references for the ADC  
DIS_ADC_BG : Enable/disable the internal ADC band gap (incl. ADC reference voltages)  
DIS_VIDEO_BUFFERS : Enable/disable the video output buffers  
DIS_75023_BUFFERS : Enable/disable the MLX75023 control buffers  
DIS_PLL : Enable/disable the FMOD Generator  
DIS_BG : Enable/disable the bandgap  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
17. FMOD Generator  
MLX75123 features a built in timing generator. This block generates all the timings, and phase shifts, for the sensor and  
illumination. This is often referred to as the modulation frequency. The output frequency changes in function on the input  
clock frequency, RDIV & NDIV values.  
ꢸꢹꢺ  
ꢽ
ꢾꢿꣀꣁ  
ꣂꢿꣀꣁ  
ꢻꢼ  
The output modulation frequency is given by  
ꢒ
(in MHz) limited between 12-40 MHz.  
This frequency can change every frame and can be used to minimize interference between one or more TOF cameras  
operating in the same environment.  
The value of RDIV has to be selected in a way that  
Examples :  
CLKIN = 80MHz  
CLKIN = 62MHz  
CLKIN = 42MHz  
RDIV = CLKIN / 8 MHz = 10  
NDIV  
3
4
5
6
7
8
9
10  
Fmod (MHz)  
12  
16  
20  
24  
28  
32  
36  
40  
RDIV = CLKIN / 8 MHz = 7.75 8  
NDIV  
3
1
4
5
6
7
8
9
10  
Fmod (MHz)  
15.5  
19.38 23.25 27.13  
31  
34.88 38.75  
RDIV = CLKIN / 8 MHz = 5.25 5  
NDIV  
3
4
5
6
7
8
9
10  
1
Fmod (MHz)  
12.6  
16.8  
21  
25.2  
29.4  
33.6  
37.8  
CLKIN = 40MHz  
RDIV = CLKIN / 8 MHz = 5  
NDIV  
3
4
5
6
7
8
9
10  
Fmod (MHz)  
12  
16  
20  
24  
28  
32  
36  
40  
Note 1 : Not a valid setting, the modulation frequency should be in range 12-40MHz.  
The corresponding RDIV & NDIV values to be written into the registers from section 13.2.3 can be found here :  
RDIV or NDIV value Hexadecimal  
3
4
0x000  
0x001  
0x010  
0x011  
0x100  
0x101  
0x110  
0x111  
5
6
7
8
9
10  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
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18. AQFN Package Dimensions  
Figure 7 : Package dimensions  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
19. Layout & Solder Recommendations  
19.1. PCB Footprint Design  
Designing a printed circuit board for MLX75123 can be quite challenging. This chapter describes a reliable,  
yet practical PCB footprint based on our experiences.  
(all dimensions are in millimeter)  
0.5  
2.775  
2.775  
0.5  
4.6  
3.275  
0.25  
0.5  
2.775  
3.275  
2.775  
0.3  
0.7  
0.3  
4.6  
Figure 8 : PCB footprint recommendation (Top Layer)  
Pad size = 0.3 x 0.3 mm (rounded rectangle)  
Pad solder mask = 0.35 x 0.35 mm (NSMD soldering)  
Pad solder paste = 0.21 x 0.21 mm (rounded rectangle)  
Exposed pad size = 4.6 x 4.6 mm (rounded rectangle)  
Exposed pad solder paste = 4x 1.5mm dots (to avoid tilting of the device)  
Exposed pad via size(s) = 1mm with 0.5mm hole (center via)  
Exposed pad via size(s) = 0.7mm with 0.3mm hole (outer vias)  
Figure 9 : Top Layer  
+ Top Paste  
The vias in the exposed pad allow an excessive amount of solder paste to flow away easily.  
Project copper clearance rule is set to 0.12mm. It’s impossible to route a trace from the inner row to the  
outside on the same layer. Microvias are an expensive solution, but connecting these pins can also be done  
with through-hole vias (0.28mm size with 0.15mm hole).  
An example Altium footprint library is available on request.  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
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19.2. Reflow Solder Profile  
Reflow soldering according to JEDEC-J-STD-020D.  
Figure 10 : Reflow profile  
Temperature  
(minimum)  
Temperature  
(maximum)  
Heating Zone  
1
2
3
4
350  
240  
350  
340  
350  
240  
350  
340  
Table 18 : Temperature setting / zone  
Version V1.2  
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MLX75123 Time-of-Flight Companion Chip  
PRELIMINARY Datasheet  
Disclaimer  
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.  
Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or  
regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications  
and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check  
with Melexis for current information. This product is intended for use in normal commercial applications. Applications  
requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military,  
medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis  
for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not  
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss  
of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection  
with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or  
any third party shall arise or flow out of Melexis’ rendering of technical or other services.  
© 2013 Melexis NV. All rights reserved.  
www.melexis.com  
Version V1.2  
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