MLX83203 [MELEXIS]
Automotive NFET pre-drivers;
| 型号： | MLX83203 |
| 厂家： | 
Melexis Microelectronic Systems |
| 描述： | Automotive NFET pre-drivers |
| 文件： | 总35页 (文件大小：1399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MLX83202/MLX83203
Automotive NFET pre-drivers
Features and Benefits
Application Examples
Level shifting between micro-controller PWM outputs
and 3 external N-FET half-bridges
100% PWM operation
Low offset, low drift, fast current sense amplifier
Operating range VSUP = [4.5, 28] V, 45V Abs. Max
Fault interrupt & feedback to microcontroller
Under & overvoltage protection
Fail-safe applications
Low-torque control applications
BLDC sine wave applications (PMSM)
Overtemperature protection
VDS and VGS external FET monitoring
Sleep mode with low quiescent current
Compatible with 3V and 5V micro-controllers
Charge-pump provides NFET reverse polarity drive
Ordering Information
Part No.
MLX83202
MLX83202
MLX83203
MLX83203
Temperature Code
K (-40°C to 125°C)
K
K
K
Package Code
Option code Comment
LQ (QFN32, 5x5mm)
PF (TQFP48, 7x7mm)
LQ (QFN32, 5x5mm)
PF (TQFP48, 7x7mm)
AAA 000
AAA 000
AAA 000
AAA 000
25 Ohm 3HB (*)
25 Ohm 3HB (*)
8 Ohm 3HB
8 Ohm 3HB (*)
(*): Derivatives of MLX83203KLQAAA-000 available on high volume request
1 Functional Diagram
2 General Description
The MLX83202/MLX83203 family of pre-drivers is
designed to drive high-current N-type FET 3-phase
motor control applications.
The built-in EEPROM allows extensive configurability
of the pre-driver without the need for external
resistors and SPI interface programming. This
reduces the package pin count to only 32.
All output voltages are monitored for failure
conditions. The microcontroller is informed of the
failure condition via a fast serial interface.
The device comprises a current shunt amplifier, with
a high gain bandwidth (GBW), offering a fast settling
time with low noise. This makes the pre-drivers ideal
for precise torque control applications like e.g.
electrical power steering and brake by wire.
A combination of bootstrap and charge pump enables
driving
6
NFETs, with gate charges up to
400nC/NFET with a minimum of device self-heating.
The IC reset level below 4.5V allows for low-voltage
operation.
3901083203
Rev 2.2
Page 1 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
Table of Contents
1 Functional Diagram____________________________________________________________________1
2 General Description ___________________________________________________________________1
3 Glossary of Terms_____________________________________________________________________3
4 Absolute Maximum Ratings _____________________________________________________________3
5 Pin Definitions and Descriptions_________________________________________________________4
6 Electrical Specifications________________________________________________________________5
7 Block diagram and application circuit ___________________________________________________10
7.1 Pinout schematics ________________________________________________________________12
7.2 Ground connections_______________________________________________________________13
8 Description__________________________________________________________________________14
8.1 Supply system ___________________________________________________________________14
8.2 Sleep mode ______________________________________________________________________14
8.2.1 Sleep mode status overview ______________________________________________________15
8.3 Enable input _____________________________________________________________________16
8.4 Protection and diagnostic functions _________________________________________________16
8.4.1 Drain-source voltage monitoring ___________________________________________________16
8.4.2 Programmable dead time_________________________________________________________16
8.4.3 Supply overvoltage shutdown _____________________________________________________16
8.4.4 Regulated supply overvoltage shutdown _____________________________________________16
8.4.5 Undervoltage warnings __________________________________________________________17
8.4.6 Over temperature warning ________________________________________________________17
8.4.7 EEPROM error warning __________________________________________________________17
8.4.8 ICOM diagnostics interface _______________________________________________________17
8.4.9 Pre-driver output state summary ___________________________________________________19
8.5 EEPROM programming ____________________________________________________________20
8.5.1 Memory map __________________________________________________________________20
8.5.2 SPI communication _____________________________________________________________21
8.6 Current sense amplifier ____________________________________________________________25
8.7 FET driver implementation _________________________________________________________27
8.7.1 Normal operation _______________________________________________________________27
8.7.2 FET driver during sleep mode _____________________________________________________28
8.8 Charge pump_____________________________________________________________________28
8.9 100% PWM with bootstrap__________________________________________________________29
9 Standard information regarding manufacturability of Melexis products with different soldering
processes ____________________________________________________________________________30
10 ESD Precautions ____________________________________________________________________30
11 Package Information_________________________________________________________________31
11.1 Package data QFN32 (5x5, 32 leads) ________________________________________________31
11.2 Package data TQFP48_EP 7x7 (48 leads, exposed pad) _______________________________32
11.3 Package Marking ________________________________________________________________33
12 Disclaimer _________________________________________________________________________34
3901083203
Rev 2.2
Page 2 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
3 Glossary of Terms
OVT
OV
Overtemperature
Overvoltage
UV
Undervoltage
POR
CP
Power-On-Reset
Charge pump
VDD
Vds
Vgs
HV
Logic supply (3.3V or 5V)
Drain-source voltage
Gate-source voltage
High Voltage (>5V)
4 Absolute Maximum Ratings
All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum
ratings given in the table below are limiting values that do not lead to a permanent damage of the device.
Exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of
the device. Reliable operation of the IC is only specified within the limits shown in “Operating conditions”.
Limit
Parameter
Symbol
Condition
Unit
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-10
Max
45
28
t < 500ms (note 1)
Permanent (functional)
V
V
V
V
V
V
mA
V
Supply voltage
VSUP, VBATF
VDD supply voltage
VDD
5.5
Voltage on Analog LV
Digital Output Voltage
Digital Input Voltage
VAN_LV
VOUT_DIG
VIN_DIG
IIN_DIG
VDD+0.3
VDD+0.3
VDD+0.3
10
Digital Input Current
Input voltage on PHASEX pins
Maximum latch–up free current at
any pin
VIN_PHASE
-0.7
45
according JEDEC JESD78,
AEC-Q100-004
ILATCH
-100
100
mA
ESD capability of any other pin
Storage temperature
ESD
Tstg
Human body model (note 2)
-2
-55
+2
150
kV
°C
150
(175
under
revision)
Junction Temperature
TJ
(note 3)
-40
°C
Thermal resistance Package
Rthja
Rthjc
in free air on multilayer pcb (JEDEC 1s2p)
referring to center of exposed pad
37
10
K/W
K/W
Table 1. Maximum ratings
Note:
1. Only during Loaddump pulse.
2. Equivalent to discharging a 100pF capacitor through a 1.5kOhm resistor conform to MIL STD 883
method 3015.7
3. For applications with Tj > 125C: The Extended temperature range is only allowed for a limited period
of time. The application mission profile has to be agreed by Melexis. Some analog parameters may
drift out of limits, but chip functionality is guaranteed.
3901083203
Rev 2.2
Page 3 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
5 Pin Definitions and Descriptions
MLX8320x MLX8320x
Name
Type
Function
QFN32
TQFP48
1
2
4
5
IBM
IBP
LV analog input Current sensor input (negative input)
LV Analog input Current sensor input (positive input)
LV Analog
3
4
5
6
7
8
9
6
7
8
9
ISENSE
FETB1
FETB2
FETB3
ICOM
EN
Current sensor output
LV Digital input PWM input for low-side N-FET1 (active low), MISO for SPI
LV Digital input PWM input for low-side N-FET2 (active low), CLK for SPI
LV Digital input PWM input for low-side N-FET3 (active low), MOSI for SPI
LV IO
LV IO
10
11
14
15
16
17
18
19
20
21
22
26
28
29
30
31
33
35
38
39
41
43
44
45
47
3
Diagnostic feedback IO, !CS for SPI
Enable input
PHASE2 HV output
GATET2 HV output
HV input
PHASE1 HV output
GATET1 HV output
HV input
PHASE3 HV output
GATET3 HV output
Motor phase 2: high-side N-FET2 Source connection
PWM output to high-side N-FET2 Gate
Supply input (bootstrap) for high-side N-FET2 Gate
Motor phase 1: high-side N-FET1 Source connection
PWM output to high-side N-FET1 Gate
Supply (bootstrap) input for high-side NFET1
Motor phase 3: high-side N-FET3 Source connection
PWM output to high-side N-FET3 Gate
Supply (bootstrap) input for high-side NFET3 Gate
Charge pump generated supply input
Regulated supply for bootstrap capacitors and low-side pre-driver
PWM output to low-side N-FET2 Gate
PWM output to low-side N-FET3 Gate
PWM output to low-side N-FET1 Gate
Driver ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP2
CP1
CP3
VBOOST HV input
VREG HV output
HV input
GATEB2 HV Output
GATEB3 HV Output
GATEB1 HV Output
DGND
CP
Ground
HV Output
HV Supply input Power supply input
HV input
Ground
LV Digital
LV Digital
LV Digital
LV Supply
Charge pump driver output to boost VBOOST
VSUP
VBATF
AGND
FETT2
FETT1
FETT3
VDD
VBAT sense input for 3 high-side N-FETs to monitor Vds
Analog ground
PWM input for high-side N-FET2
PWM input for high-side N-FET1
PWM input for high-side N-FET3
Digital IO and current sensor amplifier supply.
VREF
LV Analog input Reference voltage input for current sense
Table 2. Pin definitions and descriptions
3901083203
Rev 2.2
Page 4 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
6 Electrical Specifications
DC and AC Operating Range (unless otherwise specified)
TA
= -40oC to 125oC,
VSUP = [7, 18]V
VDD = 3.3V or 5V
Parameter
Symbol
Test Conditions
Min
Typ
Max Units
Battery Supply
P.1
P.2
Supply voltage
VSUP
7
18
7
V
V
Supply voltage extended
range low
Functional with relaxed
specification
VSUP_ERL
4.5
Supply voltage extended
range high
Quiescent current drawn
from VSUP
Functional with relaxed
specification
P.2b
P.3
VSUP_ERH
Issleep
18
28
30
V
VDD=low
uA
Pre-driver operation without
charge pump operation
(EN_CP=0) and without switching
Operating current drawn
from VSUP
P.4
Isup_int
1
mA
Battery overvoltage
threshold high
Battery overvoltage
threshold low
P.5
VSUP_OVH Warning on ICOM
VSUP_OVL ICOM released
35
V
V
P.6
30
Battery overvoltage
threshold hysteresis
Battery overvoltage
debounce time
Battery undervoltage
threshold low
Battery undervoltage
threshold high
Battery undervoltage
threshold hysteresis
Battery undervoltage
debounce time
VSUP_OVH
Y
VSUP_OV_d
eb
P.7
0.4
1
V
P.102
P.8
2
6
us
V
VSUP_UVH Warning on ICOM
VSUP_UVL ICOM released
5
0.2
3
P.9
V
VSUP_UVH
Y
VSUP_UV_d
eb
P.10
P.103
0.5
V
10
us
V
Reset released on rising edge of
VSUP, while VDD = high
P.11 Power on reset level
VPOR
4.5
Power and Temperature
Overtemperature protection
high
P.12
OVT_h
OVT_l
Warning on ICOM
ICOM released
153
123
166
137
183
153
C
C
Overtemperature protection
P.13
low
3901083203
Rev 2.2
Page 5 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
VDD IO supply input
Maximum input current
Includes ICOM current sourcing
P.14 VDD operating current
IDD
20
mA
P.15 VDD pull down resistance
P.16 VDD input voltage
P.17 VDD undervoltage high1
P.18 VDD undervoltage low
VDDRPD
VDD
200
3
2.7
2.55
300
370
5.5
2.85
2.7
KOhm
VDD= 3.3V or 5V logic supply
V
V
V
VDD_UV_H NFET control activated
VDD_UV_L NFET control disabled
VDD undervoltage
hysteresis
VDD_UV_H
Y
P.19
0.07
0.1
0.13
V
P.20 VDD sleep voltage high
P.21 VDD sleep voltage low
VDDsleepH Out of sleep
VDDsleepL Goto sleep
VDDsleepH
2.1
1.5
2.7
2.05
V
V
VDD sleep voltage
P.22
0.45
0.58
0.85
V
hysteresis
Y
On-chip oscillator
P.25 ICOM PWM frequency fast
P.26 ICOM PWM frequency slow FICOMS
FICOMF
85
10.6
6.8
100
12.5
8
115
14.4
9.2
KHz
KHz
MHz
Oscillator frequency
FOSC
Internal Oscillator
EN=Low, FETT1/2/3=low,
FETB1/2/3=high
2048/F
OSC
4096/F
OSC
P.27 SPI start up pulse duration
Tspi_su
s
Charge pump: CPMODE=x
(Silicon diodes BAS16, Cpump=1uF,Cboost=1uF +Creg=4.7uF)
Rtyp at room temperature
Rboost_leak Rmin at 150C Tj
(excluding Rvreg_leak)
Resistive Load from
VBOOST to GND
6
8
MOhm
Output slew rate
Charge pump Frequency
100
200
V/us
kHz
FreqCP
170
230
40
Charge pump: CPMODE=0
Ireg_cpmode
0
Load current on VREG
VREG > 11V, EN_CP = 1
mA
Output voltage VREG
Output voltage VREG
VBOOST undervoltage high Vboost_UVH ICOM released
VBOOST undervoltage low Vboost_UVL Warning on ICOM
Vreg
Vreg
VSUP > 8V, I reg < 40mA
VSUP =[ 7,8]V, Ireg <40mA
11
10
6.1
5.7
12
13
13
7.2
6.7
V
V
V
V
Charge pump: CPMODE=1
Ireg_cpmode
1
Load current on VREG
VREG > 11V, EN_CP = 1
20
mA
Reverse polarity NFET gate
voltage (VBOOST-VSUP)
Output voltage VREG
VBOOST undervoltage high
(VBOOST-VSUP)
VSUP > 7
Ireg < 20mA
Ireg < 20mA
Vgs_RPFET
Vreg
5
12
12
13
13
V
V
V
11
6.1
Vboost_UVH ICOM released
Vboost_UVL Warning on ICOM
7.2
VBOOST undervoltage low
(VBOOST-VSUP)
5.7
6.7
V
VBOOST overvoltage
Disable and discharge charge
pump at VSUP_OV
Vboost_dis
1 The info VDD_UV_X is used to disable the control of the external FETs
3901083203
Rev 2.2
Page 6 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
VREG warnings (CPMODE=X)
Internal Resistive Load from
VREG to GND
P.34 VREG overvoltage high
P.35 VREG overvoltage low
Rtyp at room temperature
Rmin at 150C Tj
Warning on ICOM
ICOM released
Rvreg_leak
0.3
0.4
1.3
MOhm
Vreg_OVH
Vreg_OVL
14.2
13.5
16.5
15.8
V
V
VREG overvoltage
hysteresis
P.36
Vreg_OVHY
0.65
V
P.37 VREG undervoltage high
P.38 VREG undervoltage low
Vreg_UVH
Vreg_UVL
ICOM released
Warning on ICOM
7.2
6.9
8.1
7.8
V
V
VBATF
Internal leakage from
VBATF to GND
Rvbatf_leak Pre-driver is not in sleep mode
20
uA
FET Gate drivers
P.40 Driver ON resistance 2
P.41 Rise time
P.42 Fall time
R_dr_on
Tr
Tf
4
7
7
8
15
15
Ohm
ns
ns
Cload = 1nF, 20% to 80%
Cload = 1nF, 80% to 20%
6
4
Pull-up ON resistance
low-side pre-driver
Pull-up ON resistance
high-side pre-driver
Pull-down ON resistance
low-side pre-driver
Pull-down ON resistance
high-side pre-driver
Turn-on Gate drive peak
current
P.43
2.4
4
4
7
Ohm
Ohm
Ohm
Ohm
A
-10mA Tj = -40
-10mA, Tj = 150
Ron_up
Ron_dn
8.5
5.7
9.2
-1.4
1.6
100
20
1.5
P.44
10mA Tj = -40
10mA, Tj = 150
P.45
Igon
VGS=0V
-1
1
Turn-off Gate drive peak
current
P.46
Igoff
VGS=12V
A
From logic input threshold to 2V
VGS drive output at no load
Transitions at the different phases
at no load condition
P.50 Propagation delay
Tpddrv
20
ns
P.51 Propagation delay matching Tpddrvm
-20
ns
DEAD_TIME [ 2:0]=000
0
001
010
011
100
101
110
111
0.5
0.75
1.0
1.5
2.0
3.0
6.0
Programmable dead time :
asynchronous internal delay
between high-side and low-
side pre-driver
P.52
Tdead
us
%
P.55 Dead time tolerance
Tdead_tol
Vds_mon
-15
15
VDSMON[2:0]=000: Disabled
001
010
011
100
101
110
111
0.4
0.6
0.85
1.05
1.25
1.5
0.5
0.6
0.9
0.75
1.00
1.25
1.50
1.75
2.00
Programmable Vds monitor
voltage
1.15
1.45
1.75
2.00
2.3
P.53b
V
1.70
2
The driver on resistance is < 5 Ohm at 25C, maximum values correspond with 150C
3901083203
Rev 2.2
Page 7 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
Programmable Vds monitor
blanking time: Internal delay
P.54 between GATE signal high
and enabling the
VDS_BLANK_TIME[1:0] =00
0.59
1.22
2.5
0.75
1.5
3
0.93
1.94
4.12
8.44
01
10
11
Tvds_bl
us
4.9
6
corresponding Vds monitor
Internal resistance between FET
gate-source pins to switch-off
FET. VDD = 0V (sleep mode)
VGS =0.5V
VSUP>12V, PHASE2/3 = VSUP,
CP2/3=PHASE2/3+6.5V
ICOM released
Sleep gate discharge
resistor
P.56
Rsgd
Itcp
1
KOhm
uA
Trickle charge pump current
capability
P.58 VGS undervoltage high
VGS undervoltage low
P.60 PWM frequency
P.57
-35
-25
Vgs_UVH
Vgs_UVL
F_dr_pwm
42
36
5
70
63
100
%VREG
%VREG
KHz
Warning on ICOM
20
1
Typ at room temperature
Min at 150C Tj
P.61 Leakage from CPx to PHx
Rcp_leak
0.75
MOhm
Logic IO (FET inputs, EN input)
Minimum voltage for input to be
treated as logical high
Maximum voltage for input to be
treated as logical low
P.63 Digital input high Voltage
P.64 Digital input low Voltage
VIN_dig_h
VIN_dig_l
70
%VDD
%VDD
30
P.65 Input pull-up resistance
P.66 Input pull-down resistance
P.67 Input pull-down resistance
RIN_dig_pu FETB1, FETB2, FETB3
RIN_dig_pd FETT1,FETT2, FETT3
90
90
90
410
410
410
KOhm
KOhm
KOhm
R_EN_pd
EN
SPI timing
P.68 SPI initial setup time
P.69 SPI clock frequency
P.70 Rise/fall times
Tspi_isu
Fspi
Tspi_rf
2
us
KHz
ns
500
200
CLK, CSB, MISO, MOSI
P.71 CSB setup time
P.72 CSB high time
P.73 Clock high time
P.74 Clock low time
P.75 Data in setup time
P.76 Data in hold time
P.77 Data out ready delay
EEPROM read delay
TCSB_su
TCSB_H
TCLK_H
TCLK_L
TDI_su
TDI_h
TDO_r
T_EE_RD
T_EE_WR
1
2
1
1
1
us
us
us
us
us
us
us
us
500
Cload at FETB1<50pF
EE_RD = 1
EE_RD = 1
500
6
12
EEPROM write delay
ms
ICOM output
P.78 pullup current
P.79 pulldown current
ICOM_PU
ICOM_PD
Vicom=0V
Vicom=VDD
-2.23
5
-5
2.6
mA
mA
Enable input
From Bridge enable EN <
EN_PR_DEL 0.2*VDD to VGS < 0.5V,
Cload=1nF
Bridge disable propagation
delay
P.80
1
us
3901083203
Rev 2.2
Page 8 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
Current sense amplifier
P.81 Input offset voltage
VIS_IO
-7.3
-10
7.6
10
mV
Input offset voltage thermal VIS_IO_TDR
P.82
P.83
P.84
P.85
P.86
uV/C
drift
IFT
IS_CMRR_D
C
IS_CMRR_A
C
Input common mode
rejection DC
60
40
60
40
dB
dB
dB
dB
Input diff. voltage within +/-100mV,
Common mode [-0.5,1.0]V
Input common mode
rejection 1MHz
Input power supply rejection IS_PSRR_D
DC for VDD supply
Input power supply rejection IS_PSRR_A
C
1MHz for VDD supply
C
8.0
10.3
13.3
17.2
22.2
28.7
37.0
47.8
P.87 Closed loop gain
IS_GAIN
Gain programmable in EEPROM
-3%
+3%
-
Amplified output to 99% of final
value after input change
P.88 Output settling time
IS_SET
1.0
us
V
V_ISENSEm
ax
V_ISENSEm
in
VDD-
0.020
P.89 Output voltage range high
P.90 Output voltage range low
Current sense output max level
Current sense output min level
Output current saturation level
VDD
GND
+0.020
GND
V
Output short circuit current
to ground
P.91
I_Isensesc
1.4
40
mA
P.92 GBW
P.93 Output slew rate
IS_GBW
IS_SR
10
MHz
V/us
CM spike=+- 1.5V,
duration=250nsec
P.94 CM spike recovery
P.95 VREF voltage input
IS_CM_REC
Vref
730
50
ns
0
%VDD
Table 3. Electrical specifications
3901083203
Rev 2.2
Page 9 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
7 Block diagram and application circuit
Figure 1. Block diagram
3901083203
Rev 2.2
Page 10 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
Figure 2. Application schematic 1
Figure 3. Application schematic 2: internal dead time + HS Reverse Polarity NFET
3901083203
Rev 2.2
Page 11 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
7.1 Pinout schematics
Principle schematics highlighting ESD connections:
Figure 4. Pin Internal connections
3901083203
Rev 2.2
Page 12 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
7.2 Ground connections
Figure 5. Ground connections
3901083203
Rev 2.2
Page 13 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
8 Description
8.1 Supply system
Figure 6. Supply system, CPMODE=0
Figure 7. Supply system, CPMODE=1
The supply for the IC operation is supplied via VSUP and VDD:
VDD supplies the IO’s, and the amplifier.
o
Mind when supplying VDD with a limited output impedance (for instance from a
microcontroller IO) that the performance of the amplifier may be affected.
VSUP supplies the internal operation and the charge pump.
See also chapter: 8.8 Charge pump.
8.2 Sleep mode
Sleep mode is activated when the supply input VDD is pulled below VDDsleepL.
In sleep mode the current consumption on VSUP is reduced to Issleep.
Pin
State in sleep mode
Input/Output
FETTX, FETBX,
EN, VREF, ICOM
ISENSE
Input pins, supplied from VDD.
GND
Supplied from VDD
Supply regulator is disabled
GND
GND
VREG
VBOOST, HSD
CP
Externally connected to supply
Charge pump is disabled
~VBAT
GND
CPX
Any charge that remains after VREG is disabled will leak to ground
GND
VSUP>4.5V
GATETX
PHASEX
In sleep mode gate-discharge-resistors (Rsgd) between GATETX and PHASEX
are activated (see chapter 8.7.2 FET driver during sleep mode)
VSUP>4.5V
GND
GND
GATEBX
In sleep mode gate-discharge-resistors (Rsgd) between GATEBX and DGND
are activated. (see chapter 8.7.2 FET driver during sleep mode)
Table 4. State of IC during sleep mode
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Automotive NFET pre-drivers
Note:
In case input pins are externally pulled high while VDD LOW, current will flow into VDD via internal
ESD protection diodes. This condition is not allowed.
When VDD is pulled low, also ICOM will go low. This should not be interpreted as a diagnostic
interrupt.
8.2.1 Sleep mode status overview
Name
Type
State in sleep mode
IBM
LV Analog input GND
IBP
LV Analog input GND
ISENSE
FETB1
FETB2
FETB3
ICOM
LV Analog output GND (tied to VDD)
LV Digital input
LV Digital input
LV Digital input
LV IO
GND (tied to VDD)
GND (tied to VDD)
GND (tied to VDD)
GND (tied to VDD)
EN
LV IO
GND (tied to VDD)
PHASE2
GATET2
CP2
HV output
HV output
HV input
Connected via Diode to GATE2
Internal pull down (Rsgd) to GND
Any present charge leaks to GND
Connected via Diode to GATE1
Internal pull down (Rsgd) to GND
Any present charge leaks to GND
Connected via Diode to GATE3
Internal pull down (Rsgd) to GND
Any present charge leaks to GND
Connected via CP diodes to VBAT
GND
PHASE1
GATET1
CP1
HV output
HV output
HV input
PHASE3
GATET3
CP3
HV output
HV output
HV input
VBOOST
VREG
GATEB2
GATEB3
GATEB1
DGND
CP
HV input
HV output
HV Output
HV Output
HV Output
Ground
Internal pull down (Rsgd) to GND
Internal pull down (Rsgd) to GND
Internal pull down (Rsgd) to GND
Driver ground
HV Output
GND
VSUP
VBATF
AGND
FETT2
FETT1
FETT3
VDD
HV Supply input Power supply input
HV input
Ground
Connected to supply
Analog ground
LV Digital
LV Digital
LV Digital
GND (tied to VDD)
GND (tied to VDD)
GND (tied to VDD)
LV Supply input Externally pulled low
LV Analog input GND
VREF
Table 5. Pin definitions and descriptions
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Automotive NFET pre-drivers
8.3 Enable input
Pulling the Enable input (EN) low forces the pre-driver to pull all FET gate voltages to ground, switching off all
external transistors (high impedance). While EN is low, the programming of the EEPROM via SPI can be
initiated by pulling ICOM low for a time Tspi_su.
8.4 Protection and diagnostic functions
8.4.1 Drain-source voltage monitoring
The MLX8320x provides a drain-source voltage monitoring feature for each external FET to protect against
short circuits. This drain-source voltage monitoring comparator can be enabled/disabled in EEPROM.
The drain-source voltage monitor for a certain external FET is only active when the corresponding input is set
to “on” and the dead time is over. An additional blanking time can be programmed in EEPROM. If the drain-
source voltage stays higher than the VDS monitor threshold voltage, the VDS error is raised. This threshold
voltage is configurable in EEPROM.
The reaction of the pre-driver on a VDS error can be configured in EEPROM with the Bridge Feedback bit. If
this bit is set the pre-driver will automatically disable the drivers when a VDS error is detected. If not set the
pre-driver remains active. In any case the VDS error will be reported.
VDS_COMP_EN
VDS_BF_EN
Pre-driver reaction on error event
Any drain-source over voltage event is ignored
and no error is reported on ICOM.
0
1
1
x
0
1
VDS_ERR is reported on ICOM, but the pre-driver remains active.
VDS_ERR is reported on ICOM and the pre-driver is disabled.
Table 6. Pre-driver reaction on VDS error
8.4.2 Programmable dead time
The pre-drivers’ internal implementation guarantees that low side and high side of the same external half
bridge can not be “on” at the same time connecting supply directly to ground. See Figure 12 for this internal
implementation of the pre-driver. The pre-driver also provides a programmable dead time in EEPROM.
8.4.3 Supply overvoltage shutdown
The pre-driver has an integrated VSUP over voltage shut down to prevent destruction of the pre-driver at high
supply voltages. A VSUP_OV event will always switch off the pre-driver, this reaction can not be masked.
8.4.4 Regulated supply overvoltage shutdown
The pre-driver has an integrated VREG over voltage shut down. The reaction of the pre-driver on this
VREG_OV depends on the status of the Bridge Feedback bit in EEPROM. If this VREG_OV_BF_EN bit is set
the pre-driver will pull all gate voltages low, switching off all external FETs.
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Automotive NFET pre-drivers
VREG_OV_BF_EN
Pre-driver reaction on error event
0
1
VREG_OV is reported on ICOM, but the pre-driver remains active.
VREG_OV is reported on ICOM and the pre-driver is disabled.
Table 7. Pre-driver reaction on VREG_OV
8.4.5 Undervoltage warnings
Comparators are implemented to detect an under voltage on VSUP, VBOOST, VREG, VDD and VGS. If an
under voltage is detected, it will be reported to the MCU. It is the responsibility of the user to take action to
assure functional operation.
8.4.6 Over temperature warning
If the junction temperature exceeds the specified threshold, a warning will be communicated to the MCU. The
pre-driver will continue in normal operation. It is the responsibility of the user to protect the IC against over
temperature destruction.
8.4.7 EEPROM error warning
To ensure reliable communication with EEPROM the pre-driver provides an automatic single bit error
correction. If two bits in the addressed word are bad the EEPROM gives the EEP_ERR warning, indicating a
double error was detected.
8.4.8 ICOM diagnostics interface
ICOM is a serial interface that feeds back detailed diagnostics information to the MCU over a single wire. In
normal operation, when no error is detected, ICOM is high. When an error is detected the pre-driver will
inform the MCU via a PWM duty cycle on ICOM. It is the responsibility of the MCU to catch the ICOM duty
cycle and disable the driver if necessary, by pulling EN low.
Each error corresponds to a duty cycle with a 5 bit resolution. The duty cycle is transmitted until the MCU
acknowledges the reception of the duty cycle.
For the MCU to acknowledge the error, it should be able to keep the line low while ICOM is pulling the line
high, for a period TAck > TICOM. At each ICOM falling edge the pre-driver checks the actual voltage on ICOM to
detect an acknowledgement. When an acknowledgement is detected the PWM duty cycle is changed to the
corresponding duty cycle of the next error to be transmitted.
Figure 8. ICOM diagnostics interface
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Automotive NFET pre-drivers
This sequence of capturing duty cycle and acknowledging continues until all error duty cycles are
communicated and the End Of Frame (EOF) duty cycle is being transmitted. By acknowledging this EOF all
error latches are reset and the ICOM line goes high again, until a new error is detected.
(2)
(2)
(1)
(2)
(2)
(3)
Error 3
(1)
T
(3)
(3)
(1)
T
(1)
T
(3)
T
Error 2
Error 1
EOF
ICOM
T
T
T
T
T
T
T
T
T
T
Tack
Tack
Tack
Tack
(1): MCU pulls ICOM low
(2): MLX8320x detects acknowledge on falling edge
(3): MCU releases ICOM line
Figure 9. ICOM serial interface for diagnostics information over a single wire
In case multiple errors occur at the same time, priority is defined: 0 is the highest priority and 16 is the lowest
priority. See Table 8 for an overview of all error conditions that are monitored, the corresponding PWM duty
cycle and the priority.
Input error
code
ICOM_EOF
EEP_ERR
VDD_UV
% Duty
cycle
93.5
55.0
49.5
Debounce
Priority
Description
time
n/a
n/a
8us
16
9
8
End of frame
EEPROM DED error
VDD Under Voltage
VSUP Over Voltage
VSUP Under Voltage
OVT (over temperature)
VREG Under Voltage
7
6
5
4
VSUP_OV
VSUP_UV
OVT
44.0
38.5
33.0
27.5
2us
8us
2us
VREG_UV
16us
Vgs Under Voltage
This event can be masked by setting VGS_UV_COMP_EN=0
VBOOST Under Voltage
3
2
1
VGS_UV
22.0
16.5
11.0
2us
16us
2us
VBOOST_UV
VREG_OV
Voltage regulator over voltage
This event can be masked by setting VREG_OV_BF_EN=0
Vds Error =VDS_T1 || VDS_T2 || VDS_T3 || VDS_B1 ||
VDS_B2 || VDS_B3
Can be Masked by VDS_COMP_EN
0
VDS_ERR
5.5
2us
To avoid erronous triggering due to switching there is a
programmable blanking time on top of the debounce time:
VDS_BLANKTIME[1:0].
Table 8. Overview diagnostic errors over ICOM
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Two modes for supplying diagnostic feedback to the MCU are possible and can be set in EEPROM.
The first mode is the slow response diagnostic mode and uses a larger PWM period to communicate
diagnostics information to the MCU over ICOM.
The second mode is the fast response diagnostic mode and uses a PWM period that is ~8 times smaller.
This fast mode allows the fastest response time of the interrupt routine form the external MC, but also implies
the MCU needs to be fast enough in order to be able to capture the duty cycle. For the fast response
diagnostic mode the MCU clock needs to be minimum 20MHz.
Note:
The different diagnostic feedback modes (slow/fast) are applicable independent of the configuration
of the internal hardware protection features.
When VDD is pulled low to put the pre-driver in sleep mode ICOM will go low as well. As soon as
VDD goes high, ICOM will go high as well and remains high. No EOF may be required.
At POR it is possible that the voltages on VSUP, VBOOST and VREG have not been achieved (dut
to charging of the external capacitors) and thus it is possible ICOM may immediately go in diagnostic
mode. This implies the MCU has to acknowledge these errors until the under voltage conditions have
been resolved. As soon as the EOF duty cycle is acknowledged and ICOM remains high, the pre-
driver is ready for normal operation.
8.4.9 Pre-driver output state summary
Below table shows all conditions due to which the pre-driver may be disabled:
The pre-driver is disabled (high-impedance state) The Pre-driver is released again
As soon as an error condition appears for which the hardware
protection is activated
VSUP_OV
VDS
VREG_OV
As soon as the EOF has been acknowledged.
As soon as VDD = LOW
As soon as EN = LOW
As soon as VDD = HIGH
As soon as EN = HIGH
Table 9. Pre-driver output summary
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8.5 EEPROM programming
The EEPROM data can be programmed during customer production testing by using a PTC-04, or by
the microcontroller via an SPI interface. The pre-driver is programmed with default settings per table
below.
The EEPROM features single error correction and double error detection.
Note: SPI_Address[6] == SPI_Address[7] == SPI_Address[5]
8.5.1 Memory map
SPI
Address[2:0]
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
0
1
2
3
Res.
Res.
Res.
Res.
DEAD_TIME[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
VDSMON[2:0]
Res.
Res.
Res.
Res.
CPMODE
Res.
Res.
Res.
Res.
VDS_BLANK_TIME[1:0]
PWM_SPEED
Res.
VGS_UV_C
OMP_EN
Res.
CUR_GAIN[2:0].
VREG_OV
_BF_EN
SPI_EN
VDS_
BF_EN
1
VDS_
COMP_EN
Res.
4
5
EN_TCP
Res.
EN_CP
Res.
Res.
Res.
Res.
Res.
Table 10. Memory map EEPROM
Bit name
Description
Default
Driver configuration
DEAD_TIME[2:0]
VDSMON[2:0]
VDS_BLANK_TIME[1:0]
CUR_GAIN[2:0]
Defines the DEAD TIME between the HS FET and LS FET of the same phase
Defines the detection threshold level of the Vds monitoring
Defines the duration of the Vds monitor blanking time after the on-transition of the FET
Defines the gain of the current sense amplifier
011
111
10
011
1: VBOOST voltage is regulated relative to VSUP.
0: VBOOST voltage is regulated relative to ground
CPMODE
0
IC configuration
When set, the SPI block is enabled.
When reset, no SPI possible.
SPI_EN
1
1
1
(In SPI mode this value can only be programmed from 1 to 0, not from 0 to 1)
VREG Over voltage Bridge Feedback Enable
1: When VREG_OV=1 Bridge driver is SET in tri-state
0: When VREG_OV=1 No effect on Bridge driver.
VDS Bridge Feedback Enable
1: When VDS_ERR=1 Bridge driver is SET in tri-state
0: When VDS_ERR=1 No effect on Bridge driver.
1: VDS comparator enabled
0: VDS comparator disabled
1: VGS_UV comparator enabled
0: VGS_UV comparator disabled
1: PWM = FICOMF
VREG_OV_BF_EN
VDS_BF_EN
VDS_COMP_EN
VGS_UV_COMP_EN
PWM_SPEED
EN_CP
1
1
0
1
0: PWM = FICOMS
1: enables boost charge pump
0: disables boost charge pump
1: enables trickle charge pump
0: disables trickle charge pump
Undefined
EN_TCP
0
0
OUT_RESERVE_RG
Table 11. EEPROM bits
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Automotive NFET pre-drivers
8.5.2 SPI communication
When the chip is in SPI mode the EEPROM is programmable and readable via the SPI port.
8.5.2.1 Entering / exiting SPI mode
The MLX83203 will enter from NORMAL mode into SPI mode when ALL below conditions are present:
EN = 0
All FETTx = low AND all FETBx high (all FET inputs are disabled)
ICOM:
o
o
Any pending errors have been acknowledged
A Low Level pulse is applied on ICOM between 256us (2048/FOSC) and 512us (4096/FOSC)
The chip will return from SPI MODE to NORMAL MODE when
EN = 1.
This means that
any ongoing EEPROM writes will be completed
the EEPROM state machine will copy all EEPROM contents into registers
During this time the ICOM pin will be kept low.
Similar to when the MLX83203 comes out of POR, after leaving SPI MODE and returning to NORMAL
MODE, the MLX83203 will be blocked until the data have been copied to the registers. This assures that all
chip parameters are set correctly before starting.
Note: It only makes sense for the MCU to call for SPI if all errors are clear and acknowledged.
8.5.2.1 SPI protocol
Figure 10. SPI waveform example for read and write (LSB first)
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Automotive NFET pre-drivers
The 16 bit MISO/MOSI shift registers are controlled via 4 pins which are shared with other functions:
Pin
SPI signal Comment
FETB1
FETB2
FETB3
MISO
CLK
The signal on the MISO output is guaranteed to be stable while CLK is low
Clock input
MOSI
The MOSI shift register is reading in data on the rising edge of CLK
Frames are defined by CSB low and have to consist of 16 clock pulses on CLK.
On the rising edge of CSB:
If COMM_ERR=0 the read/write action is started as requested in the previous frame.
Else (COMM_ERR = MISO[14]=1): a communication error is detected. No action will
occur (EE_READY latch will remain 0). This can be:
Either due to a parity bit failure: MOSI[15] in frame N was incorrect.
Or because less or more then 16 rising edges were received during CSB low of
frame N
ICOM_IN
CSB
CSB has to remain high until the read (T_EE_RD) / write (T_EE_WR) action is completed.
In this case EE_READY= MISO[13] bit in the next frame will be high
Else IF CSB goes low before the requested action is completed
EE_READY= MISO[13] bit in the next frame will be low.
Table 12. SPI signals
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Automotive NFET pre-drivers
8.5.2.2 SPI registers
Figure 11. SPI REGISTERS and relation to internal Data latches
MOSI
Bit[7]
Bit[6]
MOSI_DATA [3:0]
Bit[5]
Bit[4]
Bit[3]
x
Bit[2]
Bit[1]
Address [2:0]
Bit[0]
Bit[8]
Bit[15]
Bit[14]
Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
CMD [1:0]
00: EE_RD
01: EE_WR
Mosi_Parity
x
x
MOSI_DATA [6:4]
10: EE_RDAW1
11: EE_RDAW2
MISO
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
MISO_DATA [3:0] (*)
x
The content from previous MOSI[2:0]
Bit[15]
Bit[14] Bit[13]
Bit[12]
Bit[11]
Bit[10]
Bit[9]
Bit[8]
The content from previous
MOSI[12:11]
Miso_ Parity COMM_ERR EE_READY
MISO_DATA [6:4] (*)
Table 13. SPI registers description
(*) MISO_DATA [10:4]
Comment
IF
The data received via MOSI have been shifted into the MISO
register. This allows the MCU to verify the correct data have
been transmitted.
MOSI(N)[11:12] = EE_WR (Write command)
THEN
MISO(N+1)[10:4] = MOSI(N)[10:4] from previous WR
instruction
In order to verify if the data have been correct stored into the
EEPROM, a dedicated read command is required.
In case a read command is received, the data in the MISO
register have been copied out of the designated address in the
EEPROM. Mind that 3 read consecutive read commands have
to be successful to ensure retention time.
ELSE
; MOSI(N)[11:12] <> EE_WR
MISO(N+1)[10:4] = EEPROM(address=MOSI(N)[2:0])
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Automotive NFET pre-drivers
8.5.2.3 Bit definition
Bit
Comment
MISO_PAR
MOSI_PAR
Odd parity of the actual data. So respectively the odd parity of the actual MOSI data, or the odd parity of the
actual MISO data.
0: EE_WR or EE_RD command were not completed when the new frame was started (on the falling edge of CSB)
1: No EE_WR or EE_RD activity ongoing on falling edge of CSB
EE_READY
1: Communication error occurred during the previous MOSI message. Possible errors:
COMM_ERR
Parity bit failure
Less or more the 16 rising edges received during CSB low
0: Previous dataframe was received ok: no communication error
EE_RD, EE_RDAW1, EE_RDAW2:
1. A MOSI frame is sent with command: MOSI[12:11] = EE_RD (below is also applicable for EE_RDAWx).
2. CSB is kept high long enough (>T_EE_RD) to ensure the read command can be completed. (else
EE_READY will be 0 in next MISO frame)
3. The requested data will be transmitted in the next MISO frame.
4. The data in this frame is valid in case
a. COMM_ERR = 0 (there was no comm. error during the previous MOSI frame)
b. EE_READY =1 (the read command was completed on the falling edge of CSB)
c. MISO [15] has the correct parity.
EE_WR
1. A MOSI frame N is sent with MOSI[12:11] = EE_WR.
2. CSB is kept high long enough (>T_EE_WR) to ensure the write command can be completed. (else
EE_READY will be 0 in next MISO frame)
3. The received data are used in the next MISO frame as a first verification step in a total of 3 steps need to
verify if the EE_WR was successful.
a. Verification of the N+1 MISO frame.
The N+1 MISO frame should have.
CMD [1:0]
i. COMM_ERR = 0 (there was no comm. error during the previous MOSI frame)
ii. EE_READY =1 (the EE_WR command was completed on the falling edge of CSB)
iii. MISO[15] has the correct parity.
iv. MISO_DATA(N+1) = MOSI_DATA(N)
b. Verification step2: EE_RDAW1:
The N+1 MOSI frame should have CMD = EE_RDAW1
Then the N+2 MISO frame should have.
i. COMM_ERR = 0 (there was no comm. error during the previous MOSI frame)
ii. EE_READY =1 (the EE_WR command was completed on the falling edge of CSB)
iii. MISO[15] has the correct parity.
iv. MISO_DATA(N+2) = MOSI_DATA(N)
c. Verification step3: EE_RDAW2:
The N+2 MOSI frame should have CMD = EE_RDAW2
Then the N+3 MISO frame should have.
i. COMM_ERR = 0 (there was no comm. error during the previous MOSI frame)
ii. EE_READY =1 (the EE_WR command was completed on the falling edge of CSB)
iii. MISO[15] has the correct parity.
iv. MISO_DATA(N+3) = MOSI_DATA(N)
Conclusion: in total 3 MOSI frames should be generated to ensure successful writing of data.
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4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
8.6 Current sense amplifier
The sense amplifier offers low input offset, and fast settling times. Its input range can be adjusted by applying
a suitable voltage on the VREF pin, typically as a resistor divider from VDD to GND. For the definition of
VREF, the input offset, the current range, and the linear output range of the ISENSE pin should all be taken
into account.
For input signal:
Vin = Visp - Visn,
Max input offset:
Voffsetmax = Vis_iomax + Trange * Vis_io_tdrift
(over full temperature range =Trange)
Visense = (Vin +/-Voffset)*IS_Gain + VREF has to be in the range [V_ISENSEmin, V_ISENSEmax]
Imin = [ (Visensemin – VREF) / IS_GAIN + Voffset ] / Rshunt
Imax = [ (Visensemax – VREF) / IS_GAIN - Voffset ] / Rshunt
Input offset voltage
Vis_io
Input offset voltage thermal drift
Vis_io_tdrift
Closed loop gain
IS_GAIN
ISENSE Output voltage range HIGH V_ISENSEmax
ISENSE Output voltage range LOW V_ISENSEmin
The below table shows the current input range (Amp) for two resistive divider settings on VREF:
1) VREF = VDD/2 for a symmetrical input range
2) VREF = VDD/18 for a maximum current level, while ensuring it is possible to measure the input
offset before starting the motor (Isense_min > 0A).
Remark: for ease of calculation a max temperature offset drift of 1mV was added to the 5mV offset
=> max input offset = 6mV
VDD
3.3
0.02
3.28
2
3.3
0.02
3.28
18
3(**)
0.02
2.98
2
3(**)
0.02
2.98
18
5
0.02
4.98
2
5
0.02
4.98
18
4.5(**)
0.02
4.48
2
4.5(**)
0.02
4.48
18
Visensemin
Visensemax
div
VREF
1.65
0.18
1.50
0.17
2.50
0.28
2.25
0.25
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Automotive NFET pre-drivers
Voffset
0.006
1
Isense min.
mOhm
gain
8
DIV2
DIV18
-14.4
-9.9
DIV2
-179
-138
-105
-80
DIV18
-12
DIV2
-304
-235
-180
-138
-106
-80
DIV18
-26.2
-19.0
-13.4
-9.0
DIV2
-273
-211
-162
-124
-94
DIV18
-23
-16
-11
-7
-198
-152
-117
-89
10.3
13.3
17.2
22.2
28.7
37.0
47.8
-8
-6.3
-5
-3.5
-3
-67
-1.4
-61
-0.6
0.9(*)
2.0(*)
3(*)
-5.6
-4
-51
0.3(*)
1.6(*)
2.6(*)
-46
-3.0
-72
-2
-38
-34
-61
-1.0
-54
0
-28
-25
-46
0.6
-41
1
Isense max.
gain
8
DIV2
198
152
117
89
DIV18
381
295
227
174
133
102
78
DIV2
179
138
105
80
DIV18
346
267
206
158
121
92
DIV2
304
235
180
138
106
80
DIV18
582
451
348
267
206
158
121
92
DIV2
273
211
162
124
94
DIV18
523
405
312
240
185
141
108
82
10.3
13.3
17.2
22.2
28.7
37.0
47.8
67
61
51
46
72
38
34
70
61
54
28
59
25
53
46
41
Table 14. Sense amplifier current ranges in Amp. Examples for 1mOhm shunt
Note:
(*) Applying a GAIN of 28.7 or higher with DIV 18 for 3.3V does not allow the measure the input offset
(**) examples taking a 10% supply variation into account.
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Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
8.7 FET driver implementation
8.7.1 Normal operation
The top side FET drivers are bootstrapped drivers. Each of the 6 external FET transistors can be controlled
directly via the 6 digital inputs. The 6 external FET transistors (or 3 half bridges) can also be controlled with
only 3 digital input signals. This can be done by connecting the FETTi to VDD and control the 3 phases via
the FETBi inputs. In this mode the MLX83203 will automatically generate the programmed dead times. Figure
12 shows the internal implementation of the driver stage from input to output.
The drain source voltage VDS as well as the gate voltage VGS are monitored to ensure fail safe operation.
The FET gate outputs are all pulled low by pulling EN low.
Figure 12. Internal implementation of the driver stage
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Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
8.7.2 FET driver during sleep mode
When the MLX83203 is in sleep mode a gate discharge resistance (Rsgd~1kOhm) is activated which
ensures the FET gates remain fully in OFF state.
Note that is the responsibility of the microcontroller to ensure all gate voltages are low, for instance by setting
the EN input low, prior to switching to sleep mode.
Figure 13. State of pre-driver in sleep mode
Figure 13 PHASEx is kept low with GATETx through the internal body diode of the pre-driver.
8.8 Charge pump
EEPROM configuration bits
Default
1: VBOOST voltage is regulated relative to VSUP.
0: VBOOST voltage is regulated relative to ground
1: enables boost charge pump
0: disables boost charge pump
CPMODE
EN_CP
0
1
Table 15. CP configuration in EEPROM
Standard operation of the Charge pump (CPMODE=0) is to ensure sufficient gate voltage to the bootstrap
capacitors in case of low battery voltage conditions. In this case VBOOST is regulated compared to GND
level. The charge pump will not be switching when VSUP > VREG + 2* Vf, with Vf= forward voltage of the
charge pump diodes.
Alternatively (CPMODE=1) the charge pump can regulate VBOOST compared to VSUP. In this case the
Cboost cap should be connected to VSUP to ensure any supply variations are coupled to the VBOOST level.
In this case VBOOST can be applied to drive a high side reverse polarity NFET.
The disadvantage is an additional amount of dissipation inside the driver to regulate VREG.
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Rev 2.2
Page 28 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
8.9 100% PWM with bootstrap
A current is drawn from the CP bootstrap pin to the phase pins. This current will discharge the gate voltage
on top of any external pull down gate resistance. The below tables show some calculation examples.
bootstrap
Vreg
330 nF
12
bootstrap
Vreg
100 nF
12
V
V
Qbootstr
3960 nC
Qbootstr
1200 nC
QFET
200 nC
QFET
120 nC
Vgs_initial
11.4
V
Vgs_initial
10.9
V
Rcp_leak
leakage
On time
Qleak
0.75 Mohm
15 uA
leakage
On time
Qleak
15 uA
10 ms
152 nC
60 ms
914 nC
Vgs_end
Vgs drop
9.4
V
V
Vgs_end
Vgs drop
9.8
V
V
2.06
1.13
This gate leakage will limit the maximum state time during which 100% PWM can be applied.
3901083203
Rev 2.2
Page 29 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
9 Standard information regarding manufacturability of Melexis
products with different soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity
level according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EIA/JEDEC JESD22-B102 and EN60749-21
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of
the use of certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality.asp
10 ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
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Rev 2.2
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Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
11 Package Information
11.1 Package data QFN32 (5x5, 32 leads)
A
A1
A3
b
D/E
D2/E2
e
K
L
N
min
0.80
0.00
0.20
REF
0.18
5.00
B.S.C
3.50
0.50
B.S.C
0.2
0.3
32
max
1.00
0.05
0.30
3.70
-
0.5
Table 16. Mechanical Dimensions QFN32 5x5, all dimensions in mm
[1]
[2]
General tolerance of D and E is +/-0.1mm
Bottom pin 1 identification may vary depending on supplier
Figure 14. Package QFN32
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Rev 2.2
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Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
11.2 Package data TQFP48_EP 7x7 (48 leads, exposed pad)
A
-
1.20
A1
0.05
0.15
A2
0.95
1.05
D/E
9.00
B.S.C
D1/E1
7.00
B.S.C
D2/E2
4.00
B.S.C
e
L
0.45
0.75
N
48
b
0.17
0.27
c
0.09
0.20
0o
7o
Min
Max
0.50
B.S.C
Table 17. Mechanical Dimensions TQFP48_EP 7x7, all dimensions in mm
Figure 15. Package TQFP48_EP
3901083203
Rev 2.2
Page 32 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
11.3 Package Marking
Product name:
Date Code:
Lot number
MLX8320X
YYWW
ZZZZZZZZ
X = 2 or 3
year and week
format free
Top view of the package
8320x
YYWW
ZZZZZZZZ
3901083203
Rev 2.2
Page 33 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
12 Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the
information set forth herein or regarding the freedom of the described devices from patent infringement.
Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with Melexis for current information. This
product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-
support or life-sustaining equipment are specifically not recommended without additional processing by
Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical
data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering
of technical or other services.
© Melexis NV. All rights reserved.
For the latest version of this document, go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe, Africa, Asia:
Phone: +32 1367 0495
E-mail: sales_europe@melexis.com
America:
Phone: +1 603 223 2362
E-mail: sales_usa@melexis.com
ISO/TS 16949 and ISO14001 Certified
3901083203
Rev 2.2
Page 34 of 35
Prelim. Data Sheet
4 Dec 2013
MLX83202/MLX83203
Automotive NFET pre-drivers
13 History of changes
Revision
Author
Date
Description
EE_RD meaning in SPI description corrected
RDSon specification split up in ON/OFF
Added RDSon for 83202 variant
Added package marking
1.1
DLM
1-3-12
28-3-12
1.2
DLM
TQFP48 pin out included
Added appl. Schematics, Pin internal structures, updated block diagram
Updated SPI enabling.
Updated ICOM duty cycles
Updated sleep mode
Updated leakage spec on VBATF
1.3
DLM
15-5-12
Max voltage on all pins
1.4
1.5
1.6
1.7
DLM
RRR
SOE
SOE
3-7-12
Final package dimensions.
Parameters updated per test data.
Device description updated
Information about DC variant of pre-driver moved to separate datasheet
Protection and diagnostic functions updated
Trickle Charge Pump included
28-11-12
21-12-12
15-01-13
26-02-13
2.0
2.1
2.1
SOE
SOE
SOE
06-05-13 Max voltage on phase pins updated
04-12-13 Entering SPI mode by disabling all 6x FET input signals
3901083203
Rev 2.2
Page 35 of 35
Prelim. Data Sheet
4 Dec 2013
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