W3H128M72ER-667SBC [MERCURY]
DDR DRAM, 128MX72, 0.5ns, CMOS, PBGA255, 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255;型号: | W3H128M72ER-667SBC |
厂家: | MERCURY UNITED ELECTRONICS INC |
描述: | DDR DRAM, 128MX72, 0.5ns, CMOS, PBGA255, 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总30页 (文件大小:1193K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
W3H128M72ER-XNBX
ADVANCED*
128M x 72 REGISTERED DDR2 SDRAM 255 PBGA
FEATURES
BENEFITS
Data rate = 667, 533, 400 Mb/s
45% Space savings vs. FBGA
Package:
Reduced part count
• 255 Plastic Ball Grid Array (PBGA), 23 x 21mm2
• 1.27mm pitch
51% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Core Supply Voltage = 1.8V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
* This product is under development, is not fully qualified or characterized and is subject to
change or cancellation without notice.
DLL for alignment of DQ and DQS transitions with clock
signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 4, 5 or 6
CK/CK# Termination options available
• 0 ohm, 20 ohm
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Commercial, Industrial and Military Temperature Ranges
1GByte Organized as 128M x 72
Weight: W3H128M72ER-XNBX - 4 grams max
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
W3H128M72ER-XNBX
S
A
V
I
N
G
S
5.5
11.5
11.5
11.5
11.5
11.5
21
84
FBGA
84
FBGA
84
FBGA
84
FBGA
84
FBGA
96
FBGA
14.0
13.5
W3H32M64EA-XSBX
23
Area
5 x 161mm2 + 1 x 74mm2 = 879mm2
5 x 84 balls + 1 x 96 balls = 516 balls
483mm2
45%
51%
I/O Count
255 Balls
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
CSB#
WEB#
RASB#
CASB#
CKEB
CS# WE# RAS# CAS# CKE
ODTB
ODT
A0-13
BA0-2
DQ0
DQ0
CK0
CK0#
CK
•
•
•
•
•
•
•
•
•
•
•
•
CK#
LDM0
LDM
U0
UDM0
UDM
LDQS0
LDQS0#
UDQS0
UDQS0#
LDQS
LDQS#
UDQS
UDQS#
DQ15
DQ15
74SSTUBF32866B
A0-13
BA0-2
CS# WE# RAS# CAS# CKE
ODT
A0-13
BA0-2
CK
DQ0
•
•
•
DQ16
•
•
•
CK1
CK1#
CAS#
RAS#
WE#
CS#
CASB#
U5
CK#
RASB#
WEB#
CSB#
CKEB
ODTB
LDM1
LDM
U1
•
•
•
•
•
•
UDM1
UDM
LDQS1
LDQS1#
UDQS1
UDQS1#
LDQS
LDQS#
UDQS
UDQS#
CKE
ODT
DQ15
DQ31
RESET# CK
CK#
RESET#
CKREG
CKREG#
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
•
•
•
DQ32
•
•
•
BA0-2
CK2
CK2#
CK
CK#
U2
LDM2
LDM
•
•
•
•
•
•
UDM2
UDM
LDQS2
LDQS2#
UDQS2
UDQS2#
LDQS
LDQS#
UDQS
UDQS#
DQ15
DQ47
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
•
•
•
DQ48
•
•
•
BA0-2
CK3
CK3#
CK
CK#
LDM3
LDM
U3
•
•
•
•
•
•
UDM3
UDM
LDQS3
LDQS3#
UDQS3
UDQS3#
LDQS
LDQS#
UDQS
UDQS#
DQ15
DQ63
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
•
•
•
•
•
DQ64
•
•
•
•
•
BA0-2
CK4
CK4#
CK
CK#
LDM4
LDM
U4
VCC
UDM
LDQS4
LDQS4#
UDQS4
UDQS4#
LDQS
LDQS#
UDQS
UDQS#
•
•
DQ7
DQ71
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
FIGURE 3 – PIN CONFIGURATION
TOP VIEW
NC
NC
NC
NC
NC
NC
Vss
Vss
Vss
Vss
NC
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
RAS#
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vcc
Vss
Vcc
NC
LDQS4
DQ70
DQ37
DQ50
DQ69
DQ66
DQ1
LDQS4#
LDQS2
DQ53
DQ55
DQ39
DQ23
DQ20
DQ4
UDQS3
LDQS2#
DQ64
DQ48
DQ34
DQ6
UDQS3#
Vcc
UDQS2#
UDQS4#
DQ42
UDQS2
UDQS4
DQ56
DQ40
DQ9
Vcc
Vss
NC
VSS
VSS
VCC
NC
VCC
NC
NC
NC
NC
Vcc
Vss
DQ45
DQ61
DQ28
DQ12
UDQS0#
UDQS0
UDM0
UDM1
UDM2
UDM3
DQ47
DQ63
Vss
NC
NC
Vcc
A11
A4
Vcc
Vss
DQ58
NC
CKE
ODT
Vcc
Vcc
Vss
Vss
A6
A8
Vcc
DQ32
DQ16
LDQS1
LDQS1#
DQ10
DQ26
DQ13
DQ29
Vcc
LDQS3#
LDQS3
LDQS0
LDQS0#
DQ30
NC
A13
Vss
Vss
Vcc
Vcc
A2
NC
NC
NC
DQ25
UDQS1#
UDQS1
DQ14
DQ15
DQ11
DNU
DNU
CKReg
CKReg#
CS#
NC
DNU
VSS
VSS
VCC
VCC
A12
A9
Vcc
Vcc
Vss
Vss
A1
A3
A0
Vss
Vss
Vcc
Vcc
DQ54
NC
DQ22
DQ3
A10
WE#
NC
BA0
Reset#
CAS#
BA1
Vss
NC
DQ5
LDM0
DQ2
DQ7
DQ18
DQ21
DQ0
DQ19
LDM2
LDM1
DQ67
LDM3
DQ71
DQ49
DQ27
BA2
NC
DQ36
DQ17
DQ52
DQ35
DQ65
LDM4
DQ8
A7
A5
NC
DQ31
DQ24
DQ46
DQ62
DQ43
DQ59
NC
CK2
CK2#
CK0#
CK0
CK1#
CK1
CK3#
CK3
Vss
CK4#
CK4
NC
Vcc
Vcc
Vcc
Vcc
Vss
Vcc
Vss
Vcc
Vcc
DQ38
Vref
DQ41
NC
VSS
VCC
VCC
NC
Vss
Vss
DQ60
NC
Vss
DQ68
DQ51
Vss
DQ44
VSS
Vss
DQ33
DQ57
Vcc
VSS
NOTE: Pins F1, F2, and G1 are reserved for the optional parity function. Please contact factory for more info.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
TABLE 1 – BALL DESCRIPTIONS
Symbol
Type
Description
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if
disabled via the LOAD MODE command.
ODT
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CK, CK#
CKE
Input
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE
is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during
self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once VCC is applied during first power-up. After VREF has
become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH operation, VREF must be maintained.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when
CS# is registered HIGH.
CS#
Input
Input
RAS#, CAS#, WE#
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4
LDM, UDM
BA0–BA2
Input
Input
Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–
BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10
HIGH) The address inputs also provide the op-code during a LOAD MODE command.
A0-A13
Input
DQ0-63
I/O
I/O
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
UDQS, UDQS#
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
LDQS, LDQS#
I/O
VCC
VREF
VSS
NC
Supply
Supply
Supply
-
Power Supply: I/O + Core; VCCQ is common to VCC
SSTL_18 reference voltage.
Ground
No connect: These balls should be left unconnected.
Future use; address bits A14 and A15 are reserved for future densities. Address bits F1, F2, and G2 are reserved for optional parity
function
DNU
-
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
DESCRIPTION
GENERAL NOTES
The 8Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-
access memory containing four 2Gb 2,147, 483, 648 bits chips.
Each of the four chips in the MCP are internally configured as
8-bank DRAM. The block diagram of the device is shown in Figure
2. Ball assignments and are shown in Figure 3.
• The functionality and the timing specifications discussed
in this data sheet are for the DLL-enabled mode of
operation.
• Throughout the data sheet, the various figures and text
refer to DQs as “DQ.” The DQ term is to be interpreted
as any and all DQ collectively, unless specifically stated
otherwise. Additionally, each chip is divided into 2 bytes,
the lower byte and upper byte. For the lower byte (DQ0–
DQ7), DM refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8–DQ15), DM refers to UDM and DQS
refers to UDQS.
The 8Gb DDR2 SDRAM uses a double-data-rate architecture to
achieve high-speed operation. The double data rate architecture is
essentially a 4n-prefetch architecture, with an interface designed
to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the 8Gb DDR2 SDRAM effectively consists
of a single 4n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and four corresponding n-bit-wide, one-half-clock-cycle
data transfers at the I/O balls.
• Complete functionality is described throughout the
document and any page or diagram may have been
simplified to convey a topic and may not be inclusive of
all requirements.
A bidirectional data strobe (DQS, DQS#) is transmitted externally,
along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM during READs and by
the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. There
are strobes, one for the lower byte (LDQS, LDQS#) and one for
the upper byte (UDQS, UDQS#).
• Any specific requirement takes precedence over a
general statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. The following
sequence is required for power up and initialization and is
shown in Figure 4 on page 7.
The 8Gb DDR2 SDRAM operates from a differential clock (CK and
CK#); the crossing of CK going HIGH and CK# going LOW will
be referred to as the positive edge of CK. Commands (address
and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of anACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write
burst lengths of four or eight locations. DDR2 SDRAM supports
interrupting a burst read of eight with another read, or a burst
write of eight with another write. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent operation,
thereby providing high, effective bandwidth by hiding row precharge
and activation time.
Aself refresh mode is provided, along with a power-saving power-
down mode.
All inputs are compatible with the JEDEC standard for SSTL_18.
All full drive-strength outputs are SSTL_18-compatible.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
FIGURE 4 – POWER-UP AND INITIALIZATION
VCC
VCC
L
V
CC
Q
1
1
tVTD
V
tt
Vref
Tk0
Tl0
Tm0
Tg0
Th0
Ti0
Tj0
Te0
Tf0
Tb0
Tc0
Td0
T0
Ta0
t
CK
CK#
CK
t
t
CL
CL
LVCMOS
SSTL_18
2
2
CKE low level
low level
ODT
10
REF
7
14
Valid
5
6
8
9
10
REF
11
12
13
LM
3
Command
LM
PRE
LM
LM
LM
PRE
LM
LM
NOP
15
DM
16
Address
Code
Code
Code
A10 = 1
Code
Code
Code
Code
A10 = 1
Valid
15
High-Z
DQS
15
High-Z
High-Z
DQ
Rtt
4
3
t
t
t
t
t
t
t
t
t
MRD
t
T = 400ns (MIN)
t
T = 200μs (MIN)
RPA
MRD
MRD
MRD
MRD
RPA
RFC
RFC
MRD
MRD
See no te 10
Power-up:
EMR(2)
EMR(3)
EMR
V
and stable
cldodck (CK, CK#)
MR without
EMR with
EMR with
OCD exit
DLL RESET OCD default
200 cycles of CK are required before a READ command can be issued
Normal
operation
MR with
DLL RESET
Indicates a Break in
Time Scale
Don’t care
NOTES:
1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee
TT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball
3. PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode Register, EMR =
extended mode register, EMR2 = extended mode register 2, EMR3 = extended mode register
3, REF = REFRESH command, ACT = ACTIVE command, A10 = PRECHARGE ALL, CODE
= desired value for mode registers (blank addresses are required to be decoded), VALID - any
valid command/address, RA = row address, bank address.
R
(all other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp
time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions
(A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF
,
and VTT are between their minimum and maximum values as stated in DC Operating Conditions
table):
4. DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS#,
DQ represents DQ0-71.
A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer
than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V. Once supply voltage ramping
is complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table specifications
apply.
5. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
6. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
7. Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command, provide LOW to
BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or "1;" all others must be "0".
8. Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command, provide HIGH to
BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0".
•
•
•
V
V
V
CC, VCCQ are driven from a single power converter output
TT is limited to 0.95V MAX
REF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp
time.
VCCQ ≥ VREF at all times
B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage ramping,
9. Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL ENABLE command
provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits E7, E8 and E9 can be set to "0" or
"1;" Micron recommends setting them to "0".
•
for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses
10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock the
DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA2 = BA1 = BA0 = 0.)
CKE must be HIGH the entire time. .
VCC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table
specifications apply.
• Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be ≤ 200ms
from when VCC ramps from 300mV to VCC (MIN)
11. Issue PRECHARGE ALL command.
12. Issue two or more REFRESH commands.
• Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program
operating parameters without resetting the DLL). To access the mode registers, BA0 = 0, BA1 =
0, BA2 = 0.
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
E9 to “1,” and then setting all other desired parameters. To access the extended mode register,
BA2 = 0, BA1 = 0, BA0 = 1.
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to
“0,” and then setting all other desired parameters. To access the extended mode registers, BA2
= 0, BA1 = 0, BA0 = 1.
16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the
DLL RESET at Tf0.
VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤ 500ms; while VCC is
ramping, current can be supplied from VCC through the device to VCCQ
VREF must track VCCQ/2, VREF must be within ±0.3V with respect to VCCQ/2 during supply
ramp time; VCCQ ≥ VREF must be met at all times
•
• Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT
(MIN) is achieved must be no greater than 500ms
2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-
up prior to VREF. being stable. After state T0, Cke is required to have SSTL_18 input levels.
Once CKE transitions to a high level, it must stay HIGH for the duration on the initialization
sequence.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
6
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
FIGURE 5 – MODE REGISTER (MR) DEFINITION
MODE REGISTER (MR)
The mode register is used to define the specific mode of operation
of the DDR2 SDRAM. This definition includes the selection of a
burst length, burst type, CL, operating mode, DLL RESET, write
recovery, and power-down mode, as shown in Figure 5. Contents of
the mode register can be altered by re-executing the LOAD MODE
(LM) command. If the user chooses to modify only a subset of the
MR variables, all variables (M0–M14) must be programmed when
the command is issued.
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
MR
0
0
PD
WR
DLL TM CAS# Latency BT Burst Length
Mode
Normal
Test
M7
0
M2 M1 M0
Burst Length
Reserved
Reserved
4
The mode register is programmed via the LM command (bits
BA2–BA0 = 0, 0, 0) and other bits (M12–M0) will retain the stored
information until it is programmed again or the device loses power
(except for bit M8, which is self-clearing). Reprogramming the
mode register will not alter the contents of the memory array,
provided it is performed correctly.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
PD mode
Fast Exit
(Normal)
Slow Exit
M12
0
DLL Reset
No
M8
0
8
1
Reserved
Reserved
Reserved
Reserved
1
Yes
(Low Power)
Write Recovery
M11 M10 M9
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts are in
progress. The controller must wait the specified time tMRD before
initiating any subsequent operations such as anACTIVE command.
Violating either of these requirements will result in unspecified
operation.
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
Burst Type
Sequential
Interleaved
M3
0
3
4
1
5
6
CAS Latency (CL)
M6 M5 M4
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
BURST LENGTH
Reserved
Mode Register Definition
Mode Register (MR)
M17 M16 M15
3
Burst length is defined by bits M0–M3, as shown in Figure 5. Read
and write accesses to the DDR2 SDRAM are burst-oriented, with
the burst length being programmable to either four or eight. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
0
1
0
1
0
0
0
0
0
0
1
1
4
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
5
6
Reserved
NOTE: Not all listed CL options are supported in any individual speed grades.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =
8 (where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved. The burst type is selected via bit M3,
as shown in Figure 5. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting
column address, as shown in Table 2. DDR2 SDRAM supports
4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,
full interleave address ordering is supported; however, sequential
address ordering is nibble-based.
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WR values of 2, 3, 4, 5, or 6 clocks may be used for programming
bits M9–M11. The user is required to program the value of WR,
which is calculated by dividing tWR (in ns) by tCK (in ns) and rounding
up a non integer value to the next integer; WR [cycles] = tWR [ns] /
TABLE 2 – BURST DEFINITION
Order of Accesses Within a Burst
Burst
Length
Starting Column
Address
Type = Sequential
Type = Interleaved
A1
0
A0
t
CK [ns]. Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
0
POWER-DOWN MODE
1
0
Active power-down (PD) mode is defined by bit M12, as shown
in Figure 5. PD mode allows the user to determine the active
power-down mode, which determines performance versus power
savings. PD mode bit M12 does not apply to precharge PD mode.
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-0-5-6-7-4
2-3-0-1-6-7-4-5
3-0-1-2-7-4-5-6
4-5-6-7-0-1-2-3
5-6-7-4-1-2-3-0
6-7-4-5-2-3-0-1
7-4-5-6-3-0-1-2
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
When bit M12 = 0, standard active PD mode or “fast-exit” active PD
mode is enabled. The tXARD parameter is used for fast-exit active
PD exit timing. The DLL is expected to be enabled and running
during this mode.
0
1
0
8
0
1
1
1
0
0
1
0
1
When bit M12 = 1, a lower-power active PD mode or “slow-exit”
active PD mode is enabled. The tXARD parameter is used for slow-
exit active PD exit timing. The DLL can be enabled, but “frozen”
during active PD mode since the exit-to-READ command timing is
relaxed. The power difference expected between PD normal and
PD low-power mode is defined in the ICC table.
1
1
0
1
1
1
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column
within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column
within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting
column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
OPERATING MODE
The normal operating mode is selected by issuing a command
with bit M7 set to “0,” and all other bits set to the desired values,
as shown in Figure 5. When bit M7 is “1,” no other bits of the
mode register are programmed. Programming bit M7 to “1” places
the DDR2 SDRAM into a test mode that is only used by the
manufacturer and should not be used. No operation or functionality
is guaranteed if M7 bit is ‘1.’
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 5.
Programming bit M8 to “1” will activate the DLL RESET function.
Bit M8 is self-clearing, meaning it returns back to a value of “0”
after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must
occur before a READ command can be issued to allow time for the
internal clock to be synchronized with the external clock. Failing
to wait for synchronization to occur may result in a violation of the
t
AC or tDQSCK parameters.
WRITE RECOVERY
Write recovery (WR) time is defined by bits M9–M11, as shown in
Figure 5. The WR register is used by the DDR2 SDRAM during
WRITE with auto precharge operation. During WRITE with auto
precharge operation, the DDR2 SDRAM delays the internal auto
precharge operation by WR clocks (programmed in bits M9–M11)
from the last data burst.
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CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure
5. CL is the delay, in clock cycles, between the registration of a
READ command and the availability of the first bit of output data.
The CL can be set to 4, 5 or 6 clocks, depending on the speed
grade option being used.
DDR2 SDRAM also supports a feature called posted CAS additive
latency (AL). This feature allows the READ command to be issued
prior to tRCD (MIN) by delaying the internal command to the DDR2
SDRAM by AL clocks.
An example of CL = 4 is shown in Figure 6; assume AL = 0. If a
READ command is registered at clock edge n, and the CL is m
clocks, the data will be available nominally coincident with clock
edge n+m (this assumes AL = 0).
DDR2 SDRAM does not support any half-clock latencies. Reserved
states should not be used as unknown operation or incompatibility
with future versions may result.
FIGURE 6 – CAS LATENCY (CL)
T0
T1
T2
T3
T4
T5
T6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
DQ
D
OUT
D
OUT
D
OUT
DOUT
n + 3
n
n + 1
n + 2
CL = 4 (AL = 0)
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
DON’T CARE
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EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are
DLL enable/disable, output drive strength, on die termination
(ODT) (RTT), posted AL, off-chip driver impedance calibration
(OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,
and output disable/enable. These functions are controlled via the
bits shown in Figure 7. The EMR is programmed via the LOAD
MODE (LM) command and will retain the stored information until it
is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts
are in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Extended Mode
Register (Ex)
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MRS
RTT RTT ODS DLL
Posted CAS#
0
0
out
OCD Program
RDQS DQS#
Outputs
Enabled
Disabled
E0
0
DLL Enable
Enable (Normal)
E12
0
RTT (nominal)
E6 E2
1
1
RTT disabled
0
0
1
1
0
1
0
1
Disable (Test/Debug)
75Ω
150Ω
50Ω
Output Drive Strength
RDQS Enable
E11
0
E1
0
No
Full strength (18Ω target)
1
Yes
1
Reduced strength (40Ω target)
E10 DQS# Enable
Posted CAS# Additive Latency (AL)
E5 E4 E3
0
1
Enable
Disable
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
E9 E8 E7
OCD Operation
OCD not supported1
3
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OCD default state1
Mode Register Set
Mode register set (MRS)
E17 E16 E15
0
1
0
1
0
0
0
0
0
0
1
1
Extended mode register (EMRS)
Extended mode register (EMRS2)
Extended mode register (EMRS3)
NOTES:
1. During initialization, all three bits must be set to "1" for OCD default state, then must be
set to "0" before initialization is finished, as detailed in the initialization procedure.
2. E14 (A14) is not used on this device.
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elected by enabling switch “sw1,” which enables all R1 values that
are 150Ω each, enabling an effective resistance of 75Ω (RTT2(EFF)
= R2/2). Similarly, if “sw2” is enabled, all R2 values that are 300Ω
each, enable an effective ODT resistance of 150Ω (RTT2(EFF) =
R2/2). Switch “sw3” enables R1 values of 100Ω enabling effective
resistance of 50Ω Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
DLL ENABLE/DISABLE
The DLL may be enabled or disabled by programming bit E0
during the LM command, as shown in Figure 7. The DLL must
be enabled for normal operation. DLL enable is required during
power-up initialization and upon returning to normal operation after
having disabled the DLLfor the purpose of debugging or evaluation.
Enabling the DLL should always be followed by resetting the DLL
using an LM command.
The ODT control ball is used to determine when RTT(EFF) is turned
on and off, assuming ODT has been enabled via bits E2 and E6 of
the EMR. The ODT feature and ODT input ball are only used during
active, active power-down (both fast-exit and slow-exit modes), and
precharge power-down modes of operation. ODT must be turned
off prior to entering self refresh. During power-up and initialization
of the DDR2 SDRAM, ODT should be disabled until issuing the
EMR command to enable the ODT feature, at which point the ODT
ball will determine the RTT(EFF) value. Any time the EMR enables
the ODT function, ODT may not be driven HIGH until eight clocks
after the EMR has been enabled. See “ODT Timing” section for
ODT timing diagrams.
The DLL is automatically disabled when entering SELF REFRESH
operation and is automatically re-enabled and reset upon exit of
SELF REFRESH operation.
Any time the DLL is enabled (and subsequently reset), 200 clock
cycles must occur before a READ command can be issued, to
allow time for the internal clock to synchronize with the external
clock. Failing to wait for synchronization to occur may result in a
violation of the tAC or tDQSCK parameters.
OUTPUT DRIVE STRENGTH
The output drive strength is defined by bit E1, as shown in Figure
7. The normal drive strength for all outputs are specified to be
SSTL_18. Programming bit E1 = 0 selects normal (full strength)
drive strength for all outputs. Selecting a reduced drive strength
option (E1 = 1) will reduce all outputs to approximately 60 percent of
the SSTL_18 drive strength. This option is intended for the support
of lighter load and/or point-to-point environments.
DQS# ENABLE/DISABLE
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is
the complement of the differential data strobe pair DQS/DQS#.
When disabled (E10 = 1), DQS is used in a single ended mode
and the DQS# ball is disabled. When disabled, DQS# should be
left floating. This function is also used to enable/disable RDQS#. If
RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then
both DQS# and RDQS# will be enabled.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by bit E12, as shown in
Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#,
RDQS, RDQS#) function normally. When disabled (E12 = 1), all
DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are
disabled, thus removing output buffer current. The output disable
feature is intended to be used during ICC characterization of read
current.
ON-DIE TERMINATION (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6
of the EMR, as shown in Figure 7. The ODT feature is designed
to improve signal integrity of the memory channel by allowing the
DDR2 SDRAM controller to independently turn on/off ODT for any
or all devices. RTT effective resistance values of 50Ω ,75Ω, and
150Ω are selectable and apply to each DQ, DQS/DQS#, RDQS/
RDQS#, UDQS/UDQS#, LDQS/LDQS# and UDM/LDM signals.
Bits (E6, E2) determine what ODT resistance is enabled by turning
on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
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POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in
Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an inverseAL of 0, 1, 2, 3, or 4 clocks. Reserved states should
not be used as unknown operation or incompatibility with future
versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE
command to be issued prior to tRCD (MIN) with the requirement
that AL ≤ tRCD (MIN). A typical application using this feature would
set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is
held for the time of theAL before it is issued internally to the DDR2
SDRAM device. RL is controlled by the sum of AL and CL; RL =
AL+CL. Write latency (WL) is equal to RL minus one clock; WL =
AL + CL - 1 x tCK
.
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Extended Mode
Register (Ex)
17 16 15 14 13 12 11 10
EMR2
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
Mode Register Definition
Mode register (MR)
M17 M16 M15
High Temperature Self Refresh rate enable
Commercial temperature default
E7
0
1
0
1
0
0
0
0
0
0
1
1
0
1
Extended mode register (EMR)
Industrial temperature option;
use if TC exceeds 85°C
Extended mode register (EMR2)
Extended mode register (EMR3)
NOTE: 1. E14 (A14)-E8(A8) and E6 (A6) - E0 (A0) are reserved for future use and
must be programmed to "0." A14 is not used in this device.
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EXTENDED MODE REGISTER 2
EXTENDED MODE REGISTER 3
The extended mode register 2 (EMR2) controls functions beyond
those controlled by the mode register. Currently all bits in EMR2
are reserved, as shown in Figure 8. The EMR2 is programmed
via the LM command and will retain the stored information until it
is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
The extended mode register 3 (EMR3) controls functions beyond
those controlled by the mode register. Currently, all bits in EMR3
are reserved, as shown in Figure 9. The EMR3 is programmed
via the LM command and will retain the stored information until it
is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
Bit E7 (A7) must be programmed as"1" to provide a faster refresh
rate on devices if the TCASE exceeds 85°C
EMR3 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
EMR2 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
COMMAND TRUTH TABLES
The following tables provide a quick reference of DDR2 SDRAM
available commands, including CKE power-down modes, and
bank-to-bank commands.
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Extended Mode
Register (Ex)
17 16 15 14 13 12 11 10
EMR3
9
0
8
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Mode Register Definition
Mode register (MR)
M17 M16 M15
0
1
0
1
0
0
0
0
0
0
1
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
NOTE: 1. E14 (A14)-E0 (A0) are reserved for future use and must be programmed to "0." A14 is not used in this device.
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TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
CKE
BA2
A13
Function
CS#
RAS#
CAS#
WE#
BA1
BA0
A12
A11
A10
A9-A0
Notes
Previous
Cycle
Current Cycle
LOAD MODE
REFRESH
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
H
H
X
H
L
BA
X
OP Code
2
X
X
X
X
X
X
SELF-REFRESH Entry
L
X
X
H
H
H
H
SELF-REFRESH Exit
L
H
X
X
X
X
7
2
Single bank precharge
All banks PRECHARGE
Bank activate
H
H
H
H
H
H
X
X
X
X
L
H
X
X
L
L
BA
Row Address
Column
Address
Column
Address
WRITE
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
L
BA
BA
BA
BA
L
H
L
2, 3
2, 3
2, 3
2, 3
Column
Address
Column
Address
WRITE with auto precharge
READ
Column
Address
Column
Address
H
H
Column
Address
Column
Address
READ with auto precharge
H
NO OPERATION
H
H
X
X
L
H
H
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
Device DESELECT
POWER-DOWN entry
POWER-DOWN exit
H
L
L
X
X
X
X
X
X
X
X
4
4
H
L
H
NOTES:
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level).
7. Self refresh exit is asynchronous.
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FIGURE 10 – ACTIVE COMMAND
DESELECT
The DESELECT function (CS# HIGH) prevents new commands
from being executed by the DDR2 SDRAM. The DDR2 SDRAM
is effectively deselected. Operations already in progress are not
affected.
CK#
CK
CKE
CS#
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the
selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,
CAS#, and WE are HIGH). This prevents unwanted commands
from being registered during idle or wait states. Operations already
in progress are not affected.
RAS#
CAS#
WE#
LOAD MODE (LM)
The mode registers are loaded via inputs BA2–BA0, andA12–A0.
BA2–BA0 determine which mode register will be programmed.
See “Mode Register (MR)”. The LM command can only be issued
when all banks are idle, and a subsequent execute able command
cannot be issued until tMRD is met.
Row
ADDRESS
BANK ADDRESS
Bank
BANK/ROW ACTIVATION
ACTIVE COMMAND
DON’T CARE
The ACTIVE command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the BA2–
BA0 inputs selects the bank, and the address provided on inputs
A12–A0 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a different
row in the same bank.
ACTIVE OPERATION
Before any READ or WRITE commands can be issued to a
bank within the DDR2 SDRAM, a row in that bank must be
opened (activated), even when additive latency is used. This is
accomplished via the ACTIVE command, which selects both the
bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ or
WRITE command may be issued to that row, subject to the tRCD
specification. tRCD (MIN) should be divided by the clock period and
rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or
WRITE command can be entered. The same procedure is used
to convert other specification limits from time units to clock cycles.
For example, a tRCD (MIN) specification of 20ns with a 266 MHz
clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6.
A subsequent ACTIVE command to a different row in the same
bank can only be issued after the previous active row has
been closed (precharged). The minimum time interval between
successiveACTIVE commands to the same bank is defined by tRC
A subsequent ACTIVE command to another bank can be issued
while the first bank is being accessed, which results in a reduction
of total row-access overhead. The minimum time interval between
successiveACTIVE commands to different banks is defined by tRRD
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FIGURE 11 – READ COMMAND
READ COMMAND
The READ command is used to initiate a burst read access to an
active row. The value on the BA2–BA0 inputs selects the bank,
and the address provided on inputs A0–i (where i = A9) selects
the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end
of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
CK#
CK
CKE
CS#
READ OPERATION
RAS#
CAS#
READ bursts are initiated with a READ command. The starting
column and bank addresses are provided with the READ command
and auto precharge is either enabled or disabled for that burst
access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto
precharge is disabled, the row will be left open after the completion
of the burst.
WE#
ADDRESS
Col
During READ bursts, the valid data-out element from the starting
column address will be available READ latency (RL) clocks later.
RL is defined as the sum of AL and CL; RL = AL + CL. The value
forAL and CL are programmable via the MR and EMR commands,
respectively. Each subsequent data-out element will be valid
nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#).
ENABLE
A10
AUTO PRECHARGE
BANK ADDRESS
DISABLE
Bank
DON’T CARE
DQS/DQS# is driven by the DDR2 SDRAM along with output data.
The initial LOW state on DQS and HIGH state on DQS# is known
as the read preamble (tRPRE). The LOW state on DQS and HIGH
state on DQS# coincident with the last data-out element is known
as the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have
been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with data from a
subsequent READ command to provide a continuous flow of data.
The first data element from the new burst follows the last element
of a completed burst. The new READ command should be issued x
cycles after the first READ command, where x equals BL/ 2 cycles.
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The time between the WRITE command and the first rising DQS
edge is WL ± tDQSS. Subsequent DQS positive rising edges are
timed, relative to the associated clock edge, as ± tDQSS. tDQSS is
specified with a relatively wide range (25 percent of one clock
cycle). All of the WRITE diagrams show the nominal case, and
where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might
not be intuitive, they have also been included. Upon completion of
a burst, assuming no other commands have been initiated, the DQ
will remain High-Z and any additional input data will be ignored.
WRITE COMMAND
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA2–BA0 inputs selects the bank,
and the address provided on inputs A0–9 selects the starting
column location. The value on input A10 determines whether or
not auto precharge is used. If auto precharge is selected, the
row being accessed will be precharged at the end of the WRITE
burst; if auto precharge is not selected, the row will remain open
for subsequent accesses.
Data for any WRITE burst may be concatenated with a subsequent
WRITE command to provide continuous flow of input data. The first
data element from the new burst is applied after the last element
of a completed burst. The new WRITE command should be issued
x cycles after the first WRITE command, where x equals BL/2.
Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW, the corresponding
data will be written to memory; if the DM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
DDR2 SDRAM supports concurrent auto precharge options, as
shown in Table 4.
WRITE OPERATION
DDR2 SDRAM does not allow interrupting or truncating any WRITE
burst using BL = 4 operation. Once the BL = 4 WRITE command is
registered, it must be allowed to complete the entire WRITE burst
cycle. However, a WRITE (with auto precharge disabled) using BL
= 8 operation might be interrupted and truncated ONLY by another
WRITE burst as long as the interruption occurs on a 4-bit boundary,
due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst
BL = 8 operations may not to be interrupted or truncated with any
command except another WRITE command.
WRITE bursts are initiated with a WRITE command, as shown in
Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock
cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and
bank addresses are provided with the WRITE command, and auto
precharge is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is precharged at
the completion of the burst.
During WRITE bursts, the first valid data-in element will be
registered on the first rising edge of DQS following the WRITE
command, and subsequent data elements will be registered on
successive edges of DQS. The LOW state on DQS between the
WRITE command and the first rising edge is known as the write
preamble; the LOW state on DQS following the last data-in element
is known as the write postamble.
Data for any WRITE burst may be followed by a subsequent READ
command. The number of clock cycles required to meet tWTR is
either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst
may be followed by a subsequent PRECHARGE command. tWT
starts at the end of the data burst, regardless of the data mask
condition.
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FIGURE 12 – WRITE COMMAND
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
CA
ADDRESS
EN AP
A10
DIS AP
BANK ADDRESS
BA
DON’T CARE
NOTE: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge.
TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE
Minimum Delay (With Concurrent Auto
Precharge)
From Command (Bank n)
To Command (Bank m)
Units
READ OR READ w/AP
WRITE or WRITE w/AP
PRECHARGE or ACTIVE
(CL-1) + (BL/2) + tWTR
tCK
tCK
tCK
WRITE with Auto Precharge
(BL/2)
1
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FIGURE 13 – PRECHARGE COMMAND
PRECHARGE COMMAND
The PRECHARGE command, illustrated in Figure 13, is used
to deactivate the open row in a particular bank or the open row
in all banks. The bank(s) will be available for a subsequent row
activation a specified time (tRP) after the PRECHARGE command
is issued, except in the case of concurrent auto precharge, where
a READ or WRITE command to a different bank is allowed as long
as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Once a bank has
been precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank. A
PRECHARGE command is allowed if there is no open row in that
bank (idle state) or if the previously open row is already in the
process of precharging. However, the precharge period will be
determined by the last PRECHARGE command issued to the bank.
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
PRECHARGE OPERATION
InputA10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged, inputs BA2–
BA0 select the bank. Otherwise BA2–BA0 are treated as “Don’t Care.”
ADDRESS
ALL BANKS
A10
When all banks are to be precharged, inputs BA2–BA0 are treated
as “Don’t Care.” Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. tRPA timing applies when the
PRECHARGE (ALL) command is issued, regardless of the number
of banks already open or closed. If a single-bank PRECHARGE
command is issued, tRP timing applies. tRPA (MIN) applies to all
8-bank DDR2 devices.
ONE BANK
BA0 - BA2
BA
DON’T CARE
NOTE: BA = bank address (if A10 is LOW; otherwise "Don't Care").
SELF REFRESH COMMAND
The SELF REFRESH command can be used to retain data in the
DDR2 SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR2 SDRAM retains data
without external clocking. All power supply inputs (including VREF
)
must be maintained at valid levels upon entry/exit and during SELF
REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH
command except CKE is LOW. The DLL is automatically disabled
upon entering self refresh and is automatically enabled upon exiting
self refresh (200 clock cycles must then occur before a READ
command can be issued). The differential clock should remain
stable and meet tCKE specifications at least 1 x tCK after entering
self refresh mode. All command and address input signals except
CKE are “Don’t Care” during self refresh.
The procedure for exiting self refresh requires a sequence of
commands. First, the differential clock must be stable and meet
tCK specifications at least 1 x tCK prior to CKE going back HIGH.
Once CKE is HIGH (tCLE(MIN) has been satisfied with four clock
registrations), the DDR2 SDRAM must have NOP or DESELECT
commands issued for tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm
for meeting both refresh and DLL requirements is to apply NOP
or DESELECT commands for 200 clock cycles before applying
any other command.
NOTE: Self refresh not available at military temperature..
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ADVANCED
REGISTER FUNCTION TABLES
Inputs
Output
RESET
DCS#
CSR#
CLK
CLK#
Dn
H
H
H
H
H
H
L
L
X
↑
↓
L
L
H
L
X
↑
↓
H
X
L
↑
↓
L
L
X
L
↑
↑
↓
↓
H
H
H
X
H
X
X
X
Q0
Q0
L
L or H
X or floating
L or H
X or floating
X or floating
X or floating
X or floating
Inputs
Outputs
RESET#
CLK
↑
CLK#
DCKE, DCS, DODT
QCKE, QCS#, QODT
H
H
H
L
↓
↓
H
H
L
↑
L
X
L or H
L or H
X or floating
Q0
L
X or floating
X or floating
REGISTER RECOMMENDED OPERATING CONDITIONS*
Symbol
VCC
VREF
VI
Parameter
Test Condition
MIN
1.7
NOM
MAX
UNIT
Supply voltage
1.9
0.51 x VCC
VCC
V
V
V
V
V
Reference voltage
0.49 x VCC
0
0.5 x VCC
Input voltage
VIH
AC high-level input voltage
AC low-level input voltage
Data inputs, CSR#
Data inputs, CSR#
VREF +250 mV
VIL
VREF -250mV
VREF -125mV
VIH
DC high-level input voltage
Data inputs, CSR#
VREF +125mV
0.65 x VCC
V
VIL
VIH
DC low-level input voltage
High-level input voltage
Data inputs, CSR#
RESET#, Cn
RESET#, Cn
CLK, CLK#
V
V
VIL
Low-level input voltage
0.35 x VCC
1.125
V
VICR
VI(PP)
Common-mode input voltage range
Peak-to-peak input voltage
0.675
600
V
CLK, CLK#
mV
* The RESET# and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET# is low.
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ADVANCED
REGISTER ELECTRICAL CHARACTERISTICS*
Symbol
Parameter
All inputs
Test Conditions
VCC
MIN
TYP1
MAX
±5
UNIT
μA
IL
VI = VCC or GND
RESET# = GND
1.9 V
Static standby
100
40
μA
ICC
IO = 0
Static operating
RESET# = VCC, VI = VIH(AC) or VIL(AC)
1.9 V
1.8 V
mA
RESET# = VCC, VI = VIH(AC) or VIL(AC), CLK and
CLK# switching 50% duty cycle
Dynamic operating clock
28
18
μA/MHz
RESET# = VCC, VI = VIH(AC) or VIL(AC), CLK and
CLK# switching 50% duty cycle, one data input
switching at one-half clock frequency, 50% duty
cycle
ICCD
IO = 0
μA/clock
MHz/D
input
Dynamic operating per
each data input
Chip-select-enabled
low-power active mode -
clock only
RESET# = VCC, VI = VIH(AC) or VIL(AC)CLK and
CLK# switching 50% duty cycle
27
2
μA/MHz
ICCDLP
IO = 0
1.8 V
RESET# = VCC, VI = VIH(AC) or VIL(AC), CLK and
CLK# switching 50% duty cycle, one data input
switching at one-half cock frequency, 50% duty
cycle
μA/clock
MHz/D
input
Chip-select-enabled low-
power active mode
1 All typical calues are at VCC = 1.8 v, TA = 25ºC.
REGISTER TIMING REQUIREMENTS
(note1)
Symbol
Parameter
Test Conditions
MIN
MAX
UNIT
MHz
ns
fclock
tw
Clock frequency
500
Pulse duration, CLK, CLK# high or low
Differential inputs active time (see note 2)
Differential inputs inactive time (see note 3)
1
tact
10
15
ns
tinact
ns
DCS# before CLK↑, CLK#↓, CSR# high,CSR# before
CLK↑, CLK↓, DCS# high
0.7
tsu
Set up time
ns
ns
DCS# before CLK↑,CLK#↓, CSR# low
0.5
0.5
0.5
DODT, DCKE, and Data before CLK↑, CLK#↓
DCS#, DODT, DCKE, and Data after CLK↑, CLK#↓
th
Hold time
NOTES:
1. All input slew rates are 1 V/ns ±20%
2.
3.
V
V
REF must be held at a valid input level and data inputs must be held low for a minimum time of tactmax, after RESET# is taken high.
REF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinactmax, after RESET# is taken low.
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DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1 .7
Typical
1 .8
Max
1 .9
Unit
V
Notes
Supply voltage
I/O Reference voltage
I/O Termination voltage
NOTES:
1
2
3
VREF
VTT
0.49 x VCCQ
VREF-0.04
0.50 x VCCQ
VREF
0.51 x VCCQ
VREF + 0.04
V
V
1.
2.
V
V
CC and VCCQ are tied on the device.
REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise
on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3.
V
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VCC/ VCCQ
VIN, VOUT
TSTG
MIN
-0.5
-0.5
-55
-20
-5
MAX
2.3
2.3
125
20
U nit
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage temperature
V
°C
μA
μA
μA
IL
Input leakage current; Any input 0V<VIN<VCC; Other pins not under test = 0V
Output leakage current; 0V<VOUT<VCC; DQs and ODT are disabled
VREF leakage current; VREF = Valid VREF level
IOZ
5
IVREF
-8
8
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 1.8V
Parameter
Symbol
CIN1
Max
TBD
TBD
TBD
TBD
Unit
pF
Input capacitance (A0 - A13, BA0 - BA2 ,CS#, RAS#,CAS#,WE#, CKE, ODT)
Input capacitance CK, CK#
CIN2
pF
Input capacitance DM, DQS, DQS#
CIN3
pF
Input capacitance DQ0 - 63
COUT
pF
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W3H128M72ER-XNBX
ADVANCED
BGA THERMAL RESISTANCE
Description
Symbol
Theta JA
Theta JB
Theta JC
Typical
19.7
Units
°C/W
°C/W
°C/W
Notes
Junction to Ambient (No Airflow)
Junction to Ball
1
1
1
20.6
Junction to Case (Top)
10.8
NOTE: These typical thermal resistances are for each DRAM die, if using the total power of the MCP, divide the given values by 4.
Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.whiteedc.com in the application notes section for modeling conditions.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.1 25
-0.300
Max
Unit
V
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VCC + 0.300
VREF - 0.125
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
—
Unit
V
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667
VREF + 0.250
VREF + 0.200
—
V
—
—
VREF - 0.250
VREF - 0.200
V
V
ODT DC ELECTRICAL CHARACTERISTICS
All voltages referenced to VSS
Symbol
RTT1(EFF)
RTT2(EFF)
RTT3(EFF)
∆VM
Min
52
Nom
75
Max
97
Unit
Ω
Notes
Parameter
R
TT effective impedance value for 75Ω setting EMR (A6, A2) = 0, 1
TT effective impedance value for 150Ω setting EMR (A6, A2) = 1, 0
1
1
1
2
R
105
35
150
50
195
65
Ω
RTT effective impedance value for 50Ω setting EMR (A6, A2) = 1, 1
Ω
Deviation of VM with respect to VCCQ/2
-6
6
%
NOTES: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL (AC) to the ball being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.
RTT(EFF)
=
VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC)
)
2. Measure voltage (VM) at tested ball with no load
∆VM =
(
2 x VM - 1
VCC
)
x 100
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W3H128M72ER-XNBX
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
-55°C ≤ TA ≤ 125°C
Symbol
Proposed Conditions
667 CL6 533 CL5 400 CL4
Units
Operating one bank active-precharge current;
ICC0
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
540
640
32
460
540
32
460
540
32
mA
Operating one bank active-read-precharge current;
ICC1
ICC2P
ICC2Q
ICC2N
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is
mA
mA
mA
mA
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
260
280
180
240
160
200
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
160
40
140
40
120
40
mA
mA
ICC3P
Active standby current;
ICC3N
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
300
220
760
200
640
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC4W
1,000
Operating burst read current;
ICC4R
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING
1,100
1,120
16
780
1,040
16
720
1,000
16
mA
mA
mA
Burst auto refresh current;
ICC5
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
ICC6
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
Normal
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC),
tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data bus inputs are switching
ICC7
1,580
1,420
1,420
mA
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W3H128M72ER-XNBX
ADVANCED
AC TIMING PARAMETERS
-55°C ≤ TA ≤ +125°C
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Parameter
DQ hold skew factor
Symbol
Min
-
Max
340
Min
Max
400
Min
Max
tQHS
tAC
-
-
450
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
DQS Low-Z window from CK/CK#
DQ Low-Z window from CK/CK#
-450
450
-500
+500
-600
+600
tHZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ1
tLZ2
tDSa
tDHa
tDSb
tDHb
tDIPW
tQHS
tAC(MN)
2*tAC(MN)
300
tAC(MN)
2*tAC(MN)
350
tAC(MN)
2*tAC(MN)
400
300
350
400
DQ and DM input setup time relative to DQS
100
100
150
175
225
275
DQ and DM input pulse width (for each input)
Data hold skew factor
0.35
0.35
0.35
340
400
450
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tQH - tDQSQ
0.35*tCK
0.35*tCK
-400
tQH - tDQSQ
0.35*tCK
0.35*tCK
-450
tQH - tDQSQ
0.35*tCK
0.35*tCK
-500
ns
tCK
tCK
ps
DQS input low pulse width
DQS output access time fromCK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
400
240
+450
300
+500
350
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
tCK
tCK
tDSH
DQS-DQ skew, DOS to last DQ valid, per group, per
access
tDQSQ
ps
DQS read preamble
tRPRE
tRPST
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
tWPRES
DQS write preamble
tWPRE
0.35
0.25
0.25
tCK
DQS write postamble
tWPST
tDQSS
0.4*tCK
-0.25*tCK
WL-tDQSS
0.6*tCK
0.25*tCK
WL+tDQSS
0.4*tCK
-0.25*tCK
WL-tDQSS
0.6*tCK
0.25*tCK
WL+tDQSS
0.4*tCK
-0.25*tCK
WL-tDQSS
0.6*tCK
0.25*tCK
WL+tDQSS
tCK
tCK
tCK
Positive DQS latching edge to associated clock edge
Write command to first DQS latching transition
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
25
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
AC TIMING PARAMETERS (continued)*
-55°C ≤ TA ≤ +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Parameter
DQ hold skew factor
Symbol
Min
Max
400
Min
-
Max
400
Min
Max
tQHS
tAC
-
-
450
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
DQS Low-Z window from CK/CK#
DQ Low-Z window from CK/CK#
-500
+500
-500
+500
-600
+600
tHZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ1
tLZ2
tDSa
tDHa
tDSb
tDHb
tDIPW
tQHS
tAC(MN)
2*tAC(MN)
350
tAC(MN)
2*tAC(MN)
350
tAC(MN)
2*tAC(MN)
400
350
350
400
DQ and DM input setup time relative to DQS
100
100
150
225
225
275
DQ and DM input pulse width (for each input)
Data hold skew factor
0.35
0.35
0.35
400
400
450
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tQH - tDQSQ
0.35*tCK
0.35*tCK
-450
tQH - tDQSQ
0.35*tCK
0.35*tCK
-450
tQH - tDQSQ
0.35*tCK
0.35*tCK
-500
ns
tCK
tCK
ps
DQS input low pulse width
DQS output access time fromCK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
+450
240
+450
300
+500
350
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
tCK
tCK
tDSH
DQS-DQ skew, DOS to last DQ valid, per group,
per access
tDQSQ
ps
DQS read preamble
tRPRE
tRPST
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
tWPRES
DQS write preamble
tWPRE
0.35*tCK
0.25*tCK
0.25
tCK
DQS write postamble
tWPST
tDQSS
0.4*tCK
-0.25*tCK
WL-tDQSS
0.6*tCK
0.25*tCK
WL+tDQSS
0.4*tCK
-0.25*tCK
WL-tDQSS
0.6*tCK
0.25*tCK
WL+tDQSS
0.4*tCK
-0.25*tCK
WL-tDQSS
0.6*tCK
0.25*tCK
WL+tDQSS
tCK
tCK
tCK
Positive DQS latching edge to associated clock edge
Write command to first DQS latching transition
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
26
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
AC TIMING PARAMETERS (continued)
-55°C ≤ TA ≤ +125°C
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Parameter
Address and control input pulse width for each input
Symbol
Min
Max
Min
0.6
Max
Min
Max
tIPW
tISa
0.6
400
200
400
275
2
0.6
tCK
ps
ps
ps
ps
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
500
250
500
375
2
600
350
600
475
2
Address and control input setup time
Address and control input hold time
tISb
tIHa
tIHb
CAS# to CAS# command delay
tCCD
tRC
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
55
55
55
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
10
10
10
15
15
15
50
50
50
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
40
70,000
40
70,000
40
70,000
7.5
7.5
7.5
15
15
15
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
tDAL
tWTR
tRP
tWR + tRP
7.5
tWR + tRP
7.5
tWR + tRP
10
15
15
15
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
tRPA
tMRD
tDELAY
tRP + tCK
2
tRP + tCK
2
tRP + tCK
2
tIS +tIH + tCK
tIS +tIH + tCK
tIS +tIH + tCK
REFRESH to Active or Refresh to Refresh command
interval
tRFC
tREFI
197.5
70,000
197.5
70,000
197.5
70,000
ns
Average periodic refresh interval (commercial and
industrial)
7.8
7.8
7.8
μs
Average periodic refresh interval (military)
Exit self refresh to non-READ command
Exit self refresh to READ
Exit self refresh timing reference
ODT tum-on delay
tREFIM
tXSNR
tXSRD
tlSXR
1.95
1.95
1.95
μs
ns
tCK
ps
tCK
ps
tCK
ps
tRFC(MIN) + 10
tRFC(MIN) + 10
tRFC(MIN) + 10
200
tIS
200
tIS
200
tIS
tAOND
tAON
tAOFD
tAOF
2
2
2
2
2
2
ODT turn-on
tAC(MIN)
2.5
tAC(MAX) + 700
2.5
tAC(MIN)
2.5
tAC(MAX) + 1000
2.5
tAC(MIN)
2.5
tAC(MAX) + 1000
2.5
ODT turn-off delay
ODT tum-off
tAC(MIN)
tAC(MAX) + 600
tAC(MIN)
tAC(MAX) + 600
tAC(MIN)
tAC(MAX) + 600
tAC(MIN)
2000
+
2 x tCK
tAC(MAX) + 1000
2.5 x tCK
tAC(MAX) + 1000
+
tAC(MIN)
2000
+
2 x tCK
tAC(MAX) + 1000
2.5 x tCK
tAC(MAX) + 1000
+
tAC(MIN)
2000
+
2 x tCK
tAC(MAX) + 1000
2.5 x tCK
tAC(MAX) + 1000
+
ODT tum-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAOFPD
ps
ps
tAC(MIN)
2000
+
+
tAC(MIN)
2000
+
+
tAC(MIN)
2000
+
+
ODT to power-down entry latency
ODT power-down exit latency
ODT enable from MRS command
tANPD
tAXPD
tMOD
3
8
3
8
3
8
tCK
tCK
ns
12
12
12
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
tCK
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
Exit precharge power-down to any non-READ
command
tXP
2
3
2
3
2
3
tCK
tCK
CKE minimum high/low time
tCKE
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
27
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
PACKAGE DIMENSION: 255 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM VIEW
23.15 (0.911) MAX
1 2 3 4 5 6 7 8 9 10 111213141516
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.61
(0.024)
NOM
1.27 (0.050)
BSC
255 x Ø 0.762 (0.030) BSC
19.05 (0.750) NOM
2.946 (0.116)
MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
28
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
ORDERING INFORMATION
W 3H 128M 72 E R X - XXX SB X
MICROSEMI CORPORATION
DDR2 SDRAM
CONFIGURATION, 128M x 72
1.8V POWER SUPPLY
REGISTERED
OPTIONS*
Blank = 0 ohm termination on CK\CK#
2 = 20 ohm termination on CK\CK#
DATA RATE (Mbs)
400 = 400Mb/s
533 = 533Mb/s
667 = 667Mb/s
PACKAGE:
SB = 255 Plastic Ball Grid Array (PBGA)
DEVICE GRADE:
M = Military
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
I
= Industrial
C
= Commercial
* Other termination values may be available, contact factory for options.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
29
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
W3H128M72ER-XNBX
ADVANCED
Document Title
128M x 72 Registered DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Initial Release
June 2008
Advanced
Changes (Pg. 1, 26)
October 2008
Preliminary
1.1 Add weight W3H128M72ER-XSBX - 4grams max
1.2 Move location of saving to the saving box
1.3 Add BGA thermal resistance
1.4 Changed package height dimensions
Rev 2
Changes (Pg. 1, 2, 5, 6, 7, 8, 9, 13, 14, 16, 19, 22 - 28, 30)
1.1 Updated electrical characteristics throughout data sheet
1.2 Removed I/O supply voltage = 1.8V ± 0.1V - (SSTL-18 compatible)
1.3 Corrected SPACE SAVINGS vs FPBGA to Space savings vs FBGA
1.4 Functional block diagram - Removed note
October 2008
Preliminary
1.5 Changed VCC = I/O + Core; VCCQ is common to VCC
1.6 Removed VCCQ from Table 1
1.7 Replaced Figure 4 on pg. 7
1.8 Replaced Figure 8 on pg. 8
1.9 Removed VCCQ from CD Operating Conditions, VCC and VCCQ are tied on the
device
Rev 3
Changes (Pg. 1, 3)
December 2008
Preliminary
3.1 Correction to Figure 1, removed actual size, moved 45% and 55% to saving
box
3.2 Correction to Figure 3, replace column 11 with corrected pinout, and #'s to K1
and K7
Rev 4
Rev 5
Changes (Pg. 3)
December 2008
January 2009
Preliminary
Preliminary
4.1 Correction to Figure 3, change B2 and C2 to VSS
Changes (Pg. 3, 4)
5.1 Change pins F1, F2, and G1 to reserved for the optional parity function.
5.2 Add in DNU symbol: Address bits F1, F2, and G2 are reserved for optional
parity function
Rev 6
Rev 7
Rev 8
Change (Pg. 1)
February 2009
January 2010
July 2011
Preliminary
Advanced
Advanced
6.1 Part number change from -XSBX to -XNBX
Change (Pg. 1)
7.1 Change data sheet back to Advanced
Change (Pg. 1-30)
8.1 Change document layout from White Electronic Designs to Microsemi
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 8
30
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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