W3H32M72E-667BI [MERCURY]
DDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208;
| 型号： | W3H32M72E-667BI |
| 厂家： | 
MERCURY UNITED ELECTRONICS INC |
| 描述： | DDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 动态存储器 双倍数据速率 |
| 文件： | 总23页 (文件大小：1040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3H32M72E-XBX
W3H32M72E-XBXF
256MB – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
BENEFITS
Data rate = 667, 533, 400 Mb/s
36% space savings vs. FPBGA
Package:
Reduced part count
• 208 Plastic Ball Grid Array (PBGA), 16 x 20mm
• 1.0mm pitch
50% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Upgradable to 64M x 72 density
• Moisture Sensitivity Level (MSL): 3
Single 1.8V supply
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
Lead free - available (Pb free – component and material are
lead free in accordance with IPC-1752)
* This product is subject to change without notice.
DLL for alignment of DQ and DQS transitions with clock
signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
TYPICAL APPLICATION
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 3, 4, 5, 6 or 7
Posted CAS additive latency: 0, 1, 2, 3, 4, 5 or 6
Write latency = Read latency - 1* tCK
Commercial, Industrial and Military Temperature Ranges
Organized as 32M x 72
RAM
DDR2/DDR3
W3H32M72E-XBI
Host
FPGA/
Processor
SSD (SLC)
MSM32/MSM64 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
M512/M256/M128 (SATA, 2.5in)
Weight: W3H32M72E-XBX - 2.5 grams typical
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
W3H32M72E-XBX
S
A
8
8
8
8
8
V
I
N
G
S
20
84
FBGA
84
FBGA
84
FBGA
84
FBGA
84
FBGA
12.5
W3H32M72E-XBX
16
Area
5 x 100mm2 = 500mm2
5 x 84 balls = 420 balls
320mm2
36%
50%
I/O Count
208 Balls
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 2
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3H32M72E-XBX
W3H32M72E-XBXF
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
CS#
WE#
RAS#
CAS#
CKE
CS# WE# RAS# CAS# CKE
ODT
A0-12
BA0-1
ODT
A0-12
BA0-1
DQ0
DQ0
CK0
CK0#
CK
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
CK#
LDM0
LDM
U1
UDM0
UDM
LDQS0
LDQS0#
UDQS0
UDQS0#
LDQS
LDQS#
UDQS
UDQS#
¥
DQ15
DQ15
CS# WE# RAS# CAS# CKE
ODT
A0-12
BA0-1
CK
DQ0
¥
¥
¥
DQ16
¥
¥
¥
CK1
CK1#
CK#
LDM1
LDM
U2
¥
¥
¥
¥
¥
¥
UDM1
UDM
LDQS1
LDQS1#
UDQS1
UDQS1#
LDQS
LDQS#
UDQS
UDQS#
DQ15
DQ31
CS# WE# RAS# CAS# CKE
ODT
A0-12
DQ0
¥
¥
¥
¥
¥
DQ32
¥
¥
¥
¥
¥
BA0-1
CK2
CK2#
CK
CK#
U3
LDM2
LDM
UDM2
UDM
LDQS2
LDQS2#
UDQS2
UDQS2#
LDQS
LDQS#
UDQS
UDQS#
¥
¥
DQ15
DQ47
CS# WE# RAS# CAS# CKE
ODT
A0-12
DQ0
¥
¥
¥
¥
¥
DQ48
¥
¥
¥
¥
¥
BA0-1
CK3
CK3#
CK
CK#
LDM3
LDM
U4
UDM3
UDM
LDQS3
LDQS3#
UDQS3
UDQS3#
LDQS
LDQS#
UDQS
UDQS#
¥
¥
DQ15
DQ63
CS# WE# RAS# CAS# CKE
ODT
A0-12
DQ0
¥
¥
¥
¥
¥
¥
DQ7
DQ64
¥
¥
¥
BA0-1
CK4
CK4#
CK
CK#
LDM4
LDM
U5
¥
¥
¥
LDQS4
LDQS4#
UDQS4
UDQS4#
LDQS
LDQS#
UDQS
UDQS#
DQ71
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 2
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3H32M72E-XBX
W3H32M72E-XBXF
FIGURE 3 – PIN CONFIGURATION
TOP VIEW
1
2
3
4 5 6 7 8 9 10 11
VCC
VSS
VSS
NC
VCC
NC
VCC
NC
VSS
NC
VCC
NC
VCC
NC
VSS
NC
VCC
VSS
VSS
VCC
A
B
C
D
E
F
A
B
C
D
E
F
VCC
VSS
DQ35
DQ52
LDM3
DQ38
UDM3
VCC
NC
NC
NC
NC
NC
NC
DQ34
DQ53
LDQS2
DQ58
DQ56
DQ47
A3
CK3
CK3#
CK2#
DQ48
LDQS2#
DQ61
UDQS3
DNU*
BA1
VSS
DQ51
DQ36
LDM2
DQ54
DQ44
A6
NC
NC
NC
NC
DQ50
DQ39
DQ55
DQ63
UDQS2#
VCC
DQ37
LDQS3
DQ42
DQ40
UDQS2
A12
CK2
DQ33
DQ49
DQ60
DQ41
A10
NC
DNU**
DQ59
UDM2
DQ62
VCC
DNU
DNU
VSS
DQ32
LDQS3#
DQ45
UDQS3#
VCC
DQ43
DQ57
DQ46
A9
G
H
J
G
H
J
VCC
VSS
VSS
A0
A11
VCC
VSS
VREF
VSS
VSS
VCC
A1
VSS
K
L
K
L
VCC
A2
A4
A8
VCC
VCC
BA0
A5
A7
VCC
UDQS1#
DQ13
LDQS1#
DQ0
UDQS1
DQ29
LDQS0#
DQ16
CK0#
CK1#
VSS
UDQS0
DQ8
DQ10
LDQS1
DQ5
CK1
DQ15
DQ24
DQ26
LDQS0
DQ21
DQ2
CK4
VCC
UDQS0#
DQ31
DQ23
DQ7
VCC
DQ30
UDM0
DQ27
UDQS4
DQ71
DQ64
DQ69
Vcc
DQ14
DQ25
DQ11
UDQS4#
CKE
DQ9
DQ12
DQ22
LDM0
DQ4
UDM1
DQ6
M
N
P
R
T
M
N
P
R
T
VSS
DQ28
DQ17
DQ1
ODT
LDQS4#
LDQS4
CAS#
DQ66
VSS
LDM1
DQ20
DQ3
CK0
DQ18
RAS#
CS#
WE#
DQ65
DQ67
VSS
DQ19
DQ68
VSS
VSS
DQ70
LDM4
VCC
VSS
U
V
W
U
V
W
VCC
CK4#
VSS
VCC
VSS
VCC
VCC
VCC
VSS
1
2
3
4 5 6 7 8 9 10 11
* Pin J10 is reserved for signal A13 on 128Mx72 and higher densities.
** Pin E5 is reserved for signal BA2 on higher densities.
Note: UDQS4 requires a 1K pull down resistor. UDQS4# requires a 1K pull up resistor. UDM4 is internally tied to Vcc
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 2
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3H32M72E-XBX
W3H32M72E-XBXF
TABLE 1 – BALL DESCRIPTIONS
Symbol
Type
Description
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be
ignored if disabled via the LOAD MODE command.
ODT
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQS and DQS/DQS#) is referenced to the crossings of CK and CK#.
CK, CK#
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM.
The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE
LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row
active in any bank). CKE is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry.
CKE is asynchronous for self refresh exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input
buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once
CKE
Input
V
CC is applied during first power-up. After VREF has become stable during the power on and initialization sequence, it must be
maintained for proper operation of the CKE receiver. For proper SELF-REFRESH operation, VREF must be maintained.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH.
CS#
Input
Input
RAS#, CAS#, WE#
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during
a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match
that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4
LDM, UDM
BA0–BA1
Input
Input
Bank address inputs: BA0–BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
BA0–BA1 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10)
for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA1–BA0) or
all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD MODE command.
A0-A12
Input
DQ0-71
I/O
I/O
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
UDQS, UDQS#
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
LDQS, LDQS#
I/O
VCC
VREF
VSS
Supply
Power Supply: I/O + Core, VCCQ is common to VCC
Supply
SSTL_18 reference voltage.
Supply
Ground
NC
-
-
No connect: These balls should be left unconnected.
DNU
Future use; Row address bits A14 and A15 are reserved for 8Gb and 16Gb densities. BA2 is reserved for 4Gb device.
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 2
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3H32M72E-XBX
W3H32M72E-XBXF
DESCRIPTION
GENERAL NOTES
The 2Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-
access memory containing 2,147,483,648 bits. Each of the four
chips in the MCP are internally configured as 8-bank DRAM. The
block diagram of the device is shown in Figure 2. Ball assignments
and are shown in Figure 3.
The functionality and the timing specifications discussed in this
data sheet are for the DLL-enabled mode of operation.
Throughout the data sheet, the various figures and text refer to
DQs as “DQ.” The DQ term is to be interpreted as any and all DQ
collectively, unless specifically stated otherwise.Additionally, each
chip is divided into 2 bytes, the lower byte and upper byte. For
the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to
LDQS. For the upper byte (DQ8–DQ15), DM refers to UDM and
DQS refers to UDQS.
The 2Gb DDR2 SDRAM uses a double-data-rate architecture to
achieve high-speed operation. The double data rate architecture is
essentially a 4n-prefetch architecture, with an interface designed
to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the 4Gb DDR2 SDRAM effectively consists
of a single 4n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and four corresponding n-bit-wide, one-half-clock-cycle
data transfers at the I/O balls.
Complete functionality is described throughout the document and
any page or diagram may have been simplified to convey a topic
and may not be inclusive of all requirements.
Any specific requirement takes precedence over a general
statement.
A bidirectional data strobe (DQS, DQS#) is transmitted externally,
along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM during READs and by
the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. There
are strobes, one for the lower byte (LDQS, LDQS#) and one for
the upper byte (UDQS, UDQS#).
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. The following sequence is required
for power up and initialization and is shown in Figure 4 on page 6.
The 2Gb DDR2 SDRAM operates from a differential clock (CK and
CK#); the crossing of CK going HIGH and CK# going LOW will
be referred to as the positive edge of CK. Commands (address
and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of anACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write
burst lengths of four or eight locations. DDR2 SDRAM supports
interrupting a burst read of eight with another read, or a burst
write of eight with another write. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent operation,
thereby providing high, effective bandwidth by hiding row precharge
and activation time.
Aself refresh mode is provided, along with a power-saving power-
down mode.
All inputs are compatible with the JEDEC standard for SSTL_18.
All full drive-strength outputs are SSTL_18-compatible.
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 2
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3H32M72E-XBX
W3H32M72E-XBXF
FIGURE 4 – POWER-UP AND INITIALIZATION
VCC
VCCQ
1
tVTD
TT1
V
VREF
Tk0
Tl0
Tm0
Tg0
Th0
Ti0
Tj0
Te0
Tf0
Tb0
Tc0
Td0
T0
Ta0
t
CK
CK#
CK
t
t
CL
CL
SSTL_18
LVCMOS
8
8
low level
CKE low level
ODT
10
REF
7
14
Valid
5
6
8
9
10
REF
11
12
13
LM
3
Command
LM
PRE
LM
LM
LM
PRE
LM
LM
NOP
7
DM
9
Address
Code
Code
Code
A10 = 1
Code
Code
Code
Code
A10 = 1
Valid
7
High-Z
High-Z
High-Z
DQS
7
DQ
RTT
4
3
t
t
t
t
t
t
t
t
t
MRD
t
T = 400ns (MIN)
t
T = 200μs (MIN)
RPA
MRD
MRD
MRD
MRD
RPA
RFC
RFC
MRD
MRD
See note 4
Power-up:
EMR(2)
EMR(3)
EMR with
DLL ENABLE
V
and stable
clCoCck (CK, CK#)
MR without
EMR with
EMR with
OCD exit
DLL RESET OCD default
Indicates a Break in
Time Scale
Don’t care
Normal
operation
MR with
DLL RESET
200 cycles of CK3
NOTES:
1.Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee RTT
(ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball (all
other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp time
to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions (A or
B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF, and VTT
are between their minimum and maximum values as stated in DC Operating Conditions table):
5.For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
6.Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
7.Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command, provide LOW to
BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or "1;" all others must be "0".
8.Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command, provide HIGH to
BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0".
A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer
than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V. Once supply voltage ramping is
complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table specifications apply.
9.Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL ENABLE command
provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits E7, E8 and E9 can be set to "0" or
"1;" Micron recommends setting them to "0".
•
•
•
VCC, VCCQ are driven from a single power converter output
VTT is limited to 0.95V MAX
10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock
the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA2 = BA1 = BA0 = 0.)
CKE must be HIGH the entire time. .
VREF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp
time.
•
VCCQ ≥ VREF at all times
11. Issue PRECHARGE ALL command.
B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage ramping,
12. Issue two or more REFRESH commands.
for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program
operating parameters without resetting the DLL). To access the mode registers, BA0 = 0, BA1 = 0,
BA2 = 0.
V
CC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table
specifications apply.
• Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be ≤ 200ms
from when VCC ramps from 300mV to VCC (MIN)
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
E9 to “1,” and then setting all other desired parameters. To access the extended mode register,
BA2 = 0, BA1 = 0, BA0 = 1.
• Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when
V
CC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤ 500ms; while VCC is
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9
to “0,” and then setting all other desired parameters. To access the extended mode registers, BA2
= 0, BA1 = 0, BA0 = 1.
ramping, current can be supplied from VCC through the device to VCCQ
•
VREF must track VCCQ/2, VREF must be within ±0.3V with respect to VCCQ/2 during supply
ramp time; VCCQ ≥ VREF must be met at all times
16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the
DLL RESET at Tf0.
• Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT
(MIN) is achieved must be no greater than 500ms
2.CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-up
prior to VREF. being stable. After state T0, Cke is required to have SSTL_18 input levels. Once CKE
transitions to a high level, it must stay HIGH for the duration on the initialization sequence.
3.PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode Register, EMR =
extended mode register, EMR2 = extended mode register 2, EMR3 = extended mode register
3, REF = REFRESH command, ACT = ACTIVE command, A10 = PRECHARGE ALL, CODE =
desired value for mode registers (blank addresses are required to be decoded), VALID - any valid
command/address, RA = row address, bank address.
4.DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS#,
DQ represents DQ0-63.
Microsemi Corporation reserves the right to change products or specifications without notice.
October 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 2
6
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3H32M72E-XBX
W3H32M72E-XBXF
FIGURE 5 – MODE REGISTER (MR) DEFINITION
MODE REGISTER (MR)
The mode register is used to define the specific mode of operation
of the DDR2 SDRAM. This definition includes the selection of a
burst length, burst type, CL, operating mode, DLL RESET, write
recovery, and power-down mode, as shown in Figure 5. Contents of
the mode register can be altered by re-executing the LOAD MODE
(LM) command. If the user chooses to modify only a subset of the
MR variables, all variables (M0–M14) must be programmed when
the command is issued.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
MR
01 PD
WR
DLL TM CAS# Latency BT Burst Length
Mode
Normal
Test
M7
0
M2 M1 M0
Burst Length
Reserved
Reserved
4
The mode register is programmed via the LM command (bits
BA2–BA0 = 0, 0, 0) and other bits (M12–M0) will retain the stored
information until it is programmed again or the device loses power
(except for bit M8, which is self-clearing). Reprogramming the
mode register will not alter the contents of the memory array,
provided it is performed correctly.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
PD mode
M12
0
Fast Exit
(Normal)
Slow Exit
DLL Reset
No
M8
0
8
1
Reserved
Reserved
Reserved
Reserved
1
Yes
(Low Power)
WRITE RECOVERY
M11 M10 M9
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts are in
progress. The controller must wait the specified time tMRD before
initiating any subsequent operations such as anACTIVE command.
Violating either of these requirements will result in unspecified
operation.
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
Burst Type
Sequential
Interleaved
M3
0
1
CAS Latency (CL)
M6 M5 M4
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
BURST LENGTH
Reserved
M16 M15 M14
Mode Register Set
Mode Register (MR)
3
4
5
6
7
Burst length is defined by bits M0–M3, as shown in Figure 5. Read
and write accesses to the DDR2 SDRAM are burst-oriented, with
the burst length being programmable to either four or eight. The
burst length dete rmines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
0
1
0
1
0
0
0
0
0
0
1
1
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =
8 (where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
Note: 1. A13 is not used on this device
2. Not all listed CL options are supported in any individual speed grades
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved. The burst type is selected via bit M3,
as shown in Figure 5. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting
column address, as shown in Table 2. DDR2 SDRAM supports
4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,
full interleave address ordering is supported; however, sequential
address ordering is nibble-based.
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WR values of 2, 3, 4, 5, 6, 7 or 8 clocks may be used for
programming bits M9–M11. The user is required to program the
value of WR, which is calculated by dividing tWR (in ns) by tCK (in
ns) and rounding up a non integer value to the next integer; WR
[cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used
as unknown operation or incompatibility with future versions may
result.
TABLE 2 – BURST DEFINITION
Order of Accesses Within a Burst
Burst
Length
Starting Column
Address
Type = Sequential
Type = Interleaved
A1
0
A0
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
0
1
0
POWER-DOWN MODE
1
1
Active power-down (PD) mode is defined by bit M12, as shown
in Figure 5. PD mode allows the user to determine the active
power-down mode, which determines performance versus power
savings. PD mode bit M12 does not apply to precharge PD mode.
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-0-5-6-7-4
2-3-0-1-6-7-4-5
3-0-1-2-7-4-5-6
4-5-6-7-0-1-2-3
5-6-7-4-1-2-3-0
6-7-4-5-2-3-0-1
7-4-5-6-3-0-1-2
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
0
When bit M12 = 0, standard active PD mode or “fast-exit” active PD
mode is enabled. The tXARD parameter is used for fast-exit active
PD exit timing. The DLL is expected to be enabled and running
during this mode.
8
0
1
1
1
0
0
1
0
1
When bit M12 = 1, a lower-power active PD mode or “slow-exit”
active PD mode is enabled. The tXARD parameter is used for slow-
exit active PD exit timing. The DLL can be enabled, but “frozen”
during active PD mode since the exit-to-READ command timing is
relaxed. The power difference expected between PD normal and
PD low-power mode is defined in the ICC table.
1
1
0
1
1
1
NOTES:
1.For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column
within the block.
2.For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column
within the block.
3.For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column
within the block.
4.Whenever a boundary of the block is reached within a given sequence above, the following access
wraps within the block.
OPERATING MODE
The normal operating mode is selected by issuing a command
with bit M7 set to “0,” and all other bits set to the desired values,
as shown in Figure 5. When bit M7 is “1,” no other bits of the
mode register are programmed. Programming bit M7 to “1” places
the DDR2 SDRAM into a test mode that is only used by the
manufacturer and should not be used. No operation or functionality
is guaranteed if M7 bit is ‘1.’
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 5.
Programming bit M8 to “1” will activate the DLL RESET function.
Bit M8 is self-clearing, meaning it returns back to a value of “0”
after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must
occur before a READ command can be issued to allow time for the
internal clock to be synchronized with the external clock. Failing
to wait for synchronization to occur may result in a violation of the
t
AC or tDQSCK parameters.
WRITE RECOVERY
Write recovery (WR) time is defined by bits M9–M11, as shown in
Figure 5. The WR register is used by the DDR2 SDRAM during
WRITE with auto precharge operation. During WRITE with auto
precharge operation, the DDR2 SDRAM delays the internal auto
precharge operation by WR clocks (programmed in bits M9–M11)
from the last data burst.
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CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in
Figure 5. CL is the delay, in clock cycles, between the registration
of a READ command and the availability of the first bit of output
data. The CL can be set to 3, 4, 5, 6 or 7 clocks, depending on the
speed grade option being used.
DDR2 SDRAM also supports a feature called posted CAS additive
latency (AL). This feature allows the READ command to be issued
prior to tRCD (MIN) by delaying the internal command to the DDR2
SDRAM by AL clocks.
Examples of CL= 3 and CL= 4 are shown in Figure 6; both assume
AL = 0. If a READ command is registered at clock edge n, and the
CL is m clocks, the data will be available nominally coincident with
clock edge n+m (this assumes AL = 0).
DDR2 SDRAM does not support any half-clock latencies. Reserved
states should not be used as unknown operation or incompatibility
with future versions may result.
FIGURE 6 – CAS LATENCY (CL)
T0
T1
T2
T3
T4
T5
T6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUT
D
OUT
D
OUT
DOUT
n + 3
DQ
n
n + 1
n + 2
CL = 3 (AL = 0)
T0
T1
T2
T3
T4
T5
T6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUT
D
OUT
D
OUT
DOUT
n + 3
DQ
n
n + 1
n + 2
CL = 4 (AL = 0)
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal tAC, tDQSCK and tDQSQ
TRANSITIONING DATA
DON’T CARE
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EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are
DLL enable/disable, output drive strength, on die termination
(ODT) (RTT), posted AL, off-chip driver impedance calibration
(OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,
and output disable/enable. These functions are controlled via the
bits shown in Figure 7. The EMR is programmed via the LOAD
MODE (LM) command and will retain the stored information until it
is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
FIGURE 7 – EXTENDED MODE REGISTER (EMR) DEFINITION
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Extended Mode
Register (Ex)
16 15 14 13 12 11 10
9
8
7
6
RTT
5
4
3
2
RTT
1
0
02 out
OCD Program
Posted CAS#
ODS DLL
MRS
RDQS DQS#
Outputs
Enabled
Disabled
E0
0
DLL Enable
Enable (Normal)
E12
0
RTT (nominal)
E6 E2
1
R
TT disabled
1
0
0
1
1
0
1
0
1
Disable (Test/Debug)
75Ω
150Ω
50Ω
Output Drive Strength
RDQS Enable
E11
0
E1
0
No
Full strength (18 Ω target)
1
Yes
1
Reduced strength (40 Ω target)
E10
Posted CAS# Additive Latency (AL)
E5 E4 E3
0
1
Enable
Disable
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
E9 E8 E7
OCD Operation
3
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD not supported
Reserved
4
5
6
Reserved
Reserved
Reserved
1
OCD default state
Mode Register Set
Mode register set (MRS)
Extended mode register (EMRS)
E16 E15 E14
0
1
0
1
0
0
0
0
0
0
1
1
Extended mode register (EMRS2)
Extended mode register (EMRS3)
Note:
1. During initialization, all three bits must be set to "1" for OCD default state, then must be set to
"0" before initialization is finished, as detailed in the initialization procedure.
2. E13 (A13) is not used on this device.
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elected by enabling switch “sw1,” which enables all R1 values that
are 150Ω each, enabling an effective resistance of 75Ω (RTT2(EFF)
= R2/2). Similarly, if “sw2” is enabled, all R2 values that are 300Ω
each, enable an effective ODT resistance of 150Ω (RTT2(EFF) =
R2/2). Switch “sw3” enables R1 values of 100Ω enabling effective
resistance of 50Ω Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
DLL ENABLE/DISABLE
The DLLmay be enabled or disabled by programming bit E0 during
the LM command, as shown in Figure 7. The DLL must be enabled
for normal operation. DLL enable is required during power-up
initialization and upon returning to normal operation after having
disabled the DLL for the purpose of debugging or evaluation.
Enabling the DLL should always be followed by resetting the DLL
using an LM command.
The ODT control ball is used to determine when RTT(EFF) is turned
on and off, assuming ODT has been enabled via bits E2 and E6 of
the EMR. The ODT feature and ODT input ball are only used during
active, active power-down (both fast-exit and slow-exit modes), and
precharge power-down modes of operation. ODT must be turned
off prior to entering self refresh. During power-up and initialization
of the DDR2 SDRAM, ODT should be disabled until issuing the
EMR command to enable the ODT feature, at which point the ODT
ball will determine the RTT(EFF) value. Any time the EMR enables
the ODT function, ODT may not be driven HIGH until eight clocks
after the EMR has been enabled. See “ODT Timing” section for
ODT timing diagrams.
The DLL is automatically disabled when entering SELF REFRESH
operation and is automatically re-enabled and reset upon exit of
SELF REFRESH operation.
Any time the DLL is enabled (and subsequently reset), 200 clock
cycles must occur before a READ command can be issued, to
allow time for the internal clock to synchronize with the external
clock. Failing to wait for synchronization to occur may result in a
violation of the tAC or tDQSCK parameters.
OUTPUT DRIVE STRENGTH
The output drive strength is defined by bit E1, as shown in Figure
7. The normal drive strength for all outputs are specified to be
SSTL_18. Programming bit E1 = 0 selects normal (full strength)
drive strength for all outputs. Selecting a reduced drive strength
option (E1 = 1) will reduce all outputs to approximately 45 to 60
percent of the SSTL_18 drive strength. This option is intended
for the support of lighter load and/or point-to-point environments.
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in
Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an inverse AL of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states
should not be used as unknown operation or incompatibility with
future versions may result.
DQS# ENABLE/DISABLE
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is
the complement of the differential data strobe pair DQS/DQS#.
When disabled (E10 = 1), DQS is used in a single ended mode
and the DQS# ball is disabled. When disabled, DQS# should be
left floating. This function is also used to enable/disable RDQS#. If
RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then
both DQS# and RDQS# will be enabled.
In this operation, the DDR2 SDRAM allows a READ or WRITE
command to be issued prior to tRCD (MIN) with the requirement
that AL ≤ tRCD (MIN). A typical application using this feature would
set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command
is held for the time of the AL before it is issued internally to the
DDR2 SDRAM device. RL is controlled by the sum of AL and CL;
RL = AL+CL. Write latency (WL) is equal to RL minus one clock;
WL = AL + CL - 1 x tCK
.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by bit E12, as shown in
Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#,
RDQS, RDQS#) function normally. When disabled (E12 = 1), all
DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are
disabled, thus removing output buffer current. The output disable
feature is intended to be used during ICC characterization of read
current.
ON-DIE TERMINATION (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6
of the EMR, as shown in Figure 7. The ODT feature is designed
to improve signal integrity of the memory channel by allowing the
DDR2 SDRAM controller to independently turn on/off ODT for any
or all devices. RTT effective resistance values of 50Ω ,75Ω, and
150Ω are selectable and apply to each DQ, DQS/DQS#, RDQS/
RDQS#, UDQS/UDQS#, LDQS/LDQS#, and UDM/LDM signals.
Bits (E6, E2) determine what ODT resistance is enabled by turning
on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
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EXTENDED MODE REGISTER 2
The extended mode register 2 (EMR2) controls functions beyond
those controlled by the mode register. Currently all bits in EMR2
are reserved, except for E7 as shown in Figure 8. The EMR2
is programmed via the LM command and will retain the stored
information until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the memory
array, provided it is performed correctly.
Bit E7 (A7) must be programmed as"1" to provide a 2X refresh rate.
EMR2 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA1
A13(1)
A11
A9
A7
A5
A3
A1
BA2(1)
BA0
A12
A10
A8
A6
A4
A2
A0
Address Bus
Extended Mode
Register (Ex)
16 15 14 13 12 11 10
MRS
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
Mode Register Set
Mode register (MR)
High Temperature Self Refresh rate enable
1X refresh rate
M13 M14
E7
0
0
0
1
1
0
1
0
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
2X refresh rate
1
Note: 1. E13 (A13) and E16 (BA2) are reserved for future use and must be programmed to "0."
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EXTENDED MODE REGISTER 3
The extended mode register 3 (EMR3) controls functions beyond
those controlled by the mode register. Currently, all bits in EMR3
are reserved, as shown in Figure 9. The EMR3 is programmed
via the LM command and will retain the stored information until it
is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
BA1
BA2(1)
A13(1)
BA0
A11
A9
A7
A5
A3
A1
A12
A10
A8
A6
A4
A2
A0
Address Bus
Extended Mode
Register (Ex)
16 15 14 13 12 11 10
MRS
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
M16 M15 M14
Mode Register Set
Mode register (MR)
0
0
0
0
0
0
1
1
0
1
0
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to "0." A13 is not used in this device.
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COMMAND TRUTH TABLES
The following tables provide a quick reference of DDR2 SDRAM
available commands, including CKE power-down modes, and bank-
to-bank commands.
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
CKE
BA2
BA1
BA0
A12
A11
Function
CS#
RAS#
CAS#
WE#
A10
A9-A0
Notes
Previous
Cycle
Current Cycle
LOAD MODE
REFRESH
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
H
H
X
H
L
BA
X
OP Code
4, 6
X
X
X
X
X
X
SELF-REFRESH Entry
L
X
X
H
H
H
H
SELF-REFRESH Exit
L
H
X
X
X
X
4, 7
6
Single bank precharge
All banks PRECHARGE
Bank activate
H
H
H
H
H
H
BA
X
X
X
L
H
X
X
L
H
BA
Row Address
4
Column
Address
Column
Address
WRITE
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
BA
BA
BA
BA
L
H
L
4, 5, 6, 8
Column
Address
Column
Address
WRITE with auto precharge
READ
4, 5, 6, 8
4, 5, 6, 8
4, 5, 6, 8
Column
Address
Column
Address
H
H
Column
Address
Column
Address
READ with auto precharge
H
NO OPERATION
H
H
X
X
L
H
H
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
Device DESELECT
POWER-DOWN entry
POWER-DOWN exit
H
L
L
X
X
X
X
X
X
X
X
9
9
H
L
H
Notes:
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.
3. “X” means “H or L” (but a defined logic level) for valid IDD measurements.
4. BA2 is only applicable for densities ≥1Gb.
5. An n is the most significant address bit for a given density and configuration. Some larger address bits may be “Don’t Care” during column addressing, depending on density and configuration.
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD MODE command selects which mode register is programmed.
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted.t
9. The power-down mode does not perform any REFRESH operations. The duration of power-down is limited by the refresh requirements outlined in the AC parametric section.
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Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW, the corresponding
data will be written to memory; if the DM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands
from being executed by the DDR2 SDRAM. The DDR2 SDRAM
is effectively deselected. Operations already in progress are not
affected.
NO OPERATION (NOP)
PRECHARGE
The NO OPERATION (NOP) command is used to instruct the
selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,
CAS#, and WE are HIGH). This prevents unwanted commands
from being registered during idle or wait states. Operations already
in progress are not affected.
The PRECHARGE command is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will
be available for a subsequent row activation a specified time (tRP)
after the PRECHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE command to
a different bank is allowed as long as it does not interrupt the data
transfer in the current bank and does not violate any other timing
parameters.After a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command is allowed
if there is no open row in that bank (idle state) or if the previously
open row is already in the process of precharging. However, the
precharge period will be determined by the last PRECHARGE
command issued to the bank.
LOAD MODE (LM)
The mode registers are loaded via bank address and address
inputs. The bank address balls determine which mode register
will be programmed. See Mode Register (MR). The LM command
can only be issued when all banks are idle, and a subsequent
executable command cannot be issued until tMRD is met.
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the bank
address inputs determines the bank, and the address inputs select
the row. This row remains active (or open) for accesses until a
precharge command is issued to that bank.Aprecharge command
must be issued before opening a different row in the same bank.
REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM
and is analogous to CAS#-before-RAS# (CBR) REFRESH. All
banks must be in the idle mode prior to issuing a REFRESH
command. This command is nonpersistent, so it must be issued
each time a refresh is required. The addressing is generated by
the internal refresh controller. This makes the address bits a “Don’t
Care” during a REFRESH command.
READ
The READ command is used to initiate a burst read access to
an active row. The value on the bank address inputs determine
the bank, and the address provided on address inputs selects
the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end
of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
DDR2 SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR2 SDRAM retains data
without external clocking. All power supply inputs (including Vref)
must be maintained at valid levels upon entry/exit and during SELF
REFRESH operation.
DDR2 SDRAM also supports theAL feature, which allows a READ
or WRITE command to be issued prior to tRCD (MIN) by delaying
the actual registration of the READ/WRITE command to the internal
device by AL clock cycles.
The SELF REFRESH command is initiated like a REFRESH
command except CKE is LOW. The DLL is automatically disabled
upon entering self refresh and is automatically enabled upon
exiting self refresh.
WRITE
The SELF REFRESH command is initiated when CKE is LOW. The
differential clock should remain stable and meet tCKE specifications
at least 1 × tCK after entering self refresh mode. The procedure
for exiting self refresh requires a sequence of commands. First,
the differential clock must be stable and meet tCK specifications at
least 1 × tCK prior to CKE going back to HIGH. Once CKE is HIGH
(tCKE [MIN] has been satisfied with three clock registrations), the
DDR2 SDRAM must have NOP or DESELECT commands issued
for tXSNR. A simple algorithm for meeting both refresh and DLL
requirements is used to apply NOP or DESELECT commands for
200 clock cycles before applying any other command.
The WRITE command is used to initiate a burst write access to an
active row. The value on the bank select inputs selects the bank, and
the address provided on inputs selects the starting column location.
The value on input A10 determines whether or not auto precharge
is used. If auto precharge is selected, the row being accessed will
be precharged at the end of the WRITE burst; if auto precharge is
not selected, the row will remain open for subsequent accesses.
DDR2 SDRAM also supports theAL feature, which allows a READ
or WRITE command to be issued prior to tRCD (MIN) by delaying
the actual registration of the READ/WRITE command to the internal
device by AL clock cycles.
*NOTE: Self refresh not available at military temperature.
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W3H32M72E-XBX
W3H32M72E-XBXF
TABLE 4 – ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
MIN
-0.5
-0.5
-55
MAX
2.3
U nit
V
Voltage on VCC/VCCQ pin relative to VSS
Voltage on any pin relative to VSS
Storage temperature
VIN, VOUT
TSTG
2.3
V
125
°C
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
-25
25
μA
Input leakage current; Any input 0V<VIN<VCC; VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
IL
CK, CK#
DM
-5
-5
5
5
μA
μA
Output leakage current;
0V<VOUT<VCCQ; DQs and ODT are disable
IOZ
DQ, DQS, DQS#
-5
5
μA
μA
IVREF
VREF leakage current; VREF = Valid VREF level
-10
10
TABLE 5 – DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1 .7
Typical
1 .8
Max
1 .9
Unit
V
Notes
Supply voltage
1
2
3
I/O Reference voltage
VREF
VTT
0.49 x VCCQ
VREF-0.04
0.50 x VCCQ
VREF
0.51 x VCCQ
VREF + 0.04
V
I/O Termination voltage
Notes:
V
1.VCC and VCCQ are tied on the device.
2.VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise on
REF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
V
3.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
TABLE 6 – BGA THERMAL RESISTANCE
Description
Symbol
Theta JB
Theta JC
Typical
TBD
Units
°C/W
°C/W
Notes
Junction to Board
Junction to Case (Top)
1
1
TBD
The JEDEC JESD51 specifications are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input
to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board definition specifications; therefore, Microsemi PMG recommends a customized
evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request.
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W3H32M72E-XBXF
TABLE 7 – INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.1 25
-0.300
Max
Unit
V
(1)
Input High (Logic 1) Voltage
VCC
Input Low (Logic 0) Voltage
VREF - 0.125
V
Note 1: VCC + 0.3V allowed provided 1.9V is not exceeded.
TABLE 8 – INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
VREF + 0.250
VREF + 0.200
-0.3
Max
Unit
V
(1)
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
VCC
(1)
VCC
V
VREF - 0.250
VREF - 0.200
V
AC Input Low (Logic 0) Voltage DDR2-667
-0.3
V
Note 1: VCC + 0.3V allowed provided 1.9V is not exceeded.
TABLE 9 – ODT DC ELECTRICAL CHARACTERISTICS
All voltages referenced to VSS
Parameter
Symbol
RTT1(EFF)
RTT2(EFF)
RTT3(EFF)
∆VM
Min
52
Nom
75
Max
97
Unit
Ω
Notes
RTT effective impedance value for 75Ω setting EMR (A6, A2) = 0, 1
RTT effective impedance value for 150Ω setting EMR (A6, A2) = 1, 0
RTT effective impedance value for 50Ω setting EMR (A6, A2) = 1, 1
1
1
1
2
105
35
150
50
195
65
Ω
Ω
Deviation of VM with respect to VCCQ/2
-6
6
%
Note: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL (AC) to the ball being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.
RTT(EFF)
=
VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC)
)
2. Measure voltage (VM) at tested ball with no load
∆VM =
(
2 x VM - 1
VCC
)
x 100
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W3H32M72E-XBX
W3H32M72E-XBXF
TABLE 10 – DDR2 ICC SPECIFICATIONS AND CONDITIONS
Symbol
Proposed Conditions
667 CL5
533 CL4
400 CL3
Units
Operating one bank active-precharge current;
ICC0
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
600
750
550
550
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
ICC1
675
650
mA
Precharge power-down current;
ICC2P
ICC2Q
ICC2N
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
50
50
50
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
275
300
225
250
200
225
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
200
100
175
100
150
100
mA
mA
ICC3P
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC3N
350
1,250
1,175
1,100
50
300
1,025
975
250
800
775
1,000
50
mA
mA
mA
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4W
ICC4R
ICC5
tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDAD6W
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
1,050
50
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs
ICC6
Normal
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
ICC7
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
1,700
1,700
1,700
mA
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R
;
Refer to the following page for detailed timing conditions
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W3H32M72E-XBXF
TABLE 11 – AC TIMING PARAMETERS
667Mbs CL5
533Mbs CL4
400Mbs CL3
Unit
Parameter
Symbol
Min
Max
8,000
8,000
8,000
0.52
Min
Max
Min
Max
CL=5
CL=4
CL=3
tCK(5)
3,000
3,750
ps
ps
ps
tCK
tCK
ps
ps
ps
ps
ps
ps
tCK
ps
ps
ns
tCK
tCK
Ps
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
Clock cycle time
t
CK(4)
3,750
5,000
8,000
8,000
0.52
5,000
5,000
8,000
8,000
0.52
tCK(3)
tCH
5,000
CK high-level width
0.48
0.48
0.48
CK low-level width
tCL
0.48
0.52
0.48
0.52
0.48
0.52
Half clock period
tHP
MIN (tCH, tCL)
-550
MIN (tCH, tCL)
-550
MIN (tCH, tCL)
-600
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
tAC
+650
+650
+600
tHZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ
tAC(MN)
400
tAC(MN)
400
tAC(MN)
450
tDS
tDH
500
500
450
tDIPW
tQHS
tQH
0.35
0.35
0.35
400
400
450
DQ-DQS hold, DQS to first DQ to go nonvalid, per access
Data valid output window (DVW)
DQS input high pulse width
tHP - tQHS
tQH - tDQSQ
0.35
0.35
-550
0.2
tHP - tQHS
tQH - tDQSQ
0.35
tHP - tQHS
tQH - tDQSQ
0.35
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tDQSQ
tRPRE
tRPST
tWPRES
tWPRE
tWPST
DQS input low pulse width
0.35
0.35
DQS output access time fromCK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
DQS-DQ skew, DOS to last DQ valid, per group, per access
DQS read preamble
+650
-550
+650
-600
+600
0.2
0.2
0.2
0.2
0.2
300
300
1.1
0.6
350
1.1
0.6
0.9
1.1
0.6
0.9
0.4
0
0.9
0.4
0
DQS read postamble
0.4
DQS write preamble setup time
DQS write preamble
0
0.25
0.4
0.25
0.4
0.25
0.4
DQS write postamble
0.6
0.6
0.6
WL-
TDQSS
WL+
TDQSS
WL-
TDQSS
WL+
TDQSS
WL-
TDQSS
WL+
TDQSS
Write command to first DQS latching transition
tCK
tCK
Positive DQs latch edge to associated edge
tDQSS
-0.18
+0.18
-0.25
+0.25
-0.25
+0.25
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TABLE 11 – AC TIMING PARAMETERS (continued)
667Mbs CL5
533Mbs CL4
400Mbs CL3
Unit
Parameter
Address and control input pulse width for each input
Symbol
Min
Max
Min
Max
Min
Max
tIPW
tISa
0.6
400
0.6
500
0.6
tCK
ps
ps
ps
ps
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
600
Address and control input setup time
Address and control input hold time
tISb
200
250
350
tIHa
400
500
600
tIHb
275
375
475
CAS# to CAS# command delay
tCCD
tRC
2
2
2
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
55
55
55
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
10
10
10
15
15
15
Four Bank Activate period
50
50
50
40
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
40
70,000
40
70,000
70,000
7.5
7.5
7.5
15
15
15
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
tDAL
tWTR
tRP
tWR + tRP
7.5
tWR + tRP
7.5
tWR + tRP
10
15
15
15
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
tRPA
tMRD
tDELAY
tRFC
tRP + tCK
2
tRP + tCK
2
tRP + tCK
2
tIS +tIH + tCK
127.5
tIS +tIH + tCK
127.5
tIS +tIH + tCK
127.5
REFRESH to Active or Refresh to Refresh command interval**
70,000
7.8
70,000
7.8
70,000
7.8
Average periodic refresh interval
(Comm + Ind Temp) 1X
tREFI
tREFI
tXSNR
tXSRD
tlSXR
μs
μs
ns
tCK
ps
Average periodic refresh interval (Military Temp) 4X
Exit self refresh to non-READ command
Exit self refresh to READ
1.9
1.9
1.9
tRFC(MIN)
10
+
tRFC(MIN)
10
+
tRFC(MIN)
10
+
200
200
200
Exit self refresh timing reference
tIS
tIS
tIS
ODT tum-on delay
ODT turn-on
tAOND
tAON
tAOFD
tAOF
2
2
2
2
2
2
tCK
ps
tCK
ps
tAC(MAX)
1000
+
tAC(MAX)
1000
+
tAC(MAX)
1000
+
tAC(MIN)
2.5
tAC(MIN)
2.5
tAC(MIN)
2.5
ODT turn-off delay
ODT tum-off
2.5
2.5
2.5
tAC(MAX)
600
+
tAC(MAX)
600
+
tAC(MAX)
600
+
tAC(MIN)
tAC(MIN)
tAC(MIN)
2 x tCK
tAC(MAX)
1000
+
+
2 x tCK
tAC(MAX)
1000
+
+
2 x tCK
tAC(MAX)
1000
+
+
tAC(MIN)
2000
+
tAC(MIN)
2000
+
tAC(MIN)
2000
+
ODT tum-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
ps
ps
2 x tCK
tAC(MAX)
1000
+
+
2 x tCK
tAC(MAX)
1000
+
+
2 x tCK
tAC(MAX)
1000
+
+
tAC(MIN)
2000
+
tAC(MIN)
2000
+
tAC(MIN)
2000
+
tAOFPD
ODT to power-down entry latency
tANPD
tAXPD
tXARD
tXARDS
tXP
3
8
3
8
3
8
tCK
tCK
tCK
tCK
tCK
tCK
ODT power-down exit latency
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
Exit precharge power-down to any non-READ command
CKE minimum high/low time
2
2
2
7-AL
2
6-AL
2
6-AL
2
tCKE
3
3
3
Notes:
* The refresh period is 64ms (commercial and industrial) or 16ms (military). This equates to an average refresh rate of 7.8μs or 1.95μs. To ensure all rows of all banks are properly refreshed, 8192
REFRESH commands must be issued every 64ms or 16ms. The JEDEC tRFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is allowed.
** DRAM component is 1Gb with bank address BA2 tied to GND.
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W3H32M72E-XBX
W3H32M72E-XBXF
FIGURE 10 – PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM VIEW
208 x Ø 0.60 (0.024) NOM
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
0.50
(0.020)
NOM
1.0 (0.039)NOM
10.0 (0.394) NOM
2.33 (0.092) MAX
16.10 (0.634) MAX
• Pads are solder mask defined, pad opening = 0.48mm
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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W3H32M72E-XBX
W3H32M72E-XBXF
ORDERING INFORMATION
W
3H 32M 72 E - XXX
B
X
F
MICROSEMI CORPORATION
DDR2 SDRAM
CONFIGURATION, 32M x 72
1.8V Power Supply
DATA RATE (Mbs)
400 = 400Mbs CL3
533 = 533Mbs CL4
667 = 667Mbs CL5
PACKAGE:
B = 208 Plastic Ball Grid Array (PBGA), 16 x 20mm
DEVICE GRADE:
M = Military
= Industrial
-55°C to +125°C
-40°C to +85°C
I
C = Commercial 0°C to +70°C
SOLDER BALLS:
Blank = Eutectic Sn63Pb37
F = Lead free, SAC305
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Document Title
256MB – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
March 2015
Advanced
Rev 1
Rev 2
Changes (Pg. 1-23) (ECN 9472)
August 2015
Final
1.1 Change data sheet status to Final
Changes (Pg 5)
October 2015
Final
2.1 Correct typos in description
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October 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 2
23
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相关型号：
W3H32M72E-667BM
DDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
MERCURY
W3H32M72E-667BMF
DDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, LEAD FREE, PLATSIC, BGA-208
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W3H32M72E-667SB2C
DDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
WEDC
W3H32M72E-667SB2C
DDR DRAM, 32MX72, 0.6ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
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W3H32M72E-667SB2CF
DDR DRAM, 32MX72, 0.6ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-208
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W3H32M72E-667SB2I
DDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
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W3H32M72E-667SB2I
DDR DRAM, 32MX72, 0.6ns, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
MICROSEMI
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