W3J512M32K-1066B2I [MERCURY]
DDR DRAM, 512MX32, CMOS, PBGA204, BGA-204;![W3J512M32K-1066B2I](http://pdffile.icpdf.com/pdf2/p00244/img/icpdf/W3J512M32K-1_1480468_icpdf.jpg)
型号: | W3J512M32K-1066B2I |
厂家: | ![]() |
描述: | DDR DRAM, 512MX32, CMOS, PBGA204, BGA-204 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总40页 (文件大小:1655K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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W3J512M32K-XBX
W3J512M32KT-XB2X
*PRELIMINARY
2GB – 512M x 32 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip
Package
FEATURES
BENEFITS
DDR3 Data Rate = 800, 1,066, 1333 Mb/s
67% Space savings vs. FBGA
Reduced part count
35% I/O reduction vs. FBGA
Optional:
Packages:
• 136 PBGA, 204 PBGA 10 x 14.5mm
• 0.8mm pitch
• Moisture Sensitivity Level (MSL): 3
Supply Voltage = 1.35V
• Address/control terminations
Differential clock terminations (not populated in XBX
package)
Center terminated push/pull I/O
Differential bidirectional data strobe
Differential clock inputs (CK, CK#)
8n-bit prefetch architecture
Output drive calibration resistors (RZQ)
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Enhanced thermal management
Eight internal banks
Fixed Burst length (BL) of 8 and Burst Chop (BC) of 4
Selectable BC4 or BL8 on-the-fly (OTF)
Auto Refresh and Self Refresh Modes
Nominal and dynamic On Die Termination (ODT)
Programmable CAS read latency (CL)
Posted CAS additive latency
* This product is under development, is not qualified or characterized and is subject to change or
cancellation without notice.
TYPICAL APPLICATION
Write leveling
RAM
Smart
Programmable CAS write latency (CWL) based on tCK
Commercial, industrial and military temperature ranges
Organized as 1 rank of 512M x 32
Fusion2
DDR3
W3J512M32K-XBX
Host
FPGA/
Processor
SSD (SLC)
1.5V option available in same packages.
Refer to W3J512M32G data sheet.
W3J512M32K-XBX is footprint compatible with Micron®
MSM32/MSM64 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
MSD1TB / 512 / 256 / 128 (SATA, 2.5in)
M41K256M32 device.
Micron© is a registered trademark of Micron Technology, Inc.
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
S
A
V
I
N
G
S
W3J512M32KT-XB2X
2.0
2.0
2.0
9
9
9
9
78
78
78
78
10.5
14.5
FBGA
FBGA
FBGA
FBGA
W3J512M32KT-XB2X
10
Area
441 mm2
4 x 78 balls = 312 balls
145 mm2
204 Balls
67%**
35%
I/O Count
** not including terminations
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
FIGURE 2A – FUNCTIONAL BLOCK DIAGRAM FOR W3J512M32K-XBX
A0-15, BA0-2, RAS#, CAS#
WE#, RST#, CKE, ODT, CS#
CK#
CK
26
CK# CK
DM
11
DQS0, DQS0#
DM0, DQ0-7
512M x 8
IC1
DQ
DQS
240Ω
ZQ
26
CK# CK
DM
DQ
DQS
11
DQS1, DQS1#
DM1, DQ8-15
512M x 8
IC2
240Ω
ZQ
26
CK# CK
DM
DQ
DQS
11
DQS2, DQS2#
DM2, DQ16-23
512M x 8
IC3
240Ω
ZQ
26
CK# CK
DM
DQ
DQS
11
DQS3, DQS3#
DM3, DQ24-31
512M x 8
IC4
240Ω
ZQ
NOTES: Block diagram shows actual fly-by order.
Calibration resistors (RZQ) are included.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
FIGURE 2B – FUNCTIONAL BLOCK DIAGRAM FOR W3J512M32KT-XB2X
A0-15, BA0-2, RAS#, CAS#
WE#, RST#, CKE, ODT, CS#
CK#
CK
26
CK# CK
DM
11
DQS0, DQS0#
DM0, DQ0-7
512M x 8
IC1
DQ
DQS
240Ω
ZQ
26
CK# CK
DM
DQ
DQS
11
DQS1, DQS1#
DM1, DQ8-15
512M x 8
IC2
240Ω
ZQ
26
CK# CK
DM
DQ
DQS
11
DQS2, DQS2#
DM2, DQ16-23
512M x 8
IC3
240Ω
ZQ
26
CK# CK
DM
DQ
DQS
11
DQS3, DQS3#
DM3, DQ24-31
512M x 8
IC4
NOTES:
240Ω
ZQ
25
• Block diagram shows actual fly-by order.
• Calibration resistors (RZQ) are included.
• Clock termination is included.
• Address/Control terminations are included.
VTT
RTT
RTT
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
FIGURE 3 – 136 PBGA (XBX) PIN CONFIGURATION
TOP VIEW
1
2
3
4
9
10
11
12
A
B
C
D
E
F
VCC GND GND DQ1
VCC DQ0 GND DQ3
VCC DQ2 GND DM0
GND VCC DQS0 DQS0#
GND DQ4 VCC DQ5
GND DQ6 VCC DQ7
DQ9 GND GND VCC
DQ11 GND DQ8 VCC
DM1 GND DQ10 VCC
DQS1# DQS1 VCC GND
DQ13 VCC DQ12 GND
DQ15 VCC DQ14 GND
A
B
C
D
E
F
G
H
VCC
NC CAS# RAS#
CK
A10
A1
CK# CKE VCC
A14 A15 NC
NC GND VREFCA
G
H
J
RST# BA2 ODT CS#
J VREFDQ GND NC
WE#
A0
K
L
BA0
VCC
A9
A7
A2
A5
A4
A6
A12 BA1
A13 VCC
K
L
A3
A8
A11
M
N
P
R
T
GND DQ24 VCC DQ25
GND DQ26 VCC DQ27
GND VCC DQS3 DQS3#
VCC DQ28 GND DM3
VCC DQ30 GND DQ29
VCC GND GND DQ31
DQ17 VCC DQ16 GND
DQ19 VCC DQ18 GND
DQS2# DQS2 VCC GND
DM2 GND DQ20 VCC
DQ21 GND DQ22 VCC
DQ23 GND GND VCC
M
N
P
R
T
U
U
1
2
3
4
9
10
11
12
NOTE: Calibration resistors (RZQ) are included inside the package.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
FIGURE 3A – 204 PBGA PIN CONFIGURATION (XB2X)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
VCC GND GND DQ1 VCC VTT** VTT** VCC DQ9 GND GND VCC
VCC DQ0 GND DQ3 GND VTT** VTT** GND DQ11 GND DQ8 VCC
VCC DQ2 GND DM0 GND VTT** NC GND DM1 GND DQ10 VCC
A
B
C
D
E
F
GND VCC DQS0 DQS0# VCC
GND DQ4 VCC DQ5 VCC
NC
NC
NC
NC
VCC DQS1# DQS1 VCC GND
VCC DQ13 VCC DQ12 GND
GND DQ6 VCC DQ7 GND NC
VCC NC CAS# RAS# GND NC
RST# BA2 ODT CS#
NC GND DQ15 VCC DQ14 GND
G
H
NC GND
CK
A10
A1
CK# CKE VCC
A14 A15 NC
NC GND VREFCA
G
H
J
VCC
NC
NC
NC
NC
VCC
VCC
J VREFDQ GND NC
WE# VCC
K
L
BA0
VCC
A9
A7
A2
A5
A0
A3
GND NC
GND NC
NC GND
VCC GND
A4
A6
A12 BA1
A13 VCC
K
L
A8
A11
M
N
P
R
T
GND DQ24 VCC DQ25 VCC GND GND VCC DQ17 VCC DQ16 GND
GND DQ26 VCC DQ27 VCC GND GND VCC DQ19 VCC DQ18 GND
M
N
P
R
T
GND VCC DQS3 DQS3# GND VCC
VCC DQ28 GND DM3 GND VCC
VCC GND DQS2# DQS2 VCC GND
VCC GND DM2 GND DQ20 VCC
VCC DQ30 GND DQ29 VCC GND GND VCC DQ21 GND DQ22 VCC
VCC GND GND DQ31 VCC GND GND VCC DQ23 GND GND VCC
U
U
1
2
3
4
5
6
7
8
9
10
11
12
NOTE: Calibration resistors (RZQ) are included inside the package.
** VTT is only used with address/control terminations option
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 1 – BALL DESCRIPTIONS
Symbol
ODT
Type
Input
Input
Description
On-Die termination: ODT (registered HIGH) enables and (registered LOW) disables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM. The ODT
input will be ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Output data (DQS and DQS#) is referenced to the crossings of CK and CK#.
CK, CK#
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking
CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle),or active power-down (row
active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for
self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers
(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CKE
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# is considered part of the command code. CS# is referenced to VREFCA
CS#
Input
Input
RAS#, CAS#, WE#
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered and are referenced to VREFCA
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the
input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and
DQS balls. DM is referenced to VREFDQ.
DM0-7
BA0–BA2
RST#
Input
Input
Input
Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA2 define which mode register including (MR, MR0, MR1, MR2, MR3) is loaded during the LOAD MODE
command. BA0-2 are referenced to VREFCA
Reset = RST# or RESET# is an active low CMOS input referenced to VSS. The RST# input receiver is a CMOS input
defined as a rail-to-rail signal with DC HIGH ≥ 0.8 x VCCQ and DC LOW ≤ 0.2 x VCCQ. RST# assertion and desertion are
asynchronous
Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10)
for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0])
or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs
are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst
chop).
A0-A15
Input
DQ0-X
DQS0-X, DQS0-X#
VCC
I/O
I/O
Data input/output: Bidirectional data bus. DQs are referenced to VREFDQ.
Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data.
Single Power Supply – VCC and VCCQ are internally tied together
Termination supply
Supply
Supply
Supply
Supply
Supply
-
VTT
Reference voltage for control, command, and address. VREFCA must be maintained at all times (including self refresh) for
proper device operation.
VREFCA
V
REFDQ
GND
NC
Reference voltage for data. VREFDQ must be maintained at all times (including self refresh) for proper device operation.
Ground.
No connect: These balls should be left unconnected.
Future use
DNU
-
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
6
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
DESCRIPTION
GENERAL NOTES
The 2GB DDR3 SDRAM is a high-speed CMOS, dynamic random-
access memory containing 4 4Gb, (4,294,967,296) bit chips. Each
of the 4 chips in the MCP are internally configured as 8-bank
DRAM. The block diagram of the device is shown in Figure 2. Ball
assignments and are shown in Figure 3.
• The functionality and the timing specifications discussed
in this data sheet are for the DLL-enabled mode of
operation. (normal operation)
• Throughout the data sheet, the various figures and text
refer to DQs as “DQ.” The DQ term is to be interpreted
as any and all DQ collectively, unless specifically stated
otherwise. The terms "DQS" and "CK" found throughout
the data sheet are to be interpreted as DQS, DQS#
and CK, CK# respectively, unless specifically stated
otherwise.
The 2GB DDR3 SDRAM uses a double-data-rate architecture to
achieve high-speed operation. The double data rate architecture
is a 8n-prefetch architecture, with an interface designed to transfer
two data words per clock cycle at the I/O balls. A single read or
write access for the 2GB DDR3 SDRAM consists of a single 8n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and
eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
• Complete functionality is described throughout the
document and any page or diagram may have been
simplified to convey a topic and may not be inclusive of
all requirements.
A differential data strobe (DQS, DQS#) is transmitted externally,
along with data, for use in data capture at the receiver. DQS is
center-aligned with data for writes. The read data is transmitted by
the DDR3 SDRAM and edge-aligned to the data strobes.
• Any specific requirement takes precedence over a
general statement.
• Any functionality not specifically stated here within is
considered illegal, and not supported and can result in
unknown operations.
The 2GB DDR3 SDRAM operates from a differential clock (CK and
CK#); the crossing of CK going HIGH and CK# going LOW will be
referred to as the positive edge of CK. Commands (address and
control signals) are registered at every positive edge of CK. Input
data is registered in the first rising edge of "DQS" after the "WRITE"
preamble, and output data is referenced on the first rising edge of
"DQS" after the "READ" preamble.
Read and write accesses to the DDR3 SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVATE command
are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE command are
used to select the bank and the starting column location for the
burst access.
DDR3 SDRAM use "READ" and "WRITE" BL8 and "BC4" An auto
precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR3 SDRAMs allows for concurrent operation,
thereby providing high, effective bandwidth by hiding row precharge
and activation time.
Aself refresh mode is provided, along with a power-saving power-
down mode.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
7
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
INITIALIZATION
DDR3 SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. The following
sequence is required for power up and initialization and is
shown in Figure 4.
5. After this CKE LOW time, CKE may be brought HIGH
(synchronously) and only NOP or DES commands may be
issued. The clock must be present and valid for at least 10ns
(and a minimum of five clocks) and ODT must be driven
LOW at least tIS prior to CKE being registered HIGH. When
CKE is registered HIGH, it must be continuously registered
HIGH until the full initialization process is complete.
1. Applying power; RST# is recommended to be below 0.2
x VCCQ during power ramp to ensure the outputs remain
disabled. (HIGH-Z) and ODT off (RTT is also HIGH-Z). All
other inputs, including ODT, may be undefined.
6. After CKE is registered HIGH and after tXPR has been
satisfied, MRS commands may be issued. Issue an MRS
(LOAD MODE) command to MR2 with the applicable settings
(provide LOW to BA2 and BA0 and HIGH to BA1).
During power up, either of the following conditions may
exist and must be met:
7. Issue an MRS command to MR3 with the applicable settings.
Condition A:
8. Issue an MRS command to MR1 with the applicable settings,
• VCC and VCCQ are driven from a single-power converter
output and are ramped with a maximum delta voltage
between them of ΔV ≤ 300mV. Slope reversal of any
power supply signal is allowed. The voltage levels on
all balls other than VCC, VCCQ, VSS, VSSQ must be less
than or equal to VCCQ and VCC on one side, and must be
greater than or equal to VSSQ and VSS on the other side.
including enabling the DLL and configuring ODT.
9. Issue an MRS command to MR0 with the applicable settings,
including a DLL RESET command. tDLLK (512) cycles of clock
input are required to lock the DLL.
10. Issue a ZQCL command to calibrate RTT and RON values
for the process voltage temperature (PVT). Prior to normal
operation, tZQINIT must be satisfied.
• Both VCC and VCCQ power supplies ramp to VCC (MIN)
and VCCQC (MIN) within tVDDPR = 200ms.
11. When tDLLK and tZQINIT have been satisfied, the DDR3
• VREFDQ tracks VCC × 0.5, VREFCA tracks VCC × 0.5.
SDRAM will be ready for normal operation.
• VTT is limited to 0.875V when the power ramp is complete
and is not applied directly to the DRAM components;
however, tVTD should be greater than or equal to zero to
avoid device latchup.
Condition B:
• Vcc may be applied before or at the same time as VCCQ
• VCCQ may be applied before or at the same time as VTT,
REFDQ, and VREFCA.
.
V
• No slope reversals are allowed in the power supply ramp
for this condition.
2. Until stable power, maintain RST# LOW to ensure the
outputs remain disabled (High-Z). After the power is
stable, RST# must be LOW for at least 200μs to begin the
initialization process. ODT will remain in the High-Z state
while RST# is LOW and until CKE is registered HIGH.
3. CKE must be LOW 10ns prior to RST# transitioning HIGH.
4. After RST# transitions HIGH, wait 500μs (minus one clock)
with CKE LOW.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
8
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
FIGURE 4 – POWER-UP AND INITIALIZATION
Notes appear on page 8
T (MAX) = 200ms
VCC
See power-up
conditions
in the
initialization
sequence text,
set up 1
VTT
VREF
Stable and
valid clock
Tc0
Td 0
Tb0
T1
T0
Ta0
Power-up
ramp
t
t
CK
VTD
CK#
CK
t
t
t
CL
CL
CKSRX
t
IO
= 20ns
z
RESET#
t
IS
T (MIN) = 10ns
Valid
Valid
CKE
ODT
t
IS
NOP
Command
DM
MRS
MRS
MRS
MRS
ZQCL
Valid
Address
A10
Valid
Code
Code
Code
Code
Code
Code
Code
Code
Valid
Valid
A10 = H
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
BA[2:0]
DQS
DQ
RTT
t
t
t
MOD
T = 200μs (MIN)
T = 500μs (MIN)
t
t
t
ZQINIT
MRD
MRD
XPR
MRD
MR0 with
DLL reset
MR1 with
DLL enable
MR2
MR3
ZQ calibration
All voltage
supplies valid
and stable
t
DLLK
DRAM ready for
external commands
Normal
operation
Indicates A Break in
Time Scale
Don’t Care
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
9
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
a burst is determined by the burst length, the burst type, and the
starting column address, as shown in Table 4. DDR3 only supports
4-bit burst chop and 8-bit burst access modes. Full interleave
address ordering is supported for READs, while WRITEs are
restricted to nibble (BC4) or word (BL8) boundaries.
MODE REGISTERS
Mode registers (MR0–MR3) are used to define various modes of
programmable operations of the DDR3 SDRAM. A mode register
is programmed via the MODE REGISTER SET (MRS) command
during initialization, and it retains the stored information (except
for MR0[8] which is self-clearing) until it is either reprogrammed,
RESET# goes LOW, or until the device loses power. Contents of a
mode register can be altered by re-executing the MRS command.
If the user chooses to modify only a subset of the mode register’s
variables, all variables must be programmed when the MRS
command is issued. Reprogramming the mode register will not alter
the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or reissued) when all banks
are idle and in the precharged state (tRP is satisfied and no data
bursts are in progress). After an MRS command has been issued,
two parameters must be satisfied: tMRD and tMOD. The controller
must wait tMRD before initiating any subsequent MRS commands
The controller must also wait tMOD before initiating any non MRS
commands (excluding NOP and DES). The DRAM requires tMOD in
order to update the requested features, with the exception of DLL
RESET, which requires additional time. Until tMOD has been satisfied,
the updated features are to be assumed unavailable.
DLL RESET
DLL RESET is defined by MR0[8] (see Figure 5). Programming
MR0[8] to “1” activates the DLL RESET function. MR0[8] is self-
clearing, meaning it returns to a value of “0” after the DLL RESET
function has been initiated. Anytime the DLL RESET function is
initiated, CKE must be HIGH and the clock held stable for 512
(tDLLK) clock cycles before a READ command can be issued. This
is to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may
result in invalid output timing specifications, such as tDQSCK timings.
WRITE RECOVERY
WRITE recovery time is defined by MR0[11:9] (see Figure 5).
Write recovery values of 5, 6, 7, 8, 10, 12 or 14 may be used by
programming MR0[11:9]. The user is required to program the
correct value of write recovery and is calculated by dividing tWR
(ns) by tCK (ns) and rounding up a non integer value to the next
integer: WR (cycles) = roundup (tWR [ns]/tCK [ns]).
MODE REGISTER 0 (MR0)
The base register, MR0, is used to define various DDR3 SDRAM
modes of operations. These definitions include the selection of a
burst length, burst type, CAS latency, operating mode, DLLRESET,
write recovery, and precharge power-down mode.
PRECHARGE POWER-DOWN
(PRECHARGE PD)
The precharge PD bit applies only when precharge power-down
mode is being used. When MR0[12] is set to “0,” the DLL is off
during precharge power-down providing a lower standby current
mode; however, tXPDLL must be satisfied when exiting. When
MR0[12] is set to “1,” the DLL continues to run during precharge
power-down mode to enable a faster exit of precharge power-down
mode; however, tXP must be satisfied when exiting.
BURST LENGTH
Burst length is defined by MR0[1: 0]. (see figure 9) Read and
write accesses to the DDR3 SDRAM are burst-oriented, with
the burst length being programmable to “4” (chop mode), “8”
(fixed), or selectable using A12 during a READ/WRITE command
(on-the-fly). The burst length determines the maximum number
of column locations that can be accessed for a given READ or
WRITE command. When MR0[1:0] is set to “01” during a READ/
WRITE command, if A12 = 0, then BC4 (chop) mode is selected.
If A12 = 1, then BL8 mode is selected. Specific timing diagrams,
and turnaround between READ/WRITE, are shown in the READ/
WRITE sections of this document. When a READ or WRITE
command is issued, a block of columns equal to the burst length
is effectively selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected byA[i:2] when
the burst length is set to “4” and by A[i:3] when the burst length is
set to “8” (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
CAS LATENCY (CL)
The CAS latency (CL) is defined by MR0[6:4], as shown in Figure
6. CL is the delay, in clock cycles, between the internal READ
command and the availability of the first bit of output data. The CL
can be set to 5, 6, 7, 8, 9, 10, 11, 12, or 13. DDR3 SDRAM does
not support any half-clock latencies.
MODE REGISTER 1 (MR1)
The mode register 1 (MR1) controls additional functions and
features not available in the other mode registers: Q OFF (OUTPUT
DISABLE), TDQS (for the x8 configuration only, DLLENABLE/DLL
DISABLE, RTT_NOM value (ODT), WRITE LEVELING, POSTED
CASADDITIVE latency, and OUTPUT DRIVE STRENGTH. These
functions are controlled via the bits shown in Figure 7. The MR1
register is programmed via the MRS command and retains the
stored informations until it is reprogrammed, until RESET# goes
LOW, or until the device loses power. Reprogramming the MR1
register will not alter the contents of the memory array, provided
it is performed correctly.
BURST TYPE
Accesses within a given burst may be programmed to either a
sequential or an interleaved order. The burst type is selected via
MR0[3], as shown in Figure 5. The ordering of accesses within
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PRELIMINARY
FIGURE 5 – MODE REGISTER 0 (MR0) DEFINITIONS
BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
18 17 16 15 14 13 12 11 10
9
8
7
1
6
5
4
3
2
1
0
Mode register 0 (MR0)
1
1
1
1
0
0
0
0
0
0
PD
WR
DLL
0
CAS# latency BT
M1 M0
Burst Length
M17 M16
Mode Register
0
0
1
1
0
1
0
1
Fixed BL8
4 or 8 (on-the-fly via A12)
Fixed BC4 (chop)
Reserved
0
0
1
1
0
1
0
1
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
M12 Precharge PD
M8 DLL Reset
0
1
DLL off (slow exit)
DLL on (fast exit)
0
1
No
Yes
M11 M10 M9 Write Recovery
M6 M5 M4 M2
CAS Latency
M3
READ Burst Type
Sequential (nibble)
Interleaved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
Reserved
0
1
5
6
6
7
7
8
8
10
12
14
9
10
11
12
13
NOTE: 1. MR0[18, 15:13, 7] are reserved for future use and must be programmed to 0.
TABLE 4 – BURST ORDER
Burst
READ/
WRITE
Burst Length
Starting Column Address
Notes
Type = Sequential
0, 1, 2, 3, Z, Z, Z, Z
1, 2, 3, 0, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 0, 1, 2, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 6, 7, 4, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 4, 5, 6, Z, Z, Z, Z
0, 1, 2, 3, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
5, 6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
Type = Interleaved
0, 1, 2, 3, Z, Z, Z, Z
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
V
0
0
1
1
0
0
1
1
V
V
0
0
1
1
0
0
1
1
V
0
1
0
1
0
1
0
1
V
V
0
1
0
1
0
1
0
1
V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 3, 4
1, 3, 4
1
1, 0, 3, 2, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
READ
4 CHOP
WRITE
1
1
1
READ
8
1
1
1
1
WRITE
1, 3
NOTES:
1. Internal read and write operations start at the same point in time for BC4 as they do for BL8
2. Z = Data strobe output drives are in tri-state
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins
4. X = "Don't care".
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The MR1 register must be loaded when all banks are idle and no
bursts are in progress. The controller must satisfy the specified
timing parameters. tMRD and tMOD before initiating a subsequent
operation
disabled (MR1[12] = 1), all DDR3 SDRAM outputs (DQ and DQS,
DQS#) are tri-stated. The output disable feature is intended to be
used during ICC characterization of the READ current and during
tDQSS margining (write leveling) only.
DLL ENABLE/DLL DISABLE
ON-DIE TERMINATION (ODT)
The DLL may be enabled or disabled by programming MR1[0]
during the LOAD MODE command, as shown in Figure 11.
The DLL must be enabled for normal operation. DLL enable is
required during power-up initialization and upon returning to
normal operation after having disabled the DLL for the purpose
of debugging or evaluation. Enabling the DLL should always be
followed by resetting the DLL using the appropriate LOAD MODE
command.
ODT resistance RTT_NOM is defined by MR1[9, 6, 2] (see Figure
7). The RTT termination value applies to the DQ, DM, DQS,
DQS#, and TDQS, TDQS# balls. DDR3 supports multiple RTT
termination values based on RZQ/n where n can be 2, 4, 6, 8, or
12 and RZQ is 240Ω. Unlike DDR2, DDR3 ODT must be turned
off prior to reading data out and must remain off during a READ
burst. RTT_NOM termination is allowed any time after the DRAM
is initialized, calibrated, and not performing read access, or when
it is not in self refresh mode. Additionally, write accesses with
dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM
with RTT_WR.
If the DLL is enabled prior to entering self refresh mode, the
DLL is automatically disabled when entering SELF REFRESH
operation an is automatically reenabled and reset upon exit of SELF
REFRESH operation. IF the DLL is disabled prior to entering self
refresh mode, the DLL remains disabled even upon exit of SELF
REFRESH operation until it is reenabled and reset.
The actual effective termination, RTT_EFF, may be different from
the RTT targeted due to nonlinearity of the termination.
The ODT feature is designed to improve signal integrity of the
memory channel by enabling the DDR3 SDRAM controller to
independently turn on/off ODT for any or all devices. The ODT
input control pin is used to determine when RTT is turned on
(ODTL on) and off (ODTL off), assuming ODT has been enabled
via MR1[9, 6, 2].
The DRAM is not tested to check-nor does Microsemi warrant
compliance with normal mode timings or functionality when the
DLL is disabled. An attempt has been made to have the DRAM
operate in the normal mode where reasonably possible when the
DLL has been disabled; however, by industry standard, a few
known exceptions are defined:
WRITE LEVELING
1. ODT is not allowed to be used.
The WRITE LEVELING function is enabled by MR1[7], as shown in
Figure 7. Write leveling is used (during initialization) to deskew the
DQS strobe to clock offset as a result of fly-by topology designs.
For better signal integrity, DDR3 SDRAM memory adopted fly-by
topology for the commands, addresses, control signals, and clocks.
2. The output data is no longer edge-aligned to the clock.
3. CL and CWL can only be six clocks.
When the DLL is disabled, timing and functionality can vary from
the normal operation specifications when the DLL is enabled (see
"DLL Disable Mode"). Disabling the DLL also implies the need to
change the clock frequency.
The fly-by topology benefits from a reduced number of stubs and
their lengths. However, fly-by topology induces flight time skews
between the clock and DQS strobe (and DQ) at each DRAM.
Controllers will have a difficult time maintaining tDQSS, tDSS, and
tDSH specifications without supporting write leveling in systems
which use fly-by topology-based designs.
OUTPUT DRIVE STRENGTH
The DDR3 SDRAM uses a programmable impedance output buffer.
The drive strength mode register setting is defined by MR1[5,
1]. RZQ/7 (34Ω [NOM]) is the primary output driver impedance
setting for DDR3 SDRAM devices. To calibrate the output driver
impedance, an external precision resistor (RZQ) is connected
between the ZQ ball and VSSQ. The value of the resistor must be
240Ω ±1 percent. The output impedance is set during initialization.
Additional impedance calibration updates do not affect device
operation, and all data sheet timings and current specifications
are met during an update.
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths in
DDR3 SDRAM. MR1 [4, 3] define the value of AL, as shown in
Figure 7. MR1 [4, 3] enable the user to program the DDR3 SDRAM
with an Al = 0, CL-1 or CL -2.
With this feature, the DDR3 SDRAM enables a READ or WRITE
command to be issued after theACTIVATE command for that bank
prior to tRCD (MIN). The only restriction is ACTIVATE to READ or
WRITE + AL ≥ tRCD (MIN) must be satisfied. Assuming tRCD (MIN)
To meet the 34Ω specification, the output drive strength must be
set to 34Ω during initialization. To obtain a calibrated output driver
impedance after power-up, the DDR3 SDRAM needs a calibration
command that is part of the initialization and reset procedure
= CL, a typical application using this feature sets AL = CL - 1tCK
=
t
RCD (MIN) - 1 tCK. The READ or WRITE command is held for the
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown
in Figure 7. When enabled (MR1[12] = 0), all outputs (DQ, DQS,
DQS#) function when in the normal mode of operation. When
time of the AL before it is released internally to the DDR3 SDRAM
device. READ latency (RL) is controlled by the sum of the AL and
CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum
of CAS WRITE latency and AL, WL = AL + CWL.
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PRELIMINARY
FIGURE 6 – READ LATENCY
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
AL = 0, CL = 6
DQS, DQS#
DQ
DI
n
DI
DI
DI
DI
n + 1
n + 2
n + 3
n + 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Command
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
AL = 0, CL = 8
DQS, DQS#
DQ
DI
n
NOTES:
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal tDQSCK and nominal tDSDQ
Transitioning Data
Don’t Care
.
automatically from 1X to 2X when temperature exceeds 85°C.
This enables the user to operate the DRAM beyond the 85°C
temperature limit up to 95°C for military grade devices while in
self refresh mode.
MODE REGISTER 2 (MR2)
The mode register 2 (MR2) controls additional functions and
features not available in the other mode registers. These additional
functions are CAS WRITE latency (CWL), AUTO SELF REFRESH
(ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC
ODT (RTT_WR). These functions are controlled via the bits shown in
Figure 9. The MR2 is programmed via the MRS command and will
retain the stored information until it is programmed again or until the
device loses power. Reprogramming the MR2 register will not alter
the contents of the memory array, provided it is performed correctly.
The MR2 register must be loaded when all banks are idle and not
data bursts are in progress, and the controller must wait the specified
time tMRD and tMOD before initiating a subsequent operation.
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[7] is used to disable/enable the SRT function.
When SRT is disabled, the self refresh mode’s refresh rate is
assumed to be at the 85°C max temperature (sometimes referred
to as 1X refresh rate). In the disabled mode, SRT requires the user
to ensure the DRAM never exceeds a temperature of 85°C while
in self refresh mode unless the user enables ASR.
When SRT is enabled, the DRAM self refresh is changed internally
from 1X to 2X, regardless of the temperature. This enables the
user to operate the DRAM beyond 85°C up to 95°C while in self
refresh mode. The standard self refresh current test specifies test
conditions to 85°C only, meaning if SRT is enabled, the standard
self refresh current specifications do not apply.
CAS WRITE LATENCY (CWL)
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from
the releasing of the internal write to the latching of the first data in.
CWL must be correctly set to the corresponding operating clock
frequency (see Figure 9). The overall WRITE latency (WL) is equal
to CWL + AL (Figure 10)
SRT vs. ASR
If the temperature limit of 85°C is not exceeded then neither
SRT nor ASR is required, and both can be disabled throughout
operation. However, if the temperature exceeds 85°C (but lower
than 95°C), the user is required to provide a 2X refresh rate during
(manual) refresh and to enable either the SRT or theASR to ensure
self refresh is performed at the 2X rate. Beyond 95°C , neither SRT
or ASR are functional and user is required to provide 4X refresh
rate using (manual) refresh commands.
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASR function.
When ASR is disabled, the self refresh mode’s refresh rate is
assumed to be at the maximum temperature of 85°C (sometimes
referred to as 1X refresh rate). In the disabled mode,ASR requires
the user to ensure the DRAM never exceeds a temperature of 85°C
while in self refresh unless the user enables the SRT feature listed
below when temperature is between 85°C and 95°C.
SRT forces the DRAM to switch the internal self refresh rate from
1X to 2X. Self refresh is performed at the 2X refresh rate regardless
of the temperature.
Enabling ASR assumes the DRAM self refresh rate is changed
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ASR automatically switches the DRAM’s internal self refresh rate
from 1X to 2X. However, while in self refresh mode, ASR enables
the refresh rate to automatically adjust between 1X to 2X over the
supported temperature range. One other disadvantage with ASR is
the DRAM cannot always switch from a 1X to a 2X refresh rate at
an exact temperature of 85°C. Although the DRAM will support data
integrity when it switches from a 1X to a 2X refresh rate, it may switch
at a lower temperature than 85°C. Since only one mode is necessary,
SRT and ASR cannot be enabled at the same time.
Dynamic ODT is only applicable during WRITE cycles. If ODT
(RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted.
RTT_NOM and RTT_WR can be used independent of one
other. Dynamic ODT is not available during write leveling mode,
regardless of the state of ODT (RTT_NOM).
MODE REGISTER 3 (MR3)
The mode register 3 (MR3) controls additional functions and
features not available in the other mode registers. Currently
defined is the MULTIPURPOSE REGISTER (MPR). This function is
controlled via the bits shown in Figure 11. The MR3 is programmed
via the LOAD MODE command and retains the stored information
until it is programmed again or until the device loses power.
Reprogramming the MR3 register will not alter the contents of the
memory array, provided it is performed correctly. The MR3 register
must be loaded when all banks are idle and no data bursts are in
progress, and the controller must wait the specified time tMRD and
For military grade devices (max temperature of +125°C), it is
recommended to use manual 4X refresh rate.
DYNAMIC ODT
The dynamic ODT (RTT_WR) feature is defined by MR2[10, 9].
Dynamic ODT is enabled when a value is selected. This new DDR3
SDRAM feature enables the ODT termination value to change
without issuing an MRS command, essentially changing the ODT
termination “on-the-fly.”
tMOD before initiating a subsequent operation.
With dynamic ODT (RTT_WR) enabled, the DRAM switches
from normal ODT (RTT_NOM) to dynamic ODT (RTT_WR) when
beginning a WRITE burst and subsequently switches back to ODT
(RTT_NOM) at the completion of the WRITE burst. If RTT_NOM
is disabled, the RTT_NOM value will be High-Z. Special timing
parameters must be adhered to when dynamic ODT (RTT_WR)
is enabled: ODTLCNW, ODTLCNW4, ODTLCNW8, ODTH4,
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a
predefined system timing calibration bit sequence. Bit 2 is the
master bit that enables or disables access to the MPR register,
and bits 1 and 0 determine which mode the MPR is placed in. The
basic concept of the multipurpose register is shown in Figure 12.
ODTH8, and tADC
.
FIGURE 7 – MODE REGISTER 1 (MR1) DEFINITION
BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA2
Address bus
18 17 16 15 14 13 12 11 10
9
RTT
8
7
6
RTT
5
ODS
4
AL
3
2
RTT
1
0
Mode register 1 (MR1)
01
0
1
01
1
01
TDQS 01
01 WL
ODS DLL
Q Off
M0
0
DLL Enable
Enable (normal)
Disable
M17 M16
Mode Register
M12
Q Off
M11
TDQS
Disabled
Enabled
0
0
1
1
0
1
0
1
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
1
0
1
Enabled
Disabled
0
1
M5 M1 Output Drive Strength
0
0
1
1
0
1
0
1
RZQ/6 (40Ω [NOM])
RZQ/7 (34Ω [NOM])
Reserved
RTT, nom (ODT)2
Non-Writes
RTT, nom (ODT)3
Writes
M7
Write Levelization
Disable (normal)
Enable
0
1
M9 M6 M2
R
TT, nom disabled
RTT, nom disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
RZQ/4 (60Ω [NOM]) RZQ/4 (60Ω [NOM])
RZQ/2 (120Ω [NOM]) RZQ/2 (120Ω [NOM])
RZQ/6 (40Ω [NOM]) RZQ/6 (40Ω [NOM])
Additive Latency (AL)
Disabled (AL = 0)
AL = CL - 1
M4 M3
0
0
1
1
0
1
0
1
RZQ/12 (20Ω [NOM])
RZQ/8 (30Ω [NOM])
Reserved
n/a
n/a
AL = CL - 2
Reserved
Reserved
Reserved
Reserved
NOTES:
1. R1[18, 15:13, 10, 8] are reserved for future use and must be programmed to 0.
2. During write leveling, if MR1[7] and MR1[12] are 1, then all RTT, nom values are available for use.
3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT, nom write values are available for use.
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PRELIMINARY
If MR3[2] is a “0,” then the MPR access is disabled, and the
DRAM operates in normal mode. However, if MR3[2] is a “1,” then
the DRAM no longer outputs normal read data but outputs MPR
data as defined by MR3[0, 1]. If MR3[0, 1] is equal to “00,” then a
predefined read pattern for system calibration is selected.
NO OPERATION (NOP)
The NOP command (CS# LOW) prevents unwanted commands
from being registered during idle or wait states. Operations already
in progress are not affected.
To enable the MPR, the MRS command is issued to MR3, and
MR3[2] = 1 (see Table 5). Prior to issuing the MRS command, all
banks must be in the idle state (all banks are precharged, and
ZQ CALIBRATION
ZQ CALIBRATION LONG (ZQCL)
The ZQCLcommand is used to perform the initial calibration during
a power-up initialization and reset sequence. This command may
be issued at any time by the controller depending on the system
environment. The ZQCL command triggers the calibration engine
inside the DRAM.After calibration is achieved, the calibrated values
are transferred from the calibration engine to the DRAM I/O, which
are reflected as updated RON and ODT values.
t
RP is met). When the MPR is enabled, any subsequent READ or
RDAP commands are redirected to the multipurpose register. The
resulting operation when either a READ or a RDAP command is
issued, is defined by MR3[1:0] when the MPR is enabled (see Table
6). When the MPR is enabled, only READ or RDAP commands are
allowed until a subsequent MRS command is issued with the MPR
disabled (MR3[2] = 0). Power-down mode, self refresh, and any
other nonREAD/RDAP command is not allowed during MPR enable
mode. The RESET function is supported during MPR enable mode.
The DRAM is allowed a timing window defined by either tZQINIT
or tZQOPER to perform the full calibration and transfer of values.
When ZQCL is issued during the initialization sequence, the timing
parameter tZQINIT must be satisfied. When initialization is complete,
subsequent ZQCLcommands require the timing parameter tZQOPER
to be satisfied.
MPR FUNCTIONAL DESCRIPTION
The MPR JEDEC definition enables either a prime DQ (DQ0 on a
x4 and a x8; on a x16, DQ0 = lower byte and DQ8 = upper byte)
to output the MPR data with the remaining DQs driven LOW, or for
all DQs to output the MPR data . The MPR readout supports fixed
READ burst and READ burst chop (MRS and OTF via A12/BC#)
with regular READ latencies and AC timings applicable, provided
the DLL is locked as required.
ZQ CALIBRATION SHORT (ZQCS)
The ZQCS command is used to perform periodic calibrations to
account for small voltage and temperature variations. The shorter
timing window is provided to perform the reduced calibration and
transfer of values as defined by timing parameter tZQCS. A ZQCS
command can effectively correct a minimum of 0.5 percent RON
and RTT impedance error within 64 clock cycles, assuming the
maximum sensitivities.
MPR addressing for a valid MPR read is as follows:
A[1:0] must be set to “00” as the burst order is fixed per
nibble
A2 selects the burst order:
ACTIVATE
• BL8, A2 is set to “0,” and the burst order is fixed to 0, 1,
The ACTIVATE command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the BA[2:0]
inputs selects the bank, and the address provided on inputsA[n:0]
selects the row. This row remains open (or active) for accesses
until a PRECHARGE command is issued to that bank.
2, 3, 4, 5, 6, 7
For burst chop 4 cases, the burst order is switched on the
nibble base and:
• A2 = 0; burst order = 0, 1, 2, 3
• A2 = 1; burst order = 4, 5, 6, 7
A PRECHARGE command must be issued before opening a
different row in the same bank.
Burst order bit 0 (the first bit) is assigned to LSB, and burst
order bit 7 (the last bit) is assigned to MSB
READ
A[9:3] are a “Don’t Care”
A10 is a “Don’t Care”
A11 is a “Don’t Care”
The READ command is used to initiate a burst read access to
an active row. The address provided on inputs A[2:0] selects the
starting column address depending on the burst length and burst
type selected. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the READ burst.
If auto precharge is not selected, the row will remain open for
subsequent accesses. The value on input A12 (if enabled in the
mode register) when the READ command is issued determines
whether BC4 (chop) or BL8 is used. After a READ command is
issued, the READ burst may not be interrupted. A summary of
READ commands is shown in Table 9.
A12: Selects burst chop mode on-the-fly, if enabled within
MR0
A13 is a “Don’t Care”
BA[2:0] are a “Don’t Care”
DESELECT (DES)
The DES command (CS# HIGH) prevents new commands from
being executed by the DRAM. Operations already in progress are
not affected.
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PRELIMINARY
FIGURE 8 – READ LATENCY (AL = 5, CL = 6)
BC4
T2
T11
T0
T1
T6
T12
T13
T14
CK#
CK
Command
ACTIVEn
READn
NOP
NOP
NOP
NOP
NOP
NOP
t
RCD (MIN)
DQS, DQS#
AL = 5
CL = 6
DO
n
DO
DO
DO
DQ
n + 1
n + 2
n + 3
RL = AL + CL = 11
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
analogous to CAS#- before-RAS# (CBR) refresh or auto refresh.
This command is nonpersistent, so it must be issued each time
a refresh is required. The addressing is generated by the internal
refresh controller. This makes the address bits a “Don’t Care” during
a REFRESH command. The DRAM requires REFRESH cycles
at an average interval (tREFI). Refer to “AC Timing Parameters”
table for tREFI (MAX) which depends of temperature. To allow
for improved efficiency in scheduling and switching between
tasks, some flexibility in the absolute refresh interval is provided.
A maximum of eight REFRESH commands can be posted to
any given DRAM, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH
command is nine times the maximum average interval refresh rate.
The REFRESH period begins when the REFRESH command is
registered and ends tRFC (MIN) later.
WRITE
The WRITE command is used to initiate a burst write access to
an active row. The value on the BA[2:0] inputs selects the bank.
The value on inputA10 determines whether or not auto precharge
is used. The value on input A12 (if enabled in the MR) when the
WRITE command is issued determines whether BC4 (chop) or
BL8 is used. The WRITE command summary is shown in Table 10.
Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW, the corresponding
data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will
not be executed to that byte/column location.
PRECHARGE
SELF REFRESH
The PRECHARGE command is used to deactivate the open row
in a particular bank or in all banks. The bank(s) are available
for a subsequent row access a specified time (tRP) after the
PRECHARGE command is issued, except in the case of concurrent
auto precharge. A READ or WRITE command to a different bank
is allowed during concurrent auto precharge as long as it does not
interrupt the data transfer in the current bank and does not violate
any other timing parameters. Input A10 determines whether one
or all banks are precharged. In the case where only one bank is
precharged, inputs BA[2:0] select the bank; otherwise, BA[2:0]
are treated as “Don’t Care.” After a bank is precharged, it is in
the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command
is treated as a NOP if there is no open row in that bank (idle
state) or if the previously open row is already in the process of
precharging. However, the precharge period is determined by the
last PRECHARGE command issued to the bank.
The SELF REFRESH command is used to retain data in the DRAM,
even if the rest of the system is powered down. When in the self
refresh mode, the DRAM retains data without external clocking.
The self refresh mode is also a convenient method used to enable/
disable the DLL (see “DLL Disable Mode”) as well as to change the
clock frequency within the allowed synchronous operating range
(see “Input Clock Frequency Change”). All power supply inputs
(including VREFCA and VREFDQ) must be maintained at valid levels
upon entry/exit and during SELF REFRESH operation. For SELF
REFRESH limitations see SRT vs ASR on pg. 14.
DLL DISABLE MODE
If the DLL is disabled by the mode register (MR1[0] can be
switched during initialization or later), the DRAM is targeted, but
not guaranteed, to operate similarly to the normal mode with a
few notable exceptions:
The DRAM supports only one value of CAS latency (CL =
REFRESH
6) and one value of CAS WRITE latency (CWL = 6).
REFRESH is used during normal operation of the DRAM and is
continued on page 16
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PRELIMINARY
FIGURE 9 – MODE REGISTER 2 (MR2) DEFINITION
A15 A14 A13
BA2 BA1 BA0
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
CWL
3
2
1
0
Mode register 2 (MR2)
01
1
0
01 01 01 01 01
01 SRTASR
01 01 01
RTT(WR)
M17 M16
Mode Register
M7 Self Refresh Temperature
M5 M4 M3
CAS Write Latency (CWL)
5 CK (tCK ≥ 2.5ns)
0
0
1
1
0
1
0
1
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
1X refresh rate (+85°C
max temperature)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6 CK (2.5ns > tCK ≥ 1.875ns)
7 CK (1.875ns > tCK ≥ 1.5ns)
8 CK (1.5ns > tCK ≥ 1.25ns)
9 CK (1.25ns > tCK ≥ 1.071ns)
10 CK (1.071ns > tCK ≥ 0.938ns)
Reserved
1
2X refresh rate (+85°C to
95°C temperature)
Auto Self Refresh
Dynamic ODT
(RTT(WR)
M6
0
(Optional)
)
M10 M9
Reserved
Disabled: Manual
Enabled: Automatic
RTT(WR) disabled
RZQ/4
0
0
1
1
0
1
0
1
1
RZQ/2
Reserved
NOTE:
1. MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
FIGURE 10 – CAS WRITE LATENCY
BC4
T11
T0
T1
T2
T6
T12
T13
T14
CK#
CK
ACTIVEn
WRITEn
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
RCD (MIN)
DQS, DQS#
AL = 5
CWL = 6
DI
n
DI
DI
DI
DQ
n + 1
n + 2
n + 3
WL = AL + CWL = 11
Indicates A Break in
Time Scale
Transitioning Data
Don’t Care
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DLL disable mode affects the read data clock-to-data strobe
relationship (tDQSCK), but not the read data-to-data strobe
relationship (tDQSQ, tQH). Special attention is needed to line
the read data up with the controller time domain when the
DLL is disabled.
AZQCLcommand should be issued with the appropriate timings
met as well.
The clock frequency range for the DLL disable mode is specified
by the parameter tCKDLL_DIS. Due to latency counter and timing
restrictions, only CL = 6 and CWL = 6 are supported.
In normal operation (DLL on), tDQSCK starts from the rising
clock edge AL + CL cycles after the READ command. In
DLL disable mode, tDQSCK starts AL + CL - 1 cycles after the
READ command. Additionally, with the DLL disabled, the
DLL disable mode will affect the read data clock to data strobe
relationship (tDQSCK) but not the data strobe to data relationship
(tDQSQ, tQH). Special attention is needed to line up read data to the
controller time domain.
value of tDQSCK could be larger than tCK
.
Compared to the DLL on mode where tDQSCK starts from the rising
clock edge AL + CL cycles after the READ command, the DLL
disable mode tDQSCK starts AL + CL - 1 cycles after the READ
command.
The ODT feature is not supported during DLL disable mode
(including dynamic ODT). The ODT resistors must be disabled
by continuously registering the ODT ball LOW by programming
RTT_NOM MR1[9, 6, 2] and RTT_WR MR2[10, 9] to “0” while in
the DLL disable mode.
WRITE operations function similarly between the DLL enable and
DLL disable modes; however, ODT functionality is not allowed with
DLL disable mode.
Specific steps must be followed to switch between the DLL
enable and DLL disable modes due to a gap in the allowed clock
rates between the two modes (tCK [AVG]MAX and tCK [DLL disable] MIN
,
INPUT CLOCK FREQUENCY CHANGE
respectively). The only time the clock is allowed to cross this clock
rate gap is during self refresh mode. Thus, the required procedure
for switching from the DLL enable mode to the DLL disable mode
is to change frequency during self refresh:
When the DDR3 SDRAM is initialized, it requires the clock to be
stable during most normal states of operation. This means that
after the clock frequency has been set to the stable state, the clock
period is not allowed to deviate except what is allowed for by the
clock jitter and spread spectrum clocking (SSC) specifications.
1. Starting from the idle state (all banks are precharged, all timings
are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR
are High-Z), set MR1[0] to “1” to disable the DLL.
The input clock frequency can be changed from one stable clock
rate to another under two conditions: self refresh mode and
precharge power-down mode. Outside of these two modes, it is
illegal to change the clock frequency. For the self refresh mode
condition, when the DDR3 SDRAM has been successfully placed
into self refresh mode and tCKSRE has been satisfied, the state of
the clock becomes a “Don’t Care.” When the clock becomes a
“Don’t Care,” changing the clock frequency is permissible, provided
the new clock frequency is stable prior to tCKSRX. When entering
and exiting self refresh mode for the sole purpose of changing
the clock frequency, the self refresh entry and exit specifications
must still be met.
2. Enter self refresh mode after tMOD has been satisfied.
3. After tCKSRE is satisfied, change the frequency to the desired
clock rate.
4. Self refresh may be exited when the clock is stable with the
new frequency for tCKSRX. After tXS is satisfied, update the mode
registers with appropriate values.
5. The DRAM will be ready for its next command in the DLLdisable
mode after the greater of tMRD or tMOD has been satisfied.AZQCL
command should be issued with appropriate timings met as well.
A similar procedure is required for switching from the DLL disable
mode back to the DLL enable mode. This also requires changing
the frequency during self refresh mode.
The precharge power-down mode condition is when the DDR3
SDRAM is in precharge power-down mode (either fast exit
mode or slow exit mode). Either ODT must be at a logic LOW or
RTT_NOM and RTT_WR must be disabled via MR1 and MR2.
This ensures RTT_NOM and RTT_WR are in an off state prior
to entering precharge power-down mode, and CKE must be at a
logic LOW. A minimum of tCKSRE must occur after CKE goes LOW
before the clock frequency can change. The DDR3 SDRAM input
clock frequency is allowed to change only within the minimum and
maximum operating frequency specified for the particular speed
grade (tCK [AVG]MIN to tCK [AVG]MAX). During the input clock frequency
change, CKE must be held at a stable LOW level. When the input
clock frequency is changed, a stable clock must be provided to
the DRAM tCKSRX before precharge power-down may be exited.
After precharge power-down is exited and tXP has been satisfied,
the DLL must be reset via the MRS. Depending on the new clock
frequency, additional MRS commands may need to be issued.
During the DLLlock time, RTT_NOM and RTT_WR must remain in
an off state. After the DLL lock time, the DRAM is ready to operate
with a new clock frequency.
1. Starting from the idle state (all banks are precharged, all timings
are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR
are High-Z), enter self refresh mode.
2. After tCKSRE is satisfied, change the frequency to the new clock
rate.
3. Self refresh may be exited when the clock is stable with the
new frequency for tCKSRX. After tXS is satisfied, update the mode
registers with the appropriate values.At a minimum, set MR1[0]
to “0” to enable the DLL. Wait tMRD, then set MR0[8] to “1” to
enable DLL RESET.
4. After another tMRD delay is satisfied, then update the remaining
mode registers with the appropriate values.
5. The DRAM will be ready for its next command in the DLL
enable mode after the greater of tMRD or tMOD has been satisfied.
However, before applying any command or function requiring a
locked DLL, a delay of tDLLK after DLL RESET must be satisfied.
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PRELIMINARY
FIGURE 11 – MODE REGISTER 3 (MR3) DEFINITION
BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
18 17 16 15 14 13 12 11 10
9
8
1
7
1
6
5
4
1
3
1
2
1
0
Mode register 3 (MR3)
MPR READ Function
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
MPR MPR_RF
0
Mode Register
M2
MPR Enable
M17 M16
M1 M0
2
3
Mode register set (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
1
Normal DRAM operations
Dataflow from MPR
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Predefined pattern
Reserved
Reserved
Reserved
NOTES:
1. MR3[18 and 15:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
MPR READ PREDEFINED PATTERN
MODE REGISTER SET (MRS)
The predetermined read calibration pattern is a fixed pattern of 0,
1, 0, 1, 0, 1, 0, 1. The following is an example of using the read
out predetermined read calibration pattern. The example is to
perform multiple reads from the multipurpose register in order to
do system level read timing calibration based on the predetermined
and standardized pattern.
The mode registers are loaded via inputs BA[2:0],A[13:0]. BA[2:0]
determine which mode register is programmed:
BA2 = 0, BA1 = 0, BA0 = 0 for MR0
BA2 = 0, BA1 = 0, BA0 = 1 for MR1
BA2 = 0, BA1 = 1, BA0 = 0 for MR2
BA2 = 0, BA1 = 1, BA0 = 1 for MR3
The following protocol outlines the steps used to perform the read
calibration:
The MRS command can only be issued (or reissued) when all
banks are idle and in the precharged state (tRP is satisfied and no
data bursts are in progress). The controller must wait the specified
time tMRD before initiating a subsequent operation such as an
ACTIVATE command. There is also a restriction after issuing an
MRS command with regard to when the updated functions become
available. This parameter is specified by tMOD. Violating either of
these requirements (tMOD, TMRD) will result in unspecified operation.
Precharge all banks
After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0]
= 00. This redirects all subsequent reads and loads the
predefined pattern into the MPR. As soon as tMRD and tMOD
are satisfied, the MPR is available
Data WRITE operations are not allowed until the MPR
returns to the normal DRAM state
Issue a read with burst order information (all other address
pins are “Don’t Care”):
• A[1:0] = 00 (data burst order is fixed starting at nibble)
• A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7)
• A12 = 1 (use BL8)
After RL = AL + CL, the DRAM bursts out the predefined
read calibration pattern (0, 1, 0, 1, 0, 1, 0, 1)
The memory controller repeats the calibration reads until
read data capture at memory controller is optimized
After the last MPR READ burst and after tMPRR has been
satisfied, issue MRS, MR3[2] = 0, and MR3[1:0] = “Don’t
Care” to the normal DRAM state. All subsequent read and
write accesses will be regular reads and writes from/to the
DRAM array
When tMRD and tMOD are satisfied from the last MRS, the
regular DRAM commands (such as activate a memory bank
for regular read or write access) are permitted
(continued on page 19)
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PRELIMINARY
FIGURE 12 – MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM
Memory core
MR3[2] = 0 (MPR off)
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
DQ, DM, DQS, DQS#
NOTES:
1. A predefined data pattern can be read out of the MPR with an external READ command.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the
data flow is defined, the MPR contents can be read out continuously with a regular READ or
RDAP command.
TABLE 5 – MPR FUNCTIONAL DESCRIPTION OF MR3 BITS
MR3(2)
MPR
MR3(1:0)
Function
MPR Read Function
Normal operation, no MPR transaction
0
1
"Don't Care"
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
Enable MPR mode, subsequent READ/RDAP commands defined by bits
A(1:0)
1 and 2
TABLE 6 – MPR READOUTS AND BURST ORDER BIT MAPPING
MR3(2)
MR3(1:0)
Functions
Burst Length
Read A[2:0]
Function
Burst order: 0 ,1, 2, 3, 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
BL8
000
Read predefined
pattern for
system
Burst order: 0 ,1, 2, 3
Predefined pattern: 0, 1, 0, 1
1
00
BC4
BC4
000
100
calibration
Burst order: 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1
1
1
1
01
10
11
RFU
RFU
RFU
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
NOTE:
1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent.
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PRELIMINARY
still applies. The tFAW (MIN) parameter applies, regardless of the
number of banks already opened or closed.
ZQ CALIBRATION OPERATION
The ZQ CALIBRATION command is used to calibrate the DRAM
output drivers (RON) and ODT values (RTT) over process, voltage,
and temperature, provided a dedicated 240Ω (±1 percent) external
resistor is connected from the DRAM’s ZQ ball to VSSQ. DDR3
SDRAM need a longer time to calibrate RON and ODT at power-
up initialization and self refresh exit and a relatively shorter time
to perform periodic calibrations. DDR3 SDRAM defines two ZQ
CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and
ZQ CALIBRATION SHORT (ZQCS).
READ OPERATION
READ bursts are initiated with a READ command. The starting
column and bank addresses are provided with the READ command
and auto precharge is either enabled or disabled for that burst
access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto
precharge is disabled, the row will be left open after the completion
of the burst.
All banks must be precharged and tRP must be met before ZQCLor
ZQCS commands can be issued to the DRAM. No other activities
(other than another ZQCL or ZQCS command may be issued to
another DRAM) can be performed on the DRAM channel by the
controller for the duration of tZQINIT or tZQOPER . The quiet time on
the DRAM channel helps accurately calibrate RON and ODT.After
DRAM calibration is achieved, the DRAM should disable the ZQ
ball’s current consumption path to reduce power.
During READ bursts, the valid data-out element from the starting
column address is available READ latency (RL) clocks later. RL
is defined as the sum of POSTED CAS ADDITIVE latency (AL)
and CAS latency (CL) (RL = AL + CL). The value of AL and CL is
programmable in the mode register via the MRS command. Each
subsequent data-out element will be valid nominally at the next
positive or negative clock edge (that is, at the next crossing of
CK and CK#).
ZQ CALIBRATION commands can be issued in parallel to DLL
RESET and locking time. Upon self refresh exit, an explicit ZQCL
is required if ZQ calibration is desired.
DQS, DQS# is driven by the DRAM along with the output data. The
initial low state on DQS and HIGH state on DQS# is known as the
READ preamble (tRPRE). The low state on DQS and the HIGH state
on DQS#, coincident with the last data-out element, is known as
the READ postamble (tRPST). Upon completion of a burst, assuming
no other commands have been initiated, the DQ will go High-Z.
ACTIVATE OPERATION
Before any READ or WRITE commands can be issued to a bank
within the DRAM, a row in that bank must be opened (activated).
This is accomplished via the ACTIVATE command, which selects
both the bank and the row to be activated.
Data from any READ burst may be concatenated with data from a
subsequent READ command to provide a continuous flow of data.
The first data element from the new burst follows the last element
of a completed burst. The new READ command should be issued
After a row is opened with an ACTIVATE command, a READ or
WRITE command may be issued to that row, subject to the tRCD
specification. However, if the additive latency is programmed
correctly, a READ or WRITE command may be issued prior to tRCD
(MIN). In this operation, the DRAM enables a READ or WRITE
command to be issued after theACTIVATE command for that bank,
but prior to tRCD (MIN) with the requirement that (ACTIVATE-to-
READ/WRITE) + AL ≥ tRCD (MIN) (see "POSTED CAS ADDITIVE
Latency (AL)"). tRCD (MIN) should be divided by the clock period
and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or
WRITE command can be entered. The same procedure is used
to convert other specification limits from time units to clock cycles.
tCCD cycles after the first READ command. If BC4 is enabled, tCCD
must still be met which will cause a gap in the data output. DDR3
SDRAM do not allow interrupting or truncating any READ burst.
Data from any READ burst must be completed before a subsequent
WRITE burst is allowed. To ensure the read data is completed
before the write data is on the bus, the minimum READ-to-WRITE
timing is RL + tCCD - WL + 2tCK
.
AREAD burst may be followed by a PRECHARGE command to the
same bank provided auto precharge is not activated. The minimum
READ-to-PRECHARGE command spacing to the same bank is
four clocks and must also satisfy a minimum analog time from the
READ command. This time is called tRTP (READ-to-PRECHARGE).
tRTP starts AL cycles later than the READ command. Following
the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. The PRECHARGE
command followed by another PRECHARGE command to the
same bank is allowed. However, the precharge period will be
determined by the last PRECHARGE command issued to the bank.
When at least one bank is open, any READ-to-READ command
delay or WRITE-to-WRITE command delay is restricted to tCCD
(MIN).
A subsequent ACTIVATE command to a different row in the
same bank can only be issued after the previous active row has
been closed (precharged). The minimum time interval between
successive ACTIVATE commands to the same bank is defined
If A10 is HIGH when a READ command is issued, the READ with
auto precharge function is engaged. The DRAM starts an auto
precharge operation on the rising edge which is AL + tRTP cycles
after the READ command. DRAM support a tRAS lockout feature. If
by tRC
.
AsubsequentACTIVATE command to another bank can be issued
while the first bank is being accessed, which results in a reduction
of total row-access overhead. The minimum time interval between
successive ACTIVATE commands to different banks is defined
by tRRD. No more than four bank ACTIVATE commands may be
issued in a given tFAW (MIN) period, and the tRRD (MIN) restriction
t
RAS (MIN) is not satisfied at the edge, the starting point of the auto
precharge operation will be delayed until tRAS (MIN) is satisfied. If
RTP (MIN) is not satisfied at the edge, the starting point of the auto
t
precharge operation will be delayed until tRTP (MIN) is satisfied.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 7 – TRUTH TABLE - DDR3 COMMANDS
CKE
Previous
Cycle
BA2
BA1
BA0
A11,
A9-A0
Function
Symbol
CS#
RAS#
CAS#
WE#
An
A12
A10
Notes
Next
Cycle
MODE REGISTER SET
REFRESH
MRS
REF
SRE
H
H
H
H
L
L
L
L
L
L
L
L
BA
V
OP Code
H
V
V
V
V
V
V
V
V
SELF-REFRESH Entry
H
L
H
L
L
L
L
L
V
H
L
L
V
H
H
H
H
H
V
H
L
V
6
SELF-REFRESH Exit
SRX
L
H
V
V
V
V
V
6, 7
Single bank precharge
All banks PRECHARGE
Bank activate
PRE
PREA
ACT
H
H
H
H
H
H
BA
V
V
V
V
V
L
V
V
L
L
H
L
H
BA
Row address (RA)
BL8MRS,
BC4MRS
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
8
WRITE
BC4OTF
WRS4
WRS8
H
H
H
H
L
L
H
H
L
L
L
L
BA
BA
RFU
RFU
L
L
L
CA
CA
8
8
BL8OTF
H
BL8MRS,
WRAP
H
H
L
H
L
L
BA
RFU
V
H
CA
8
WRITE
with auto
precharge
BC4MRS
BC4OTF
BL8OTF
WRAPS4
WRAPS8
H
H
H
H
L
L
H
H
L
L
L
L
BA
BA
RFU
RFU
L
H
H
CA
CA
8
8
H
BL8MRS
BC4MRS
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
8
READ
BC4OTF
BL8OTF
RDS4
RDS8
H
H
H
H
L
L
H
H
L
L
H
H
BA
BA
RFU
RFU
L
L
L
CA
CA
8
8
H
BL8MRS
BC4MRS
RDAP
H
H
L
H
L
H
BA
RFU
V
H
CA
8
READ
with auto
precharge
BC4OTF
BL8OTF
RDAPS4
RDAPS8
NOP
H
H
H
H
H
H
H
H
L
L
H
H
H
X
H
V
H
V
H
H
L
L
H
H
H
X
H
V
H
V
L
BA
BA
V
RFU
RFU
V
L
H
V
X
H
H
V
X
CA
CA
V
8
8
NO OPERATION
L
H
X
H
V
H
V
H
H
9
Device DESELECT
DES
H
L
X
X
X
10
POWER-DOWN entry
PDE
PDX
H
L
L
V
V
V
V
V
V
V
V
V
V
6
H
L
POWER-DOWN exit
H
6, 11
12
H
L
ZQ CALIBRATION LONG
ZQ QALIBRATION SHORT
ZQCL
ZQCS
H
H
H
H
X
X
X
X
X
X
H
L
X
X
L
L
NOTES: (notes 1-5 apply to the entire table)
1.
Commands are defined by states of CAS#, RAS#, CAS#, WE# and CKE at the rising edge of
the clock. The MSB of BA, RA and CA are device-density and configuration-dependent.
commands. A NOP will not terminate an operation that is executing.
The DES and NOP commands perform similarly.
10.
11.
12.
2.
RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be
held HIGH during any normal operation.
The power-down mode does not perform any REFRESH operations.
ZQ CALIBRATION LONG is used for either ZQINIT (first ZQCL command during initialization)
or ZQ oper(ZQCL command after initialization)
3.
4.
The state of ODT doesn not affect the states described in this table.
Operations apply to the bank defined by the bank address. For MRS, BA selects one of four
mode registers.
5.
6.
7.
8.
“V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
See Table 8 for additional information on CKE transition.
Self refresh exit is asynchronous.
Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC
are defined in MR0.
9.
The purpose of the NOP command is to prevent the DRAM from registering any unwanted
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 8 – TRUTH TABLE - CKE 1, 2
CKE
Current State3
Command5
Action5
Notes
Previous Cycle4 (n - 1)
Previous Cycle4 (n )
L
L
L
L
L
H
L
"Don't Care"
DES or NOP
"Don't Care"
DES or NOP
Maintain power-down
Power-down exit
Power-down
Maintain self refresh
Self refresh exit
Self Refresh
H
Active power-down
entry
Bank(s) Active
H
L
DES or NOP
Reading
Writing
H
H
H
L
L
L
DES or NOP
DES or NOP
DES or NOP
Power-down entry
Power-down entry
Power-down entry
Precharging
Precharge power-
down entry
Refreshing
H
L
DES or NOP
Precharge power-
down entry
H
H
L
L
DES or NOP
REFRESH
All banks idle
6
Self Refresh
NOTES:
1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
2. CKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks.
Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (MIN) + tIH
t
.
3. Current state = The state of the DRAM immediately prior to clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge.
5. COMMAND is the command registered at the clock edge (must be a legal command as defined in Table 7). Action is a result of COMMAND. ODT does not affect the states described in this table and is not
listed.
6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied — All self refresh exit and power-down exit parameters are also satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at
the point at which the internal precharge happens (not at the next
rising clock edge after this event). The time from READ with auto
precharge to the next ACTIVATE command to the same bank is
AL + (tRTP + tRP)*, where “*” means rounded up to the next integer.
In any event, internal precharge does not start earlier than four
clocks after the last 8n-bit prefetch.
During power-down entry, if any bank remains open after all in-
progress commands are complete, the DRAM will be in active
power-down mode. If all banks are closed after all in-progress
commands are complete, the DRAM will be in precharge power-
down mode. Precharge power-down mode must be programmed
to exit with either a slow exit mode or a fast exit mode. When
entering precharge power-down mode, the DLL is turned off in
slow exit mode or kept on in fast exit mode.
POWER-DOWN MODE
The DLL remains on when entering active power-down as well.
ODT has special timing constraints when slow exit mode precharge
power-down is enabled and entered.
Power-down is synchronously entered when CKE is registered
LOW coincident with a NOP or DES command. CKE is not
allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or
WRITE operation is in progress. CKE is allowed to go LOW while
any of the other legal operations (such as ROW ACTIVATION,
PRECHARGE, auto precharge, or REFRESH) are in progress.
However, the power-down ICC specifications are not applicable until
such operations have been completed. Depending on the previous
DRAM state and the command issued prior to CKE going LOW,
certain timing constraints must be satisfied.
While in either power-down state, CKE is held LOW, RESET# is
held HIGH, and a stable clock signal must be maintained. ODT
must be in a valid state but all other input signals are a “Don’t Care.”
If RESET# goes LOW during power-down, the DRAM will switch
out of power-down mode and go into the reset state. After CKE is
registered LOW, CKE must remain LOW until tPD (MIN) has been
satisfied. The maximum time allowed for powerdown duration is
tPD (MAX) (9 × tREFI).
Entering power-down disables the input and output buffers,
excluding CK, CK#, ODT, CKE, and RESET#. NOP or DES
commands are required until tCPDED has been satisfied, at which
time all specified input/output buffers will be disabled. The DLL
should be in a locked state when power-down is entered for the
fastest power-down exit timing. If the DLL is not locked during
power-down entry, the DLL must be reset after exiting power-down
mode for proper READ operation as well as synchronous ODT
operation.
The power-down states are synchronously exited when CKE is
registered HIGH (with a required NOP or DES command). CKE
must be maintained HIGH until tCKE has been satisfied. A valid,
executable command may be applied after power-down exit
latency, tXP tXPDLL have been satisfied.
For certain CKE-intensive operations, for example, repeating a
power-down exit to refresh to power-down entry sequence, the
number of clock cycles between power-down exit and power-
down entry may not be sufficient enough to keep the DLL properly
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
updated. In addition to meeting tPD when the REFRESH command
is used in between power-down exit and power-down entry, two
other conditions must be met. First, tXP must be satisfied before
issuing the REFRESH command. Second, tXPDLL must be satisfied
before the next power-down may be entered.
The memory controller may drive DQS LOW and DQS# HIGH after
tWLDQSEN has been satisfied. The controller may begin to toggle
DQS after tWLMRD (one DQS toggle is DQS transitioning from a
LOW state to a HIGH state with DQS# transitioning from a HIGH
state to a LOW state, then both transition back to their original
states).At a minimum, ODTL on and tAON must be satisfied at least
one clock prior to DQS toggling.
WRITE LEVELING
After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied,
the memory controller may provide either a single DQS toggle or
multiple DQS toggles to sample CK for a given DQS-to-CK skew.
Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN)
specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not
applicable during write leveling mode. The DQS must be able to
distinguish the CK’s rising edge within tWLS and tWLH. The prime
DQ will output the CK’s status asynchronously from the associated
DQS rising edge CK capture within tWLO. The remaining DQ that
always drive LOW when DQS is toggling must be LOW within
tWLOE after the first tWLO is satisfied (the prime DQ going LOW).
As previously noted, DQS is an input and not an output during
this process.
For better signal integrity, DDR3 SDRAM memory modules
adopted fly-by topology for the commands, addresses, control
signals, and clocks. Write leveling is a scheme for the memory
controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK
relationship at the DRAM with a simple feedback feature provided
by the DRAM. Write leveling is generally used as part of the
initialization process, if required. For normal DRAM operation, this
feature must be disabled. This is the only DRAM operation where
the DQS functions as an input (to capture the incoming clock) and
the DQ function as outputs (to report the state of the clock). Note
that nonstandard ODT schemes are required.
The memory controller using the write leveling procedure must
have adjustable delay settings on its DQS strobe to align the rising
edge of DQS to the clock at the DRAM pins. This is accomplished
when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller
repeatedly delays the DQS strobe until a CK transition from “0” to
“1” is detected. The DQS delay established through this procedure
helps ensure tDQSS, tDSS, and tDSH specifications in systems that
use fly-by topology by deskewing the trace length mismatch.
The memory controller will likely sample each applicable prime DQ
state and determine whether to increment or decrement its DQS
delay setting. After the memory controller performs enough DQS
toggles to detect the CK’s “0-to-1” transition, the memory controller
should lock the DQS delay setting for that DRAM. After locking
the DQS setting, leveling for the rank will have been achieved,
and the write leveling mode for the rank should be disabled or
reprogrammed (if write leveling of another rank follows).
When write leveling is enabled, the rising edge of DQS samples
CK, and the prime DQ outputs the sampled CK’s status. The prime
DQ for a x8 configuration is DQ0 with all other DQ[7:1] driving low.
WRITE LEVELING MODE EXIT PROCEDURE
After the DRAM are leveled, they must exit from write leveling
mode before the normal mode can be used. After the last rising
DQS (capturing a “1” at T0), the memory controller should stop
driving the DQS signals after tWLO (MAX) delay plus enough delay
to enable the memory controller to capture the applicable prime
DQ state (at ~Tb0). The DQ balls become undefined when DQS
no longer remains LOW, and they remain undefined until tMOD after
the MRS command (at Te1).
The write leveling mode register interacts with other mode registers
to correctly configure the write leveling functionality. Besides using
MR1[7] to disable/enable write leveling, MR1[12] must be used to
enable/disable the output buffers. The ODT value, burst length,
and so forth need to be selected as well. It should also be noted
that when the outputs are enabled during write leveling mode,
the DQS buffers are set as inputs, and the DQ are set as outputs.
Additionally, during write leveling mode, only the DQS strobe
terminations are activated and deactivated via the ODT ball. The
DQ remain disabled and are not affected by the ODT ball.
The ODT input should be deasserted LOW such that ODTL off
(MIN) expires after the DQS is no longer driving LOW. When ODT
LOW satisfies tIS, ODT must be kept LOW (at ~Tb0) until the
DRAM is ready for either another rank to be leveled or until the
normal mode can be used. After DQS termination is switched off,
write level mode should be disabled via the MRS command (at
Tc2). After tMOD is satisfied (at Te1), any valid command may be
registered by the DRAM. Some MRS commands may be issued
after tMRD (at Td1).
WRITE LEVELING PROCEDURE
A memory controller initiates the DRAM write leveling mode by
setting MR1[7] to a “1,” assuming the other programable features
(MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset
and locked. The DQ balls enter the write leveling mode going from
a High-Z state to an undefined driving state, so the DQ bus should
not be driven. During write leveling mode, only the NOP or DES
commands are allowed. The memory controller should attempt
to level only one rank at a time; thus, the outputs of other ranks
should be disabled by setting MR1[12] to a “1” in the other ranks.
The memory controller may assert ODT after a tMOD delay as the
DRAM will be ready to process the ODT transition. ODT should
be turned on prior to DQS being driven LOW by at least ODTL on
delay (WL - 2 tCK), provided it does not violate the aforementioned
t
MOD delay requirement.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 9 – READ COMMAND SUMMARY
CKE
Previous
Cycle
Next
Cycle
BA
[3:0]
A[11,
9:0]
Function
BL8MRS, BC4MRS
Symbol
RD
CS#
L
RAS#
CAS#
WE#
H
An
A12
V
A10
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
BA
BA
BA
BA
BA
BA
RFU
RFU
RFU
RFU
RFU
RFU
CA
CA
CA
CA
CA
CA
Read
BC4OTF
BL8OTF
RDS4
L
H
L
L
RDS8
L
H
H
L
BL8MRS, BC4MRS
BC4OTF
RDAP
RDAPS4
RDAPS8
L
H
V
H
Read with auto
precharge
L
H
L
H
BL8OTF
L
H
H
H
TABLE 10 – WRITE COMMAND SUMMARY
CKE
Previous
Cycle
Next
Cycle
BA
[3:0]
A[11,
9:0]
Function
Symbol
WR
CS#
L
RAS#
CAS#
WE#
An
A12
V
A10
L
BL8MRS, BC4MRS
BC4OTF
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
BA
BA
BA
BA
BA
BA
RFU
RFU
RFU
RFU
RFU
RFU
CA
CA
CA
CA
CA
CA
Write
WRS4
L
L
L
BL8OTF
WRS8
L
H
L
BL8MRS, BC4MRS
BC4OTF
WRAP
WRAPS4
WRAPS8
L
V
H
Write with auto
precharge
L
L
H
BL8OTF
L
H
H
TABLE 11 – READ ELECTRICAL CHARACTERISTICS, DLL DISABLE MODE
Parameter
Access window of DQS from CK, CK#
Symbol
Min
Max
Units
tDQSCK (DLL_DIS)
1
10
ns
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 12 – ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
MIN
-0.4
-0.4
-0.4
-55
MAX
1.85
1.85
1.85
125
Unit
V
Notes
Voltage on VCC pin relative to VSS
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage temperature
1
VCCQ
V
VIN, VOUT
TSTG
V
°C
NOTES:
1.
V
CC and VCCQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VCCQ. When VCC and VCCQ are less than 500mV, VREF may be ≤300mV.
TABLE 13 – DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Typical
1.35
Max
1.45
1.45
Unit
V
Notes
1, 2, 3
1, 2, 3
Min
Supply voltage
1.283
1.283
I/O Supply voltage
Input leakage current
VCCQ
1.35
V
Any input 0V ≤ VIN ≤ VCC, VREF pin 0V ≤ VIN ≤ 1.1V (All
other pins not under test = 0V)
II
-20
-10
-
20
10
μA
μA
VREF supply leakage current
VREFDQ = VCC/2 or VREFCA = VCC/2
IVREF
4
-
(All other pins not under test = 0V)
NOTES:
1.
2.
3.
V
V
V
CC and VCCQ must track one another. VCCQ must be less than or equal to VCC. VSS = VSSQ.
CC and VCCQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0Hz to 250 kHz) specifications. VCC and VCCQ must be at same level for valid AC timing parameters.
CC and VCCQ are tied.
4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal.
Table 14 – DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
VSS
Nom
n/a
Max
See table 18
VCC
Units
Notes
VIN low; DC/commands/address busses
VIL
V
V
V
V
V
V
IN high; DC/commands/address busses
VIH
See table 18
0.49 X VCC
0.49 x VCC
Vss
n/a
Input reference voltage command/address bus
I/O reference voltage DQ bus
VREFCA(DC)
VREFDQ(DC)
VREFDQ(sr)
0.5 X VCC
0.5 X VCC
0.5 X VCC
0.51 X VCC
0.51 x VCC
VCC
1, 2
2, 3
4
I/O reference voltage DQ bus in SELF REFRESH
Command/address termination voltage
(system level, not direct DRAM input)
NOTES:
VTT
–
0.5 x VCC
Q
–
V
5
1.
V
REFCA(DC) is expected to be approximately 0.5 x VCC and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed
±1 % x VCC around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC)
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces aCCitional AC noise greater than 20 MHz in frequency.
.
3.
VREFDQ(DC) is expected to be approximately 0.5 x VCC and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed
±1 % x VCC around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC)
.
4.
5.
V
V
REFDQ(DC) may transition to VREFDQ(sr) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section.
TT is not applied directly to the DRAM component. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent.
TABLE 15 – BGA THERMAL RESISTANCE FOR W3J512M32K-XBX
Description
Symbol
Theta JB
Theta JC
Typical
TBD
Units
°C/W
°C/W
Notes
Junction to Board
Junction to Case (Top)
1
1
TBD
The JEDEC JESD51 specifications are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input
to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board definition specifications; therefore, Microsemi PMG recommends a customized
evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 16 – BGA THERMAL RESISTANCE FOR W3J512M32KT-XB2X
Description
Symbol
Theta JB
Theta JC
Typical
TBD
Units
°C/W
°C/W
Notes
Junction to Board
Junction to Case (Top)
1
1
TBD
The JEDEC JESD51 specifications are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input
to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board definition specifications; therefore, Microsemi PMG recommends a customized
evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request.
TABLE 17 – AC INPUT OPERATING CONDITIONS
DDR3-800
DDR3-1066
Parameter
Symbol
DDR3-1333
Unit
Command and Address
VIH(AC160)min
VIH(AC135)min
VIH(DC90)min
Input high AC voltage: Logic 1
Input high AC voltage: Logic 1
Input high DC voltage: Logic 1
Input low DC voltage: Logic 0
Input low AC voltage: Logic 0
Input low AC voltage: Logic 0
+160
+135
+90
+160
+135
+90
mV
mV
mV
mV
mV
mV
VIL(DC90)max
VIL(AC135)max
VIL(AC160)max
DQ and DM
–90
–90
–135
–160
–135
–160
Input high AC voltage: Logic 1
Input high AC voltage: Logic 1
Input high DC voltage: Logic 1
Input low DC voltage: Logic 0
Input low AC voltage: Logic 0
Input low AC voltage: Logic 0
VIH(AC160)min
VIH(AC135)min
VIH(DC90)min
+160
+135
+90
+160
+135
+90
mV
mV
mV
mV
mV
mV
VIL(DC90)max
VIL(AC135)max
VIL(AC160)max
–90
–90
–135
–160
–135
–160
NOTE
1. All voltages are referenced to VREF, VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs.
TABLE 18 – ON-DIE TERMINATION DC ELECTRICAL CHARACTERISICS
Parameter
RTT effective impedance
Deviation of VM with respect to VCCQ/2
Symbol
RTT_EFF
∆VMM
Min
Nom
Max
Unit
Ω
Notes
1, 2
See Table 20
-10
+5
%
1, 2, 3
NOTES
1. 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VCCQ = VCC, VSSQ = VSS).
2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]:
RTT = VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC)
)
3. Measure voltage (VM) at the tested pin with no load:
∆VM =
(
2 x VM - 1
VCCQ
)
x 100
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
27
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 19 – AC INPUT OPERATING CONDITIONS
MR1 [9, 6, 2]
RTT
Resistor
VOUT
0.2 x VCCQ
Min
0.6
0.9
0.9
0.9
0.9
0.6
0.8
0.6
0.9
0.9
0.9
0.9
0.6
0.8
0.6
0.9
0.9
0.9
0.9
0.6
0.8
0.6
0.9
0.9
0.9
0.9
0.6
0.8
0.6
0.9
0.9
0.9
0.9
0.6
0.8
Nom
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
1.15
1.15
1.45
1.45
1.15
1.15
1.85
1.15
1.15
1.45
1.45
1.15
1.15
1.85
1.15
1.15
1.45
1.45
1.15
1.15
1.85
1.15
1.15
1.45
1.45
1.15
1.15
1.85
1.15
1.15
1.45
1.45
1.15
1.15
1.85
Units
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/4
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/6
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/8
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/12
0, 1, 0
120Ω
RTT120PD240
0.5 x VCCQ
0.8 x VCCQ
RTT120PU240
0.2 x VCCQ
0.5 x VCCQ
0.8 x VCCQ
120Ω
RTT60PD120
VIL(AC) to VIH(AC)
0.2 x VCCQ
0, 0, 1
0, 1, 1
1, 0, 1
1, 0, 0
60Ω
40Ω
30Ω
20Ω
0.5 x VCCQ
0.8 x VCCQ
RTT60PU120
0.2 x VCCQ
0.5 x VCCQ
0.8 x VCCQ
60Ω
40Ω
30Ω
20Ω
VIL(AC) to VIH(AC)
0.2 x VCCQ
RTT40PD80
0.5 x VCCQ
0.8 x VCCQ
RTT40PU80
0.2 x VCCQ
0.5 x VCCQ
0.8 x VCCQ
VIL(AC) to VIH(AC)
0.2 x VCCQ
RTT30PD60
0.5 x VCCQ
0.8 x VCCQ
RTT30PU60
0.2 x VCCQ
0.5 x VCCQ
0.8 x VCCQ
VIL(AC) to VIH(AC)
0.2 x VCCQ
RTT20PD40
0.5 x VCCQ
0.8 x VCCQ
RTT20PU40
0.2 x VCCQ
0.5 x VCCQ
0.8 x VCCQ
VIL(AC) to VIH(AC)
NOTES
1. Values assume an RZQ of 240ꢀ (±1 percent).
2. RTTXXPU and RTTXXPD are for reference only. Only RTT for VOUT from VIL(AC) to VIH(AC) are tested and guaranteed.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
28
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 20 – DDR3 ICC SPECIFICATIONS AND CONDITIONS – W3J512M32K(T)
800 CL6
1,066 CL8
Symbol
Proposed Conditions
1,333 CL10
Units
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
220
188
248
mA (1, 2)
ICC0
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bud inpuyd str plosyinh
264
mA (1, 2)
ICC1
ICC2P
ICC2Q
Fast
128
72
112
72
mA (1, 2)
mA (1, 2)
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Slow
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
128
112
mA (1, 2)
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
128
152
152
116
140
140
mA (1, 2)
mA (1, 2)
mA (1, 2)
ICC2N
ICC3P
ICC3N
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
All banks open, Continuous burst writes; BL = 8, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS#
is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
500
628
940
440
560
912
mA (1, 2)
mA (1, 2)
mA (1, 2)
ICC4W
ICC4R
ICC5B
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W
Burst auto refresh current;
t
CK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK, CK# and CKE are low. Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
80
80
mA (1, 2, 3)
mA (2, 4)
ICC6
Self refresh current extended temperature:
CK, CK# and CKE are low; other control and address bus inputs are floating; data bus inputs are floating
100
100
ICC6ET
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD
= 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDAD6R; Refer to the following page for detailed timing conditions
880
760
mA (1, 2)
ICC7
NOTES:
1. SRT and ASR are disabled.
2. Enabling ASR could increase ICCx by up to an additional 8mA
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
29
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 21 – DDR3-800 SPEED BINS
CL-tRCD-tRP
6-6-6
Units
Notes
Parameter
ACTIVATE to internal READ or WRITE delay time
PRECHARGE command period
Symbol
tRCD
Min
15
Max
–
ns
ns
tRP
15
–
–
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
52.5
37.5
2.5
ns
ACTIVATE-to-PRECHARGE command period
tRAS
9 x tREFI
3.3
ns
1
2
CL = 6
CWL = 5
tCK (AVG)
ns
Supported CL settings
Supported CWL setting
NOTES:
6
5
CK
CK
1. tREFI depends on TOPER
.
2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled.
TABLE 22 – DDR3-1,066 SPEED BINS (3)
CL-tRCD-tRP
8-8-8
Units
Notes
Parameter
ACTIVATE to internal READ or WRITE delay time
PRECHARGE command period
Symbol
tRCD
Min
15
Max
–
–
ns
ns
tRP
15
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
52.5
37.5
1.875
–
ns
ACTIVATE-to-PRECHARGE command period
tRAS
9 x tREFI
<2.5
ns
1
2
CL = 8
CWL = 6
tCK (AVG)
ns
Supported CL settings
Supported CWL setting
NOTES:
5, 6, 8
5, 6
CK
CK
1. tREFI depends on TOPER
.
2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled.
3. These devices may not operate correctly under all conditions at 1066Mbs and 1333Mbs speeds. The proposed work around at both speeds is to enable
the auto pre-charge function in the DDR controller and to accommodate the setup and hold time changes on the DQS and DQS# signals.
TABLE 23 – DDR3-1,333 SPEED BINS (3)
CL-tRCD-tRP
10-10-10
Units
Notes
Parameter
Symbol
tAA
Min
15
Max
Internal READ command to fist data
–
–
ACTIVATE to internal READ or WRITE delay time
PRECHARGE command period
tRCD
15
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
tRP
15
–
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
51
-
ACTIVATE-to-PRECHARGE command period
tRAS
36
9 x tREFI
3.3
1
2
2
2
2
CL = 5
CWL = 5
CWL = 5
CWL = 6
CWL = 7
tCK (AVG)
tCK (AVG)
tCK (AVG)
tCK (AVG)
3.0
2.5
1.875
1.5
CL = 6
3.3
CL = 8
<2.5
<1.875
CL = 10
Supported CL settings
Supported CWL setting
NOTES:
5, 6, 8, 10
5, 6, 7
1. tREFI depends on TOPER
.
2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled.
3. These devices may not operate correctly under all conditions at 1066Mbs and 1333Mbs speeds. The proposed work around at both speeds is to enable
the auto pre-charge function in the DDR controller and to accommodate the setup and hold time changes on the DQS and DQS# signals.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
30
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 24 – AC TIMING PARAMETERS
DDR3-800
Min Max
Clock Timing
DDR3-1066
DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Commercial and Industrial
Military
8
8
7,800
3,900
8
8
7,800
3,900
8
8
7,800
3,900
ns
ns
9, 42
42
Clock period average: DLL
disable mode
tCKDLL_DIS
Clock period average: DLL enable mode
High pulse width average
tCK (AVG)
tCH (AVG)
tCL (AVG)
tJITPER
See “Speed Bin Tables” on page 35 for tCK range allowed
ns
10, 11
12
0.47
0.47
–100
–90
0.53
0.53
100
90
0.47
0.47
–90
–80
0.53
0.53
90
0.47
0.47
–80
–70
0.53
0.53
80
CK
CK
ps
Low pulse width average
12
DLL locked
13
Clock period jitter
DLL locking
tJITPER, LCK
tCK(ABS)
tCH (ABS)
tCL (ABS)
tJITCC
80
70
ps
13
Clock absolute period
MIN = tCK (AVG) MIN + tJITPER MIN; MAX = tCK (AVG) MAX + tJITPER MAX
ps
Clock absolute high pulse width
Clock absolute low pulse width
0.43
0.43
–
–
0.43
0.43
–
–
0.43
0.43
–
–
tCK (AVG)
tCK (AVG)
ps
14
15
16
16
17
17
17
17
17
17
17
17
17
17
17
DLL locked
DLL locking
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
200
180
180
160
160
140
Cycle-to-cycle jitter
tJITCC
,
ps
LCK
tERR2PER
tERR3PER
tERR4PER
tERR5PER
tERR6PER
tERR7PER
tERR8PER
tERR9PER
tERR10PER
tERR11PER
tERR12PER
–147
–175
–194
–209
–222
–232
–241
–249
–257
–263
–269
147
175
194
209
222
232
241
249
257
263
269
–132
–157
–175
–188
–200
–209
–217
–224
–231
–237
–242
132
157
175
188
200
209
217
224
231
237
242
–118
–140
–155
–168
–177
–186
–193
–200
–205
–210
–215
118
140
155
168
177
186
193
200
205
210
215
ps
ps
ps
ps
ps
ps
Cumulative error across
ps
ps
ps
ps
ps
tERRnPER MIN = (1 + 0.68ln[n]) × tJITPER MIN
tERRnPER MAX = (1 + 0.68ln[n]) × tJITPER MAX
n = 13, 14 . . . 49, 50 cycles
tERRnPER
ps
17
DQ Input Timing
Base (specification)
90
–
–
–
–
–
–
–
40
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ps
ps
ps
ps
ps
ps
ps
18, 19, 44
19, 20
18, 19, 44
19, 20
18,19
Data setup time to DQS, DQS#
Data setup time to DQS, DQS#
tDS AC160
V
REF @ 1 V/ns
Base (specification)
REF @ 1 V/ns
Base (specification)
REF @ 1 V/ns
250
140
275
160
250
600
200
90
–
90
tDS AC135
V
225
110
200
490
225
110
200
400
Data hold time from DQS,
DQS#
tDH DC90
tDIPW
V
19, 20
41
Minimum data pulse width
DQ Output Timing
DQS, DQS# to DQ skew, per access
tDQSQ
tQH
tLZ (DQ)
tHZ (DQ)
–
0.38
–800
–
200
–
–
0.38
–600
–
150
–
–
0.38
–500
–
125
–
ps
tCK (AVG)
ps
DQ output hold time from DQS, DQS#
DQ Low-Z time from CK, CK#
DQ High-Z time from CK, CK#
21
400
400
300
300
250
250
22, 23
22, 23
ps
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
31
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 24 – AC TIMING PARAMETERS (continued)
DDR3-800
Min Max
DQ Strobe Input Timing
DDR3-1066
DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
DQS, DQS# rising to CK, CK# rising
tDQSS
tDQSL
tDQSH
tDSS
–0.25
0.45
0.45
0.2
0.25
0.55
0.55
–
–0.25
0.45
0.45
0.2
0.25
0.55
0.55
–
–0.25
0.45
0.45
0.2
0.25
0.55
0.55
–
CK
CK
CK
CK
CK
CK
CK
25
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# falling setup to CK, CK# rising
DQS, DQS# falling hold from CK, CK# rising
DQS, DQS# differential WRITE preamble
DQS, DQS# differential WRITE postamble
25
25
tDSH
0.2
–
0.2
–
0.2
–
tWPRE
tWPST
0.9
–
0.9
–
0.9
–
0.3
–
0.3
–
0.3
–
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
tDQSCK
–400
1
400
10
–300
1
300
10
–255
1
255
10
ps
ns
23
26
DQS, DQS# rising to/from rising CK, CK# when DLL is disabled tDQSCK DLL_DIS
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# Low-Z time (RL - 1)
tQSH
tQSL
0.38
0.38
–800
–
–
0.38
0.38
–600
–
–
0.40
0.40
–500
–
–
CK
CK
ps
21
–
–
–
21
tLZ (DQS)
tHZ (DQS)
tRPRE
400
300
250
22, 23
22, 23
23, 24
23, 27
DQS, DQS# High-Z time (RL + BL/2)
DQS, DQS# differential READ preamble
DQS, DQS# differential READ postamble
400
300
250
ps
0.9
0.3
Note 24
Note 27
0.9
0.3
Note 24
Note 27
0.9
0.3
Note 24
Note 27
CK
CK
tRPST
Command and Address Timing
DLL locking time
tDLLK
512
215
375
365
500
285
375
900
–
–
–
–
–
–
–
–
512
140
300
290
425
210
300
780
–
–
–
–
–
–
–
–
512
80
–
–
–
–
–
–
–
–
CK
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
28
29, 30
20, 30
29, 30, 44
20, 30
29, 30
20, 30
41
Base (specification)
VREF @ 1 V/ns
CTRL, CMD, ADDR setup to CK,CK#
tIS AC160
240
205
340
150
240
620
Base (specification)
VREF @ 1 V/ns
CTRL, CMD, ADDR hold from CK,CK#
tIH (AC135)
tIH DC90
Base (specification)
VREF @ 1 V/ns
CTRL, CMD, ADDR setup to CK,CK#
Minimum CTRL, CMD, ADDR pulse width
tIPW
tRCD
tRP
ACTIVATE to internal READ or WRITE delay
PRECHARGE command period
See “Speed Bin Tables” on page 30 for tRCD
See “Speed Bin Tables” on page 30 for tRP
See “Speed Bin Tables” on page 30 for tRAS
See “Speed Bin Tables” on page 30 for tRC
31
31
ACTIVATE-to-PRECHARGE command period
ACTIVATE-to-ACTIVATE command period
tRAS
tRC
31, 32
31, 43
MIN = greater of 4CK
or 10ns
MIN = greater of 4CK
or 7.5ns
MIN = greater of 4CK
or 6ns
1KB page size
2KB page size
CK
CK
31
31
ACTIVATE-to-ACTIVATE minimum
command period
tRRD
MIN = greater of 4CK
or 7.5ns
MIN = greater of 4CK or 10ns
Four ACTIVATE windows for 1KB page size
Four ACTIVATE windows for 2KB page size
40
50
–
37.5
50
–
–
30
45
–
–
ns
ns
31
31
tFAW
–
31, 32,
33, 34
Write recovery time
tWR
MIN = 15ns; MAX = n/a
ns
Delay from start of internal WRITE transaction to internal
READ command
tWTR
MIN = greater of 4CK or 7.5ns; MAX = n/a
CK
31, 34
31, 32
READ-to-PRECHARGE time
tRTP
tCCD
tDAL
tMRD
tMOD
MIN = greater of 4CK or 7.5ns; MAX = n/a
MIN = 4CK; MAX = n/a
CK
CK
CK
CK
CK
CAS#-to-CAS# command delay
Auto precharge write recovery + precharge time
MODE REGISTER SET command cycle time
MODE REGISTER SET command update delay
MIN = WR + tRP/tCK (AVG); MAX = n/a
MIN = 4CK; MAX = n/a
MIN = greater of 12CK or 15ns; MAX = n/a
MULTIPURPOSE REGISTER READ burst end to mode
register set for multipurpose register exit
tMPRR
MIN = 1CK; MAX = n/a
CK
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 24 – AC TIMING PARAMETERS (continued)
DDR3-800
Min Max
Calibration Timing
DDR3-1066
DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
POWER-UP and RESET
operation
tZQINIT
512
–
512
–
512
–
CK
ZQCL command: Long
calibration time
Normal operation
tZQOPER
tZQCS
256
64
–
–
256
64
–
–
256
64
–
–
CK
CK
ZQCS command: Short calibration time
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command
Begin power supply ramp to power supplies stable
RESET# LOW to power supplies stable
tXPR
tVDDPR
tRPS
MIN = greater of 5CK or tRFC + 10ns; MAX = n/a
MIN = n/a; MAX = 200
CK
ms
ms
ns
MIN = 0; MAX = 200
RESET# LOW to I/O and RTT High-Z
tIOz
MIN = n/a; MAX = 20
35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH command period
Com, Ind (1X)
tRFC
MIN = 260; MAX = 70,200
7.8 (64ms/8,192)
ns
ꢁs
36
36
Military, 85°C to 95°C
Maximum average periodic
temperature (2X)
refresh
3.9 (32ms/8,192)
1.95 (16ms/8,192)
ꢁs
ꢁs
tREFI
Military, 95°C to 125°C
temperature (4X)
36
Self Refresh Timing
Exit self refresh to commands not requiring a locked DLL
Exit self refresh to commands requiring a locked DLL
tXS
MIN = greater of 5CK or tRFC + 10ns; MAX = n/a
MIN = tDLLK (MIN); MAX = n/a
CK
CK
tXSDLL
28
Minimum CKE low pulse width for self refresh entry to self refresh
exit timing
tCKESR
MIN = tCKE (MIN) + CK; MAX = n/a
CK
Valid clocks after self refresh entry or powerdown entry
tCKSRE
tCKSRX
MIN = greater of 5CK or 10ns; MAX = n/a
MIN = greater of 5CK or 10ns; MAX = n/a
CK
CK
Valid clocks before self refresh exit, powerdown exit, or reset exit
Power-Down Timing
Greater of 3CK or
7.5ns
Greater of 3CK or
5.625ns
Greater of 3CK or
5.625ns
CKE MIN pulse width
tCKE (MIN)
CK
Command pass disable delay
tCPDED
tPD
MIN = 1; MAX = n/a
MIN = tCKE (MIN); MAX = 9 × tREFI
WL - 1CK
CK
CK
CK
Power-down entry to power-down exit timing
Begin power-down period prior to CKE registered HIGH
tANPD
Power-down entry period: ODT either synchronous or
asynchronous
PDE
PDX
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
CK
CK
Power-down exit period: ODT either synchronous or
asynchronous
t
ANPD + tXPDLL
Power-Down Entry Minimum Timing
tACTPDEN
ACTIVATE command to power-down entry
MIN = 1
MIN = 1
MIN = 1
CK
CK
CK
CK
CK
CK
CK
CK
CK
PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN
REFRESH command to power-down entry
MRS command to power-down entry
tREFPDEN
tMRSPDEN
37
MIN = tMOD (MIN)
MIN = RL + 4 + 1
READ/READ with auto precharge command to power-down entry tRDPDEN
BL8 (OTF, MRS) BC4OTF
BC4MRS
tWRPDEN
tWRPDEN
tWRAPDEN
tWRAPDEN
MIN = WL + 4 + tWR/tCK (AVG)
MIN = WL + 2 + tWR/tCK (AVG)
MIN = WL + 4 + WR + 1
MIN = WL + 2 + WR + 1
WRITE command to power-
down entry
BL8 (OTF, MRS) BC4OTF
BC4MRS
WRITE with auto precharge
command to power-down entry
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
TABLE 24 – AC TIMING PARAMETERS (continued)
DDR3-800
Min Max
Power-Down Exit Timing
DDR3-1066
Min Max
DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
DLL on, any valid command, or DLL off to commands not
requiring locked DLL
MIN = greater of 3CK or
6ns; MAX = n/a
tXP
MIN = greater of 3CK or 7.5ns; MAX = n/a
CK
CK
Precharge power-down with DLL off to commands requiring a
locked DLL
tXPDLL
MIN = greater of 10CK or 24ns; MAX = n/a
28
ODT Timing
R
TT synchronous turn-on delay
TT synchronous turn-off delay
ODTL on
ODTL off
tAON
CWL + AL - 2CK
CWL + AL - 2CK
CK
CK
ps
38
40
R
RTT turn-on from ODTL on reference
–400
0.3
400
0.7
–300
0.3
300
0.7
–250
0.3
250
0.7
23, 38
39, 40
38
RTT turn-off from ODTL off reference
tAOF
CK
ns
Asynchronous RTT turn-on delay (power-down with DLL off)
Asynchronous RTT turn-off delay (power-down with DLL off)
ODT HIGH time with WRITE command and BL8
tAONPD
tAOFPD
ODTH8
MIN = 2; MAX = 8.5
MIN = 2; MAX = 8.5
MIN = 6; MAX = n/a
ns
40
CK
ODT HIGH time without WRITE command or with WRITE
command and BC4
ODTH4
MIN = 4; MAX = n/a
CK
Dynamic ODT Timing
RTT_NOM-to-RTT_WR change skew
ODTLCNW
ODTLCNW4
ODTLCNW8
tADC
WL - 2CK
CK
CK
CK
CK
RTT_WR-to-RTT_NOM change skew - BC4
RTT_WR-to-RTT_NOM change skew - BL8
4CK + ODTL off
6CK + ODTL off
RTT dynamic change skew
0.3
0.7
0.3
0.7
0.3
0.7
39
Write Leveling Timing
First DQS, DQS# rising edge
DQS, DQS# delay
t
WLMRD
40
25
–
–
40
25
–
–
40
25
–
–
CK
CK
tWLDQSEN
Write leveling setup from rising CK, CK# crossing to rising
DQS, DQS# crossing
tWLS
325
325
–
–
245
245
–
–
195
195
–
–
ps
ps
Write leveling hold from rising DQS, DQS# crossing to rising
CK, CK# crossing
tWLH
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
0
0
9
2
ns
ns
tWLOE
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
AC Overshoot/Undershoot Specification
Table 25 – Control and Address Pins
Parameter
DDR3-800
0.4V
DDR3-1066
DDR3-1333
0.4V
Maximum peak amplitude allowed for overshoot area (see Figure 14)
Maximum peak amplitude allowed for undershoot area (see Figure 15)
Maximum overshoot area above VCC (see Figure 14)
Maximum undershoot area below VSS (see Figure 15)
0.4V
0.4V
0.4V
0.4V
0.67 Vns
0.67 Vns
0.5 Vns
0.5 Vns
0.4 Vns
0.4 Vns
Table 26 – Clock, Data, Strobe, and Mask Pins
Parameter
DDR3-800
DDR3-1066
0.4V
DDR3-1333
0.4V
Maximum peak amplitude allowed for overshoot area (see Figure 14)
Maximum peak amplitude allowed for undershoot area (see Figure 15)
Maximum overshoot area above VCC/VCCQ (see Figure 14)
0.4V
0.4V
0.4V
0.4V
0.25 Vns
0.25 Vns
0.19 Vns
0.19 Vns
0.15 Vns
0.15 Vns
Maximum undershoot area below VSS/VSSQ (see Figure 15)
FIGURE 13 – OVERSHOOT
Maximum amplitude
Overshoot area
Volts (V)
VCC/VCCQ
Time (ns)
FIGURE 14 – UNDERSHOOT
VSS/VSSQ
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
NOTES:
1. Parameters are applicable with VCC/VCCQ = +1.35V ±0.075V.
24. The maximum preamble is bound by tLZDQS (MAX).
2. All voltages are referenced to VSS.
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its
respective clock signal (CK, CK#) crossing. The specification values are not affected by
the amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.
26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by tHZDQS (MAX).
3. Output timings are only valid for RON34 output buffer selection.
4. Unit “tCK (AVG)” represents the actual tCK (AVG) of the input clock under operation. Unit “CK”
represents one clock cycle of the input clock, counting the actual clock edges.
5. AC timing and ICC tests may use a VIL-to-VIH swing of up to 900mV in the test environment,
but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points
and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input
signals used to test the device is 1 V/ns for single ended inputs and 2 V/ns for differential inputs
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands.
In addition, after any change of latency tXPDLL, timing must be met.
in the range between VIL(AC) and VIH(AC)
.
29.
t
IS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew
6. All timings that use time-based values (ns, ꢁs, ms) should use tCK (AVG) to determine the
correct number of clocks (AC Operation Table). In the case of non integer results, all minimum
limits are to be rounded up to the nearest whole integer, and all maximum limits are to be
rounded down to the nearest whole integer.
7. The use of “strobe” or “DQSDIFF” refers to the DQS and DQS# differential crossing point when
DQS is the rising edge. The use of “clock” or “CK” refers to the CK and CK# differential crossing
point when CK is the rising edge.
8. This output load is used for all AC timing (except ODT reference timing) and slew rates. The
actual test load may be different. The output signal voltage reference point is VCCQ/2 for single-
ended signals and the crossing point for differential signals.
rate and 2 V/ns CK, CK# differential slew rate.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by the
amount of clock jitter applied as the setup and hold times are relative to the clock signal
crossing that latches the command/address. These parameters should be met whether clock
jitter is present.
31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/ CK[AVG] [ns])
assuming all input clock jitter specifications are satisfied. For example, the device will support
nRP (nCK) = RU(tRP/ CK[AVG]) if all input clock jitter specifications are met. This means for DDR3-800
6-6-6, of which tRP = 15ns, the device will support tnRP = RU( RP/ CK[AVG]) = 6 as long as the input
t
,
t
t
t
t
9. When operating in DLL disable mode, Microsemi does not warrant compliance with normal
mode timings or functionality.
10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK(AVG) MIN is
the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock
jitter is allowed provided it does not exceed values specified and must be of a random Gaussian
distribution in nature.
clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE
command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal
PRECHARGE command until tRAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR
34. The start of the write recovery time is defined as follows:
.
11. Spread spectrum is not included in the jitter specification values. However, the input clock can
accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional
1 percent of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not
use a clock rate below tCK (AVG) MIN.
12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive
clocks and is the smallest clock half period allowed, with the exception of a deviation due to
clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be
of a random Gaussian distribution in nature.
13. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or
nominal clock. It is allowed in either the positive or negative direction.
14. tCH(ABS) is the absolute instantaneous clock high pulse width as measured from one rising
edge to the following falling edge.
– For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
– For BC4 (OTF): Rising clock edge four clock cycles after WL
– For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z.
Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current,
depending on bus activity.
36. The refresh period is 64ms up to +85°C. This equates to an average refresh rate of 7.8125ꢁs.
However, nine REFRESH commands must be asserted at least once every 70.3ꢁs.
37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN
(MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required.
38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on.
ODT turn-on time maximum is when the ODT resistance is fully on.
15. tCL(ABS) is the absolute instantaneous clock low pulse width as measured from one falling
edge to the following rising edge.
39. Half-clock output parameters must be derated by the actual tERR10PER and tJITDTY when input
clock jitter is present. This results in each parameter becoming larger. The parameters tADC
(MIN) and tAOF (MIN) are each required to be derated by subtracting both tERR10PER (MAX)
and tJITDTY (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by
subtracting both tERR10PER (MAX) and tJITDTY (MAX).
40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off
time maximum is when the DRAM buffer is in High-Z. This output load is used for ODT timings.
41. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and
16. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one cycle to the
next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time.
17. The cumulative jitter error (tERRnPER), where n is the number of clocks between 2 and 50, is the
amount of clock time allowed to accumulate consecutively away from the average clock over n
number of clock cycles.
18.
t
DS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns
differential DQS, DQS# slew rate.
the consecutive crossing of VREF(DC)
.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition
edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which derating
tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are
for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated by the
actual tJITPER of the input clock (output deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters
must be derated by the actual jitter error when input clock jitter is present, even when within
specification. This results in each parameter becoming larger. The following parameters are
required to be derated by subtracting tERR10PER (MAX): tDQSCK (MIN), tLZ (DQS)MIN, tLZ (DQ)
MIN, and tAON (MIN). The following parameters are required to be derated by subtracting
42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should have at
least one NOP command between it and another AUTO REFRESH command. Additionally, if
the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a
PRECHARGE ALL command.
43. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses
to a particular row address may result in reduction of the product lifetime.
44. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed
bin, the user may choose either value for the input AC level. Whichever value is used, the
associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be
used for address/command inputs and the other VIH(AC) value may be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and VIH(AC150),min
(corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/ command inputs
must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min with tIS(AC150) of 350ps;
independently, the data inputs must use either VIH(AC175),min with tDS(AC175) of 75ps or VIH(AC150),min
with tDS(AC150) of 125ps.
tERR10PER (MIN): tDQSCK (MAX), tHZ (MAX), tLZ (DQS)MAX, tLZ (DQ) MAX, and tAON (MAX). The
parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by
subtracting tJITPER (MIN).
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
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W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
FIGURE 15 – PACKAGE DIMENSION: 136 PLASTIC BALL GRID ARRAY (PBGA) for W3J512M32KT-XBX
BOTTOM VIEW
12 11 10
9
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.8 (0.031) NOM
0.3
(0.012)
NOM
8.8 (0.346) NOM
10.1 (0.398) MAX
3.540
(0.139)
MAX
• Pads are Solder Mask Defined (SMD), pads openings: 0.4mm
• Solder balls composition: Eutectic Sn63 Pb37
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
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37
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
FIGURE 15A – PACKAGE DIMENSION: 204 PBGA, for W3J512M32T-XB2X
BOTTOM VIEW
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.8 (0.031) NOM
0.3
(0.012)
NOM
8.8 (0.346) NOM
10.1 (0.398) MAX
3.540
(0.139)
MAX
• Pads are Solder Mask Defined (SMD), pads openings: 0.4mm
• Solder balls composition: Eutectic Sn63 Pb37
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 4
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
ORDERING INFORMATION
W 3J 512M 32 K T - XXXX XX X
MICROSEMI CORPORATION:
DDR3 SDRAM:
CONFIGURATION, 512M x32:
1.35V POWER SUPPLY:
OPTIONAL:
T = Address/Control Termination resistors included. B2 package only.
DATA RATE (Mb/s):
800 = 800Mb/s
1066 = 1,066Mb/s
1333 = 1,333Mb/s
PACKAGE:
B = 136 Plastic Ball Grid Array (PBGA) – No address/control termination, no clock
termination, with calibration resistors.
B2 = 204 PBGA, x32 with clock termination, with calibration resistors with address/
control termination. Only option available is 512M32KT.
DEVICE GRADE:
M = Military
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
I
= Industrial
C
= Commercial
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W3J512M32K-XBX
W3J512M32KT-XB2X
PRELIMINARY
Document Title
2GB – 512M x 32/40 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
April 2014
Preliminary
Rev 1
Rev 2
Change (Pg. 1)
June 2014
Preliminary
1.1 Change W3J512M36K(T)-XB2X to W3J512M32K(T)-XB2X “B2” package is
for X32 with termination.
Changes (Pg. 1, 3, 4, 40, 41, 42, 43)
September 2014
Preliminary
2.1 Remove all reference to x36 package
2.2 Remove functional block diagram for x36 configuration
2.3 “B2” package only available in x32 bit data configuration with address/control
terminations
Rev 3
Rev 4
Changes (Pg. 23)
December 2014
April 2015
Preliminary
Preliminary
3.1 Correct Table 7 “Bank Activate” values for RAS#, CAS# and WE#
Changes (Pgs. 1-40)
4.1 Remove x40 data width option including block diagram and package drawing
4.2 Change DQ timing for DDR3 - 1333
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2015 © 2015 Microsemi Corporation. All rights reserved.
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40
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相关型号:
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W3J512M32K-1066BC
DDR DRAM, 512MX32, 0.3ns, CMOS, PBGA136, 10 X 14.50 MM, 0.80 MM PITCH, PLASTIC, BGA-136
MICROSEMI
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W3J512M32K-1066BI
DDR DRAM, 512MX32, 0.3ns, CMOS, PBGA136, 10 X 14.50 MM, 0.80 MM PITCH, PLASTIC, BGA-136
MICROSEMI
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W3J512M32K-1066BM
DDR DRAM, 512MX32, 0.3ns, CMOS, PBGA136, 10 X 14.50 MM, 0.80 MM PITCH, PLASTIC, BGA-136
MICROSEMI
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