W764M32V1-110BC [MERCURY]
Flash, 64MX32, 110ns, PBGA107, 14 X 17 MM, 1 MM PITCH, PLASTIC, BGA-107;
| 型号： | W764M32V1-110BC |
| 厂家： | 
MERCURY UNITED ELECTRONICS INC |
| 描述： | Flash, 64MX32, 110ns, PBGA107, 14 X 17 MM, 1 MM PITCH, PLASTIC, BGA-107 内存集成电路 闪存 |
| 文件： | 总17页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W764M32V1-XBX
256MB – 64Mx32 NOR Flash Multi-Chip Package 3V Page Mode Memory
FEATURES
GENERAL DESCRIPTION
The W764M32V1-XBX device is a 3V single power flash memory.
The device utilizes two chips organized as 67,108,864 words. The
device has a 32-bit wide data bus and can be user defined as 2
ranks of 64M x 16-bit data.
Single power supply operation
• 3 Volt read, erase, and program operations
I/O Control
• Wide I/O voltage range (VIO): 1.8V to VCC
Each device requires a single 3 volt power supply for both read
and write functions.
• All input levels (address, control, and DQ input levels)
and outputs are determined by voltage on VIO input.
*This product is subject to change without notice.
Separate 1024-byte One Time Program (OTP) array with
two lockable regions
Uniform sector architecture
• One thousand twenty four 128 Kbyte sectors
100,000 erase cycles per sector typical
20-year data retention typical
Commercial, industrial and military temperature ranges
Organized as 64M x 32, user configurable as 2 ranks of
64M x 16
PERFORMANCE CHARACTERISTICS
High Performance
• 110, 120 ns
• 32-byte page read buffer
• 15, 20 ns page read times
• 512-byte write buffer reduces overall programming time
for multiple-word updates
Package option
• 107 BGA, 14mm x 17mm
• 1.0mm pitch
Footprint compatible with W764M32V-XSBX
Upgradeable to 2 x 64M x 32 and to 4 x 64M x 32 in same
footprint
Software features
• Suspend and resume commands for program and erase
operations
• Data# polling and toggle bits provide status
• CFI (Common Flash Interface) parameter table
Hardware features
• Advanced Sector Protection (ASP)
• Hardware reset input (RESET#) resets device
• Status Register, data polling, and ready/busy pin methods
to determine device status.
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 5
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W764M32V1-XBX
FIGURE 1 – PIN CONFIGURATION (TOP VIEW)
1 2 3 4 5 6 7 8 9
VCC DQ24 DQ8 GND
DQ10 DQ25 DQ9 GND
A1
A2
A4
A5
A6
VCC
A7
GND
VIO
A
B
C
D
E
F
A
VIO
B
C
D
E
F
DQ12 DQ27 DQ11 DQ26 GND OE#
RY/BY#
A8
RESET# WP#
DQ13 DQ29 DQ28 DNU GND
A3
VIO
A15
DQ14 DQ30 DQ31
VIO
VCC
VCC
VIO
GND
GND
GND
GND
CS0# WE1# A16
DQ15 GND
DQ0 GND
VIO
VIO
VCC
VCC
VIO
VIO
GND
GND
A23
A24
G
H
J
G
H
J
DQ1 DQ17 DQ16
DQ18 DQ2
DQ19 DQ4 DQ20 DQ21 GND
VIO CS1# WE0# A18
DQ3 DNU GND
A20
A0
A21
A11
A13
A14
A22
A10
A12
VCC
A19
A9
K
L
K
L
VIO
DQ5
DQ6 DQ23 GND
A17
A25
VIO
GND
VCC DQ22 DQ7 GND
GND
M
M
1 2 3 4 5 6 7 8 9
PIN DESCRIPTION
BLOCK DIAGRAM
DQ0-31
A0-25
WE#0-1
CS#0-1
OE#
Data Inputs/Outputs
Address Inputs
Write Enables
WE0#
CS0#
WE1#
CS1#
RY/BY#
RESET#
OE#
Chip Selects
Output Enable
Hardware Reset
Hardware Write Protection
Ready/Busy Output
Power Supply
A0-25
RESET#
WP#
64M X 16
DQ0-15
64M X 16
RY/BY#
VCC
VIO
I/O Power Supply
Ground
WP#
GND
DQ16-31
DNU
Do Not Use
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November 2015 © 2015 Microsemi Corporation. All rights reserved.
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W764M32V1-XBX
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
V
Supply Voltage Range (VCC)
Signal Voltage Range (other than RESET#)
I/O Voltage Range (VIO)
RESET#
-0.5 to +4.0
-0.5 to VIO +0.5
-0.5 to +4.0
V
V
-0.5 to VCC +0.5
-55 to +125
V
Storage Temperature Range
°C
NOTES:
1. Minimum DC voltage on input or input or I/Os is -0.5V. During voltage transitions, inputs or I/Os pins may overshoot GND to -2.0V for periods of up to 20ns. Maximum DC voltage on input or
I/Os pins is VCC + 0.5V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0V for periods up to 20ns
2. Stresses above those listed under Absolute Maxium Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above
those indicated in the operational sections of the data sheet is not implied. Exposure of the device to absolute maxium rating conditons for extended peroids may affect device reliability
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
Min
3.0
1.7
Max
3.6
Unit
V
Supply Voltage
I/O Voltage
VIO
VCC + 0.2
V
AC TEST CONDITIONS
Parameter
Typ
Unit
V
Input Pulse Levels
VIL = 0, VIH = VIO
1.5
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
NOTES:
ns
V
V
V
IO x 0.5
IO x 0.5
V
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 50 ohm.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
V
.
I
ATE tester includes jig capacitance.
W764M32V1 BGA THERMAL RESISTANCE
Description
Symbol
Theta JB
Theta JC
Typical
7.1
Units
°C/W
°C/W
Notes
Junction to Board
Junction to Case (Top)
1
1
5.7
The JEDEC JESD51 specifications are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input
to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board definition specifications; therefore, Microsemi PMG recommends a customized
evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request.
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 5
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W764M32V1-XBX
DC CHARACTERISTICS
Parameter
Input Load Current
Output Leakage Current
VCC Active Current for Read
VCC Intra-Page Read Current
Symbol
ILI
ILO
ICC1
ICC2
ICC3
ICC4
ICC5
Conditions
VIN = VSS to VCC, VCC = VCC(MAX)
VOUT = VSS to VCC, VCC = VCC(MAX)
CS# = VIL, OE# = VIH, VCC = VCC(MAX); address switching at 5MHz
CS# = VIL#, OE# = VIH, VCC = VCC(MAX); f = 33MHz
CS# = VIL#, OE# = VIH, VCC = VCC(MAX)
CS#, RESET#, OE# = VIH, VIH = VIO, VIL = VSS, VCC = VCC MAX
CS# = VIH, RESET# = VIL, VCC = VCC MAX
Min
Max
±2.0
±1.0
120
50
200
400
40
12
400
Unit
μA
μA
mA
mA
mA
μA
mA
mA
ꢀA
mA
V
VCC Active Erase/Program Current (1)
VCC Standby Current
VCC Reset Current (3) (5)
VIH = VIO, VIL = VSS, VCC = VCC MAX, tACC + 30 ns
Automatic Sleep Mode (2) (5)
ICC6
VIH = VIO, VIL = VSS, VCC = VCC max, tASSB
VCC current during power up (5)
ICC7
VIL
VIH
VOL
VOH
VLKO
RESET# = VIO, CS# = VIO, VCC = VCC MAX
160
Input Low Voltage
Input High Voltage
Output Low Voltage (4)
Output High Voltage
Low VCC Lock-Out Voltage (5)
-0.5
0.7 x VIO
0.3 x VIO
VIO + 0.4
0.15 x VIO
V
V
V
V
IOL = 100 μA for DQs, IOL = 2mA for RY/BY#
IOH = 100 μA
0.85 x VIO
2.25
2.5
NOTES:
1.
ICC active while Embedded Algorithm is in progress.
2. Automatic sleep mode enables the lower power mode when addresses remain stable for the specified designated time.
3. If an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation
specification until the embedded operation is stopped by the reset. If no embedded operation is in progress when reset is started,
or following the stopping of an embedded operation, ICC7 will be drawn during the remainder of tRPH. After the end of tRPH the device
will go to standby mode until the next read or write.
4. The recommended pull-up resistor for RY/BY# output is 5k to 10k Ohms.
5. Guaranteed by design, Not tested
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
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W764M32V1-XBX
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS – WE# CONTROLLED
-110
-120
Unit
Parameter
Symbol
Min
60
0
Max
Min
60
0
Max
Write Cycle Time
tAVAV
tELWL
tWC
tCS
tWP
tAS
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
sec
ns
ns
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
25
0
25
0
Data Setup Time
tDS
30
0
30
0
Data Hold Time
tDH
tAH
Address Hold Time
45
20
45
20
Write Enable Pulse Width High (3)
Single Word Programming Time (1)
Buffer Programming Time
Sector Erase (2)
tWPH
400
750
1.1
400
750
1.1
tWHWH2
tGHWL
Read Recovery Time before Write (3)
Address Setup Time to OE# low during toggle bit polling
Write Recovery Time from RY/BY# (3)
Program/Erase Valid to RY/BY# (3)
0
15
0
0
15
0
tASO
tRB
tBUSY
80
80
NOTES:
1. Typical value for tWHWH1 is 125 μs.
2. Typical value for tWHWH2 is 0.275 sec.
3. Guaranteed by design, not tested.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
-110
-120
Unit
Parameter
Symbol
Min
Max
Min
Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tRC
tACC
tCE
110
120
ns
ns
ns
ns
ns
ns
ns
Address Access Time
110
110
15
120
120
20
Chip Select Access Time
Page Access Time
tPACC
tOE
Output Enable to Output Valid
Chip Select High to Output High Z
Output Enable High to Output High Z
tGLQV
tEHQZ
tGHQZ
25
25
tDF
15
15
tDF
15
15
Output Hold from Addresses, CS# or OE# Change, Whichever
occurs first
tAXQX
tOH
0
0
ns
Read
Output Enable Hold Time (1)
0
0
ns
ns
tOEH
Toggle and Data# Polling
10
10
1. Guaranteed by design, not tested.
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
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W764M32V1-XBX
FIGURE 3 – AC WAVEFORMS FOR READ OPERATIONS
Back to Back Read (tACC) Operation Timing Diagram
tOH
tOH
tOH
tACC
A25-A0
CS#
tDF
tCE
tDF
tOE
OE#
DQ15-DQ0
Back to Back Read Operation (tRC)Timing Diagram
tRC
tACC
tOH
A25-A0
CS#
tCE
tOE
tOH
tDF
NOTE: Back to Back operations, in
which CS# remains Low between
accesses, requires an address
OE#
DQ15-DQ0
change to initiate the second access.
FIGURE 4 – PAGE READ TIMING
tACC
A25-A4
A3-A0
tCE
CS#
tOE
OE#
tPACC
DQ15-DQ0
NOTE: Word Configuration: Toggle A0, A1, A2, and A3.
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
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W764M32V1-XBX
POWER ON AND RESET PARAMETERS
Parameter
tVCS
Description
Limit
Value
300
300
35
Unit
ꢀs
VCC Setup Time to first access (1, 2)
VIO Setup Time to first access (1, 2)
RESET# Low to CS# Low (1, 2)
RESET# Pulse Width
Min
Min
Min
Min
Min
Min
tVIOS
tRPH
ꢀs
ꢀs
tRP
200
50
ns
tRH
Time between RESET# (High) and CS# (low) (1)
CS# Pulse Width High (1)
ns
tCEH
20
ns
NOTES:
1. Not tested.
2. Timing measured from VCC reaching VCC minimum and VIO reaching VIO minimum to VIH on Reset and VIL on CS#.
3. RESET# Low is optional during POR. If RESET is asserted during POR, the later of tRPH, tVIOS, or tVCS will determine when CS# may go Low. If RESET# remains Low after tVIOS, or tVCS is satisfied, tRPH is
measured from the end of tVIOS, or tVCS. RESET must also be High tRH before CS# goes Low.
4.
5.
V
V
CC ≥ VIO - 200 mV during power-up.
CC and VIO ramp rate can be non-linear.
6. Sum of tRP and tRH must be equal to or greater than tRPH
.
FIGURE 5 – POWER-UP DIAGRAM
tVCS
VCC
tVIOS
VIO
RESET#
tRH
tCEH
CS#
FIGURE 6 – HARDWARE RESET
tRP
RESET#
CS#
tRH
tRPH
tCEH
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November 2015 © 2015 Microsemi Corporation. All rights reserved.
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W764M32V1-XBX
FIGURE 7 – BACK TO BACK WRITE OPERATION TIMING DIAGRAM
tWC
A25-A0
tAS
tAH
tCS
tCH
CS#
OE#
tWP
tWPH
WE#
tDS
tDH
DQ15-DQ0
FIGURE 8 – BACK TO BACK (CS#VIL) WRITE OPERATION TIMING DIAGRAM
tWC
A25-A0
tAS
tAH
tCS
CS#
OE#
tWP
tWPH
WE#
tDS
tDH
DQ15-DQ0
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
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W764M32V1-XBX
FIGURE 9 – WRITE TO READ (tACC) OPERATION TIMING DIAGRAM
tAH
tAS
tSR_W
tACC
tOH
A25-A0
CS#
tOH
tCS
tDF
tOH
tOEH
tOE
tDF
OE#
WE#
tWP
tDH
tDS
DQ15-DQ0
FIGURE 10 – WRITE TO READ (tCE) OPERATION TIMING DIAGRAM
tAH
tSR_W
tACC
tAS
tOH
A25-A0
CS#
tOH
tCS
tCE
tCH
tDF
tOH
tOE
tOEH
tDF
OE#
WE#
tWP
tDH
tDS
DQ15-D0
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W764M32V1-XBX
FIGURE 11 – READ TO WRITE (CS# VIL) OPERATION TIMING DIAGRAM
tAS
tACC
tOH
tAH
A25-A0
CS#
tCE
tCH
tGHWL
tOH
tOE
tDF
OE#
WE#
tWP
tDS
tDH
DQ15-A0
FIGURE 12 – READ TO WRITE (CS# TOGGLE) OPERATION TIMING DIAGRAM
tAS
tACC
tAH
A25-A0
CS#
tOH
tDF
tCE
tCS
tCH
tGHWL
tOH
tDF
tOE
OE#
WE#
tWP
tDH
tDS
DQ15-A0
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W764M32V1-XBX
FIGURE 13 – PROGRAM OPERATIONS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC
tAS
Addresses
555h
PA
PA
PA
tAH
CS#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
A0h
tDH
DOUT
PD
Status
Data
tBUSY
tRB
RY/BY#
NOTE: 1. PA = program address, PD = program data, DOUT is the true data at the program address.
FIGURE 14 – CHIP/SECTOR ERASE OPERATION TIMINGS
Erase Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC
tAS
SA
VA
VA
Addresses
CS#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
55h
30h
Complete
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
NOTE: 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data
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W764M32V1-XBX
FIGURE 15 – DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
tRC
VA
Addresses
CS#
VA
VA
tACC
tCE
tCH
tOE
OE#
WE#
tDF
tOEH
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
True
DQ6–DQ0
Valid Data
Status Data
Status Data
tBUSY
RY/BY#
NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
FIGURE 16 – TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
tAHT
tAS
Addresses
CS#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Valid
Valid
DQ2 and DQ6
RY/BY#
Valid Data
Status
Status
Status
(first read)
(second read)
(stops toggling)
NOTE: 1. DQ6 will toggle at any read address while the device is busy. DQ2 will toggle if the address is within the actively erasing sector.
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W764M32V1-XBX
FIGURE 17 – DQ2 Vs. DQ6
Enter
Embedded
Erasing
Erase
Enter Erase
Erase
Suspend
Suspend Program
Resume
Erase
Erase Suspend
Read
Erase
Erase Suspend
Read
Erase
Erase
WE#
Suspend
Program
Complete
DQ6
DQ2
NOTE: The system may use OE# or CS# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
AC CHARACTERISTICS – ALTERNATE CS# CONTROLLED ERASE AND PROGRAM OPERATIONS
Parameter
JEDEC
Speed Options
Std
tWC
Description
110
120
60
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
sec
tAVAV
tAVWL
tELAX
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
60
0
tAS
Address Setup Time
tAH
Address Hold Time
45
0
45
0
tAHT
tDS
Address Hold Time From CS# or OE# High during toggle bit polling
Data Setup Time
tDVEH
tEHDX
30
0
30
0
tDH
Data Hold Time
tCEPH
t0EPH
tGHEL
TWS
tWH
CS# High during toggle bit polling (1)
OE# High during toggle bit polling (1)
Read Recovery Time Before Write (OE# High to WE# Low) (1)
WE# Setup Time
20
20
0
20
20
0
tGHEL
tWLEL
0
0
tEHWH
WE# Hold Time
0
0
tELEH
tCP
CS# Pulse Width
25
20
180
0.3
25
20
180
0.3
tEHEL
tCPH
tWHWH1
tWHWH2
CS# Pulse Width High
tWHWH1
Buffer Programming Time
Sector Erase Operation
tWHWH2
NOTE: 1. Not tested.
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
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W764M32V1-XBX
FIGURE 18 – BACK TO BACK (CS#) WRITE OPERATION TIMING DIAGRAM
tWC
A25-A0
tAS
tAH
tCP
tCPH
CS#
OE#
tWS
tWH
WE#
tDS
tDH
DQ15-DQ0
FIGURE 19 – (CS#) WRITE TO READ OPERATION TIMING DIAGRAM
tWC
tAS
tACC
A25-A0
CS#
tAH
tCE
tDF
tOEH
tOE
OE#
tWS
tWH
WE#
tDH
tDS
tOH
DQ15-D0
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W764M32V1-XBX
PACKAGE 107 – PBGA (PLASTIC BALL GRID ARRAY)
BOTTOM VIEW
107 X Ø0.60 (0.024)NOM
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
1.00
0.50 (0.020) NOM
(0.039)NOM
8.00 (0.315) NOM
1.85 (0.073) MAX
14.10 (0.555) MAX
• Pads are solder mask defined, pad opening = 0.48mm
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
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W764M32V1-XBX
ORDERING INFORMATION
W 7 64M32 V 1 - XXX B X
MICROSEMI CORPORATION
NOR FLASH
ORGANIZATION, 64M x 32
3.3V POWER SUPPLY
1 = 1G Based Component
ACCESS TIME (ns)
110 = 110ns
120 = 120ns
PACKAGE TYPE
B = 107 PBGA, 14mm x 17mm
TEMPERATURE RATING
M = Military
-55°C to +125°C
I
= Industrial
-40°C to +85°C
0°C to +70°C
C
= Commercial
Blank = No temperature range specified for non-qualified product
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 5
16
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
W764M32V1-XBX
Document Title
64Mx32 NOR Flash Multi-Chip Package 3V Page Mode Memory
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
June 2012
Advanced
Rev 1
Changes (Pgs. 1, 3, 13)
November 2012
Preliminary
1.1 Add two bullets to Features and one bullet to Performance Characteristics
1.2 Delete Operating Junction Temp. lines from Recommended Operating
Conditions
1.3 Change thickness value on package drawing
1.4 Change data sheet from Advanced to Preliminary
Rev 2
Rev 3
Changes (Pg. 1)
October 2013
Final
Final
2.1 Change data sheet from Preliminary to Final
Changes (Pgs. 1, 3, 4, 5, 7, 13, 15, 16)
3.1 Add VIO for 1.8V operations
3.2 Misc. updates and timings
December 2013
Rev 4
Rev 5
Changes (Pgs. 3, 15)
November 2014
November 2015
Final
Final
4.1 Deleted special marking code
Changes (Pgs. 3) (ECN #9688)
5.1 Updated BGA Thermal Resistance table
Microsemi Corporation reserves the right to change products or specifications without notice.
November 2015 © 2015 Microsemi Corporation. All rights reserved.
Rev. 5
17
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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