W78M32VP-100BC_技术文档

W78M32VP-XBX

8Mx32 NOR Flash 3.3V Page Mode Multi-Chip Package

FEATURES

GENERAL DESCRIPTION

 Access Times of 110, 120ns

The W78M32VP-XBX is a 256Mb, 3.3 volt-only Page Mode

memory device.

 Packaging

The device offers fast page access times allowing high speed

microprocessors to operate without wait states. To eliminate bus

contention the device has separate chip enable (CS#), write enable

(WE#) and output enable (OE#) controls.

• 159 PBGA, 13x22mm – 1.27mm pitch

 Page Mode

• Page size is 8 words: Fast page read access from

random locations within the page.

The device offers uniform 64 Kword (128Kb) Sectors:

 Uniform Sector Architecture

• One hundred twenty-eight 64 kword

 Single power supply operation

• 3 volt read, erase, and program operations

 I/O Control

PAGE MODE FEATURES

The page size is 8 words.After initial page access is accomplished,

the page mode operation provides fast read access speed of

random locations within that page.

STANDARD FLASH MEMORY FEATURES

The device requires a 3.3 volt power supply for both read and write

functions. Internally generated and regulated voltages are provided

for the program and erase operations Page Mode Features

• All input levels (address, control, and DQ input levels)

and outputs are determined by voltage on V_IOinput. V_IO

range is 1.65 to V_CC

 Write operation status bits indicate program and erase

operation completion

DEVICE OPERATIONS

 Suspend and Resume commands for program and erase

This section describes the read, program, erase, handshaking,

and reset features of the Flash devices. Operations are initiated by

writing speciﬁc commands or a sequence with speciﬁc address and

data patterns into the command registers ( see Table 38 and Table

39). The command register itself does not occupy andy addressable

memory location; rather, it is composed of latches that store the

commands, along with the address and data information needed

to execute the command. The contents of the register serves as

input to the internal state machine and the state machine outputs

dictate the function of the device. Writing incorrect address and

data values or writing them in an improper sequence may place

the device in an unknown state, in which case the system must

pull the RESET# pin low or power cycle the device to return the

device to the reading array data mode.

operations

 Hardware Reset# input resets device

 WP#/ACC Input

• Accelerates programming time for greater throughput.

• Protects ﬁrst and last sector regardless of sector

protection settings

 Secured Silicon Sector region

• 128-word sector for permanent, secure identiﬁcation

through an 8-word random Electronic Serial Number,

accessible through a command sequence

• May be programmed and locked at the factory or by the

customer

 100,000 erase cycles per sector typical

 20-year data retention typical

DEVICE OPERATION TABLE

The device must be setup appropriately for each operation. Table

2 describes the required state of each control pin for any particular

operation.

* This product is subject to change without notice.

VersatileIO™ (V_IO) CONTROL

The VersatileIO™ (V_IO) control allows the host system to set the

voltage levels that the device generates and tolerates on all inputs

and outputs (address, control, and DQ signals). V_IOrange is 1.65

to V_CC

.

For example, a V_IOof 1.65-3.6 volts allows for I/O at the 1.8 or 3

volt levels, driving and receiving signals to and from other 1.8 or

3 V devices on the same data bus.

Continued on page 3

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FIGURE 1 – PIN CONFIGURATION

FOR W78M32VP-XBX (TOP VIEW)

FIGURE 2 – PIN DESCRIPTION

DQ_0-31

A_0-22

Data Inputs/Outputs

Address Inputs

WE#_1-2

CS#_1-2

OE#

Write Enables

1

2

GND

3

4

5

V_CC

V_IO

6

VIO

NC

7

GND

DNU

NC

8

9 10

Chip Selects

Output Enable

GND

V_CC

A

B

C

D

E

F

RESET#

WP#/ACC

RY/BY#

V_CC

Hardware Reset

Hardware Write Protection/Acceleration

Ready/Busy Output

Power Supply

V_IO

DQ25 WE₂#

NC

V_CC

NC

V_IO

V_CC

DQ17 DQ27 DQ29 DQ31

DQ24 DQ19 DQ21 DQ23

DQ16 DQ26 DQ28 DQ30

NC

V_CC

V_IO

I/O Power Supply

Ground

V_IO

NC

V_IO

GND

DNU

Do Not Use

V_CC

NC

V_CC

GND

V_IO

NC

Not Connected

GND

V_IO

CS₂#

OE#

A2

DQ18 DQ20 DQ22

NC

A0

A22

A11

V_CC

GND

V_CC

GND

DNU*

NC

A12

V_IO

A16

A7

A21

A10

RESET#

A20

A15

A13

A8

G

H

J

WP#/A^CC

A3

A6

A17

NC

A9

GND

A14

DQ9

DQ1

DQ8

DQ0

CS₁#

V_CC

A1

FIGURE 3 – BLOCK DIAGRAM

RY/BY#

A4

A5

A18

WE₁#

DQ6

K

L

NC

DQ4

DQ11

DQ3

DQ10

DQ2

GND

A19

DQ15

DQ7

DQ14

GND

WE1#

CS1#

WE2#

CS2#

NC

M

N

P

R

T

RY/BY#

RESET#

OE#

V_CC

NC

DQ13

DQ5

V_CC

A_0-22

V_IO

NC

V_IO

8M X 16

V_CC

GND

NC

DQ12

GND

V_CC

V_IO

GND

V_IO

WP#/ACC

DQ_0-15

DQ_16-31

*Ball L5 is reserved for A23 on future upgrades

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 The Autoselect command may not be written while the

READ

device is actively programming or erasing.

All memories require access time to output array data. In a read

operation, data is read from one memory location at a time.

Addresses are presented to the device in random order, and the

propagation delay through the device causes the data on its outputs

to arrive with the address on its inputs.

 The system must write the reset command to return to the

read mode (or erase-suspend-read mode if the sector was

previously in Erase Suspend).

 It is recommended that A9 apply V_IDafter power-up

sequence is completed. In addition, it is recommended that

A9 apply from V_IDto V_IH/V_ILbefore power-down the V_CC/V_IO.

The device defaults to reading array data after device power-up or

hardware reset. To read data from the memory array, the system

must ﬁrst assert a valid address onA22-A0, while driving OE# and

CE# to VIL. WE# must remain at V_IH. All addresses are latched

on the falling edge of CE#. Data will appear on DQ15-DQ0 after

address access time (t_ACC), which is equal to the delay from stable

addresses to valid output data.

 See Table 39 for command sequence details.

 When verifying sector protection, the sector address

must appear on the appropriate highest order address

bits (see Table 5 to Table 6). The remaining address bits

are don't care. When all necessary bits have been set

as required, the programming equipment may then read

the corresponding identiﬁer code on DQ15-DQ0. The

Autoselect codes can also be accessed in-system through

the command register.

The OE# signal must be driven to V_IL. Data is output on DQ15-DQ0

pins after the access time (t_OE) has

elapsed from the falling edge of OE#, assuming the t_ACCaccess

time has been meet.

PROGRAM/ERASE OPERATIONS

PAGE READ MODE

These devices are capable of several modes of programming and

or erase operations which are described in detail in the following

sections.

The device is capable of fast page mode read and is compatible

with the page mode Mask ROM read operation. This mode provides

faster read access speed for random locations within a page. The

page size of the device is 8 words. The appropriate page is selected

by the higher address bits A(22)-A3.

During a write operation, the system must drive CE# and WE# to

V_ILand OE# to V_IHwhen providing address, command, and data.

Addresses are latched on the last falling edge of WE# or CE#, while

data is latched on the 1st rising edge of WE# or CE#.

Address bits A2-A0 in word mode determine the speciﬁc word

within a page. The microprocessor supplies the speciﬁc word

location. The random or initial page access is equal to t_ACCor t_CE

and subsequent page read accesses (as long as the locations

speciﬁed by the microprocessor falls within that page) is equivalent

to t_PACC. When CE# is deasserted and reasserted for a subsequent

access, the access time is t_ACCor t_CE. Fast page mode accesses

are obtained by keeping the “read-page addresses” constant and

changing the “intra-read page” addresses.

The Unlock Bypass feature allows the host system to send program

commands to the Flash device without ﬁrst writing unlock cycles

within the command sequence. See Unlock Bypass section for

details on the Unlock Bypass function.

Note the following:

 When the Embedded Program algorithm is complete, the

device returns to the read mode.

AUTOSELECT

 The system can determine the status of the program

operation by reading the DQ status bits. Refer to the Write

Operation Status for information on these status bits.

The Autoselect mode provides manufacturer ID, Device

identiﬁcation, and sector protection information, through identiﬁer

codes output from the internal register (separate from the

memory array) on DQ7-DQ0. This mode is primarily intended for

programming equipment to automatically match a device to be

programmed with its corresponding programming algorithm (see

Table 4). The Autoselect codes can also be accessed in-system.

 An “0” cannot be programmed back to a “1.” A succeeding

read shows that the data is still “0.”

 Only erase operations can convert a “0” to a “1.”

 Any commands written to the device during the Embedded

Program/Erase are ignored except the Suspend

commands.

There are two methods to access autoselect codes. One uses

the autoselect command, the other applies V_IDon address pin A9.

 Secured Silicon Sector, Autoselect, and CFI functions are

When using programming equipment, the autoselect mode requires

V_ID(11.5 V to 12.5 V) on address pin A9. Address pins must be

as shown in Table 3.

unavailable when a program operation is in progress.

 A hardware reset and/or power removal immediately

terminates the Program/Erase operation and the

 To access Autoselect mode without using high voltage on

 Program/Erase command sequence should be reinitiated

once the device has returned to the read mode to ensure

data integrity.

A9, the host system must issue the Autoselect command.

 The Autoselect command sequence may be written to an

address within a sector that is either in the read or erase-

suspend-read mode.

 Programming is allowed in any sequence and across sector

boundaries for single word programming operation. See

Write Buffer Programming when using the write buffer.

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 Programming to the same word address multiple times

The “write-buffer-page” addresses must be the same for all

address/data pairs loaded into the write buffer. (This means Write

Buffer Programming cannot be performed across multiple “write-

buffer-pages.” This also means that Write Buffer Programming

cannot be performed across multiple sectors. If the system attempts

to load programming data outside of the selected “write-buffer-

page”, the operation ABORTs.)

without intervening erases is permitted.

SINGLE WORD PROGRAMMING

Single word programming mode is one method of programming the

Flash. In this mode, four Flash command write cycles are used to

program an individual Flash address. The data for this programming

operation could be 8 or 16-bits wide.

After writing the StartingAddress/Data pair, the system then writes

the remaining address/data pairs into the write buffer.

While the single word programming method is supported by most

Spansion devices, in general Single Word Programming is not

recommended for devices that support Write Buffer Programming.

See Table 39 for the required bus cycles and Figure 4 for the

ﬂowchart. When the Embedded Program algorithm is complete,

the device then returns to the read mode and addresses are no

longer latched. The system can determine the status of the program

operation by reading the DQ status bits. Refer to Write Operation

Status for information on these status bits.

Note that if a Write Buffer address location is loaded multiple

times, the “address/data pair” counter is decremented for every

data load operation. Also, the last data loaded at a location before

the “Program Buffer to Flash” confirm command is the data

programmed into the device. It is the software's responsibility to

comprehend ramiﬁcations of loading a write-buffer location more

than once. The counter decrements for each data load operation,

NOT for each unique write-buffer-address location. Once the

speciﬁed number of write buffer locations have been loaded, the

system must then write the “Program Buffer to Flash” command

at the Sector Address. Any other address/data write combinations

abort the Write Buffer Programming operation. The Write Operation

Status bits should be used while monitoring the last address

location loaded into the write buffer. This eliminates the need to

store an address in memory because the system can load the

last address location, issue the program conﬁrm command at the

last loaded address location, and then check the write operation

status at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1

should be monitored to determine the device status during Write

Buffer Programming.

 During programming, any command (except the Suspend

Program command) is ignored.

 The Secured Silicon Sector, Autoselect, and CFI functions

are unavailable when a program operation is inprogress.

 A hardware reset immediately terminates the program

operation. The program command sequence should

 be reinitiated once the device has returned to the read

mode, to ensure data integrity.

 Programming to the same address multiple times

continuously (for example, “walking” a bit within a word) is

permitted.

The write-buffer “embedded” programming operation can be

suspended using the standard suspend/resume commands. Upon

successful completion of the Write Buffer Programming operation,

the device returns to READ mode. The Write Buffer Programming

Sequence is ABORTED under any of the following conditions:

WRITE BUFFER PROGRAMMING

Write Buffer Programming allows the system to write a maximum

of 32 words in one programming operation. This results in a

faster effective word programming time than the standard “word”

programming algorithms.

 Load a value that is greater than the page buffer size during

the “Number of Locations to Program” step.

The Write Buffer Programming command sequence is initiated by

ﬁrst writing two unlock cycles. This is followed by a third write cycle

containing the Write Buffer Load command written at the Sector

Address in which programming occurs. At this point, the system

writes the number of “word locations minus 1” that are loaded

into the page buffer at the Sector Address in which programming

occurs. This tells the device how many write buffer addresses are

loaded with data and therefore when to expect the “Program Buffer

to Flash” conﬁrm command. The number of locations to program

cannot exceed the size of the write buffer or the operation aborts.

(Number loaded = the number of locations to program minus 1.

For example, if the system programs 6 address locations, then

05h should be written to the device.)

 Write to an address in a sector different than the one

speciﬁed during the Write-Buffer-Load command.

 Write an Address/Data pair to a different write-buffer-page

than the one selected by the “Starting Address” during the

“write buffer data loading” stage of the operation.

 Writing anything other than the Program to Buffer Flash

Command after the speciﬁed number of “data load” cycles.

 The ABORT condition is indicated by DQ1 = 1, DQ7 =

DATA# (for the “last address location loaded”), DQ6 =

TOGGLE, DQ5 = 0. This indicates that the Write Buffer

Programming Operation was ABORTED. A “Write-to- Buffer-

Abort reset” command sequence is required when using the

write buffer Programming features in Unlock Bypass mode.

Note that the Secured Silicon sector, autoselect, and CFI

functions are unavailable when a program operation is in

progress.

The system then writes the starting address/data combination. This

starting address is the ﬁrst address/data pair to be programmed,

and selects the “write-buffer-page” address. All subsequent

address/data pairs must fall within the elected-write-buffer-page.

The “write-buffer-page” is selected by using the addresses

AMAX–A5.

Write buffer programming is allowed in any sequence of memory

(or address) locations. These ﬂash devices are capable of handling

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multiple write buffer programming operations on the same write

buffer address range without intervening erases.

Deﬁnitions shows the address and data requirements for the chip

erase command sequence.

Use of the write buffer is strongly recommended for programming

when multiple words are to be programmed.

When the Embedded Erase algorithm is complete, that sector

returns to the read mode and addresses are no longer latched.

The system can determine the status of the erase operation by

using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for

information on these status bits.

SECTOR ERASE

The sector erase function erases one or more sectors in the

memory array. (See Table 39 and Figure 6.) The device does not

require the system to preprogram a sector prior to erase. The

Embedded Erase algorithm automatically programs and veriﬁes the

entire memory to an all zero data pattern prior to electrical erase.

After a successful sector erase, all locations within the erased

sector contain FFFFh. The system is not required to provide any

controls or timings during these operations.

The Unlock Bypass feature allows the host system to send program

commands to the Flash device without ﬁrst writing unlock cycles

within the command sequence. See Unlock Bypass Section for

details on the Unlock Bypass function.

Any commands written during the chip erase operation are ignored.

However, note that a hardware reset immediately terminates the

erase operation. If that occurs, the chip erase command sequence

should be reinitiated once that sector has returned to reading array

data, to ensure the entire array is properly erased.

After the command sequence is written, a sector erase time-out

of no less than tSEA occurs. During the timeout period, additional

sector addresses may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sectors may be

from one sector to all sectors. The time between these additional

cycles must be less than 50 μs. Any sector erase address and

command following the exceeded time-out (50μs) may or may

not be accepted. Any command other than Sector Erase or Erase

Suspend during the time-out period resets that sector to the read

mode. The system can monitor DQ3 to determine if the sector erase

timer has timed out. The time-out begins from the rising edge of

the ﬁnal WE# pulse in the command sequence.

ERASE SUSPEND/ERASE RESUME

COMMANDS

The Erase Suspend command allows the system to interrupt a

sector erase operation and then read data from, or program data to,

any sector not selected for erasure. The sector address is required

when writing this command. This command is valid only during the

sector erase operation, including the minimum tSEAtime-out period

during the sector erase command sequence. The Erase Suspend

command is ignored if written during the chip erase operation.

When the Embedded Erase algorithm is complete, the sector

returns to reading array data and addresses are no longer latched.

The system can determine the status of the erase operation by

reading DQ7 or DQ6/DQ2 in the erasing sector. Refer to Section

write operation status section for information on these status bits.

When the Erase Suspend command is written during the sector

erase operation, the device requires a maximum of 20 μs (5 μs

typical) to suspend the erase operation. However, when the Erase

Suspend command is written during the sector erase time-out, the

device immediately terminates the time-out period and suspends

the erase operation.

Once the sector erase operation has begun, only the Erase

Suspend command is valid. All other commands are ignored.

However, note that a hardware reset immediately terminates

the erase operation. If that occurs, the sector erase command

sequence should be reinitiated once that sector has returned to

reading array data, to ensure the sector is properly erased.

After the erase operation has been suspended, the device enters

the erase-suspend-read mode. The system can read data from or

program data to any sector not selected for erasure. (The device

“erase suspends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors produces status

information on DQ7-DQ0. The system can use DQ7, or DQ6,

and DQ2 together, to determine if a sector is actively erasing or

is erase-suspended.

The Unlock Bypass feature allows the host system to send program

commands to the Flash device without ﬁrst writing unlock cycles

within the command sequence. See Unlock Bypass Section for

details on the Unlock Bypass function.

After an erase-suspended program operation is complete, the

device returns to the erase-suspend-read mode. The system can

determine the status of the program operation using write operation

status bits, just as in the standard program operation.

Figure 6 illustrates the algorithm for the erase operation. Refer

to Erase and Programming Performance Section for parameters

and timing diagrams.

In the erase-suspend-read mode, the system can also issue the

Autoselect command sequence. Refer to Write Buffer Programming

Section and the Autoselect Section.

CHIP ERASE COMMAND SEQUENCE

Chip erase is a six-bus cycle operation as indicated by Table

39. These commands invoke the Embedded Erase algorithm,

which does not require the system to preprogram prior to erase.

The Embedded Erase algorithm automatically preprograms and

veriﬁes the entire memory to an all zero data pattern prior to

electrical erase. After a successful chip erase, all locations of

the chip contain FFFFh. The system is not required to provide

any controls or timings during these operations. The Command

To resume the sector erase operation, the system must write the

Erase Resume command. The address of the erase-suspended

sector is required when writing this command. Further writes of the

Resume command are ignored.Another Erase Suspend command

can be written after the chip has resumed erasing.

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 The WP#/ACC pin must not be at V_HHfor operations other

than accelerated programming, or device damage may

result.

PROGRAM SUSPEND/PROGRAM RESUME

COMMANDS

The Program Suspend command allows the system to interrupt

an embedded programming operation or a “Write to Buffer”

programming operation so that data can read from any non-

suspended sector. When the Program Suspend command is written

during a programming process, the device halts the programming

operation within 15 μs maximum (5 μs typical) and updates the

status bits. Addresses are “don't-cares” when writing the Program

Suspend command.

 It is recommended that WP#/ACC apply V_HHafter power-up

sequence is completed. In addition, it is recommended that

WP#/ACC apply from V_HHto V_IH/V_ILbefore powering down

V

_CC/V_IO.

UNLOCK BYPASS

This device features an Unlock Bypass mode to facilitate shorter

programming commands. Once the device enters the Unlock

Bypass mode, only two write cycles are required to program data,

instead of the normal four cycles.

After the programming operation has been suspended, the system

can read array data from any nonsuspended sector. The Program

Suspend command may also be issued during a programming

operation while an erase is suspended. In this case, data may be

read from any addresses not within a sector in Erase Suspend or

Program Suspend. If a read is needed from the Secured Silicon

Sector area, then user must use the proper command sequences

to enter and exit this region.

This mode dispenses with the initial two unlock cycles required

in the standard program command sequence, resulting in faster

total programming time. The Command Deﬁnitions shows the

requirements for the unlock bypass command sequences.

During the unlock bypass mode, only the Read, Program, Write

Buffer Programming, Write-to-Buffer-Abort Reset, and Unlock

Bypass Reset commands are valid. To exit the unlock bypass

mode, the system must issue the two-cycle unlock bypass reset

command sequence. The ﬁrst cycle must contain the sector

address and the data 90h. The second cycle need only contain

the data 00h. The sector then returns to the read mode.

The system may also write the Autoselect Command Sequence

when the device is in Program Suspend

mode. The device allows reading Autoselect codes in the

suspended sectors, since the codes are not stored in the memory

array. When the device exits the Autoselect mode, the device

reverts to Program Suspend mode, and is ready for another valid

operation. See Autoselect Section.

WRITE OPERATION STATUS

The device provides several bits to determine the status of a program

or erase operation. The following subsections describe the function of

DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.

After the Program Resume command is written, the device reverts

to programming. The system can determine the status of the

program operation using the write operation status bits, just as

in the standard program operation. See Write Operation Status

Section for more information.

DQ7: DATA# POLLING

The system must write the Program Resume command (address

bits are “don't care”) to exit the Program Suspend mode and

continue the programming operation. Further writes of the

Program Resume command are ignored. Another Program

Suspend command can be written after the device has resumed

programming.

The Data# Polling bit, DQ7, indicates to the host system whether

an Embedded Program or Erase algorithm is in progress or

completed, or whether the device is in Erase Suspend. Data#

Polling is valid after the rising edge of the ﬁnal WE# pulse in the

command sequence. Note that the Data# Polling is valid only for

the last word being programmed in the write-buffer-page during

Write Buffer Programming. Reading Data# Polling status on any

word other than the last word to be programmed in the write-buffer-

page returns false status information.

ACCELERATED PROGRAM

Accelerated single word programming and write buffer programming

operations are enabled through the WP#/ACC pin. This method is

faster than the standard program command sequences.

During the Embedded Program algorithm, the device outputs on

DQ7 the complement of the datum programmed to DQ7. This

DQ7 status also applies to programming during Erase Suspend.

When the Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system must provide

the program address to read valid status information on DQ7. If a

program address falls within a protected sector, Data# polling on

DQ7 is active, then that sector returns to the read mode.

NOTE

The accelerated program functions must not be used more than 10

times per sector. If the system asserts VHH on this input, the device

automatically enters the aforementioned Unlock Bypass mode and

uses the higher voltage on the input to reduce the time required for

program operations. The system can then use the Write Buffer Load

command sequence provided by the Unlock Bypass mode. Note

that if a “Write-to-Buffer-Abort Reset” is required while in Unlock

Bypass mode, the full 3-cycle RESET command sequence must

be used to reset the device. Removing V_HHfrom the ACC input,

upon completion of the embedded program operation, returns the

device to normal operation.

During the Embedded EraseAlgorithm, Data# polling produces a “0”

on DQ7. When the Embedded Erase algorithm is complete, or if the

device enters the Erase Suspend mode, Data# Polling produces a

“1” on DQ7. The system must provide an address within any of the

sectors selected for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected

 Sectors must be unlocked prior to raising WP#/ACC to V_HH

.

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for erasing are protected, Data# Polling on DQ7 is active for

approximately 100 μs, then the device returns to the read mode.

If not all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at

an address within a protected sector, the status may not be valid.

algorithm is in progress), or whether that sector is erase-suspended.

Toggle Bit II is valid after the rising edge of the ﬁnal WE# pulse in

the command sequence. DQ2 toggles when the system reads at

addresses within those sectors that have been selected for erasure.

But DQ2 cannot distinguish whether the sector is actively erasing

or is erase-suspended. DQ6, by comparison, indicates whether

the device is actively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure. Thus, both

status bits are required for sector and mode information. Refer to

Table 18 to compare outputs for DQ2 and DQ6.

Just prior to the completion of an Embedded Program or Erase

operation, DQ7 may change asynchronously with DQ6-DQ0 while

Output Enable (OE#) is asserted low. That is, the device may

change from providing status information to valid data on DQ7.

Depending on when the system samples the DQ7 output, it may

read the status or valid data. Even if the device has completed

the program or erase operation and DQ7 has valid data, the data

outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00

appears on successive read cycles.

READING TOGGLE BITS DQ6/DQ2

Whenever the system initially begins reading toggle bit status, it

must read DQ7–DQ0 at least twice in a row to determine whether

a toggle bit is toggling. Typically, the system would note and store

the value of the toggle bit after the ﬁrst read.After the second read,

the system would compare the new value of the toggle bit with the

ﬁrst. If the toggle bit is not toggling, the device has completed the

program or erases operation. The system can read array data on

DQ7–DQ0 on the following read cycle. However, if after the initial

two read cycles, the system determines that the toggle bit is still

toggling, the system also should note whether the value of DQ5 is

high (see DQ5: Exceeded Timing Limits). If it is, the system should

then determine again whether the toggle bit is toggling, since the

toggle bit may have stopped toggling just as DQ5 went high. If

the toggle bit is no longer toggling, the device has successfully

completed the program or erases operation. If it is still toggling, the

device did not complete the operation successfully, and the system

must write the reset command to return to reading array data. The

remaining scenario is that the system initially determines that the

toggle bit is toggling and DQ5 has not gone high. The system may

continue to monitor the toggle bit and DQ5 through successive

read cycles, determining the status as described in the previous

paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the operation.

Refer to Figure 7 for more details.

See the following for more information: Table 18, shows the outputs

for Data# Polling on DQ7. Figure 7, shows the Data# Polling

algorithm; and Figure 22, shows the Data# Polling timing diagram.

DQ6: TOGGLE BIT I

Toggle Bit I on DQ6 indicates whether an Embedded Program or

Erase algorithm is in progress or complete, or whether the device

has entered the Erase Suspend mode. Toggle Bit I may be read

at any address, and is valid after the rising edge of the ﬁnal WE#

pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation,

successive read cycles to any address that is being programmed

or erased causes DQ6 to toggle. When the operation is complete,

DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected

for erasing are protected, DQ6 toggles for approximately 100μs,

then returns to reading array data. If not all selected sectors are

protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether

a sector is actively erasing or is erasesuspended. When the

device is actively erasing (that is, the Embedded Erase algorithm

is in progress), DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-

suspended. Alternatively, the system can use DQ7 (see DQ7:

Data# Polling).

NOTE

When verifying the status of a write operation (embedded program/

erase) of a memory sector, DQ6 and DQ2 toggle between high and

low states in a series of consecutive and contiguous status read

cycles. In order for this toggling behavior to be properly observed,

the consecutive status bit reads must not be interleaved with read

accesses to other memory sectors. If it is not possible to temporarily

prevent reads to other memory sectors, then it is recommended

to use the DQ7 status bit as the alternative method of determining

the active or inactive status of the write operation.

If a program address falls within a protected sector, DQ6 toggles

for approximately 1μs after the program command sequence is

written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and

stops toggling once the Embedded ProgramAlgorithm is complete.

DQ5: EXCEEDED TIMING LIMITS

DQ5 indicates whether the program or erase time has exceeded

a speciﬁed internal pulse count limit. Under these conditions DQ5

produces a “1,” indicating that the program or erase cycle was not

successfully completed. The device does not output a 1 on DQ5

if the system tries to program a 1 to a location that was previously

programmed to 0. Only an erase operation can change a 0 back

to a 1. Under this condition, the device ignores the bit that was

Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted

and reasserted to show the change in state.

DQ2: TOGGLE BIT II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether

a particular sector is actively erasing (that is, the Embedded Erase

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incorrectly instructed to be programmed from a 0 to a 1, while any

other bits that were correctly requested to be changed from 1 to

0 are programmed. Attempting to program a 0 to a 1 is masked

during the programming operation. Under valid DQ5 conditions, the

system must write the reset command to return to the read mode

(or to the erase-suspend-read mode if a sector was previously in

the erase-suspend-program mode).

RY/BY#

The RY/BY# is a dedicated, open-drain output pin that indicates

whether an Embedded Algorithm is in progress or complete. The

RY/BY# status is valid after the rising edge of the ﬁnal WE# pulse

in the command sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied together in parallel with a pull-

up resistor to V_CC. This feature allows the host system to detect

when data is ready to be read by simply monitoring the RY/BY#

pin, which is a dedicated output and controlled by CE# (not OE#).

DQ3: SECTOR ERASE TIMEOUT STATE

INDICATOR

After writing a sector erase command sequence, the system may

read DQ3 to determine whether or not erasure has begun. (The

sector erase timer does not apply to the chip erase command.)

If additional sectors are selected for erasure, the entire time-out

also applies after each additional sector erase command. When

the time-out period is complete, DQ3 switches from a “0” to a “1.”

If the time between additional sector erase commands from the

system can be assumed to be less than tSEA, then the system

need not monitor DQ3. See Sector Erase for more details.

HARDWARE RESET

The RESET# input provides a hardware method of resetting the

device to reading array data. When RESET# is driven low for at

least a period of t_RP(RESET# Pulse Width), the device immediately

terminates any operation in progress, tristates all outputs, resets

the conﬁguration register, and ignores all read/write commands

for the duration of the RESET# pulse. The device also resets the

internal state machine to reading array data.

To ensure data integrity Program/Erase operations that were

interrupted should be reinitiated once the device is ready to accept

another command sequence.

After the sector erase command is written, the system should

read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to

ensure that the device has accepted the command sequence,

and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm

has begun; all further commands (except Erase Suspend) are

ignored until the erase operation is complete. If DQ3 is “0,” the

device accepts additional sector erase commands. To ensure the

command has been accepted, the system software should check

the status of DQ3 prior to and following each sub-sequent sector

erase command. If DQ3 is high on the second status check, the

last command might not have been accepted. Table 18 shows the

status of DQ3 relative to the other status bits.

When RESET# is held at V_SS, the device draws V_CCreset current

(I_CC5). If RESET# is held at V_IL, but not at V_SS, the standby current

is greater. RESET# may be tied to the system reset circuitry which

enables the system to read the boot-up ﬁrmware from the Flash

memory upon a system reset.

SOFTWARE RESET

Software reset is part of the command set (see Table 12.1 on page

69) that also returns the device to arrayread mode and must be

used for the following conditions:

DQ1: WRITE TO BUFFER ABORT

1. to exit Autoselect mode

DQ1 indicates whether a Write to Buffer operation was aborted.

Under these conditions DQ1 produces a “1”. The system must issue

the “Write to BufferAbort Reset” command sequence to return the

device to reading array data. See Write Buffer Programming for

more details.

2. when DQ5 goes high during write status operation that indicates

program or erase cycle was not successfully completed

3. exit sector lock/unlock operation.

4. to return to erase-suspend-read mode if the device was

previously in Erase Suspend mode.

WRITING COMMANDS/COMMAND

SEQUENCES

5. after any aborted operations

The following are additional points to consider when using the

reset command:

During a write operation, the system must drive CE# and WE# to

V_ILand OE# to V_IHwhen providing an address, command, and

data. Addresses are latched on the last falling edge of WE# or

CE#, while data is latched on the 1st rising edge of WE# or CE#.

An erase operation can erase one sector, multiple sectors, or

the entire device. Table 1 indicate the address space that each

sector occupies. The device address space is divided into uniform

64KW/128KB sectors. A sector address is the set of address bits

required to uniquely select a sector. I_CC2 in “DC Characteristics”

represents the active current speciﬁcation for the write mode. “AC

Characteristics” contains timing speciﬁcation tables and timing

diagrams for write operations.

 This command resets the sectors to the read and address

bits are ignored.

 Reset commands are ignored during program and erase

operations.

 The reset command may be written between the cycles in a

program command sequence before programming begins

(prior to the third cycle). This resets the sector to which the

system was writing to the read mode.

 If the program command sequence is written to a sector

that is in the Erase Suspend mode, writing the reset

command returns that sector to the erase-suspend-read

mode.

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 The reset command may be written during an Autoselect

2. Dynamically locked. The selected sectors are protected and

can be altered via software commands.

command sequence.

 If a sector has entered the Autoselect mode while in the

Erase Suspend mode, writing the reset command returns

that sector to the erase-suspend-read mode.

3. Unlocked. The sectors are unprotected and can be erased

and/or programmed.

PERSISTENT PROTECTION BITS

 If DQ1 goes high during a Write Buffer Programming

operation, the system must write the “Write to Buffer abort

Reset” command sequence to RESET the device to reading

array data. The standard RESET command does not work

during this condition.

The Persistent Protection Bits are unique and nonvolatile for each

sector and have the same endurances as the Flash memory.

Preprogramming and veriﬁcation prior to erasure are handled by

the device, and therefore do not require system monitoring.

 To exit the unlock bypass mode, the system must issue a

two-cycle unlock bypass reset command sequence [see

Command Deﬁnitions for details].

NOTES

1. Each PPB is individually programmed and all are erased in

parallel.

2. While programming PPB for a sector, array data can be read

from any other sector, except Sector 0 (used for Data# Polling)

and the sector in which sector PPB is being programmed.

ADVANCED SECTOR PROTECTION/

UNPROTECTION

The Advanced Sector Protection/Unprotection feature disables or

enables programming or erase operations in any or all sectors and

can be implemented through software and/or hardware methods,

which are independent of each other. This section describes the

various methods of protecting data stored in the memory array. An

overview of these methods in shown in Figure 8.

3. Entry command disables reads and writes for the sector

selected.

4. Reads within that sector return the PPB status for that sector.

5. All Reads must be performed using the read mode.

6. The speciﬁc sector address (A22-A16) are written at the same

time as the program command.

LOCK REGISTER

7. If the PPB Lock Bit is set, the PPB Program or erase command

does not execute and times-out without programming or

erasing the PPB.

As shipped from the factory, all devices default to the persistent

mode when power is applied, and all sectors are unprotected. The

device programmer or host system must then choose which sector

protection method to use. Programming (setting to “0”) any one of

the following two one-time programmable, non-volatile bits locks

the part permanently in that mode:

8. There are no means for individually erasing a speciﬁc PPB

and no speciﬁc sector address is required for this operation.

9. Exit command must be issued after the execution which resets

the device to read mode and reenables reads and writes for

Sector 0.

 Lock Register Persistent Protection Mode Lock Bit (DQ1)

 Lock Register Password Protection Mode Lock Bit (DQ2)

10. The programming state of the PPB for a given sector can be

veriﬁed by writing a PPB Status Read Command to the device

as described by the ﬂow chart shown in Figure 9.

NOTES

1. If the password mode is chosen, the password must be

programmed before setting the corresponding lock register bit.

DYNAMIC PROTECTION BITS

2. After the Lock Register Bits Command Set Entry command

sequence is written, reads and writes for Sector 0 are disabled,

while reads from other sectors are allowed until exiting this

mode.

Dynamic Protection Bits are volatile and unique for each sector

and can be individually modiﬁed. DYBs only control the protection

scheme for unprotected sectors that have their PPBs cleared

(erased to “1”). By issuing the DYB Set or Clear command

sequences, the DYBs are set (programmed to “0”) or cleared

(erased to “1”), thus placing each sector in the protected or

unprotected state respectively. This feature allows software to

easily protect sectors against inadvertent changes yet does not

prevent the easy removal of protection when changes are needed.

3. If both lock bits are selected to be programmed (to zeros) at

the same time, the operation aborts.

4. Once the Password Mode Lock Bit is programmed, the

Persistent Mode Lock Bit is permanently disabled, and no

changes to the protection scheme are allowed. Similarly, if the

Persistent Mode Lock Bit is programmed, the Password Mode

is permanently disabled.

NOTES

1. The DYBs can be set (programmed to “0”) or cleared (erased

to “1”) as often as needed. When the parts are ﬁrst shipped,

the PPBs are cleared (erased to “1”) and upon power up or

reset, the DYBs can be set or cleared depending upon the

ordering option chosen.

After selecting a sector protection method, each sector can operate

in any of the following three states:

1. Constantly locked. The selected sectors are protected and

can not be reprogrammed unless PPB lock bit is cleared via a

password, hardware reset, or power cycle.

2. If the option to clear the DYBs after power up is chosen, (erased

to “1”), then the sectors may be modiﬁed depending upon the

PPB state of that sector (see Table 20).

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3. The sectors would be in the protected state If the option to

set the DYBs after power up is chosen (programmed to “0”).

7. The Password Mode Lock Bit is not erasable.

8. The lower two address bits (A1–A0) are valid during the

Password Read, Password Program, and Password Unlock.

4. It is possible to have sectors that are persistently locked with

sectors that are left in the dynamic state.

9. The exact password must be entered in order for the unlocking

function to occur.

5. The DYB Set or Clear commands for the dynamic sectors

signify protected or unprotectedstate of the sectors respectively.

However, if there is a need to change the status of the persistently

locked sectors, a few more steps are required. First, the PPB

Lock Bit must be cleared by either putting the device through a

power-cycle, or hardware reset. The PPBs can then be changed

to reﬂect the desired settings. Setting the PPB Lock Bit once

again locks the PPBs, and the device operates normally again.

10. The Password Unlock command cannot be issued any faster

than 1 μs at a time to prevent a hacker from running through

all the 64-bit combinations in an attempt to correctly match a

password.

11. Approximately 1 μs is required for unlocking the device after

the valid 64-bit password is given to the device.

12. Password veriﬁcation is only allowed during the password

6. To achieve the best protection, it is recommended to execute

the PPB Lock Bit Set command early in the boot code and

protect the boot code by holding WP#/ACC = V_IL. Note that the

PPB and DYB bits have the same function when WP#/ACC =

programming operation.

13. All further commands to the password region are disabled and

all operations are ignored.

V

_HHas they do when ACC =V_IH.

14. If the password is lost after setting the Password Mode Lock

Bit, there is no way to clear the PPB Lock Bit.

PERSISTENT PROTECTION BIT LOCK BIT

15. Entry command sequence must be issued prior to any of any

operation and it disables reads and writes for Sector 0. Reads

and writes for other sectors excluding Sector 0 are allowed.

The Persistent Protection Bit Lock Bit is a global volatile bit for all

sectors. When set (programmed to “0”), it locks all PPBs and when

cleared (programmed to “1”), allows the PPBs to be changed. There

is only one PPB Lock Bit per device.

16. If the user attempts to program or erase a protected sector,

the device ignores the command and returns to read mode.

NOTES

17. A program or erase command to a protected sector enables

status polling and returns to read mode without having modiﬁed

the contents of the protected sector.

1. No software command sequence unlocks this bit unless the

device is in the password protection mode; only a hardware

reset or a power-up clears this bit.

18. The programming of the DYB, PPB, and PPB Lock for a

given sector can be veriﬁed by writing individual status read

commands DYB Status, PPB Status, and PPB Lock Status

to the device.

2. The PPB Lock Bit must be set (programmed to “0”) only after all

PPBs are conFigured to the desired settings.

PASSWORD PROTECTION METHOD

The Password Protection Method allows an even higher level of

security than the Persistent Sector Protection Mode by requiring a

64-bit password for unlocking the device PPB Lock Bit. In addition

to this password requirement, after power up and reset, the PPB

Lock Bit is set “0” to maintain the password mode of operation.

Successful execution of the Password Unlock command by

entering the entire password clears the PPB Lock Bit, allowing for

sector PPBs modiﬁcations.

HARDWARE DATA PROTECTION METHODS

The device offers two main types of data protection at the sector

level via hardware control:

 When WP#/ACC is at V_IL, the either the highest or lowest

sector is locked (device speciﬁc).

There are additional methods by which intended or accidental

erasure of any sectors can be prevented via hardware means.

The following subsections describes these methods:

NOTES

1. There is no special addressing order required for programming

the password. Once the Password is written and veriﬁed, the

Password Mode Locking Bit must be set in order to prevent

access.

WP#/ACC METHOD

The Write Protect feature provides a hardware method of protecting

one outermost sector. This function is provided by the WP#/ACC

pin and overrides the previously discussed Sector Protection/

Unprotection method.

2. The Password Program Command is only capable of

programming “0”s. Programming a “1” after a cell is

programmed as a “0” results in a time-out with the cell as a “0”.

If the system asserts V_ILon the WP#/ACC pin, the device disables

program and erase functions in the highest or lowest sector

independently of whether the sector was protected or unprotected

using the method described in Advanced Sector Protection/

Unprotection.

3. The password is all “1”s when shipped from the factory.

4. All 64-bit password combinations are valid as a password.

5. There is no means to verify what the password is after it is set.

6. The Password Mode Lock Bit, once set, prevents reading

the 64-bit password on the data bus and further password

programming.

If the system asserts V_IHon the WP#/ACC pin, the device

reverts to whether the boot sectors were last set to be protected

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or unprotected. That is, sector protection or unprotection for

these sectors depends on whether they were last protected or

unprotected.

The RESET# input provides a hardware method of resetting the

device to reading array data. When RESET# is driven low for

at least a period of t_RP, the device immediately terminates any

operation in progress, tristates all outputs, and ignores all read/

write commands for the duration of the RESET# pulse. The device

also resets the internal state machine to reading array data. The

operation that was interrupted should be reinitiated once the

device is ready to accept another command sequence to ensure

data integrity.

The WP#/ACC pin must be held stable during a command sequence

execution. WP# has an internal pull-up; when unconnected, WP#

is set at V_IH.

NOTE

If WP#/ACC is at V_ILwhen the device is in the standby mode, the

maximum input load current is increased.

When RESET# is held at V_SS± 0.3 V, the device draws I_CCreset

current (I_CC5). If RESET# is held at V_ILbut not within V_SS± 0.3 V,

the standby current is greater.

LOW V_CCWRITE INHIBIT

When V_CCis less than V_LKO, the device does not accept any write

cycles. This protects data during V_CCpower-up and power-down.

The command register and all internal program/erase circuits are

disabled, and the device resets to reading array data. Subsequent

writes are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control inputs to prevent

RESET# may be tied to the system reset circuitry and thus, a

system reset would also reset the Flash memory, enabling the

system to read the boot-up ﬁrmware from the Flash memory.

OUTPUT DISABLE (OE#)

When the OE# input is at V_IH, output from the device is disabled.

The outputs are placed in the high impedance state. (With the

exception of RY/BY#.)

unintentional writes when V_CCis greater than V_LKO

.

WRITE PULSE “GLITCH PROTECTION”

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do

not initiate a write cycle.

SECURED SILICON SECTOR FLASH

MEMORY REGION

Secured Silicon Sector Flash Memory Region The Secured Silicon

Sector provides an extra Flash memory region that enables

permanent part identiﬁcation through an Electronic Serial Number

(ESN). The Secured Silicon Sector is 128 words in length and all

Secured Silicon reads outside of the 128-word address range

returns invalid data. The Secured Silicon Sector Indicator Bit, DQ7,

(at Autoselect address 03h) is used to indicate whether or not the

Secured Silicon Sector is locked when shipped from the factory.

POWER-UP WRITE INHIBIT

If WE# = CE# = RESET# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising edge of WE#.

The internal state machine is automatically reset to the read mode

on power-up.

POWER CONSERVATION MODES

STANDBY MODE

Please note the following general conditions:

 On power-up, or following a hardware reset, the device

When the system is not reading or writing to the device, it can

place the device in the standby mode. In this mode, current

consumption is greatly reduced, and the outputs are placed in the

high impedance state, independent of the OE# input. The device

enters the CMOS standby mode when the CE# and RESET# inputs

are both held at V_CC± 0.3 V. The device requires standard access

time (t_CE) for read access, before it is ready to read data. If the

device is deselected during erasure or programming, the device

draws active current until the operation is completed. I_CC4 in “DC

Characteristics” represents the standby current speciﬁcation

reverts to sending commands to the normal address space.

 Reads outside of sector SA0 return memory array data.

 Sector SA0 is remapped from memory array to Secured

Silicon Sector array.

 Once the Secured Silicon Sector Entry Command is issued,

the Secured Silicon Sector Exit command must be issued to

exit Secured Silicon Sector Mode.

 The Secured Silicon Sector is not accessible when the

device is executing an Embedded Program or Embedded

Erase algorithm.

AUTOMATIC SLEEP MODE

 The ACC function and unlock bypass modes are not

The automatic sleep mode minimizes Flash device energy

consumption. The device automatically enables this mode

when addresses remain stable for t_ACC+ 30 ns. The automatic

sleep mode is independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new data when

addresses are changed. While in sleep mode, output data is latched

and always available to the system. _ICC6 represents the automatic

sleep mode current speciﬁcation.

available when the Secured Silicon Sector is enabled.

FACTORY LOCKED SECURED SILICON

SECTOR

The Factory Locked Secured Silicon Sector is always protected

when shipped from the factory and has the Secured Silicon Sector

Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning

of a factory locked part and ensures the security of the ESN and

customer code once the product is shipped to the ﬁeld.

HARDWARE RESET# INPUT OPERATION

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These devices are available pre-programmed with one of the

following:

SECURED SILICON SECTOR ENTRY/EXIT

COMMAND SEQUENCES

The system can access the Secured Silicon Sector region by

issuing the three-cycle Enter Secured Silicon Sector command

sequence. The device continues to access the Secured Silicon

Sector region until the system issues the four-cycle Exit Secured

Silicon Sector command sequence.

 A random, 8 Word secure ESN only within the Secured

Silicon Sector (at addresses 000000H - 000007H)

 Both a random, secure ESN and customer code through the

Spansion programming service.

Customers may opt to have their code programmed through

the Spansion programming services. Spansion programs the

customer's code, with or without the random ESN. The devices are

then shipped from the Spansion factory with the Secured Silicon

Sector permanently locked. Contact your local representative for

details on using Spansion programming services.

See Command Deﬁnitions [Secured Silicon Sector Command

Table, Appendix

Table 39 for address and data requirements for both command

sequences.

The Secured Silicon Sector Entry Command allows the following

commands to be executed

CUSTOMER LOCKABLE SECURED SILICON

SECTOR

The Customer Lockable Secured Silicon Sector is always shipped

unprotected (DQ7 set to “0”), allowing customers to utilize that

sector in any manner they choose. If the security feature is not

required, the Secured Silicon Sector can be treated as an additional

Flash memory space.

 Read customer and factory Secured Silicon areas

 Program the customer Secured Silicon Sector

After the system has written the Enter Secured Silicon Sector

command sequence, it may read the Secured Silicon Sector by

using the addresses normally occupied by sector SA0 within the

memory array. This mode of operation continues until the system

issues the Exit Secured Silicon Sector command sequence, or

until power is removed from the device.

Please note the following:

 Once the Secured Silicon Sector area is protected, the

Secured Silicon Sector Indicator Bit is permanently set to

“0.”

 The Secured Silicon Sector can be read any number of

times, but can be programmed and locked only once. The

Secured Silicon Sector lock must be used with caution as

once locked, there is no procedure available for unlocking

the Secured Silicon Sector area and none of the bits in the

Secured Silicon Sector memory space can be modiﬁed in

any way.

 The accelerated programming (ACC) and unlock bypass

functions are not available when the Secured Silicon Sector

is enabled.

 Once the Secured Silicon Sector is locked and veriﬁed, the

system must write the Exit Secured Silicon Sector Region

command sequence which return the device to the memory

array at sector 0.

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TABLE 1 – SECTOR & MEMORY ADDRESS MAP

Uniform Sector Size

Sector Count

Sector Range

Address Range (16-bit)

Notes

SA00

:

0000000h - 000FFFFh

Sector Starting Address

Sector Count

128

SA127

07F0000 - 7FFFFF

Sector Ending Address

TABLE 2 – DEVICE OPERATIONS

Addresses

(Note 1)

Operation

CE#

OE#

WE#

RESET#

WP3/ACC

DQ0 - DQ7

DQ8 - DQ15

Read

Write (Program/Erase)

Accelerated Program

Standby

L

H

X

H

X

H

L

H

X

A_IN

X

D_OUT

(Note 3)

High-Z

D_OUT

(Note 3)

High-Z

L

H

(Note 2)

L

H

V_HH

H

V_CC± 0.3V

X

H

X

V_CC± 0.3V

Output Disable

Reset

L

H

L

X

Legend

L = Logic Low = V_IL, H = Logic High = V_IH, V_HH= 11.5–12.5V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes

1. Addresses are AMax:A0 in word mode.

2. If WP# = V_IL, on the outermost sector remians protected. If WP# = V_IH, the outermost secotr is unprotected. WP# has an internal pull-up; when uconnected, WP# is a V_IH. All sectors are unprotected wen

shipped from the factory ( The Secured Silicon Sector can be factory protected depending on version ordered.)

3.

D_INor D_OUTas required by command sequence, data polling, or sector protect algorithm.

TABLE 3 – AUTOSELECT CODES, (HIGH VOLTAGE METHOD)

Amax to A14 to

DQ8 to

DQ15

Description

Cycle 1

CE#

OE#

WE#

A9

A8 to A7 A5 to A4 A3 to A2

A1

A0

DQ7 to DQ0

A16

A10

L

H

L

22

7Eh

21h

01h

Cycle 2

Cycle 3

L

H

X

V_ID

X

L

H

Sector Group Protection

01h (unprotected),

00h (unprotected)

L

H

SA

X

V_ID

X

L

H

L

H

X

Veriﬁcation

Secured Silicon Sector Indicator

Bit (DQ7), WP# protects highest

address sector

99h (factory locked),

19h (not factory

locked)

Secured Silicon Sector Indicator

Bit (DQ7), WP# protects lowest

address sector

89h (factory locked),

09h (not facotry

locked)

X

Legend

L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care. V_ID= 11.5V to 12.5V

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TABLE 4 – AUTOSELECT ADDRESSES IN SYSTEM

Uniform Sector Size

Manufacturer ID

Sector Count

(Base) + 00h

(Base) + 01h

(Base) + 0Eh

(Base) + 0Fh

Read Data (word mode)

xx02h

Device ID, Word 1

Device ID, Word 2

Device ID, Word 3

227Eh

2221h

2201h

XX19h = Note Factory Locked. XX99h = Factory locked

XX09h = Note Factory Locked. XX89h = Factory locked

xx01h = Locked. XX00h = Unlocked

Secure Device Verify

Sector Protect Verify

(Base) + 03h

(SA) + 02h

TABLE 5 – AUTOSELECT ENTRY IN SYSTEM

Cycle

Operation

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

Unlock Cycle 1

Unlock Cycle 2

Autoselect Command

0x00AAh

0x0055h

0x0090h

Write

TABLE 6 – AUTOSELECT EXIT

Cycle

Operation

Word Address

Data

Unlock Cycle 1

Write

Base + XXXh

0x00F0h

Note

1. Any offset within the device works.

2. base = base address.

TABLE 7 – SINGLE WORD PROGRAM

(LLD Function = lld_ProgramCmd)

Cycle

Operation

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Word Adress

Data

00AAh

0055h

00A0h

Data

Unlock Cycle 1

Unlock Cycle 2

Program Setup

Program

Write

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TABLE 8 – WRITE BUFFER PROGRAM

(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)

Cycle

Description

Unlock

Operation

Word Address

Base + 555h

Data

00AAh

1

2

3

4

Unlock

Base + 2AAh

Sector Address

0055h

Write

Write Buffer Load Command

Write Word Count

0025h

Word Count (N-1)h

Number of words (N) loaded into the wrtie buffer can be from 1 to 32 words (1 to 64 bytes).

5 to 36

Last

Load Buffer Word N

Write Buffer to Flash

Program Address, Word N

Sector Address

Word N

0029h

Write

Notes

1. Base = Base Address.

2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.

3. For maximum efﬁciency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.

TABLE 9 – SECTOR ERASE

(LLD Function = lld_SectorEraseCmd)

Cycle

Description

Unlock

Operation

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Base + 2AAh

Sector Address

Data

00AAh

0055h

0080h

00AAh

0055h

0030h

1

2

3

4

5

6

Unlock

Setup Command

Unlock

Write

Unlock

Sector Erase Command

Unlimited additional sectors may be selected for erase; command(s) must be written within 50μs

Notes

1. Base = Base Address.

2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.

3. For maximum efﬁciency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.

TABLE 10 – SECTOR ERASE

(LLD Function = lld_SectorEraseCmd)

Cycle

Description

Unlock

Operation

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Base + 2AAh

Base + 555h

Data

00AAh

0055h

0080h

00AAh

0055h

0010h

1

2

3

4

5

6

Unlock

Setup Command

Unlock

Write

Unlock

Chip Erase Command

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TABLE 11 – ERASE SUSPEND

(LLD Function = lld_EraseSuspendCmd)

Cycle

Operation

Word Address

Base + XXXh

Data

00B0h

1

Write

TABLE 12 – ERASE RESUME

(LLD Function = lld_EraseSuspendCmd)

Cycle

Operation

Word Address

Sector Address

Data

0030h

1

Write

TABLE 13 – PROGRAM SUSPEND

(LLD Function = lld_ProgramSuspendCmd)

Cycle

Operation

Word Address

Data

Base + XXXh

00B0h

1

Write

TABLE 14 – PROGRAM RESUME

(LLD Function = lld_ProgramSuspendCmd)

Cycle

Operation

Word Address

Base + XXXh

Data

0030h

1

Write

TABLE 15 – UNLOCK BYPASS ENTRY

(LLD Function = lld_UnlockBypassEntryCmd)

Cycle

Description

Unlock

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

00AAh

0055h

0020h

1

2

3

Unlock

Entry Command

TABLE 16 – UNLOCK BYPASS PROGRAM

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle

Description

Word Address

Base + xxxh

Data

00AAh

0055h

1

2

Program Setup Command

Program Command

Program Address

TABLE 17 – UNLOCK BYPASS PROGRAM

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle

Description

Reset Cycle 1

Reset Cycle 2

Word Address

Base + xxxh

Data

0090h

0000h

1

2

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TABLE 18 – WRITE OPERATION STATUS

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

DQ1

RY/BY#

Status

Embedded Program Algorithm

Embedded Erase Algorithm

Program-Suspended Sector

Non-Suspend Sector

DQ7#

0

Toggle

0

N/A

1

No toggle

Toggle

0

1

Standard Mode

N/A

Invalid (not allowed)

Data

Program Suspend Mode

Program Suspend Read

Erase-Suspend Read

Erase-Suspended Sector

1

No toggle

Toggle

0

N/A

Toggle

N/A

1

Non-Erase Suspended Sector

Data

Erase Suspend Mode

Erase-Suspend-Program (Embedded Program)

DQ7#

0

N/A

0

Busy (Note 3)

Abort (Note 4)

DQ7#

Toggle

0

N/A

0

1

0

Write-to-Buffer

Notes

1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer toDQ5: Exceeded Timing Limits on page 39 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation

TABLE 19 – SOFTWARE FUNCTIONS RESET

(LLD Function = lld_ResetCmd)

Cycle

Operation

Word Address

Data

Reset Command

Write

Base + xxxh

00F0h

TABLE 20 – LOCK REGISTER

DQ15-3

DQ2

DQ1

DQ0

Don't Care

Password Protection Mode Lock Bit

Persistent Protection Mode Lock Bit

Secured Silicon Sector Protection Bit

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TABLE 21 – SECTOR PROTECTION SCHEMES: DYB, PPB AND PPB LOCK BIT COMBINATIONS

Uniques Device PPB Lock Bit

0 = locked

Sector PPB

0 = locked

1 = unlock

Sector DYB

0 = locked

1 = unlock

Sector Protection Status

1 = unlock

Any Sector

0

1

0

1

0

1

x

1

0

x

0

1

Protected through PPB

Unportected

Any Sector

Protected through PPB

Unportected

Table 21 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the

sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB

Lock Bit can only be unlocked (reset to “1”) through a hardware reset or power cycle. See also Figure 8.1 for

an overview of the Advanced Sector Protection feature.

TABLE 22 – LOCK REGISTER

Secured Silicon Sector Address Range

Customer Lockable

ESN Factory Locked

ESN

ExpressFlash Factory Locked

ESN or determinded by customer

Determinined by customer

000000h-000007h

000008h-000007Fh

Determined by customer

Unavailable

TABLE 23 – SECURED SILICON SECTOR ENTRY

(LLD Function = lld_SecSiSectorEntryCmd)

Cycle

Operation

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

00AAh

0055h

0088h

Unlock Cycle 1

Unlock Cycle 2

Entry Cycle

Write

Note

Base = Base Address.

TABLE 24 – SECURED SILICON SECTOR PROGRAM

(LLD Function = lld_ProgramCmd)

Cycle

Operation

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Word Address

Data

00AAh

Unlock Cycle 1

Unlock Cycle 2

Program Setup

Program

0055h

Write

0088h

Data Word

Note

Base = Base Address.

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TABLE 25 – SECURED SILICON SECTOR EXIT

(LLD Function = lld_SecSiSectorExitCmd)

Cycle

Operation

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Base + 000h

Data

00AAh

0055h

0088h

0000h

Unlock Cycle 1

Unlock Cycle 2

Exit Cycle 3

Exit Cycle 4

Write

Note

Base = Base Address.

TABLE 26 – ABSOLUTE MAXIMUM RATINGS

Description

Rating

Storage Temperature

-55ºC to +125ºC

Ambient Temperature with Power Applied

All Inputs and I/Os except as noted below (Note 1)

-0.5V to VCC + 0.5V

-0.5V to +4.0 V

0.5V to +12.5V

V

_CC(Note 1)

Voltage with Respect to Ground

VIO

A9 and ACC (Note 2)

Notes

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may

undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11. Maximum DC voltage on

input or I/Os is VCC + 0.5 V. During voltage transitions inputs or I/Os may overshoot to VCC +

2.0 V for periods up to 20 ns. See Figure 12.

2. Minimum DC input voltage on pins A9 and ACC its -0.5V. During voltage transitions, A9 and ACC

may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11. Maximum DC voltage

on pins A9 and ACC is +12.5 V, which may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should

not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage

to the device. This is a stress rating only; functional operation of the device at these or any other

conditions above those indicated in the operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating conditions for extended periods may affect

device reliability.

TABLE 27 – CAPACITANCE

TABLE 28 – RECOMMENDED OPERATING

CONDITIONS

T_A= +25°C, f = 1.0MHz

Parameter

Symbol

C_WE

Max

10.0

25.0

10.0

15.0

Unit

pF

Parameter

Symbol

V_CC

V_IO

Min

3.0

-55

-40

Max

3.6

Unit

V

WE# capacitance

CS# capacitance

Data I/O capacitance

Address input capacitance

Supply Voltage

C_CS

pF

I/O Supply Voltage

Operating Temp. (Mil.)

Operating Temp. (Ind.)

3.6

V

C_I/O

pF

T_A

+125

+85

°C

C_AD

pF

T_A

Note: For all AC and DC speciﬁcations: V_IO= V_CC

RY/BY#

C_RB

C_OE

20.0

18.0

pF

OE# capacitance

This parameter is guaranteed by design but not tested.

TABLE 29 – DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Pattern Data

Retention Time

125°C

20

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TABLE 30 – DC CHARACTERISTICS

Parameter

Symbol

Parameter Description (Notes)

Input Load Current

Test Conditions

Min

Max

Unit

I_LI

V_IN= V_SSto V_CC

V_CC= V_{CC max}

WP/ACC

Others

10

4

μA

I_LIT

I_LO

A9 Input Load Current

V_CC= V_{CC max}; 12.5V

70

2

μA

mA

μA

Output Leakage Current

V_OUT= V_SSto V_CC, V_CC=V_{CC max}

I_CC1

I_IO2

I_CC2

I_CC3

I_CC4

V_CCactive Read Current (1)

V_IONon-active Output

CE# =V_IL, OE# = V_IH, V_CC= V_{CC max}, f = 5MHz

CE# =V_IL, OE# = V_IH

110

20

180

10

V_CCIntra-Page Read Current (1)

V_CCActive Erase/Program CUrrent (2, 3)

V_CCStandby Current

CE# =V_IL, OE# = V_IH, V_CC= V_{CC max}, f = 10MHz

CE# =V_IL, OE# = V_IH, V_CC= V_{CC max}

CE#, RESET# =V_CC±0.3V, OE# = V_IH, V_CC= V_{CC max}

V_IL= V_SS+ 0.3V/-0.1V

I_CC5

I_CC6

I_ACC

V_CCReset Current

V_CC= V_{CC max;}V_IL= V_SS+ 0.3V/-0.1V,

RESET# = V_SS±0.3V

1

mA

μA

mA

Automatic Sleep Mode (4)

ACC Accelerated Program Current

V_CC= V_{CC max}, V_IH= V_CC±0.3V,

10

V_IL= V_SS+ 0.3V/-0.1V, WP#/ACC = VIH

CE# = V_IL, OE# = V_IH

V_CC= V_{CC max}, WP#/ACC = V_HH

WP#/A_CCpin

V_CCpin

40

160

V_IL

V_IH

Input Low Voltage (5)

-0.1

0.7 x V_IO

11.5

0.3 x V_IO

V_IO+ 0.3

12.5

V

Input High Voltage (5)

V_HH

V_ID

Voltage for Program Acceleration

V_CC= 2.7 - 3.6V

Voltage for Autoselect and Temporary Sector Unportect V_CC= 2.7 - 3.6V

11.5

12.5

V_OL

V_OH

V_LKO

Output Low Voltage (5)

Output High Voltage (5)

Low VCC Lock-Out Voltage

I_OL= 100μA

I_OH= 100μA

0.15 x V_IO

0.85 x V_IO

2.3

2.5

Notes

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. I_CCactive while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.

3. Not 100% tested.

4. Automatic sleep mode enables the lower power mode when addresses remain stable tor t_ACC+ 30 ns.

5. V_IO= 1.65–3.6 V

6. V_CC= 3 V and V_IO= 3V or 1.8V. When V_IOis at 1.8V, I/O pins cannot operate at 3V.

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TABLE 31 – AC TEST CONDITIONS

Parameter

Typ

Unit

V

Input Pulse Levels

V_IL- 0, V_IH= 2.5

Input Rise and Fall

5

ns

V

Input and Output Reference Level

Output Timing Reference Level

1.5

V

Notes:

VZ is programmable from -2V to +7V.

IOL & IOH programmable from 0 to 16 mA.

Tester Impedance Z0 = 50

VZ is typically the midpoint of V_OHand V_OL.

IOL & IOH are adjusted to similate a typical resistive load circuit.

ATE tester Includes jig capacitance.

TABLE 32 – TEST SPECIFICATIONS

Test Condition

Output Load

All Speeds

Unit

1 TTL gate

Output Load Capacitance, CL (including jig capacitance)

Input Rise and Fall Times

30

5

pF

ns

V

Input Pulse Levels

0.0–V_IO

0.5V_IO

Input timing measurement reference levels (See Note)

V

Output timing measurement reference levels

Note: If V_IO< V_CC, the reference level is 0.5 V_IO.

V

TABLE 33 – AC CHARACTERISTICS — READ-ONLY OPERATIONS

V_CC= 3.3V ± 0.3V, -55°C ≤ T_A≤ +125°C

-110

-120

Min Max

Parameter

Symbol

Unit

Min Max

Read Cycle Time

t_AVAV

t_AVQV

t_ELQV

t_RC

t_ACC

t_CE

110

120

ns

Address Access Time

110

120

25

Chip Select Access Time

Page Access Time

110

25

20

t_PACC

t_OE

Output Enable to Output Valid (1)

Chip Select High to Output High Z

Output Enable High to Output High Z

t_OLQV

t_EHQZ

t_GHQZ

25

t_DF

20

t_DF

20

Output Hold from Addresses, CS# or OE# Change, Whichever occurs

ﬁrst

t_AXQX

t_OH

0

ns

Read

t_OEH

Output Enable Hold Time

Chip Enable Hold Time

Toggle and Data#

Polling

10

35

10

35

t_CEH

Note: (1) t_OEfor data polling is 45ns when V_IO= 1.65V to 2.7V and 32ns when V_IO= 2.7V to 3.6V.

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TABLE 34 – AC CHARACTERISTICS — HARDWARE RESET (1)

Parameter

Symbol

Min

Max

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode

t_ready

35

μs

RESET# Pin Low (NOT During Embedded Algorithms)

to Read Mode

t_ready

t_RP

35

200

10

0

μs

ns

μs

ns

RESET# Pulse Width

RESET# High Time Before Read

RESET# Low to Standby Mode

RY/BY# Recovery Time

t_RH

t_RPD

t_RB

TABLE 35 – POWER-UP SEQUENCE TIMINGS

Parameter

Symbol

Min

35

Max

Unit

μs

Reset Low Time from rising edge of V_CC(or last Reset pulse) to rising edge of RESET#

Reset Low Time from rising edge of V_IO(or last Reset pulse) to rising edge of RESET#

Reset High Time before Read

tV_CS

tV_IOS

t_RH

35

μs

200

μs

Notes

1. V_IO< V_CC+ 200 mV.

2. V_IOand VCC ramp must be synchronized during power up.

3. If RESET# is not stable for tV_CSor tV_IOS

:

The device does not permit any read and write operations.

A valid read operation returns FFh.

A hardware reset is required.

4. V_CCmaximum power-up current (RST=V_IL) is 20 mA.

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Table 36 – AC CHARACTERISTICS — WRITE/ERASE/PROGRAM OPERATIONS —

WE# CONTROLLED

V_CC= 3.3V ± 0.3V, -55°C ≤ T_A≤ +125°C

-110

Min Max

110

-120

Parameter

Symbol

Unit

Min Max

Write Cycle Time (3)

t_AVAV

t_ELWL

t_WC

t_CS

t_WP

t_AS

120

ns

Chip Select Setup Time (3)

Write Enable Pulse Width

Address Setup Time

0

35

0

35

0

t_WLWH

t_AVWL

t_DVWH

t_WHDX

t_WLAX

t_WHWL

t_WHWH1

t_WHWH2

t_GHWL

t_VCS

ns

Data Setup Time

t_DS

30

0

30

0

ns

Data Hold Time

t_DH

t_AH

ns

Address Hold Time

45

30

45

30

ns

Write Enable Pulse Width High (3)

Duration of Byte Programming Operation (1)

Sector Erase (2)

t_WPH

ns

480

5

480

5

μs

sec

ns

Read Recovery Time before Write (3)

0

V_CCSetup Time (3)

35

μs

sec

ns

Chip Programming Time (4)

200

Address Setup Time to OE# low during toggle bit polling

t_ASO

15

Notes:

1. Typical value for t_WHWH1is 6μs.

2. Typical value for t_WHWH2is 0.5 sec.

3. Guaranteed by design, but not tested.

4. Typical value is 50 sec. The typical chip program time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed.

TABLE 37 – AC CHARACTERISTICS — ALTERNATE CS# CONTROLLED ERASE AND PROGRAM OPERATIONS

Parameter

Description

Speed Options

Unit

JEDEC

t_VAVAV

t_AVWL

Std

t_WS

110

120

0

Write Cycle Time (1)

Min

Typ

110

0

ns

μs

sec

t_AS

Address Setup Time

t_ELAX

t_AH

Address Hold Time

45

30

0

50

30

0

t_DVEH

t_DS

Data Setup Time

t_EHDX

t_DH

Data Hold Time

t_WHEH

t_GHEL

t_CH

CE# Hold Time

0

t_GHEL

t_WS

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time

0

t_WLEL

0

t_EHWH

t_ELEH

t_WH

WE# Hold Time

0

t_CP

CS# Pulse Width

35

30

480

13.5

0.5

35

30

480

13.5

0.5

t_EHEL

t_CPH

t_WHWH1

t_WHWH2

CS# Pulse Width High (1)

Programming Operation

Accelerated Programming Operation

Sector Erase Operation

t_WHWH1

t_WHWH2

Note:

1. Not tested.

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TABLE 38 – ERASE AND PROGRAMMING PERFORMANCE

V_CC= 3.3V ± 0.3V, -55°C ≤ T_A≤ +125°C

Typ

(Note 1)

0.5

Max

(Note 2)

3.5

Parameter

Unit

Comments

Sector Erase Time

sec

μs

Excludes 00h programming prior to erasure (Note 4)

Chip Erase Time

64

256

Total Write Buffer Time (Note 3)

Total Accelerated Write Buffer Programming Time (Note 3)

Ship Program Time

480

432

μs

Excludes system level overhead (Note 5)

123

sec

Notes

1. Typical program and erase times assume the following conditions: 25ºC, 3.6V V_CC, 10,000 cycles,

checker board pattern.

4. In the pre-programming step of the embedded erase algorithm, all bits are programmed to 00H

before erasure.

2. Under corst case conditions of -40ºC, V_CC= 3.0V, 100,000 cycle.

3. Effective write buffer speciﬁcation is based upon 32-word write buffer operation.

5. System0level overhead is the time required to execute the two-or four-bus-cycle sequence for the

program command. See table 38 and 39.

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TABLE 39 – MEMORY ARRAY COMMAND DEFINITIONS

Bus Cycles (Note 1-5)

Command

First

Second

Third

Fouth

Fifth

Sixth

Addr

RA

Data

RD

F0

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (6)

Reset (7)

1

4

1

4

3

1

3

2

6

1

3

4

XXX

555

55

Manufacturer ID

AA

98

2AA

55

555

90

X00

X01

01

227E

(10)

(11)

Device ID (8)

X0E

(8)

X0F

(8)

Sector Protect Verify (10)

Secure Device Verify (11)

[SA]X02

X03

CFI Query (12)

Program

555

SA

AA

29

2AA

55

555

SA

A0

25

PA

SA

PD

Write to Buffer

WC

WBL

PD

WBL

PD

Program Buffer to Flash (Conﬁrm)

Write-to-Buffer-Abort Reset

Enter

555

XXX

555

XXX

555

AA

A0

80

2AA

PA

55

PD

30

10

00

55

555

F0

20

Program (14)

Sector Erase (14)

SA

Chip Erase (14)

80

XXX

2AA

Reset (15)

90

Chip Erase

AA

B0

30

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend/Program Suspend (16)

Erase Resume/Program Resume (17)

Secured Silicon Sector Entry

Secured SIlicon Sector Exit (18)

Legend

AA

2AA

55

555

88

90

XX

00

X

= Don’t care

RA = Address of the memory to be read.

RD = Data read from location RA during read operation.

8. See Table 7.2 for device ID values and deﬁnitions.

9. The fourth, ﬁfth, and sixth cycles of the autoselect command sequence are read cycles.

10. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect for

more information. This is same as PPB Status Read except that the protect and unprotect

statuses are inverted here.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of

the WE# or CE# pulse, whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE#

pulse, whichever happens ﬁrst.

11. The data value for DQ7 is “1” for a serialized, protected Secured Silicon Sector region and “0”

for an unserialized, unprotected region. See data and deﬁnitions.

SA = Address of the sector to be veriﬁed (in autoselect mode) or erased. Address bits Amax–A16

uniquely select any sector.

WBL = Write Buffer Location. The address must be within the same write buffer page as PA.

WC = Word Count is the number of write buffer locations to load minus 1.

12. Command is valid when device is ready to read array data or when device is in autoselect mode.

13. Command sequence returns device to reading array after being placed in a Write-to-Buffer-Abort

state. Full command sequence is required if resetting out of abort while in Unlock Bypass mode.

14. The Unlock-Bypass command is required prior to the Unlock-Bypass- Program command.

15. The Unlock-Bypass-Reset command is required to return to reading array data when the device

is in the unlock bypass mode.

Notes

1. See Table 7.1 for description of bus operations.

2. All values are in hexadecimal.

3. All bus cycles are write cycles unless otherwise noted.

4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.

5. Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA or PA

required. (AMAX is the Highest Address pin.).

16. The system can read and program/program suspend in non-erasing sectors, or enter the

autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only

during a sector erase operation.

17. The Erase Resume/Program Resume command is valid only during the Erase Suspend/

Program Suspend modes.

18. The Exit command returns the device to reading the array.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect

mode, or if DQ5 goes high (while the device is providing status data).

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TABLE 40 – SECTOR PROTECTION COMMAND DEFINITIONS

Command

Bus Cycles (Note 1-5)

First

Second

Third

Fouth

Fifth

Sixth

Addr

555

XXX

00

Data

AA

Addr

2AA

XXX

Data

55

Addr

555

Data

Addr

Data

Addr

Data

Addr

Data

Command Set Entry

Program (6)

3

2

1

2

3

2

4

A0

DATA

Read (6)

RD

90

Command Set Exit (7, 8)

Command Set Entry

Password Program (9)

Password Read (10)

XXX

555

XXX

00

XXX

2AA

PWAx

01

00

55

AA

555

A0

PWDx

PWD 1

03

PWD0

25

02

00

PWD 2

PWD 0

03

01

PWD 3

PWD 1

00

02

PWD 2

03

PWD 3

Password Unlock (10)

7

00

29

Command Set Exit (7, 8)

PPB Command Set Entry

PPB Program (11, 12)

2

3

2

1

2

3

2

1

2

3

2

1

2

XXX

555

XXX

SA

90

XXX

2AA

SA

00

55

00

30

AA

555

A0

All PPB Erase (13)

80

00

PPB Status Read (12)

RD (0)

90

PPB Command Set Exit (7, 8)

PPB Lock Cammand Set Entry

PPB Lock Set (12)

XXX

555

XXX

555

XXX

SA

XXX

2AA

XXX

00

55

00

AA

555

A0

PPB Lock Command Set Exit (7, 8)

DYB Command Set Entry

DYB Set (11, 12)

RD (0)

90

XXX

2AA

SA

00

55

00

01

AA

A0

DYB Clear (12)

A0

SA

DYB Status Read (12)

RD (0)

90

DYB Command Set Exit (7, 8)

XXX

00

Legend

X = Don’t care

RD(0) = Read data.

SA = Sector Address. Address bits Amax–A16 uniquely select any sector.

PWD = Password

PWDx = Password word0, word1, word2, and word3.

Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,

PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit.

Notes

1. See Table 7.1 for description of bus operations.

2. All values are in hexadecimal.

3. All bus cycles are write cycles unless otherwise noted.

4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.

5. Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA or PA

required. (AMAX is the Highest Address pin.)

7. The Exit command returns the device to reading the array.

8. If any Command Set Entry command was written, an Exit command must be issued to reset the

device into read mode.

9. For PWDx, only one portion of the password can be programmed per each “A0” command.

10. Note that the password portion can be entered or read in any order as long as the entire 64-bit

password is entered or read.

6. All Lock Register bits are one-time programmable. Program state = “0” and the erase state = “1.”

The Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be

programmed at the same time or the Lock Register Bits Program operation aborts and returns

the device to read mode. Lock Register bits that are reserved for future use default to “1’s.” The

Lock Register is shipped out as “FFFF’s” before Lock Register Bit program execution.

11. If ACC = VHH, sector protection matches when ACC = VIH.

12. Protected State = “00h,” Unprotected State = “01h.”

13. The All PPB Erase command embeds programming of all PPB bits before erasure.

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FIGURE 5 – SINGLE WORD PROGRAM

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Program Command:

Address 555h, Data A0h

Setup Command

Program Address (PA),

Program Data (PD)

Program Data to Address:

PA, PD

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Polling Status

= Busy?

No

Yes

Polling Status

= Done?

Error condition

(Exceeded Timing Limits)

No

PASS. Device is in

read mode.

FAIL. Issue reset command

to return to read array mode.

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Figure 6 – WRITE BUFFER PROGRAMMING OPERATION

Write Unlock Cycles:

Unlock Cycle 1

Address 555h, Data AAh

Unlock Cycle 2

Address 2AAh, Data 55h

Issue

Write Buffer Load Command:

Address SA, Data 25h

Load Word Count to Program

Program Data to Address:

SA, wc

wc = number of words – 1

Yes

Confirm command:

wc = 0?

No

SA = 0x29h

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Write Next Word,

Decrement wc:

wc = wc – 1

No

Write Buffer

Abort Desired?

Yes

Polling Status

= Done?

Write to a Different

Sector Address to Cause

Write Buffer Abort

No

Error?

Yes

Write Buffer

Abort?

No

RESET. Issue Write Buffer

Abort Reset Command

PASS. Device is in

read mode.

FAIL. Issue reset command

to return to read array mode.

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FIGURE 7 – SECTOR ERASE OPERATION

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Sector Erase Cycles:

Address 555h, Data 80h

Address 555h, Data AAh

Address 2AAh, Data 55h

Sector Address, Data 30h

Command Cycle 1

Command Cycle 2

Command Cycle 3

Specify first sector for erasure

Select

Additional

Sectors?

No

Yes

Write Additional

Sector Addresses

• Each additional cycle must be written within t_SEAtimeout

• The host system may monitor DQ3 or wait t_SEAto ensure

acceptance of erase commands

• No limit on number of sectors

Yes

Last Sector

Selected?

No

• Commands other than Erase Suspend or selecting additional

sectors for erasure during timeout reset device to reading array

data

Poll DQ3.

DQ3 = 1?

No

Yes

Perform Write Operation

Status Algorithm

Status may be obtained by reading DQ7, DQ6 and/or DQ2.

Yes

Done?

No

Error condition (Exceeded Timing Limits)

DQ5 = 1?

Yes

PASS. Device returns

to reading array.

FAIL. Write reset command

to return to reading array.

Notes

1. See table 12.1 on page 69 for earse command sequence.

2. See DQ3: Sector Erase Timeout State Indicator on page 39 for information on the sector erase timeout.

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FIGURE 8 – SECTOR ERASE OPERATION

START

- DQ 6 toggles when programming

- DQ 6 and DQ 2 toggle when erasing

- DQ 2 toggles when erase suspend

- DQ 1 set when program error

- DQ 5 set when time out

Read_1

Read_2

Read_3

DQ6 Toggles between

Read_1 & Read_2

and

Read_1

Read_2

NO

Read_2 & Read_3

YES

NO

WriteBuffer

program and

Read_1 DQ1 is

set

RETURN

WRITE ABORT

RETURN

DONE

YES

DQ2 Toggles

NO

YES

Read_1 DQ5 is

set

RETURN

TIME OUT

YES

RETURN

SUSPEND

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FIGURE 9 – SECTOR ERASE OPERATION

Hardware Methods

Software Methods

Lock Register

(One Time Programmable)

WP#/ACC = V_IL

(Highest or Lowest

Sector Locked)

Persistent Method

Password Method

(DQ1)

(DQ2)

64-bit Password

(One Time Protect)

1. Bit is volatile, and defaults to “1” on reset.

2. Programming to “0” locks all PPBs to their

current state.

3. Once programmed to “0”, requires hardware

reset to unlock.

PPB Lock Bit^1,2,3

0 = PPBs Locked

1 = PPBs Unlocked

Persistent

Protection Bit

(PPB)^4,5

Dynamic

Protection Bit

(DYB)^6,7,8

Memory Array

Sector 0

Sector 1

Sector 2

PPB 0

PPB 1

PPB 2

DYB 0

DYB 1

DYB 2

Sector N-2

Sector N-1

Sector N³

PPB N-2

PPB N-1

PPB N

DYB N-2

DYB N-1

DYB N

3. N = Highest Address Sector.

4. 0 = Sector Protected,

1 = Sector Unprotected.

6. 0 = Sector Protected,

1 = Sector Unprotected.

5. PPBs programmed individually,

but cleared collectively

7. Protect effective only if PPB Lock Bit is

unlocked and corresponding PPB is “1”

(unprotected).

8. Volatile Bits: defaults to user choice upon

power-up (see ordering options).

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FIGURE 10 – PPB PROGRAM ALGORITHM

Enter PPB

Command Set.

Addr = BA

Program PPB Bit.

Addr = SA

Read Byte Twice

Addr = SA0

No

DQ6 =

Toggle?

Yes

No

DQ5 = 1?

Yes

Wait 500 µs

Read Byte Twice

Addr = SA0

No

Read Byte.

Addr = SA

DQ6 =

Toggle?

Yes

No

DQ0 =

'0' (Pgm.)?

FAIL

Yes

Issue Reset

Command

PASS

Exit PPB

Command Set

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FIGURE 11 – LOCK REGISTER PROGRAM ALGORITHM

Write Unlock Cycles:

Unlock Cycle 1

Address 555h, Data AAh

Unlock Cycle 2

Address 2AAh, Data 55h

Write

Enter Lock Register Command:

Address 555h, Data 40h

XXXh = Address don’t care

Program Lock Register Data

Program Data (PD): See text for Lock Register definitions

Address XXXh, Data A0h

Address XXXh*, Data PD

Caution: Lock register can only be progammed once.

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Done?

No

DQ5 = 1?

Yes

Error condition (Exceeded Timing Limits)

PASS. Write Lock Register

Exit Command:

FAIL. Write rest command

to return to reading array.

Address XXXh, Data 90h

Address XXXh, Data 00h

Device returns to reading array.

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FIGURE 12 – MAXIMUM NEGATIVE OVER SHOOT WAVEFORM

20 ns

+0 .8 V

–0 .5 V

–2 .0 V

20 ns

FIGURE 13 – MAXIMUM POSITIVE OVER SHOOT WAVEFORM

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

+2.0 V

20 ns

FIGURE 14 – AC TEST CIRCUIT

I_OL

Current Source

V_Z~ 1.5v

(Bipolar Supply)

D.U.T.

C_EFF= 50pf

I_OH

Current Source

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FIGURE 15 – AC WAVEFORMS FOR READ OPERATIONS

t_RC

Addresses

CS#

Addresses Stable

t_ACC

t_CEH

t_RH

t_DF

OE#

t_OE

t_OEH

t_CE

WE#

t_OH

High Z

Outputs

Output Valid

RESET#

RY/BY#

OV

FIGURE 16 – PAGE READ OPERATION TIMINGS

Same Page

A22-A3

A2-A0

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Ad

t_PACC

Qc

Data

CS#

Qa

Qb

Qd

OE#

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FIGURE 17 – RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS

RY/BY#

CS#, OE#

RESET#

t_RH

t_RP

t_Ready

FIGURE 18 – RESET TIMINGS DURING EMBEDDED ALGORITHMS

t_Ready

RY/BY#

t_RB

CS#, OE#

RESET#

t_RP

FIGURE 19 – POWER-UP SEQUENCE TIMINGS

V

CC

V

min

CC

V

IO

t

RH

CE#

t

VIOS

t

VCS

RESET#

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FIGURE 20 – PROGRAM OPERATION

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CS#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

NOTES:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3.

D_OUTis the output of the data written to the device.

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FIGURE 21 – ACCELERATED PROGRAM TIMING DIAGRAM

V_HH

V_ILor V_IH

WP#/ACC

t_VHH

Notes:

1. Not 100% tested

2. CE#, OE# = V_IL

3. OE#, = V_IL

4. See ﬁgure 4 and Table 32 for test speciﬁcations

FIGURE 22 – CHIP/SECTOR ERASE OPERATION TIMINGS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

2AAh

SA

VA

555h for

chip erase

t_AH

CS#

OE#

t_CH

t_WHWH2

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

30h

D_OUT

55h

Status

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "write operation status")

2. These wave forms are for word mode.

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FIGURE 23 – DATA# POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)

t_RC

VA

Addresses

VA

t_ACC

t_CS

CS#

OE#

t_CH

t_OE

t_OEH

t_DF

t_OH

WE#

DQ7

High Z

Valid Data

Complement

True

Status Data

True

Valid Data

Status Data

DQ6–DQ0

RY/BY#

t_BUSY

Notes:

1. VA = Valid address. Illustration shows ﬁrst status cycle after command sequence, last status read cycle, and array data read cycle.

2. _OEfor data polling is 35ns when V_IO= 2.7 to 3.6V.

T

3. CE# does not need to go high between status bit reads.

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FIGURE 24 – TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)

t_AHT

t_AS

Addresses

CS#

t_AHT

t_ASO

t_CSPH

t_OEH

WE#

OE#

t_OEPH

t_DH

Valid Data

t_OE

Valid

Status

Valid

DQ6/DQ2

RY/BY#

Valid Data

Status

(first read)

(second read)

(stops toggling)

Note:

1. A = Valid address; Not required for DQ6. Illustration shows ﬁrst two status cycle after command sequence, last status read cycle, and array data read cycle

2. CE# does not need to go high between status bit reads.

FIGURE 25 – DQ2 VS. DQ6

Enter

Erase

Suspend

Enter Erase

Suspend Program

Embedded

Erasing

Erase

Resume

Erase

Erase Suspend

Read

Erase

WE#

Erase

Erase Suspend

Read

Suspend

Program

Complete

DQ6

DQ2

NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6.

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FIGURE 26 – SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Group Protect/Unprotec t

Verify

40h

Data

60h

Status

1 µs

CS#

WE#

OE#

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

NOTES:

For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

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FIGURE 27 – ALTERNATE CS# CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CS#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

NOTES:

1. Figure Indicated last two bus cycles of a program or erase operation.

2. PA = program address. SA = sector address, PD = program data.

3. DQ7 is the complement of the data written to the device. D_OUTis the data written to the device.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 15

42

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W78M32VP-XBX

PACKAGE – 159 PBGA (PLASTIC BALL GRID ARRAY)

BOTTOM VIEW

159 X Ø 0.762 (0.030) NOM

10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

0.61 (0.024) NOM

2.15 (0.079) MAX

1.27 (0.050) NOM

11.43 (0.450) NOM

13.10 (0.516) MAX

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 15

43

Microsemi Corporation • (602) 437-1520 • www.microsemi.com

W78M32VP-XBX

ORDERING INFORMATION

W 7 8M32 VP - XXX B X

Microsemi Corporation:

Flash:

Organization, 8M x 32:

3.3V Power Supply:

Access Time (ns):

110 = 110ns

120 = 120ns

Package Type:

B = 159 PBGA, 13mm x 22mm

Devise Grade:

M = Military

I = Industrial

-55°C to +125°C

-40°C to +85°C

C = Commercial 0°C to +70°C

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 15

44

Microsemi Corporation • (602) 437-1520 • www.microsemi.com

W78M32VP-XBX

Document Title

8Mx32 NOR Flash 3.3V Page Mode Multi-Chip Package

Revision History

Rev #

History

Release Date Status

Rev 0

Initial Release

December 2007

Advanced

Rev 1

Rev 2

Change (Pg. All)

July 2008

Advanced

1.1 Add detail to DC, AC and programming sections

Change (Pg. 1, 3, 25, 27, 47)

October 2008

Advanced

2.1 Removed 90 and 100ns access times

2.2 Added 110ns access time

Rev 3

Rev 4

Change (Pg. 2)

December 2008

March 2009

Advanced

3.1 Correct ball B6; change from "NC" to "DQ57"

Change (Pg. 2, 25, 26, 28)

4.1 Remove "TBD" from pin conﬁguration and block diagram

4.2 In Table 30; I_CC5is 2mA

4.3 In Table 30; Add Note 3 to I_{LI (WP/ACC)}, I_LIT, I_LOZ, I_CC6, I_ACC, V_HH, V_ID,V_LKO

4.4 In Table 30; Remove V_IL= V_SS+ 0.3V/-1.0V from I_CC6and I_CC5

4.5 In Table 32; Remove Note 1 from read cycle time, page access time and

output enable hold time

4.6 In Table 32; Change page access time to 25ns on both -100 and -120

4.7 In Table 35; Change output enable to output valid symbol to t_GLQV

4.8 In Table 35; Remove Note 1 from duration of byte programming operation

4.9 In Table 35; Remove Note 3 from write cycle time

4.10 Change 100 to 110 in Table 35

4.11 In Table 36; Remove Note 1 from write cycle time and correct JEDEC

symbol t_AV_AV

4.12 Add new page; Test Conditions - Figure 11 - Test Setup Diagram and Table

40 - Test Speciﬁcations

4.13 Update all ﬁgures and tables following addition of Figure 11 and Table 40

4.14 Change dimension thickness to 2.70 (0.106) max due to typo

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 15

45

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W78M32VP-XBX

Document Title

8Mx32 NOR Flash 3.3V Page Mode Multi-Chip Package (continued)

Revision History

Rev #

History

Release Date Status

Rev 5

Change (Pg. 1, 2, 3, 16 ,23, 26, 30, 39, 41, 44)

5.1 Delete V_IOrange is 1.65 to V_CC

March 2009

Advanced

5.2 Remove (*) astrisk from pin H10, A-1 from Fig 3, correct spelling of versatile

in Fig. 2

5.3 Delete versatile IO (V_IO) control pargraph

5.4 Remove paragraph on customer programming services

5.5 Remove all reference to Fig. 8.1

5.6 Change output hold from address in Table 32 to 0 for both speeds grades,

change output enable hold time - Read to 0 for both speed grades

5.7 Table 38, note 1 is Table 2, note 8 is Table3

5.8 Table 39 note 1 is Table 2

5.9 Correct Fig. 12; Maximum negative overshoot wave form, Fig. 13; maximum

positive overshoot waveform

5.10 Add Table 40; Power-up sequence timings and notes

Rev 6

Rev 7

Change (Pg. 29)

June 2009

Advanced

6.1 Table 37 notes: change notes 1-5

Change (Pg. 4, 7,25, 26, 27, 28, 29, 30, 39, 40, 41, 43, 45, 46)

7.1 Change Table 38 to 39

August 2009

7.2 Add new Table 32 - Test Speciﬁcations

7.3 Re-number table sequence from Table 32

7.4 Add Note #1 to Figure 16

7.5 Remove Table 41, duplicate to Table 35

7.6 Add Note #4 to Figure 21

7.7 Add Note #2 to Figure 24

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 15

46

Microsemi Corporation • (602) 437-1520 • www.microsemi.com

W78M32VP-XBX

Document Title

8Mx32 NOR Flash 3.3V Page Mode Multi-Chip Package (continued)

Revision History

Rev #

History

Release Date Status

Rev 8

Change (Pg. 1, 2, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27)

September 2009

Final

8.1 Remove "/128KB sectors" from uniform sector architecture - No Byte mode

8.2 Remove "/256 byte and /16 byte" from secured silicon sector region.

8.3 Remove "under development, is not qualiﬁed or characterized and is" or

cancellation.

8.4 Remove "Pin A-1" from block diagram

8.5 Remove "Byte# = V_IL" in device operations

8.6 Remove "AMax:A-1 in byte mode," from Notes in device operations

8.7 Remove all reference to "Byte Address" from pages 17 through 23

8.8 Change I_LIto 10ꢀA for WP/ACC and 4ꢀA for others, I_LIT= 70ꢀA,I_LO= 2ꢀA,

I_CC1= 110ꢀA, I_IO2= 20ꢀA, I_CC2= 20ꢀA, I_CC3= 180ꢀA, I_CC4= 10ꢀA,

I_CC5= 1mA, I_CC6= 10ꢀA, I_ACC= 40mA for WP#/A_CCPin and 160mA for

V_CCPin

8.9 Add Note (1) to AC Characteristics: t_OEfor data polling is 45ns when V_IO

1.65V to 2.7V and 32ns when V_IO= 2.7V to 3.6V.

=

Rev 9

Change (Pg. 2, 3, 39)

November 2009

Final

9.1 Change DQ0-63 to DQ0-31 inf Fig. 2

9.2 Remove "/16 Bytes" in page read mode and replace "max" with 22

9.3 Remove (A2 to A-1 in byte mode)

9.4 Remove "note" in Fig. 16

Rev 10

Change (Pg. 26, 27)

10.1 Corrected Table 35

10.2 Add “t_CH” to Table 37

Rev 11

Rev 12

Rev 13

Change (Pg. 2)

November 2009

January 2010

March 2010

Final

11.1 Corrected pinout – DQ16-31 are B3, C2-C5, D2-D5, E2-E5, and F3-F5

Change (Pg. 23)

12.1 Added capacitance measurements to table 27.

Change (Pg. 47)

13.1 Updated MO drawing thickness to 2.15 (0.079) max, length to 22.10 (0.870)

max and width to 13.10 (0.516) max

Rev 14

Rev 15

Change (Pg. 23)

February 2011

August 2011

Final

14.1 Update Table 36, AC Characteristics

14.2 Combine Rev 4 items in Revision History

Changes (1, 45, 46, 47)

15.1 Add "NOR" to headline

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 15

47

Microsemi Corporation • (602) 437-1520 • www.microsemi.com


型号：	W78M32VP-100BC
厂家：	MERCURY UNITED ELECTRONICS INC
描述：	Flash, 内存集成电路
文件：	总47页 (文件大小：1902K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W78M32VP-100BC [MERCURY]

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