DSC1131FI2-T [MICREL]
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS Oscillator;
| 型号： | DSC1131FI2-T |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS Oscillator |
| 文件： | 总6页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC2131 DSC2231
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS Oscillator
General Description
Features
The DSC2131 and DSC2231 series of
programmable, high-performance dual LVDS-
CMOS oscillators utilizes a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating high output
frequency flexibility. DSC2131 and DSC2231
allow the user to independently modify the
frequency of each output and CMOS drive
strength using I2C or SPI interface,
respectively. User can also select from two
pre-programmed default output frequencies
using the control pin.
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±25, ±50 ppm
Wide Temperature Range
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Independent LVDS and CMOS Outputs
I2C/SPI Programmable Freq & Drive
Short Lead Times: 2 Weeks
Wide Frequency Range:
o LVDS Output: 2.3 to 460 MHz
o CMOS Output: 2.3 to 170 MHz
DSC2131 and DSC2231 are packaged in 14-
pin 3.2x2.5 mm QFN package and available
in temperature grades from Ext. Commercial
to Industrial.
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
Block Diagram
High Reliability
o 20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Applications
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
Pin # DSC2131 (I2C)
DSC2231 (SPI)
3
5
6
7
NC
SDA
SCL
SCLK
MOSI
MISO
SS
CS_bar
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DSC2131 DSC2231 Page 1 MK-Q-B-P-D-12050107
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS
DSC2131 DSC2231
Pin Description
Pin No. Pin Name Pin Type
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
DSC2131: Leave unconnected or grounded
DSC2231: Serial clock from master
Ground
1
2
Enable
NC
NC
SCLK
GND
SDA
MOSI
SCL
MISO
CS_bar
SS
Output1+
Output1-
NC
I
NA
NA
I
Power
I
3
4
5
DSC2131: I2C Serial Data
DSC2231: SPI Serial Data from Master to Slave
I
O
I
I
O
O
NA
O
DSC2131: I2C Serial Clock
6
7
DSC2231: SPI Serial Data from Slave to Master
DSC2131: I2C Chip Select (Active Low)
DSC2231: SPI Slave Select (Active Low)
Positive LVDS Output
Negative LVDS Output
Leave unconnected or grounded
CMOS Output
Power Supply for CMOS Output
Power Supply
Default output clock frequency bit
8
9
10
11
12
13
14
Output 2+
VDD2
VDD
Power
Power
I
FS
Operational Description
The DSC2131/2231 is a dual LVDS oscillator
consisting of a MEMS resonator and a support
PLL IC. The outputs are generated through
independent 8-bit programmable dividers from
the output of the internal PLL.
The DSC2131/2231 has programmable CMOS
output drive strength, which can be controlled
via I2C/SPI. Table 1 displays typical rise / fall
times for the output with a 15pf load
capacitance as a function of these control bits
at VDD=3.3V and room temperature.
DSC2131/2231 allows for easy programming
of the output frequencies using I2C/SPI
interface. Upon power-up, the initial output
frequencies are controlled by an internal pre-
programmed memory (OTP). This memory
stores all coefficients required by the PLL for
two different default frequency pairs. The
control pin (FS) selects the initial pair. Once
the device is powered up, a new output
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OXS2, OXS1, OXS0] - Default [111]
X=1 for output1, and 2 for output2
000 001 010 011 100 101 110 111
tr (ns) 2.1 1.7 1.6 1.4 1.3 1.3 1.2 1.1
tf (ns) 2.5 2.4 2.4
2
1.8 1.6 1.3 1.3
frequency
pair
can
be
programmed.
VDD2 supply the CMOS output and must be
equal to or less than VDD. VDD2 can be as
low as 1.65V.
Programming details are provided in the
Programming Guide. Standard default
frequency pairs are described in the following
sections. Discera supports customer defined
versions of the DSC2131/2231.
When Enable (pin 1) is floated or connected to
VDD, the DSC2131/2231 is in operational
mode. Driving Enable to ground will tri-state
both output drivers (hi-impedance mode).
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DSC2131 DSC2231 Page 2 MK-Q-B-P-D-12050107
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS
DSC2131 DSC2231
Output Clock Frequencies
Table 1 lists the standard default frequency configurations and the associated ordering information
to be used in conjunction with the ordering code. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency pairs
Select Bit [FS] – Default is [1]
Ordering
Info
Freq
(MHz)
0
1
fOUT1
fOUT2
fOUT1
148.5
74.25
74.25
74.25
J0001
Contact factory for additional
configurations.
JXXXX
fOUT2
Frequency select bit are weakly tied high so if left unconnected the default setting will be [1] and
the device will output the associated frequency highlighted in Bold.
Absolute Maximum Ratings
Ordering Code
Item
Min
Max
Unit Condition
Prog Mode
1: I2C bus
2: SPI bus
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
Supply Voltage
-0.3
+4.0
V
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3 VDD+0.3
V
°C
°C
°C
V
-
-55
-
+150
+150
+260
DSC2 1 31 F I 2
xxxxx
T
40sec max.
ESD
HBM
MM
-
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
Freq (MHz)
See Freq. table
4000
400
CDM
1500
Note: 1000+ years of data retention on internal memory
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DSC2131 DSC2231 Page 3 MK-Q-B-P-D-12050107
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS
DSC2131 DSC2231
Specifications (Unless specified otherwise: T=25° C)
Parameter
Supply Voltage1
Condition
Min.
Typ.
Max.
3.6
Unit
V
VDD
IDD
2.25
Supply Current
EN pin low – outputs are disabled
21
49
23
mA
EN pin high – outputs are enabled
LVDS: RL=100Ω, FO1=125 MHz
CMOS: CL=15pF, FO2=75 MHz
EN pin high – outputs are enabled
RL=100Ω, FO1=FO2 =156.25 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
Supply Current2
IDD
IDD
Δf
mA
mA
Supply Current2
38
±25
±50
Frequency Stability
Aging
Startup Time3
ppm
Δf
tSU
1 year @25°C
T=25°C
±5
5
ppm
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
tDA
5
ns
ns
tEN
20
Pull-up exists on all digital IO
LVDS Output
40
kΩ
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time4
Rise Time
R=100Ω Differential
1.125
1.4
50
V
mV
mV
Single-Ended
350
200
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
ps
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Period Jitter5
SYM
JPER
FO1=125 MHz
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.28
0.4
1.7
Integrated Phase Noise
JCC
psRMS
2
CMOS Output
Output Logic Levels
Output logic high
Output logic low
Output Transition time4
Rise Time
VOH
VOL
I=±6mA
0.9xVDD
-
-
V
0.1xVDD
20% to 80%
CL=15pf
tR
tF
1.1
1.3
2
2
ns
Fall Time
Frequency
Output Duty Cycle
f0
SYM
Commercial/Industrial temp range
2.3
45
170
55
MHz
%
Period Jitter5
JPER
FO2=125 MHz
3
psRMS
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JCC
psRMS
2
Notes:
1.
Pin 4 VDD should be filtered with 0.01uf capacitor.
2.
3.
4.
5.
Output is enabled if Enable pad is floated or not connected.
tsu is time to stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2131 DSC2231 Page 4 MK-Q-B-P-D-12050107
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS
DSC2131 DSC2231
Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V)
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
156MHz-LVDS
212MHz-LVDS
320MHz-LVDS
410MHz-LVDS
25MHz-CMOS
50MHz-CMOS
106MHz-CMOS
125MHz-CMOS
0
200
400
600
800
1000
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
Low-end of integration BW: x kHz to 20 MHz
LVDS Phase jitter (integrated phase noise)
CMOS Phase jitter (integrated phase noise)
Output Waveform: LVDS
tR
tF
Output
Output
80%
50%
20%
350 mV
tEN
1/fo
tDA
VIH
Enable
VIL
Output Waveform: CMOS
tR
tF
VOH
Output
VOL
tEN
1/fo
tDA
VIH
Enable
VIL
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DSC2131 DSC2231 Page 5 MK-Q-B-P-D-12050107
Low-Jitter I2C/SPI Programmable Dual LVDS-CMOS
DSC2131 DSC2231
Solder Reflow Profile
20-40
Sec
260°C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
217°C
200°C
60-150
Sec
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
60-180 Sec
60-150 Sec
255-260°C
20-40 Sec
6°C/Sec Max.
8 min Max.
Reflow
60-180
Sec
150°C
Cool
Pre heat
25°C
Time 25°C to Peak Temperature
Time
8 min max
Package Dimensions
3.2 x 2.5 mm 14 Lead Plastic Package
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information
is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims
any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the
body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or
sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any
damages resulting from such use or sale.
MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
●
●
USA
●
Email: hbwhelp@micrel.com
www.micrel.com
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DSC2131 DSC2231 Page 6 MK-Q-B-P-D-12050107
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