DSC2011FI1-E0012T [MICREL]
Crystal-less⢠Configurable Clock Generator;
| 型号： | DSC2011FI1-E0012T |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Crystal-less⢠Configurable Clock Generator |
| 文件： | 总6页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC2011FI1-E0012
Crystal-less™ Configurable Clock Generator
General Description
Features
The DSC2011FI1-E0012 is a programmable, high
performance dual LVCMOS output oscillator utilizing
Micrel's proven silicon MEMS technology to provide
excellent jitter and stability while incorporating
additional device functionality. Two LVCMOS outputs
are controlled by separate supply voltages to allow for
independent voltage level control. The frequencies of
the outrputs can be identical or independently derived
from a common PLL frequency source.
The DSC2011FI1-E0012 has provision for up to eight
user-defined pre-programmed, pin-selectable output
frequency combinations. The DSC2011FI1-E0012 is
also equipped with independent pin-selectable output
drive strengths to reduce EMI and noise.
• Frequency and output formats:
- LVCMOS
154/65/71/108/119/130.25/148.5/162MHz
- LVCMOS
154/65/71/108/119/130.25/148.5/162MHz
• Low RMS phase jitter: <1ps (typ)
• ±50ppm frequency stability
• -40°C to +85°C industrial temperature range
• High supply noise rejection: -50dBc
• Pin-selectable configurations
- 2-bit output drive strength
- Up to 8 output frequency combinations
• Excellent shock & vibration immunity
- Qualified to MIL-STD-883
Applications
• High reliability
• Consumer Electronics
- 20x better MTF than quartz oscillators
• Supply range of 2.25 to 3.6V
• AEC-Q100 automotive qualified
• 14-pin 3.2mm x 2.5mm QFN package
• Storage Area Networks
- SATA, SAS, Fibre Channel
• Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-GPON
• Ethernet
- 1G, 10GBASE-T/KR/LR/SR, and FCoE
• HD/SD/SDI Video & Surveillance
• PCI Express
• Automotive
VDD/VDD2
Block Diagram
O1S0/O1S1
CLK1
Control Circuitry
÷ 2
÷ M1
154MHz LVCMOS
MEMS
PLL
CLK2
÷ M2
÷ 2
154MHz LVCMOS
FS0/FS1/FS2
OE
O2S0/O2S1
VSS
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 10, 2014
2441
Revision 1.0
tcghelp@micrel.comor (408) 955-1690
Micrel, Inc.
DSC2011FI1-E0012
Ordering Information
Ordering Part Number
DSC2011FI1-E0012
DSC2011FI1-E0012T
Industrial Temperature Range
-40°C to +85°C
Shipping
Tube
Package
14-pin 3.2mm x 2.5mm QFN
14-pin 3.2mm x 2.5mm QFN
-40°C to +85°C
Tape and Reel
Devices are Green and RoHS compliant. Sample material may have only a partial top mark.
Pin Configuration
OE
CLK2
O1S1
O1S0
CLK1
NC
O2S0
GND
14-pin 3.2mm x 2.5mm QFN
Pin Description
Pin Number
Pin Name
OE
Pin Type
Pin Function
Enables outputs when high and disables outputs when low
Leave unconnected or connect to ground
1
2
I
NC
3
O2S0
GND
FS0
I
Least significant bit for drive strength selection for CLK2, see Table 1 for details
Ground
4
PWR
5
I
Least significant bit for frequency selection, see Table 2 for details
Middle bit for frequency selection, see Table 2 for details
Most significant bit for frequency selection, see Table 2 for details
LVCMOS output
6
FS1
I
7
FS2
I
8
CLK1
O1S0
O1S1
CLK2
VDD2
VDD
O2S1
O
9
I
Least significant bit for drive strength selection for CLK1, see Table 1 for details
Most significant bit for drive strength selection for CLK1, see Table 1 for details
LVCMOS output
10
11
12
13
14
I
O
PWR
PWR
I
Power supply for LVCMOS output CLK2
Power supply
Most significant bit for drive strength selection for CLK2, see Table 1 for details
October 10, 2014
2441
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Micrel, Inc.
DSC2011FI1-E0012
Operational Description
The DSC2011FI1-E0012 is a dual output LVCMOS
oscillator consisting of a MEMS resonator and a
supporting PLL IC. The two LVCMOS outputs
are generated through independent 8-bit programmable
CLK1 is equal to the main supply voltage, VDD (pin 13).
VDD2 (pin 12) sets the high voltage level of CLK2.
VDD2 must be equal to or less than VDD at all times to
insure proper operation. VDD2 can be as low as 1.65V.
dividers from the output of the internal PLL. The two
constraints are imposed on the output frequencies:
1) f2 = M x f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 < 1.7GHz.
The actual frequencies output by DSC2011FI1-E0012
are controlled by an internal pre-programmed memory
(OTP). This memory stores all coefficients required by
the PLL for up to eight different frequency combinations.
Three control pins (FS0 - FS2) select the output frequency
combination.
When OE (pin 1) is floated or connected to VDD, the
DSC2011FI1-E0012 is in operational mode. Driving
Enable to ground will tri-state both output drivers
(hi-impedance mode).
DSC2011FI1-E0012 has programmable output drive
strength for each output. Using two control pins (OXS0-
OXS1) for each output, the drive strength can be indepen-
dently adjusted to match circuit board impedances to
reduce spower supply noise, overshoot/undershoot and
EMI. Table 1 displays typical rise / fall times for the
output with a 15pF load capacitance as a function of
these control pins at VDD = 3.3V and room temperature.
DSC2011FI1-E0012 has independent control of the output
voltage levels of the two outputs. The high voltage level of
Output Drive Strength Bits [OXS1, OXS0] - Default is [11]
00
1.6
2.4
01
1.4
2.2
10
1.2
1.5
11
1.1
1.4
tr (ns)
tf (ns)
Table 1. Rise/Fall Times for Drive Strengths
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [111] and the device will output the
associated frequency highlighted in bold.
Freq Select Bits [FS2, FS1, FS0] - Default is [111]
Freq (MHz)
000
001
010
108
108
011
119
119
100
101
110
162
162
111
154
154
CLK1
CLK2
65
71
130.25
130.25
148.5
148.5
65
71
Table 2. Pin-Selectable Output Frequencies
Absolute Maximum Ratings
Item
Min.
-0.3
-0.3
-
Max.
+4.0
Units
V
Condition
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
VDD + 0.3
+150
V
°C
°C
°C
-55
-
+150
+260
40sec max.
ESD
HBM
MM
4000
400
-
V
CDM
1500
1000+ years of data retention on internal memory
October 10, 2014
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tcghelp@micrel.comor (408) 955-1690
Micrel, Inc.
DSC2011FI1-E0012
Specifications (Unless specified otherwise: T = 25°C, max LVCMOS drive strength)
Parameter
Symbol
VDD
Condition
Min.
Typ.
Max.
3.6
Units
V
Supply Voltage¹
Supply Current
2.25
IDD
OE pin low - outputs are disabled
21
32
23
mA
OE pin high - outputs are enabled
CL = 15pF, F01 = F02 = 125MHz
Supply Current²
IDD
F
mA
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
Frequency Stability
±50
ppm
Aging
F
First year (@ 25°C)
T = 25°C
±5
5
ppm
ms
Startup Time³
tSU
Input Logic Levels
Input Logic High
Input Logic Low
VIH
VIL
0.75 x VDD
-
-
0.25 x VDD
V
ns
Output Disable Time4
Output Enable Time
Pull-Up Resistor²
tDA
tEN
5
20
ns
Pull-up exists on all digital IO
40
kOhms
LVCMOS Outputs
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
I = ±6mA
0.9 x VDD
-
-
V
0.1 x VDD
Output Transition Time4
Rise Time
tR
tF
20% to 80%
CL = 15pF
1.1
1.4
2
2
Fall Time
ns
CLK1
CLK2
154
154
Frequency
[FS2, FS1, FS0] = [1, 1, 1]
MHz
Output Duty Cycle
Period Jitter5
SYM
JPER
45
55
2
%
F01 = F02 = 125MHz
3
psRMS
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JPH
psRMS
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
October 10, 2014
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Micrel, Inc.
DSC2011FI1-E0012
Nominal Performance Parameters (Unless specified otherwise: T = 25°C, VDD = 3.3V)
Figure 1. LVCMOS Phase Jitter (integrated phase noise)
LVCMOS Output Waveform
Output
OE
Figure 2. LVCMOS Output Waveform
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
3°C/sec Max.
60 - 180 sec
60 - 150 sec
255 - 260°C
20 - 40 sec
Time within 5°C of actual Peak
Ramp-Down Rate
6°C/sec Max.
8 min Max.
Time 25°C to Peak Temperature
October 10, 2014
2441
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Revision 1.0
tcghelp@micrel.comor (408) 955-1690
Micrel, Inc.
DSC2011FI1-E0012
Solder Reflow Profile
Figure 3. Solder Reflow Profile
Package Information7
3.2mm x 2.5mm 14 Lead Plastic Package
Notes:
6. Connect the exposed die paddle to ground.
7. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data
sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right
to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and
conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty
relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction
of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a)
are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected
to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices
or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2014 Micrel, Incorporated.
October 10, 2014
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