MIC74BQS [MICREL]
2-Wire Serial I/O Expander and Fan Controller Advance Information; 2线串行I / O扩展和风扇控制器超前信息
| 型号： | MIC74BQS |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 2-Wire Serial I/O Expander and Fan Controller Advance Information |
| 文件： | 总20页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC74
2-Wire Serial I/O Expander and Fan Controller
Advance Information
General Description
Features
The MIC74 is a fully programmable serial-to-parallel I/O
expander compatible with the SMBus™ (system manage-
ment bus) protocol. It acts as a “slave” on the bus, providing
eight independent I/O lines.
• Provides eight bits of general purpose I/O
• Built in fan speed control logic (optional)
• 2-wire SMBus™/I C™ compatible serial interface
2
plus interrupt output
• 2.7V to 3.6V operating voltage range
• 5V-tolerant I/O
• Low quiescent current: 2µA (typical)
• Bit-programmable I/O options:
input or output
push-pull or open-drain output
interrupt on input changes
• Outputs can directly drive LEDs (10mA I
• Up to 8 devices per bus
Each I/O bit can be individually programmed as an input or
output. If programmed as an output, each I/O bit can be
programmed as an open-drain or complementary push-pull
output. If desired, the four most significant I/O bits can be
programmed to implement fan speed control. An internal
clock generator and state machine eliminate the overhead
generally associated with “bit-banging” fan speed control.
)
OL
Programming the device and reading/writing the I/O bits is
accomplishedusingseveninternalregisters.Allregisterscan
be read by the host. Output bits are capable of directly driving
high-current loads such as LEDs. A separate interrupt output
can notify the host of state changes on the input bits without
requiringtheMIC74toperformatransactionontheserialbus
or be polled by the host. Three address selection inputs are
provided, allowing up to eight devices to share the same bus
and provide a total of 64 bits of I/O.
Applications
• General purpose I/O expansion via serial bus
• Personal computer system management
• Distributed sensing and control
• Microcontroller I/O expansion
• Fan Control
The MIC74 is available in an ultra-small-footprint 16-lead
QSOP. Low quiescent current, small footprint, and low pack-
age height make the MIC74 ideal for portable and desktop
applications.
Ordering Information
Part Number
Temperature Range
Package
MIC74BQS
–40°C to +85°C
16-lead QSOP
Typical Application
3.0V
3.0V
MIC74
LED1
R1
R2
R3
R4
R5
R6
R7
R8
R9
VDD
/ALERT
DATA
CLK
A0
P0
P1
P2
P3
P4
P5
P6
P7
ALERT
DATA
CLK
A1
A2
GND
LED8
Serial-Bus-Controlled LED Annunciator
2
SMBus™ is a trademark of Intel Corporation. I C™ is a trademark of Phillips Electronics N.V.
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
August 1, 2000
1
MIC74
MIC74
Micrel
Pin Configuration
A0
A1
1
2
3
4
5
6
7
8
16 VDD
15 DATA
A2
14 CLK
P0
13 /ALERT
12 P7 (/FS2)
11 P6 (/FS1)
10 P5 (/FS0)
P1
P2
P3
GND
9 P4 (/SHDN0)
16-Lead QSOP
Pin Description
Pin Number
Pin Name
Pin Function
1–3
A0–A2
Address (Input): Slave address selection inputs; sets the three least signifi-
cant bits of the MIC74’s slave address.
4–7
P0–P3
Parallel I/O (Input/Output): General-purpose I/O pin. Direction and output
type are user programmable.
8
GND
Ground
9–12
P4–P7 (/SHDN, /FS0–/FS2) Parallel I/O (Input/output): P4–P7 are general-purpose I/O pins. Direction
and output type are user programmable.
Shutdown (Output): When the FAN bit is set, pin 9 becomes SHDN.
Fan Speed (Output): When the FAN bit is set, pins 10 through 12 become /
FS0–/FS2 respectively, controlled by the FAN_SPEED register.
13
/ALERT
Interrupt (Output): Active-low, open-drain output signals input-change-
interrupts to the host on this pin. Signal is cleared when the bus master
(host) polls the ARA (alert response address = 0001 100) or reads status.
14
15
CLK
Serial Bus Clock (Input): The host provides the serial bit clock in this input.
DATA
Serial Data (Input/Output): Serial data input and open-drain serial data
output.
16
VDD
Power Supply (Input.)
MIC74
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August 1, 2000
MIC74
Micrel
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Supply Voltage (V ) .................................................+4.6V
Supply Voltage (V ) .................................. +2.7V to +3.6V
DD
DD
Input Voltage [all pins except
Ambient Temperature (T ) ......................... –40°C to +85°C
Package Thermal Resistance ...............................163°C/W
A
V
and GND] (V ) ........................ GND – 0.3V to 5.5V
DD
IN
Junction Temperature (T ) ...................................... +150°C
J
Lead Temperature (10 sec.).................................... +260°C
ESD Rating, Note 3
V
........................................................................................... 1.5kV
DD
A0,A1,A2 .................................................................500V
Others .....................................................................200V
Electrical Characteristics
2.7V ≤ VDD ≤ 3.6V; TA = 25°C, bold values indicate –40°C ≤ TA ≤ +85°C; unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VIN
Input Voltage, any pin except
VDD and GND
GND–0.3
5.5
V
IDD
Operating Supply Current
P[7:0] inputs; P[7:0] = VDD or GND
/ALERT open; fCLK = 100kHz
2
6
µA
ISTART
Fan Startup Supply Current
(Fan Mode Only)
during tSTART; /ALERT, /SHDN,
/FS2[2:0] = open; VSMBCLK = VSMBDATA = VDD
P[3:0] = inputs
1.75
mA
;
ISTBY
Standby Supply Current
/ALERT = open, VSMBCLK = VSMBDATA = VDD
P[3:0] = inputs
;
1
3
µA
Serial I/O (DATA, CLK)
VIL
Input Low Voltage
–0.3
2.0
0.8
5.5
0.4
+1
V
V
VIH
Input High Voltage
Output Low Voltage
Leakage Current
Input Capacitance
VOL
ILEAK
CIN
IOL = 3mA
V
VIN = 5.5V or GND
–1
µA
pF
10
Parallel I/O [P0–P3, P4(/SHDN), P5(/FS0)–P7(/FS2)]
VIL
VIH
IOL
Input Low Voltage
Input High Voltage
Output Low Current
–0.5
2
0.8
5.5
V
V
VOL = 0.4V, VDD = 2.7V
VOL = 1V, VDD = 3.3V
VOH = 2.4V
7
mA
mA
mA
µA
pF
pF
10
7
IOH
Output High Current
Leakage Current
ILEAK
CIN
VIN = 5.5V or GND
–1
+1
Input Capacitance
Output Capacitance
10
10
COUT
Address Input (A0–A2)
VIL
Input Low Voltage
–0.3
0.7VDD
–250
0.3VDD
V
V
VIH
Input High Voltage
Leakage Current
V
+0.3
DD
ILEAK
VIN = VDD or GND
+250
nA
August 1, 2000
3
MIC74
MIC74
Micrel
Symbol
/ALERT
VOL
Parameter
Condition
Min
Typ
Max
Units
Output Low Voltage
Leakage Current
IOL = 1mA
0.4
V
ILEAK
VIN = VDD or VSS
–1
250
1
+1
µA
AC Characteristics
tSTART Fan Startup Interval
tPULSE
normal operation
0.5
10
3.3
sec
ns
Minimum Pulse-Width
Interrupt Delay
minimum pulse-width on Pn to
generate an interrupt, Note 7
t/INT
interrupt delay from state change
on Pn to /ALERT ≤ VOL, Note 7
4
4
µs
µs
µs
t/IR
Delay from Status Read or ARA
Response to /ALERT ≥ VOH
tHD:STA
Hold Time, Note 7
hold time after repeated start condition.
after this period, the first clock is generated.
4.0
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
Setup Time, Note 7
Stop Condition Setup Time
Data Hold Time
repeated start condition setup time
4.7
4.0
500
0
µs
µs
ns
ns
ms
µs
µs
ns
ns
µs
Note 7
Note 7
Data Setup Time
Note 7
Clock Low Time-Out
Clock Low Period
Notes 4, 7
Notes 5, 7
Notes 5, 7
Notes 6, 7
Notes 6, 7
Note 7
25
35
4.7
4.0
tHIGH
tF
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
50
300
tR
1000
tBUF
Bus free time between stop and
Start condition
4.7
Note 1. Exceeding the absolute maximum rating may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.
Note 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
Note 4. Devices participating in a transfer will timeout when any clock low exceeds the value of t of 25ms. Devices that have detected a
TIMEOUT(min)
timeout condition must reset the communication no later than t
of 35ms. The maximum value specified must be adhered to by
TIMEOUT(max)
both a master and a slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
t provides a simple guaranteed method for devices to detect bus idle conditions.
HIGH(max)
Note 5.
Note 6. Rise and fall time is defined as follows: t = V
– 0.15V to V
+ 0.15V; t = 0.9V to V
– 0.15V.
R
IL(max)
IH(min)
F
DD
IL(max)
Note 7. Guaranteed by design.
Timing Definitions
tR
tF
CLK
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:STO
tHD:STA
tSU:DAT
tBUF
tHD:DAT
DATA
StoP Start
Start
StoP
MIC74
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August 1, 2000
MIC74
Micrel
Register Descriptions
Device Configuration Register
DEV_CFG
Output Configuration Register
OUT_CFG
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Always write as zero.
FAN
IE
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
Power-On Default Value: 0000 0000 , 00
Power-On Default Value: 0000 0000 , 00
b
h
h
b
h
h
Interrupts disabled
Not in Fan Mode
all outputs open-drain
Command_byte addess: 0000 0010 , 02
b
Command_byte addess: 0000 0000 , 00
Type:
8-bits, read/write
b
Type:
8-bits, read/write
Bit Name: OUTn
Bit Name: IE
Function: Selects output driver configuration of Pn when
Pn is configured as an output.
Function: Global interrupt enable.
Operation: 1 = enabled
0 = disabled
Operation: 1 = push-pull
0 = open-drain
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain
Bit Name: FAN
Function: Selects Fan Mode
(P[7:4] vs. /FS[2:0], /SHDN)
outputs. They are then referred to as /FS[2:0]
and /SHDN. The OUT_CFG register has no
effect on these I/O bits while in Fan Mode.
Operation: 1 = Fan Mode
0 = I/O Mode
Bit Name: D[2] through D[6]
Function: Reserved
Operation: Reserved—always write as zero
Data Direction Register
DIR
Status Register
STATUS
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[7]
D[6]
D[5]
D[4]
S4
D[3]
D[2]
D[1]
D[0]
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
S7
S6
S5
S3
S2
S1
S0
Power-On Default Value: 0000 0000 , 00
Power-On Default Value: 0000 0000 , 00
b
h
h
b
h
h
all Pn’s configured as inputs
no interrupts pending
Command_byte addess: 0000 0001 , 01
Command_byte addess: 0000 0011 , 03
b
b
Type:
8-bits, read/write
Type:
8-bits, read only
Bit Name: DIRn
Bit Name: Sn
Function: Selects data direction, input or output, of Pn
Function: Flag for Pn input-change event when Pn is
configured as an input; Sn is set when the
corresponding input changes state.
Operation: 1 = output
0 = input
Operation: 1 = change occured
0 = no change occured
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain
outputs. They are then referred to as /FS[2:0]
and /SHDN. The DIR register has no effect on
these I/O bits while in Fan Mode.
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain
outputs. They are then referred to as /FS[2:0]
and /SHDN. No interrupts of any kind are
generated by these pins while in Fan Mode.
All status bits are cleared after any read
operation is performed on STATUS.
August 1, 2000
5
MIC74
MIC74
Micrel
Interrupt Mask Register
Fan Speed Register
INT_MASK
FAN_SPEED
D[4] D[3]
Always write as zero.
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[7]
D[6]
D[5]
D[2]
D[1]
D[0]
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
Fan Speed
Power-On Default Value: 0000 0000 , 00
Power-On Default Value: 0000 0000 , 00
b
h
h
b
h
h
fan off
Command_byte addess: 0000 0100 , 04
b
Command_byte addess: 0000 0110 , 06
Type:
8-bits, read/write
b
Type:
8-bits, read/write
Bit Name: IMn
Bit Name: D[0] through D[2]
Function: Interrupt enable bit for Pn when Pn is config-
ured as an input
Function: Determines bit-pattern on FS[2:0]
Operation:
Operation: 1 = enabled
0 = disabled
Output State
D[2:0]
Value
Fan Speed
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain
/FS[2:0]
/SHDN
000
001
010
011
100
101
110
111
111
110
101
100
011
010
001
000
0
1
1
1
1
1
1
1
off
speed 1 (slowest)
speed 2
outputs. They are then referred to as /FS[2:0]
and /SHDN. No interrupts of any kind are
generated by these pins while in Fan Mode.
speed 3
speed 4
speed 5
speed 6
speed 7 (fastest)
Data Register
Fan Speed Settings
DATA
Notes:
Any time the fan speed register contains zero,
that is, the fan is shut down, and a non-zero
value is written into the fan speed register, the
/FS[2:0] and /SHDN outputs will assume the
highest fan speed state for approximately one
D[7]
D[6]
D[5]
D[4]
P4
D[3]
D[2]
D[1]
D[0]
P7
P6
P5
P3
P2
P1
P0
Power-On Default Value: 1111 1111 , FF
b
h
Command_byte addess: 0000 0101 , 05
b
h
second (t
). Following this interval, the
START
Type:
8-bits, read/write
state of the fan speed control outputs will
assume the value indicated by the contents of
FAN_SPEED. This insures that the fan will
start reliably when low speed operation is
desired.
Bit Name: Pn
Function: Returns the current state of any Pn configured
as an input and the last value written to Pn’s
configured as outputs; Writing the DATA
register sets the output state of any Pn’s
configured as outputs; writes to I/O bits
configured as inputs are ignored.
Bit Name: D[3] through D[7]
Function: Reserved
Operation: Always write as zero.
Read Operation: 1 = Pn is high
0 = Pn is low
Write Operation: 1 = Pn is set to one
0 = Pn is cleared
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain
outputs. They are then referred to as /FS[2:0]
and /SHDN. The state of these pins is deter-
mined by the FAN_SPEED register. While in
Fan Mode, D[7:4] of the DATA registers have
no effect.
MIC74
6
August 1, 2000
MIC74
Micrel
Functional Diagram
INTn
IMn
EDGE
DETECT
STATUSn
Q
Q
S
R
STATUS_READn
VDD
DATAn
(INPUT)
OUT_CFGn
Pn (typical I/O port)
DIRn
DATAn
(OUTPUT)
GND
Typical I/O Port (Fan Speed Control Logic Not Shown)
Functional Description
Pin Descriptions
Inputs
MIC74 Slave Address
Binary Hex
A2
0
A1
0
A0
0
010 0000b
010 0001b
010 0010b
010 0011b
010 0100b
010 0101b
010 0110b
010 0111b
20h
21h
22h
23h
24h
25h
26h
27h
VDD
0
0
1
Power supply input connection. See “Operating Ratings.”
0
1
0
GND
0
1
1
Ground or return connection for all MIC74 functions.
1
0
0
CLK
1
0
1
An CLK signal is provided by the host (master) and is
common to all devices on the bus. The CLK signal controls all
transactions in both directions on the bus and is applied to
each MIC74 at the CLK pin.
1
1
0
1
1
1
Table 1. MIC74 Address Configuration
Alert Response Address
DATA
Serialdataisbidirectionalandiscommontoalldevicesonthe
bus. The MIC74’s DATA output is open-drain.
The MIC74 also responds to the ARA (Alert Response
Address).TheARAisusedbythemaster(host)torequestthe
addressofaslavethathasprovidedaninterrupttothemaster
via the /ALERT line.
The DATA line requires one external pull-up resistor or
current source per system that can be located anywhere
along the line.
TheARAisasingleaddress(0001100)commontoallslaves
and is described in more detail under “Interrupt Generation”
with related information under “/ALERT.” Also see Figure 7.
A2, A1, A0
An MIC74 responds to its own unique address which is
assigned using the A0–A2 pins. A0–A2 set the three LSBs
(least significant bits) of the MIC74’s 7-bit slave address. The
three address pins allow eight unique MIC74 addresses in a
system. When the MIC74’s address matches an address
received in the serial bit stream, communication is initiated.
Pn, /SHDN, and /FS0–/FS2
P0throughP7aregeneral-purposeinput/outputbits.Eachbit
is independently programmable as an input or an output. If
programmed as an output, each bit is further programmable
as either a complementary push-pull or open-drain output.
A2, A1andA0shouldbeconnectedtoGNDorV . Thestate
DD
of these pins is sampled only once at device power-on. New
slave addresses are not accepted unless the MIC74 is
powered off then on.
If properly enabled, any Pn programmed as an input will
generate an interrupt to the host using the /ALERT output
when the input changes state. In this way, the MIC74 can
August 1, 2000
7
MIC74
MIC74
Micrel
notify the host of an input change without requiring periodic
polling by the host or a message transaction on the bus.
the MIC74, the command byte is the address of the target
register. See Table 2.
Regardless of whether interrupts are enabled or disabled,
each input-change event also sets the corresponding bit in
the status register. I/O configuration is performed using the
output configuration (OUT_CFG), I/O direction (DIR), and
interrupt mask (INT_MASK) registers.
In addition, to the read byte and write byte protocols, the
MIC74 adheres to the SMBus protocol for response to the
ARA (alert response address). An MIC74 expects to be
interrogated using the ARA when it has asserted its /ALERT
output. /ALERT interrupts can be enabled or disabled using
the IE bit in the DEV_CFG register.
If the FAN bit in the device configuration register is set, the
states of P[7:4] are controlled by the FAN_SPEED register.
The bits in the OUT_CFG, DIR, and INT_MASK registers
corresponding to P[7:4] are ignored. When in Fan Mode,
P[7:4] are referred to as /FS2, /FS1, /FS0, and /SHDN. While
in this mode, no interrupts of any kind will be generated by
these pins.
Power-On
When power is initially applied, the MIC74’s internal registers
will assume their power-up default state and the state of the
address inputs, A2, A1 and A0, will be read to establish the
device’s slave address. See the individual register descrip-
tions for each registers default state. Also see Table 2.
/ALERT
I/O Ports
The alert signal is an open-drain, active-low output. The
operation of the /ALERT output is controlled by the IMn bits
in the INT_MASK register and the global interrupt enable bit
(IE) in the DEV_CFG register.
EachI/Obit, P0throughP7, maybeindividuallyprogrammed
as an input or output using the corresponding bit in the I/O
direction register, DIR.
Ifprogrammedasanoutput,eachisfurtherprogrammableas
either a complementary push-pull or open-drain output using
the output configuration register, OUT_CFG.
If the IE bit is set to zero, or if the corresponding interrupt
enable bit, IMn, is set to zero, no input-change interrupts will
be generated. (Regardless of the IE bit setting, the change
will be reflected in the status register.)
If enabled by the corresponding bit, IMn, in the interrupt mask
register INT_MASK, each Pn programmed as an input will
generate an interrupt to the host on /ALERT if the input
changes state. In this way, the MIC74 can notify the host of
an input change without requiring periodic polling by the host
or a transaction on the bus.
If the IE bit is set to one, IMn is set to one, and Pn is an input,
then /ALERT is driven active whenever Pn changes state,
(goesfromahigh-to-loworlow-to-highstate).Oncetriggered,
/ALERT is unconditionaly reset to its inactive state once the
MIC74 successfully responds to the alert response address
or STATUS is read.
Each input-change event also sets the corresponding bit in
the status register, STATUS.
Serial Port Operation
See “Functional Diagram” for the logic arrangement of a
typical MIC74 I/O port.
TheMIC74usesstandardSMBusRead_ByteandWrite_Byte
operations to communicate with its host.
Fan Speed Control
The Read_Byte operation is a composite read-write opera-
tion consisting of first sending the MIC74’s slave address
followed by a command byte (a write) and then resending the
slave address and clocking out the data byte (a read). The
commandbyteistheaddressofthetargetregister.SeeTable
2. An example of a Read_Byte operation is shown in Figure
8.
If the FAN bit in the device configuration register is set, the
state of P[7:4] is controlled by the FAN_SPEED register. The
bits in the OUT_CFG, DIR, and INT_MASK registers corre-
sponding to P[7:4] are ignored. When in Fan Control Mode,
P[7:4] are referred to as /FS2, /FS1, /FS0, and /SHDN. While
in this mode, no interrupts of any kind will be generated by
these pins. See “Applications Information” for typical fan
speed control applications.
Similarly, the write-byte operation consists of sending the
device’s slave address followed by a command byte and the
byte to be written to the target register. Again, in the case of
Address
Binary
Power-On Default
Register
Name
Register
Description
Available
Operations
Hex
Binary
Hex
DEV_CONFIG
DIR
Device Configuration
I/O Direction
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
00
8-bit read/write
8-bit read/write
8-bit read/write
8-bit read
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
00
b
b
b
b
b
b
b
h
b
b
b
b
b
b
b
h
01
00
h
h
OUT_CFG
STATUS
Output Configuration
Interrupt Status
Interrupt Mask
02
00
h
h
03
00
h
h
INT_MASK
DATA
04
8-bit read/write
8-bit read/write
8-bit read/write
00
h
h
General-Purpose I/O
Fan Speed
05
FF
h
h
FAN_SPEED
06
00
h
h
Table 2. Register Summary
MIC74
8
August 1, 2000
MIC74
Micrel
, the
Fan Start-Up
state first, then, after a delay equal to one-half of t
START
/SHDN pin is deasserted. Conversely, when the fan is shut
down (zero is written to FAN_SPEED), the /SHDN pin is de-
assertedfirst.The/FS[2:0]linesaresubsequentlydeasserted
Any time the fan speed register contains zero (fan is off) and
then a nonzero value is written to FAN_SPEED, the /FS[2:0]
and /SHDN outputs will assume the highest fan speed state
1
after a delay of ⁄2 t
. The internal oscillator is also
for approximately one second (t
). Following this inter-
START
START
powered down following the t
down. These timing relationships are illustrated in Figure 2.
/2 interval at fan shut-
val, the state of the fan speed control outputs will assume the
valueindicatedbythecontentsofFAN_SPEED. Thisinsures
that the fan will start reliably when low speed operation is
START
Interrupt Generation
desired. The t
oscillator and counters. At the end of t
powered down to reduce overall power consumption.
interval is generated by an internal
Assuming that any or all of the I/O’s are configured as inputs,
theMIC74willreflecttheoccurrenceofaninputchangeinthe
corresponding bit in the status register, STATUS. This action
cannot be masked. An input change will only generate an
interrupt to the host if interrupts are properly configured and
enabled.
START
, this oscillator is
START
Regulator
VIN VOUT
/SHDN FB
RFB
FAN
RPULL-UP
GND
The MIC74 can operate in either polled mode or interrupt
mode. In the case of polled operation, the host periodically
reads the contents of STATUS to determine the device state.
The act of reading STATUS clears its contents. Repeating
eventswhichhaveoccurredsincethelastreadfromSTATUS
will not be discernable to the host.
/SHDN
RF2
RF2
RF2
/FS2
/FS1
/FS0
Interrupts are only generated if the global interrupt enable bit,
IE, in the DEV_CFG register is set. The /ALERT signal will be
asserted (driven low) when an interrupt is generated. The
MIC74 expects to be interrogated using the ARA when it has
generated an interrupt output. Once it has successfully
respondedtotheARA(AlertResponseAddress),the/ALERT
output will be deasserted. The contents of the status register
will not be cleared until it is read using a read byte operation.
If a given system does not wish to use the SMBus ARA
protocol for reporting interrupts, the system may simply poll
the contents of the status register after detecting an interrupt
on/ALERT.ThisactionwillclearthecontentsofSTATUSand
cause /ALERT to be deasserted. Reading the status register
is an acceptable substitute for using the ARA protocol.
Presumably, however, it will involve higher system overhead
since all the devices on the bus must be polled to determine
which one generated the interrupt.
RMIN_SPEED
MIC74
Figure 1. Fan Speed Control Application
Proper sequencing of the /FS[2:0] and /SHDN signals is
performedbytheMIC74’sinternallogicstatemachine. When
activating the fan from the off state, the /FS[2:0] lines change
Fan Supply
Output
Fan
Rotation
Speed*
Voltage*
shutdown
shutdown
00h
* FAN SUPPLY OUTPUT VOLTAGE AND
SPEED ARE NOT TO SCALE.
Value written to
FAN_SPEED (00h)
01h
tSTART
01h
02h
07h
05h
/FS2
/FS1
tSTART/2
/FS0
tSTART/2
/SHDN
Figure 2. Typical MIC74 Fan-Mode Timing and System Behavior
August 1, 2000
9
MIC74
MIC74
Micrel
Applications Information
Bit Transfer
DATA
CLK
The data received on the DATA pin must be stable during the
high period of the clock.
Start
StoP
DATA
Figure 4. Start and Stop Definitions
Data Stable,
Start (S) and stop (P) conditions are always generated by the
bus master (host). After a start condition, the bus is consid-
ered to be busy. The bus becomes free again after a certain
time following a stop condition or after both CLK and DATA
lines remain high for more than 50µs.
Data Valid
CLK
Data Change Allowed
Figure 3. Acceptable Bit Transfer Conditions
Data can change state only when the CLK line is low. Refer
to Figure 3.
Serial Byte Format
Everybyteconsistsof8bits. Eachbytetransferredonthebus
must be followed by an acknowledge bit. Bytes are trans-
ferred with the MSB (most significant bit) first. See
Figure 5.
Start and Stop Conditions
Two unique bus situations define “start” and “stop” condi-
tions. A high-to-low transition of the DATA line while CLK is
high indicates a start condition. A low-to-high transition of the
DATA line while CLK is high defines a stop condition. See
Figure 4.
MSB
LSB
DATA
CLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
ACK
ACK
Start
Byte Complete
StoP
Figure 5. Serial Byte Format
MSB
LSB
Acknowledge and Not Acknowlege
DATA
(Host)
The acknowledge related clock pulse is generated by the
master. The transmitter releases the DATA line (high) during
the acknowledge clock cycle.
NAK (high)
DATA
In order to acknowledge (ACK) a byte, the receiver must pull
the DATA line low during the high period of the clock pulse
according the bus timing specifications. A slave device that
wishes to not acknowledge a byte must let the DATA line
remain high during the acknowledge clock pulse. See Fig-
ure 6.
(Slave MIC74)
1
2
3
4
5
6
7
8
9
ACK (low)
CLK
ACK
Figure 6. Acknowledge and Not Acknowledge
MIC74
10
August 1, 2000
MIC74
Micrel
Master-to-slave transmission
Slave-to-master response
R/W = READ
NOT ACKNOWLEDGE
ACKNOWLEDGE
STOP
S
0
0
0
1
1
0
0
1
A
0
1
0
0 A
2
A1
A0
0 /A P
Alert Response Address
(master requests address
of interupting device)
Slave Address
(interrupting MIC74
announces its address)
P0*
t/INT
t/IR
/ALERT
*Assumes P0 interrupts properly configured and
enabled. P0 used as an example. Timing for P1
to P7 is identical.
Figure 7. Interrupt Handling Using the Alert Response Address
Master-to-slave transmission
Slave-to-master response
R/W = WRITE
R/W = READ
NOT ACKNOWLEDGE
ACKNOWLEDGE
ACKNOWLEDGE
ACKNOWLEDGE
STOP
S
0
0
0
1 A
2
A1
A0
0
A
0
0
0
0
0
0
1
1
A
S
0
0
0
1 A
2
A1
A0
1 A X X X X X X X X /A P
Slave Address
Command Byte
Slave Address
(host addresses an MIC74)
Status Value†
(MIC74 sends status)
(host addresses an MIC74) (03h = selects status register)
P0*
t/INT
t/R
/ALERT
*Assumes P0 interrupts properly configured and
enabled. P0 used as an example. Timing for P1
to P7 is identical.
† STATUS register is cleared to zero following this
operation.
Figure 8. Interrupt Handling Without the Alert Response Address
August 1, 2000
11
MIC74
MIC74
Micrel
Initializing the MIC74
1. Write DATA
The MIC74’s internal registers are reset to their default state
at power-on. The MIC74’s default state can be summarized
as follows:
2. Write OUT_CFG
3. Write DIR
4. Write FAN_SPEED (if using fan mode)
5. Write INT_MASK (if using interrupts)
6. Read STATUS to clear it.
• All I/O’s configured as inputs (DIR = 00 )
h
• Output configuration set to open-drain
(OUT_CFG = 00 )
h
7. Write DEV_CFG to enable fan mode and/or
interrupts, if using
• All outputs high/floating (DATA = FF )
h
• Fan functions disabled (FAN_SPEED = 00 ,
h
At the conclusion of step three, any I/O’s configured as
outputs in step two will be driven to the levels programmed
into the data register in step one. The order of step 1 through
step 3 is important to insure that spurious data does not
appear at the I/O’s during configuration. Following step 7,
programming the device configuration register, the MIC74
will begin generating interrupts if they are enabled, and the
fan will be started if FAN_SPEED contains a nonzero value.
The corresponding interrupt service routines (if any) must be
initialized and enabled prior to step seven. STATUS should
be cleared (step 6) in both polled and interrupt driven sys-
tems.
FAN bit of DEV_CFG = 0)
• All interrupts masked (IE bit of DEV_CFG = 0)
The result of this configuration is that all I/O pins will essen-
tially float unless driven by external circuitry. Any system
using the MIC74 will need to initialize the internal registers to
the state required for proper system operation. The recom-
mended order for initializing the MIC74’s registers is as
follows:
Initialize for
interrupts
Write desired ouput
values to DATA
Initialize for
polling
Set output configuration
in OUT_CFG
Write desired output
values to DATA
Set desired I/O's as
outputs by writing DIR
Set output configuration
in OUT_CFG
Set initial fan speed in
FAN_SPEED (if using)
Set desired I/O's as
outputs by writing DIR
Write INT_MASK to
enable interrupts
(if using)
Set initial fan speed in
FAN_SPEED (if using)
Read STATUS to
Write DEV_CFG to
turn on fan (if using)
clear it
Write DEV_CFG to
turn on interrupts
and fan (if using)
Read STATUS
to clear it
Initialization
complete
Initialization
complete
Figure 9a. Initializing the MIC74 for Polled Operation
Figure9b. Initializing the MIC74 for Interrupts
MIC74
12
August 1, 2000
MIC74
Micrel
Polled Mode
Interrupt Mode
Input state changes on I/O’s configured as inputs will be
reflected in the status register regardless of the state of the
global interrupt enable bit (IE) and the individual interrupt
mask bits in INT_MASK. In a system utilizing polling to
monitor for input changes, the status register is periodically
read to check for input events. The act of reading STATUS
clears it in preparation for detecting future events. The status
bits corresponding to I/O’s configured as outputs or corre-
sponding to P[7:4] when in fan mode will not be set by state
changes on these pins. It is always good practice, however,
to mask the value obtained when reading STATUS to elimi-
nate any bits, output or otherwise, that are not of immediate
concern. This will help avoid problems if software changes
are made in the future.
Input state changes on I/Os configured as inputs will be
reflected in the status register regardless of the state of the
global interrupt enable bit (IE) and the individual interrupt
mask bits in INT_MASK. In a system utilizing interrupts to
detect input changes, one or more of the bits in the interrupt
mask register, INT_MASK, are set to allow interrupts on
/ALERT to be generated by input events. The global interrupt
enable bit, IE, in the device configuration register must also
be set to enable interrupts.
The flowchart shown in Figure 9b illustrates the steps in-
volved in initializing the MIC74 for interrupt-driven operation.
TheflowchartinFigure 11illustratesthecorrespondinginter-
rupt service routine using the SMBus ARA (alert response
address). The corresponding timing diagram is shown in
Figure 7. The flowchart in Figure 12 illustrates the corre-
sponding interrupt service routine using polling to determine
the interrupt source. Figure 8 illustrates the timing. Utilizing
theARAgreatlyspeedsidentificationoftheinterruptingslave
device and lowers latency, as only a single transaction on the
bus is necessary to identify the interrupt source.
The flowchart shown in Figure 9a illustrates the steps in-
volved in initializing the MIC74 for polled operation. The
flowchart in Figure 10 illustrates the corresponding polling
routine. The process for writing output data is straightfor-
ward—simply write the desired bit pattern to DATA. (Special
precautions may be required when changing output data in
an interrupt driven system, however. See the discussion
below under “Writing to the Data Register.”)
Using either method, STATUS must be read to determine the
exact source of the interrupt within the MIC74. The act of
Polling the
MIC74
Read
STATUS
Is
STATUS
≠ 00h
?
No
Yes
Is
Sn set
?
Yes
Service function n
Service function m
Service function x
No
Is
Sm set
?
Yes
Yes
No
Is
Sx set
?
No
Figure 10: Polling the MIC74
August 1, 2000
13
MIC74
MIC74
Micrel
reading STATUS clears it in preparation for detecting future
events. The status bits corresponding to I/O’s configured as
outputs or corresponding to P[7:4] when in fan mode will not
be set by state changes on these pins. It is always good
practice, however, for the interrupt service routine to mask
the value obtained when reading STATUS to eliminate any
bits, output or otherwise, that are not of immediate concern.
This will help avoid problems if software changes are made
in the future.
Writing To The Data Register
Multiple software routines may use the various output bits
available on the MIC74 to control individual functions such as
power switches, LED’s, etc. These various functions may be
handled by independent software routines which must ma-
nipulate individual output bits without regard for other bits.
Care must be taken to insure that these various software
routines do not interfere with each other when modifying
output data. The recommended procedure for changing
isolated output bits is as follows:
The process for writing output data is straightforward—
simply write the desired bit pattern to DATA. Special precau-
tions may be required, however, when changing output data
inaninterruptdrivensystem.Seethediscussionbelowunder
“Writing to the Data Register.”
1. Read DATA
2. Set desired bits by ORing the value read from
DATA with an appropriate mask value
3. Clear desired bits by ANDing the value read
from DATA with an appropriate mask value
4. Write the result back to DATA
A functionally equivalent alternative to this procedure is to
keep an image of the data register in software. Any indepen-
dent routines would make changes to this image using the
procedure above and then call a routine that actually writes
Interrupt Service
Routine
Read alert
response address
Is
No
interrupt
Service other devices
from
MIC74
Yes
Polled
I.S.R.
Read STATUS to
determine source
Read
STATUS
Is
STATUS
≠ 00h
?
Is
Sn set
?
Yes
Yes
Yes
No
Service function n
Service function m
Service function x
Service other devices
Service function n
No
Yes
Is
Sn set
?
Yes
Is
Sm set
?
No
No
Is
Sm set
?
Yes
Yes
Service function m
Is
Sx set
?
No
No
Yes
Is
Sx set
?
Interrupts
pending
?
Service function x
No
No
Return from ISR
Return from ISR
Figure 11: Interrupt Service Routine Using the ARA
Figure 12: Interrupt Service Routine Without ARA
MIC74
14
August 1, 2000
MIC74
Micrel
the new image to DATA. Interrupts would be disabled briefly
while DATA is being modified.
lowers the equivalent resistance seen in the regulator’s
feedback path, thus changing the output voltage.
Regardless of which procedure is used, it is important that
onlyonesoftwareroutineatatimeattemptstomakechanges
to the output data. In a system where polling is the exclusive
method for servicing inputs, this is usually not a problem. If
interrupts are employed to any degree in dealing with MIC74
inputs, care must be taken to insure that a software routine in
the midst of making changes to outputs is not interrupted by
another routine that proceeds to make its own changes. The
risk is that the value in DATA will be changed by an interrupt-
ing routine after it is read by a different routine in the process
of making its own changes. If this occurs, the value written to
DATA by the first routine may be incorrect. The most straight-
forward solution to this potential problem is to disable system
interrupts while the data register is actually being modified.
Any conventional adjustable regulator is usually suitable for
use with the MIC74. The output voltage corresponding to
each value to be programmed into the fan speed register can
be determined by selecting the resistors in the circuit. The
regulator itself can be chosen to meet the needs of the
application, such as input voltage, output voltage, current
handling capability, maximum power dissipation, and physi-
cal space constraints. Two circuit examples are shown be-
low.
The circuit of Figure 13 illustrates use of a typical LDO linear
regulator such as the MIC29152. A switching regulator-
based fan control circuit using the MIC4574 200kHz Simple
0.5A Buck Regulator is shown in Figure 14. Both circuits
assume a 12V fan power supply but will accommodate much
higher input voltages if required (MIC4574: 24V, MIC29152:
26V). Care must be taken, however, to insure that the
maximum power dissipation of the regulator is not exceeded.
If the regulator overheats, its internal thermal shutdown
circuitry will deactivate it. (See MIC29152 or MIC4574
datasheet.)
Application Circuits
The MIC74, in conjunction with a linear low-dropout or
switchingregulator,canbeconfiguredasafanspeedcontrol-
ler. Most adjustable regulators have a feedback pin and use
an external resistor divider to adjust the output voltage. The
MIC74 is designed to take advantage of this configuration
with its ability to manipulate multiple feedback resistors
connected to the P4–P7 outputs. Individual open-drain out-
put bits are selectively grounded or allowed to float under the
control of the internal state machine. This action raises or
Since the MIC74 powers up with all its I/O’s inputs (floating),
both circuits will power-up with the fan running at a minimum
speed determined by the value of R
MIC74’s fan mode is activated by setting the appropriate bit
. Once the
MIN_SPEED
MIC29152
+12V
C1
10µF
IN
OUT
FB
FAN
RFB
3k
C3
220µF
EN
+3.3V
A-Speed
HP2A-B3
or similar
RPU
100k
GND
MIC74
VDD
/SHDN
/FS2
RF2
1k
SMBCLK
RF1
1.8k
SMBus
Host
SMBDATA
/FS1
RF0
SMBALERT /FS0
3.5k
C4
0.1µF
A2
P3
P2
P1
P0
RMIN_SPEED
1k
A1
A0
GND
Figure 13. Fan Speed Control Using an Adjustable Low-Dropout Regulator
+3.3V +12V
RPU
200k
MIC4574
L1 100µH
2N3906
IN
SW
FB
Q1
C2
3300pF
C3
220µF
RBASE
150k
SHDN
RFB
3k
FAN
C1
10µF
A-Speed
HP2A-B3
or similar
SGND PGND
100k
+3.3V
MIC74
D1
VDD
/SHDN
/FS2
RF2
SMBCLK
RF1
1k
RF0
SMBus
Host
SMBDATA
/FS1
1.8k
SMBALERT /FS0
3.5k
C4
0.1µF
A2
P3
P2
P1
P0
RMIN_SPEED
1k
A1
A0
GND
Figure 14. Fan Speed Control Using a Buck Converter
August 1, 2000
15
MIC74
MIC74
Micrel
in the configuration register, the fan will be shutdown by the
assertion of the /SHDN output if FAN_SPEED is zero. If
FAN_SPEEDisprogrammedwithanynonzerovalue, thefan
The following equations show how to calculate the resistor
values for the fan controllers. For example, when the fan
speed register contains 011 , which is the 3rd lowest speed,
b
will be driven to its maximum speed for the duration of t
R
and R are parallel to R
to give the equivalence
START
F1
F0
MIN
(about 1 second) and then assume the programmed speed.
Note that the circuit in Figure 14 contains an additional
transistor, Q1, as an inverter because the regulator in this
example has an active-high shutdown input rather than an
enable input. Otherwise the circuits function identically.
resistor (R ) value of 545Ω.
EQ
R
R
R
= R ||R ||R
F1 F0 MIN
EQ
EQ
EQ
= 1.8k ||3.6k ||1k
= 545Ω
Table 3 lists the output voltages corresponding to all the fan
speeds and system states possible with these circuits. The
following equations are used to calculate the resistor values
used in MIC74 fan speed control circuits. It is assumed here
that the regulator’s internal reference voltage is 1.24V. If the
regulatorusesadifferentreferencevoltage,thatvalueshould
be used instead.
The output voltage is calculated by using:
R
R
FB
V
= 1.24V 1+
OUT
EQ
3k
545Ω
V
= 1.24V 1+
OUT
V
= 8.06V
OUT
FAN_SPEED Fan Speed
R
R
R
R
R
R
V
OUT
FB
MIN
F2
F1
F0
EQ
Value
Selected
power-up
fan off
0000 0000
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
3k
3k
3k
3k
3k
3k
3k
3k
3k
1k
open
open
open
open
open
1k
open
open
open
1.8k
open
open
3.6k
1k
4.96V
0V
b
b
b
b
b
b
b
b
b
1k
1k
1k
1k
1k
1k
1k
1k
1k
lowest
783
643
545
500
439
391
353
5.99V
7.03V
8.06V
8.68V
9.71V
10.75V
11.78V
2nd lowest
3rd lowest
medium
open
3.6k
1.8k
open
open
1.8k
open
3.6k
3rd highest
2nd highest
highest
1k
1k
open
3.6k
1k
1.8k
Table 3. Fan Speed Selection
MIC74
16
August 1, 2000
MIC74
Micrel
Package Information
PIN 1
DIMENSIONS:
INCHES (MM)
0.157 (3.99)
0.150 (3.81)
0.009 (0.2286)
REF
0.012 (0.30)
0.008 (0.20)
0.025 (0.635)
BSC
45°
0.0098 (0.249)
0.0075 (0.190)
0.0098 (0.249)
0.0040 (0.102)
8°
0°
0.196 (4.98)
0.189 (4.80)
0.050 (1.27)
0.016 (0.40)
SEATING 0.0688 (1.748)
PLANE
0.0532 (1.351)
0.2284 (5.801)
0.2240 (5.690)
16-Pin QSOP (QS)
August 1, 2000
17
MIC74
MIC74
Micrel
MIC74
18
August 1, 2000
MIC74
Micrel
August 1, 2000
19
MIC74
MIC74
Micrel
MICREL INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
MIC74
20
August 1, 2000
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