MICRF219AYQSTR [MICREL]
SPECIALTY CONSUMER CIRCUIT, PDSO16, 4.90 X 6 MM, QSOP-16;
| 型号： | MICRF219AYQSTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16, 4.90 X 6 MM, QSOP-16 光电二极管 商用集成电路 |
| 文件： | 总23页 (文件大小：886K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MICRF219
300MHz to 450MHz ASK Receiver with
RSSI, Auto-Poll, Bit-Check and Squelch
NOT RECOMMENDED
REFER TO MICRF219A FOR NEW DESIGNS
General Description
Features
The MICRF219 is a 300MHz to 450MHz super-
heterodyne, image-reject, RF receiver with Automatic
Gain Control, OOK/ASK demodulator and analog RSSI
output. The device integrates Auto-Poll, Valid Bit-Check,
Squelch, and Desense features. It only requires a
crystal and a minimum number of external components
to implement. It is ideal for low-cost, low-power, RKE,
TPMS, and remote actuation applications.
• –110dBm sensitivity at 1kbps with 1% BER
• Supports data rates up to 10kbps at 433.92MHz
• 25dB Image-Reject Mixer
• No IF Filter Required
• 60dB Analog RSSI Output
• 3.0V to 3.6V Supply Voltage Range
• 4.0mA supply current at 315MHz (continuous receive)
• 6.0mA supply current at 434MHz (continuous receive)
• 0.5uA supply current in Shutdown Mode
• Optional Auto-Polling (sleep mode, current < 0.1mA)
• Optional Valid Bit-Check in Auto-Poll Mode
• Optional Programmable 6dB to 42dB Desense
• Optional Data Output Squelch until valid bits detected
• 16-pin QSOP Package (4.9mm x 6.0mm)
• −40°C to +105°C Temperature Range
• 2kV HBM ESD Rating
The MICRF219 achieves −110dBm sensitivity at a data
rate of 1kbps (Manchester encoded). Four demodulator
filter bandwidths are selectable in binary steps from
1625Hz to 13kHz at 433MHz, allowing the device to
support data rates to 10kbps. The device operates from
a supply voltage of 3.0V to 3.6V, and consumes 4.0mA
of supply current at 315MHz and 6.0mA at 433.92MHz.
A shutdown mode reduces supply current to 0.5uA. The
Auto-Polling feature allows the MICRF219 to sleep and
poll for user defined periods, thus further reducing
supply current. The Valid Bit-Check feature, when
enabled in Auto-Poll mode, fully awakes the receiver
and sends bits to the microcontroller once a valid
number of bits are detected. During normal operation an
optional Squelch feature disables the data output until
valid bits are detected. An optional Desense feature
reduces gain by 6dB to 42dB, distancing the receiver
from distantly placed, undesired transmitters.
• Evaluation board QR219BPF Available
Ordering Information
Part Number
Temperature Range
Package
MICRF219AYQS
16-Pin QSOP
−40°C to +105°C
_______________________________________________________________________________________________
Typical Application
QwikRadio is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
M9999-060811
(408) 944-0800
June 2011
Micrel
MICRF219
Pin Configuration
RO1
GNDRF
ANT
1
2
3
4
5
6
7
8
16 RO2
15 SCLK
14 RSSI
13 CAGC
12 CTH
11 SEL1
10 DO
GNDRF
Vdd
SQ
SEL0
SHDN
9
GND
MICRF219AYQS
Pin Description
16-Pin
QSOP
Pin Name Pin Function
Reference Oscillator Input: Reference resonator input connection to pierce oscillator stage. May also
be driven by external reference signal of 200mVp-p to 1.5V p-p amplitude maximum. Internal
capacitance of 7pF to GND during normal operation.
1
RO1
2
3
4
5
GNDRF
ANT
Negative supply connection associated with ANT RF input.
Antenna Input: RF signal input from antenna. Internally AC coupled. It is recommended a matching
network with an inductor-to-RF ground be used to improve ESD protection.
GNDRF
VDD
Ground connection for ANT RF input.
Positive supply connection for all chip functions. Bypass with 0.1µF capacitor located as close to the
VDD pin as possible.
Squelch Control Logic-Level Input. An internal pull-up pulls the logic-input HIGH when the device is
enabled. Bit D17 sets whether squelch is enabled or disabled when a logic-level signal is applied the
SQ pin. See Squelch Enable Truth-Table on page
6
7
SQ
Demodulator Filter Bandwidth Select Logic-Level Input. Internal pull-up (3uA typical) when not in
shutdown or SLEEP mode. Used in conjunction with SEL1 to control D3 bandwidth LSB when serial
interface contains default setting. It does not need to be defined in SLEEP mode.
SEL0
Shutdown control Logic-Level Input. A logic-level LOW enables the device. A logic-level HIGH places
the device in low-power shutdown mode. An internal pull-up pulls the logic input HIGH.
8
9
SHDN
GND
Negative supply connection for all chip functions except for RF input.
Data Input and Output. Demodulated data output. May be blanked until bit checking test is acceptable.
A current limited CMOS output during normal operation this pin is also used as a CMOS Schmitt input
for serial interface data. A 25kΩ pull-down is present when device is in shutdown and sleep modes.
10
11
12
DO
SEL1
CTH
Demodulator Filter Bandwidth Select Logic-Level Input: Internal (3uA typical) pull-up when not in
shutdown or SLEEP mode. Used in conjunction with SEL0, to control D4 bandwidth MSB, when serial
interface contains default setting. It does not need to be defined in SLEEP mode.
Demodulation threshold voltage integration capacitor. Capacitor-to-GND sets the settling time for the
demodulation data slicing level. Values above 1nF are recommended and should be optimized for data
rate and data profile.
13
14
CAGC
RSSI
AGC filter capacitor. A capacitor, normally greater than 0.47μF, is connected from this pin-to-GND
Received signal strength indication (output): Output is from a switched capacitor integrating op amp
with 220Ω typical output impedance.
Serial interface input clock. CMOS Schmitt input. A 25kΩ pull-down is present when device is in
shutdown mode.
15
16
SCLK
RO2
Reference resonator connection. Internal capacitance of 7pF to GND during normal operation.
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M9999-060811
(408) 944-0800
June 2011
Micrel
MICRF219
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD)................................................ +5V
Input Voltage. ............................................................. +5V
Junction Temperature ...........................................+150ºC
Lead Temperature (soldering, 10sec.)....................300°C
Storage Temperature (Ts)...................... -65ºC to +150°C
Maximum Receiver Input Power ......................... +10dBm
EDS Rating(3)................................................... 2KV HBM
Supply voltage (VDD).............................+3.0V to +3.6V
Ambient Temperature (TA) ................. –40°C to +105°C
Input Voltage (Vin) ................................................. 3.6V
Maximum Input RF Power................................ −20dBm
Receive Modulation Duty Cycle(6) .................... 20~80%
Frequency Range...........................300MHz to 450MHz
Electrical Characteristics
Specifications apply for VDD 3.3V, GND = 0V, CAGC = 4.7µF, CTH = 0.1µF, fRX = 433.92 MHz unless otherwise noted. Bold values
=
indicate –40°C – TA – 105°C. 1kbps data rate (Manchester encoded), reference oscillator frequency = 13.52127MHz.
Parameter
Condition
Min.
Typ.
4.0
Max.
Units
mA
Continuous Operation, fRX = 315MHz
Continuous Operation, fRX = 433.92MHz
Operating Supply Current
6.0
Shutdown Current
Receiver
0.15
µA
Image Rejection
25
0.86
dB
fRX = 315MHz
1st IF Center Frequency
MHz
fRX = 433.92MHz
fRX = 315 MHz, 50Ω BER=10-2
fRX = 433.92MHz, 50Ω BER=10-2
fRX = 315MHz
1.2
−110
−110
235
Receiver Sensitivity @ 1kbps
(Note 4)
dBm
kHz
IF Bandwidth
fRX = 433.92MHz
fRX = 315MHz
330
32 – j235
19 – j174
Antenna Input Impedance
ꢀ
fRX = 433.92MHz
Note 5
Receive Modulation Duty Cycle
AGC Attack / Decay Ratio
20
80
%
tATTACK / tDECAY
0.1
±30
TA = 25ºC
nA
nA
AGC Pin Leakage Current
TA = +105ºC
±800
1.15
1.70
V
V
RFIN @ −40dBm
RFIN @ −100dBm
AGC Dynamic Range
Reference Oscillator
fRX = 315 MHz, Crystal Load Cap = 10pF
fRX = 433.92 MHz, Crystal Load Cap = 10pF
9.81563
Reference Oscillator Frequency
MHz
13.52127
Reference Oscillator Input
Impedance
RO1
RO2
1.6
kꢀ
Reference Oscillator Bias Voltage
1.15
V
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M9999-060811
(408) 944-0800
June 2011
Micrel
MICRF219
Electrical Characteristics (Continued)
Specifications apply for VDD = 3.3V, GND = 0V, CAGC = 4.7µF, CTH = 0.1µF, fRX = 433.92 MHz unless otherwise noted. Bold values
indicate –40°C – TA – 105°C. 1kbps data rate (Manchester encoded), reference oscillator frequency = 13.52127MHz.
Parameter
Condition
Min.
Typ.
Max.
Units
Reference Oscillator Input Range
0.2
1.5
VP-P
Reference Oscillator Source
Current
V(REFOSC) = 0V
300
µA
Demodulator
FREFOSC = 9.81563 MHz
FREFOSC = 13.52127MHz
165
120
CTH Source Impedance
kꢀ
TA = 25ºC
TA = +105ºC
±2
±800
CTH Leakage Current
nA
Hz
Hz
Demodulator Filter Bandwidth
@ 315MHz
Programmable, see application section
Programmable, see application section
1170
1625
9400
Demodulator Filter Bandwidth
@ 434MHz
13000
Digital / Control Functions
DO Pin Output Current
Output Rise And Fall Times
Input High Voltage
As output source @ 0.8 VDD
sink @ 0.2 VDD
260
600
µA
µsec
V
CI = 15pF, pin DO, 10-90%
2
Pins SCLK, DO (As input), SHDN,SEL0,
SEL1,SQ
0.8VDD
0.8VDD
Pins SCLK, DO (As input), SHDN, SEL0,
SEL1,SQ
Input Low Voltage
0.2VDD
0.2VDD
V
Output Voltage High
Output Voltage Low
RSSI
DO
DO
V
V
0.4
2.0
25
−100dBm
RSSI DC Output Voltage Range
V
−40dBm
RSSI Response Slope
RSSI Output Current
RSSI Output Impedance
mV/dB
µA
−110dBm to -40dBm
400
250
ꢀ
50% data duty cycle, input power to Antenna = -
20dBm
RSSI Response Time
0.3
sec
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside of its operating rating.
3. Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute maximum rating may damage the device.
4. Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is defined
as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded) at a data rate of 1kbps.
5. When data burst does not contain preamble, duty cycle is defined as total duty cycle, including any “quiet” time between data bursts. When data
bursts contain preamble sufficient to charge the slice level on capacitor CTH, then duty cycle is the effective duty cycle of the burst alone. [For
example, 100msec burst with 50% duty cycle, and 100msec “quiet” time between bursts. If burst includes preamble, duty cycle is
TON/(TON+tOFF)= 50%; without preamble, duty cycle is TON/(TON+ TOFF + TQUIET) = 50msec/(200msec)=25%. TON is the (Average number of
1’s/burst) × bit time, and TOFF = (TBURST – TON.)
4
M9999-060811
(408) 944-0800
June 2011
Micrel
MICRF219
Typical Characteristics
433MHz Selectivity and
Bandwidth by Different Temps.
-50
-60
-70
-80
-90
-40°C
-100
-110
-120
+105°C
+20°C
FREQUENCY (MHz)
433.92MHz V/I by Temperatures
7
105°C
6.5
6
20°C
5.5
-40°C
5
4.5
4
3.0 3.1 3.2 3.3 3.4 3.5 3.6
VOLTAGE (V)
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M9999-060811
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June 2011
Micrel
MICRF219
Functional Diagram
CAGC
UHF
AGC
CONTROL
CONTROL
LOGIC
DESENSE
DOWNCOVERTER
MIXER
MIXER
DETECTOR
LNA
IF AMP
-f
f
RSSI
RSSI
i
fLO
IMAGE
REJECT
FILTER
OOK
DEMODULATOR
CONTROL
LOGIC
PROGRAMMABLE
FILTER
SYNTHESIZER
SLICER
DO'
BITCHECK
SLEEP
OSCILLATOR
SLEEP
TIMER
DO
WAKE-UP
SQUELCH
CTH
AUTOPOLL
SLICE
LEVEL
DO'
CONTROL
LOGIC
DO
REFERENCE
OSCILLATOR
CONTROL
LOGIC
REFERENCE
AND CONTROL
Figure 1. Simplified Block Diagram
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M9999-060811
(408) 944-0800
June 2011
Micrel
MICRF219
The IF BW can be calculated via direct scaling:
BWIF = BWIF@433.92 MHz
Functional Description
The simplified block diagram, shown in Figure 1,
illustrates the basic structure of the MICRF219 receiver.
It is made up of four sub-blocks:
×
OperatingFreq(MHz)
⎛
⎞
⎜
⎟
•
•
•
•
UHF Down-converter
OOK Demodulator
433.92
⎝
⎠
Reference and Control logic
Auto-poll circuitry
These filters are fully integrated inside the MICRF219.
After filtering, four active gain controlled amplifier stages
enhance the IF signal to its proper level for
demodulation.
Outside the device, the MICRF219 receiver requires just
three components to operate: two capacitors (CTH, and
CAGC) and the reference frequency device (usually a
quartz crystal). An additional five components are used
to improve performance; a power supply decoupling
capacitor, two components for the matching network,
and two components for the pre-selector band-pass
filter.
OOK Demodulator
The demodulator section is comprised of detector,
programmable low pass filter, slicer, and AGC
comparator.
Detector and Programmable Low-Pass Filter
The demodulation starts with the detector removing the
carrier from the IF signal. Post detection, the signal
becomes base band information. The programmable
low-pass filter further enhances the baseband
information. There are four programmable low-pass
filter BW settings: 1625Hz, 3250Hz, 6500Hz, 13000Hz
for 433.92MHz operation. Low pass filter BW will vary
with RF Operating Frequency. Filter BW values can be
easily calculated by direct scaling. See equation below
for filter BW calculation:
Receiver Operation
UHF Downconverter
The UHF down-converter has six components: LNA,
mixers, synthesizer, image reject filter, band pass filter
and IF amp.
LNA
The RF input signal is AC-coupled into the gate circuit of
the grounded source LNA input stage. The LNA is a
Cascoded NMOS amplifier. The amplified RF signal is
then fed to the RF ports of two double balanced mixers.
OperatingFreq(MHz)
433.92
⎛
⎜
⎞
⎟
BWOperating Freq = BW@433.92MHz
*
⎝
⎠
Mixers and Synthesizer
The LO ports of the Mixers are driven by quadrature
local oscillator outputs from the synthesizer block. The
local oscillator signal from the synthesizer is placed on
the low side of the desired RF signal to allow
suppression of the image frequency at twice the IF
frequency below the wanted signal. The local oscillator
is set to 32 times the crystal reference frequency via a
phase-locked loop synthesizer with a fully integrated
loop filter.
It is very important to choose filter setting that fits best
the intended data rate to minimize data distortion.
Demod BW is set at 13000Hz @ 433.92MHz as default
(assuming both SEL0 and SEL1 pins are floating). The
low pass filter can be hardware set by external pins
SEL0 and SEL1.
SEL0
SEL1
Demod BW (@ 434MHz)
1625Hz
Image-Reject Filter and Band-Pass Filter
0
1
0
1
0
0
1
1
The IF ports of the mixer produce quadrature-down
converted IF signals. These IF signals are low-pass
filtered to remove higher frequency products prior to the
image reject filter where they are combined to reject the
image frequencies. The IF signal then passes through a
third order band pass filter. The IF center frequency is
1.2MHz. The IF BW is 330kHz @ 433.92MHz. This
varies with RF operating frequency.
3250Hz
6500Hz
13000Hz
- default
Table 1. Demodulation BW Selection
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M9999-060811
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June 2011
Micrel
MICRF219
The de-sense function is accessible only through serial
programming.
Slicer and Slicing Level
The signal, prior to the slicer, is still AM. The data slicer
converts the AM signal into ones and zeros based on
the threshold voltage built up in the CTH capacitor.
After the slicer, the signal is ASK or OOK digital data.
D0
D1
D2
MODE: Desense
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
No Desense - default
6dB Desense
16dB Desense
30dB Desense
42dB Desense
The slicing threshold is default at 50%. The slicing
threshold can be set via serial programming through
register D5 and D6.
D5
1
D6
0
Slicing Level
Slice Level 30%
Reference Control
0
1
Slice Level 40%
There are 2 components in Reference and Control sub-
block: 1) Reference Oscillator and 2) Control Logic
through parallel Inputs: SEL0, SEL1, SHDN
1
1
Slice Level 50% - default
Slice Level 60%
0
0
Reference Oscillator
AGC Comparator
The reference oscillator in the MICRF219 (Figure 2)
uses a basic Pierce crystal oscillator configuration with
MOS transconductor to provide negative resistance.
Though the MICRF219 has build-in load capacitors for
the crystal oscillator, the external load capacitors are still
required for tuning it to the right frequency. R01 and R02
are external pins of the MICRF219 to connect the crystal
to the reference oscillator.
The AGC comparator monitors the signal amplitude
from the output of the programmable low-pass filter.
When the output signal is less than 750mV thresh-hold,
1.5µA current is sourced into the external CAGC
capacitor. When the output signal is greater than
750mV, a 15µA current sink discharges the CAGC
capacitor. The voltage developed on the CAGC
capacitor acts to adjust the gain of the mixer and the IF
amplifier to compensate for RF input signal level
variation.
Reference oscillator crystal frequency can be calculated:
F
REF OSC = FRF/(32 + 1.1/12)
Desense
Desense is a function designed to reduce the sensitivity
of the MICRF219 receiver to a maximum of 45dB for
training the MICRF219 receiver. This is done in order to
recognize an intended transmitter. Very often, a receiver
needs to learn how to recognize a particular transmitter.
It is important for the receiver not to learn the signal of a
stray transmitter near by. The simplest solution is to turn
down the receiver gain, so the receiver only recognizes
the transmitter at close range.
For 433.92 MHz, FREF OSC = 13.52127 MHz.
To operate the MICRF219 with minimum offset, crystal
frequencies should be specified with 10pF loading
capacitance.
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June 2011
Micrel
MICRF219
RO2
RO1
C
C
V BIAS
R
Figure 2. Reference Oscillator Circuit
SQUELCH Decode
<=4
Data Edge Pulses
S
R
Q
Good
CLK
SQUELCH
Disables DO
8 Stage
DOUT
Shift Register
D
Edge
Detector
Window
Counter
>=7
Good
CLK
CLK
Decode
Bad Bits
Decode Good
Bit Count
Window
Decode
Good
Bit
QA1 Bad Bit
Returns to
SLEEP
D7 D8
Select 0, 2, 4, 8 Good
Bits Before Wakeup
CLK
WATCHDOG
Timer
WAKEUP
Auto Poll
Timer (300µs)
S
R
D15 = 0 for Normal Operation
D15 = 1 for Auto Polled Operation
Serial Control Register
D15
Figure 3. Autopoll, Bit-Check Block Diagram
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M9999-060811
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June 2011
Micrel
MICRF219
Auto-Polling
The auto-poll block (Figure 3) contains a low power
oscillator that drives the sleep timer when the rest of
the device is powered down. It also contains circuits to
check whether the received bits are good. Auto-
polling is controlled by bit D15 in the serial register, in
conjunction with bits D12, D13, D14 to set the sleep
timer period. Bits D7, D8, are used for control of the
bit-check operation and bits D9, D10, D11 are used to
adjust the sensitivity of the bit-check action.
that a window time set longer than this will result in all
bits being tested as bad and the device will remain in
sleep polling mode. Now, when the serial command
sets bit D15 high, the device will go to sleep for the
timer period and will then awake to receive and check
bits. The device will output data again at DO as soon
as the programmed numbers of good RTZ bits have
been received. If a bad bit is seen, the device will
return to sleep mode and poll again for good bits after
the sleep period. Both high and low periods are
checked for each RTZ bit. The device will continue to
check bits until sufficient good bits enable the device
to wake up, or bad bits return the device to sleep.
Auto-Polling without Bit-Checking
For simple auto-polling without bit-checking, send a
serial command with bit D15 set high and bits D12,
D13, D14 set to the desired sleep time. The device
will go to sleep for the programmed timer duration
then wake up to receive data if it is present. The
device will stay awake until serial bit D15 is set low,
then set high again, to enable a further sleep period.
The sleep duty cycle may be controlled by the timing
of serial commands.
Operation
Received pulse edges trigger
a programmable
window timer clocked by the reference frequency. If
the next pulse edge falls within this window the bit is
flagged as bad. Detected good bits are counted and
the device will wake up once sufficient pulses have
been received. Two bad pulses or a lack of pulses will
cause the device to go to sleep for a further sleep
timeout period.
Auto-Polling with Bit-Checking
For auto-polling with bit-checking, the serial register
bits D7and D8 need to be set for the number of bits to
be checked as good, before the receiver outputs data
at the DO pin. The bit-check window bits D9, D10,
D11 must also be set to match the data period. The
shortest default window time gives the least critical bit
check action. For better discrimination, the window
setting may be increased up towards the normal
minimum time expected between data edges. Note
Squelch
During normal operation, if four or less out of eight bit
pulses are good, the DO output is squelched. If good
bit count increases to seven or more in any eight
sequential bits, squelch is disabled allowing data to
output at DO pin.
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June 2011
Micrel
MICRF219
Serial Interface Register Programming
Default State D9, D10, D11 is 111
Control Register Individual Truth Tables:
MODE:
Sleep Time
10ms
20ms
40ms Default
80ms
160ms
320ms
640ms
1280ms
D12
D13
D14
D0
0
1
D1
X
0
D2
X
0
MODE: Desense
No Desense - default
6dB Desense
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
16dB Desense
1
0
1
30dB Desense
1
1
1
42dB Desense
MODE:
D3
D4
Demod Bandwidth (at 433.92MHz)
0
1
0
1
0
0
1
1
1625Hz
3250Hz
6500Hz
D15
0
1
MODE: Auto-Poll
Awake – does not poll - default
Auto-polls with Sleep periods
13000Hz
- default
D5
1
0
1
0
D6
MODE
Slice Level 30%
Slice Level 40%
Slice Level 50% - default
Slice Level 60%
Always Set This Bit to 0
D16
0
1
1
0
SQ Pin
D17
0
MODE: Squelch Enable
Squelch Circuit Enabled
Squelch Circuit Disabled
Squelch Circuit Disabled (default)
Squelch Circuit Enabled
0
0
1
1
1
0
1
D7
0
1
D8
0
0
MODE: Bit-Check Setting
Bit-check 0 bits - default
Bit-check 2 bits
The external pin SQ can invert the setting of squelch
on/off defined by register bit D17. The external pin
defaults high via an internal pull-up so the squelch is
off with default D17 = 0 and on if D17 = 1. Such bit
logic is reversed if SQ pin is tied to low (Ground).
0
1
1
1
Bit-check 4 bits
Bit-check 8 bits
MODE:
D9 D10
D11 Bit-Check Window Times (315
MHz)
Set D3 to
Set D4 to
D3=1 D3=0
D4=1 D4=1
D3=1 D3=0
D4=0 D4=0
D18
D19
Always Set This Bit to 1
Always Set This Bit to 0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
98us, 196us, 393us, 785us
92us, 183us, 367us, 733us
85us, 170us, 341us, 681us
79us, 157us, 314us, 629us
72us, 144us, 288us, 577us
66us, 131us, 262us, 525us
59us, 118us, 236us, 473us
53us, 105us, 210us, 420us
MODE:
D9 D10
D11 Bit-Check Window Times
(433.92MHz)
Set D3 to
Set D4 to
D3=1 D3=0
D4=1 D4=1
D3=1 D3=0
D4=0 D4=0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
71us, 143us, 285us, 570us
67us, 133us, 266us, 532us
62us, 124us, 247us, 494us
57us, 114us, 228us, 457us
52us, 105us, 209us, 419us
48us, 95us, 190us, 381us
43us, 86us, 172us, 343us
38us, 76us, 152us, 305us
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MICRF219
Application Information
Figure 4. QR219BPF Application Example, 433.92MHz
Table 2 shows the component values for most often
used frequencies.
Antenna and RF Port Connections
Figure 4 shows the schematic of the QR219BPF
configured for 433.29 MHz operation. Figure 19
through Figure 23 are PCB pictures. The QR219BPF
is a good starting point for the prototyping of most
applications. Current design offers two antenna
options: A wire antenna or 50Ω SMA antenna. The
SMA connection also allows an RF signal to be
injected for test or verification. To use an antenna
such as a 50 Ω whip, remove the SMA and solder the
whip antenna in the hole on the PCB instead. A wire
of 22AWG with 167mm (6.-inch) can be used as a
substitution if low cost antenna is needed.
Freq (MHz)
315.0
C8 (pF)
6.8
L1 (nH)
39
390.0
6.8
24
418.0
6.0
24
433.92
5.6
24
Table 2. Front Band-Pass Filter values for Various
Frequencies
This band-pass filter can be removed if the outside
band noise does not cause a problem. The MICRF219
has built-in image reject mixers which improve the
selectivity significantly and reject outside band noise.
Front-End Band Pass Filter
Components L1 and C8 form the band-pass filter at
front of the receiver. Its purpose is to attenuate
undesired outside band noise that degrades the
receiver performance. It is calculated by the parallel
resonance equation:
f = 1/(2×PI×(SQRT L1×C8))
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MICRF219
Doing the same calculation example with the Smith
Chart, would appear as follows,
Low-Noise Amplifier Input Matching
Capacitor C3 and inductor L2 form the “L” shape input
matching network. The capacitor provides additional
attenuation for low-frequency outside band noise.
The inductor provides additional ESD protection for
the antenna pin. Two methods can be used to find
these values that best matched near 50ꢀ. One
method is done by calculating the values using the
equations below and the other is using a Smith chart
utility. The latter is made easier via a software plot
where components are added on. In this way, the user
can see the impedance moving direction for best
values of C8 and L1 toward to central matching point,
like WinSmith by Noble Publishing.
First, one plots the input impedance of the device,
(Z = 18.6 – j174.2)ꢀ @ 433.92MHz.(Figure 5):
To calculate the matching values, one needs to know
the input impedance of the device. Table 3 shows the
input impedance of the MICRF219 and suggested
matching values for the most often used frequencies.
These suggested values may be different if the layout
is not exactly the same as the one made here:
Freq (MHz)
315
C3 (pF)
1.8
L2(nH)
68
Z device (Ω)
33 - j235
390
1.5
47
23 – j199
21 – j186
19 – j174
418
1.5
43
433.92
1.5
39
Figure 5. Device’s Input Impedance, Z = 19 – j174Ω
Table 3. Matching Values for the Most Used
Frequencies
Second, one plots the shunt inductor (39nH) and the
series capacitor (1.5pF) for the desired input
impedance (Figure 6). One can then see the matching
leading to the center of the Smith Chart or close to
50ꢀ.
For the frequency of 433.92MHz, the input impedance
is Z = 18.6 – j174.2ꢀ, then the matching components
are calculated by:
Equivalent parallel = B = 1/Z = 0.606 + j5.68msiemens
Rp = 1 / Re (B); Xp = 1 / Im (B)
Rp = 1.65kꢀ; Xp = 176.2ꢀ
Q = SQRT (Rp/50 + 1)
Q = 5.831
Xm = Rp / Q
Xm = 282.98ꢀ
Resonance Method for L-shape Matching Network
Lc = Xp / (2×Pi×f);
L2 = (Lc×Lp) / (Lc + Lp);
L2 = 39.8nH
Lp = Xm / (2×Pi×f)
C3 = 1 / (2×Pi×f×Xm)
C3 = 1.3pF
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Crystal Selection
Crystal Y1 or Y1A (SMT or leaded respectively) is the
reference clock for all the device internal circuits.
Crystal characteristics of 10pF load capacitance,
30ppm, ESR < 50ꢀ, −40ºC to +105ºC temperature
range are desired. Table 4 shows Micrel’s approved
crystal suppliers such as (www.hib.com.br or
http://www.abracon.com/ ) and the frequencies.
The oscillator of the MICRF219 is a Pierce-type
oscillator. Good care must be taken when laying out
the printed circuit board. Avoid long traces and place
the ground plane on the top layer close to the
REFOSC pins RO1 and RO2. When care is not taken
in the layout, and the crystals used are not verified,
the oscillator may take longer time to start. Time-to-
good-data in the DO pin will be longer as well. In
some cases, if the stray capacitance is too high (>
20pF). In this case, either the receiving central
frequency will offset too much or the oscillator may not
start.
The crystal frequency is calculated by REFOSC = RF
Carrier/(32+(1.1/12)). The local oscillator is low-side
injection (32 × 13.52127MHz = 432.68MHz), that is,
its frequency is below the RF carrier frequency and
the image frequency is below the LO frequency. See
Figure 7. The product of the incoming RF signal and
local oscillator signal will yield the IF frequency, which
will be demodulated by the detector of the device.
Figure 7. Low-Side Injection Local Oscillator
Figure 6. Plotting of Shunt Inductor and Series
Capacitor
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MICRF219
REFOSC (MHz)
9.81563
Carrier (MHz)
315.0
HIB Part Number
Abracon Part Number
SA-9.815630-F-10-H-30-30-X
ABLS-9.81563MHz-10J4Y
12.15269
390.0
SA-12.152690-F-10-H-30-30-X ABLS-12.15269MHz-10J4Y
SA-13.025190-F-10-H-30-30-X ABLS-13.025190MHz-10J4Y
SA-13.521270-F-10-H-30-30-X ABLS-13.521270MHz-10J4Y
13.02519
418.0
13.52127
433.92
Table 4. Crystal Frequencies and Vendor Part Numbers
Demodulator Bandwidth Selection and Data
Stream Optimization
Maximum
Baud Rate
for 50%
Duty Cycle
(Hz)
JP1 and JP2 are the bandwidth selection for the
demodulator bandwidth. To set it correctly, it is
necessary to know the shortest pulse width of the
encoded data sent in the transmitter. Similar to the
example of the data profile in the Figure 7, PW2 is
shorter than PW1, so PW2 should be used for the
demodulator bandwidth calculation which is found by
0.65/shortest pulse width. After this value is found, the
setting should be done according to Table 5. For
example, if the pulse period is 100µsec, 50% duty
cycle, the pulse width will be 50µsec (PW = (100µsec
× 50%) / 100). Therefore, a bandwidth of 13kHz would
be necessary (0.65 / 50µsec). However, if this data
stream had a pulse period with a 20% duty cycle, then
the bandwidth required would be 32.5kHz (0.65 /
20µsec). This would exceed the maximum bandwidth
of the demodulator circuit. If one tries to exceed the
maximum bandwidth, the pulse would appear
stretched or wider.
Demod.
Shortest
Pulse
(µsec)
SEL0
JP1
SEL1
JP2
BW
(hertz)
Short
Open
Short
Open
Short
Short
Open
Open
1565
3130
6261
12523
416
208
104
52
1204
2408
4816
9633
Table 6. P1 and JP2 Setting, 418.0MHz
Maximum
Demod.
Shortest
Pulse
(µsec)
Baud Rate
for 50%
Duty Cycle
(Hz)
SEL0
JP1
SEL1
JP2
BW
(hertz)
Short
Open
Short
Open
Short
Short
Open
Open
1170
2350
4700
9400
445
223
111
56
1123
2246
4493
8987
Maximum
Demod.
BW
(hertz)
Shortest
Pulse
(µsec)
SEL0
JP1
SEL1
JP2
Baud Rate
for 50% Duty
Cycle (Hz)
Short
Open
Short
Open
Short
Short
Open
Open
1625
3250
6500
13000
400
200
100
50
1250
2500
5000
10000
Table 7. JP1 and JP2 Setting, 315MHz
AGC Capacitor and Data Slicer Threshold
Capacitor Selection
Capacitors C6 and C4 are CTH and CAGC capacitors
respectively providing a time base reference for the
data pattern received. These capacitors are selected
according to data profile, pulse duty cycle, dead time
between two received data packets, and if the data
pattern does has or not have a preamble. See Figure
8 for example of a data profile.
Table 5. JP1 and JP2 Setting, 433.92MHz
Other frequencies will have different demodulator
bandwidth limits, which is derived from the reference
oscillator frequency. Table 6 and Table 7 shows the
limits for the other two most used frequencies.
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MICRF219
Figure 8. Example of a Data Profile
For best results, they should always be optimized for
the data pattern used. As the baud rate increases, the
capacitor values decrease. Table 8 shows suggested
values for Manchester Encoded data, 50% duty cycle.
Demod.
BW
(Hz)
Figure 9. Data Out Pin with No Squelch (SQ = 1)
SEL0
JP1
SEL1
JP2
Cth
Cagc
Short
Open
Short
Open
Short
Short
Open
Open
1625
3250
6500
13000
100nF
47nF
22nF
10nF
4.7µF
2.2µF
1µF
0.47µF
Table 8. Suggested CTH and CAGC Values
JP3 and JP4 are jumpers selectable to high or low
and used to configure the digital squelch function.
When it is tied to high, there is no squelch applied to
the digital circuits and the DO (data out) pin has a
hash signal. When the pin is low, the DO pin activity is
considerably reduced. It will have more or less than
shown in the figure below depending upon the outside
band noise. The penalty for using squelch is a delay in
getting a good signal in the DO pin. This means that it
takes longer for the data to show up. The delay is
dependent upon many factors such as RF signal
intensity, data profile, data rate, CTH and CAGC
capacitor values, and outside band noise See Figure
9 and Figure 10. Please note that Squelch action is
based on the Bitcheck operation and may be
optimized using the Bitcheck Window serial register
setting.
Figure 10. Data Out Pin with Squelch (SQ = 0)
Other components used are C5, which is a decoupling
capacitor for the VDD line; R3 for the shutdown pin
(SHDN = 0, device is operation), which can be
removed if that pin is connected to a microcontroller or
an external switch; and R1 and R2 which form a
voltage divider for the AGC pin. One can force a
voltage in this AGC pin to purposely decrease the
device sensitivity. Special care is needed when doing
this operation, as an external control of the AGC
voltage may vary from lot to lot and may not work the
same in several devices.
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Three other pins are worthy of comment. They are the
DO, RSSI, and shutdown pins. The DO pin has a
driving capability of 0.4mA. This is good enough for
most of the logic family ICs on the market today. The
RSSI pin provides a transfer function of the RF signal
intensity versus voltage. It is very useful to determine
the signal-to-noise ratio of the RF link, crude range
estimate from the transmitter source and AM
demodulation, which requires a low CAGC capacitor
value.
The shutdown pin (SHDN) is useful to save energy.
Making its level close to VDD (SHDN = 1), the device is
not in operation. Its DC current consumption is less
than 1µA (do not forget to remove R3). When toggling
from high to low, there will be a time required for the
device to come to steady-state mode, and a time for
data to show up in the DO pin. This time will be
dependent upon many things such as temperature,
the crystal used, and if there is an external oscillator
with faster startup time. See Figure 11 and Figure 12
or time-to-good-data on both 433.92MHz and 315MHz
versions.
Figure 12. Time-to-Good-Data after Shutdown Cycle,
315MHz at Room Temperature
Serial Register Programming
Programming the device is accomplished by the use
of pins DO and SCLK. Normally, D0 (Pin 10) is
outputting data and needs to switch to an input pin
made by the start sequence, as shown at Figure 13.
High at the SCLK pin tri-states the DO pin, enabling
the external drive into the DO pin with an initial low
level. The start sequence is completed by taking
SCLK low, then high while DO is low, followed by
taking DO high, then low while SCLK is high. The
serial interface is initialized and ready to receive the
programming data.
BIT TIME 0
BIT TIME 1
BIT TIME 2
T6
T7
SCLK
T1
T2
T4
T5
T8
T9
T3
“19”
D19
“0”
“0”
“1”
DO AS
OUTPUT
DO INPUT BITS:
D18
D17
Figure 11. Time-to-Good-Data after Shutdown Cycle,
433.92MHz, Room Temperature
Figure 13. Serial Interface Start Sequence
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Bits are serially programmed starting with the most
significant bit (MSB = D19) if all bits are being
programmed until the least significant bit (LSB =D0)
For instance, if only the desense bits D0, D1, and D2
are being programmed, then these are the only bits
that need to be programmed with the start sequence
D2, D1, D0, plus the stop sequence. Or, if only the
squelch bit D17 is needed, then the sequence must
be from start sequence, D17 through D0 plus the stop
sequence, making sure the other bits (besides D17)
are programmed as needed. It is recommended that
all parallel input pins (SEL0, SEL1, and SQ) be kept
high when using the serial interface. After the
programming bits are finished, a stop sequence (as
shown in Figure 14) is required to end the mode and
reestablish the DO pin as an output again. To do so,
the SCLK pin is kept high while the DO pin changes
from low to high, then low again, followed by the
SCLK pin made low. Timing of the programming bits
are not critical, but should be kept as shown below:
Serial Interface Register Loading Examples
See Figures 15 – 17. (Channel 1 is the DO pin, and
channel 2 is the SCLK pin).
T1 < 0.1µs, Time from SCLK to convert DO to
input pin
Figure 15. All Bits D19 through D0 = 0
T6 > 0.1µs, SCLK high time
T7 > 0.1µs, SCLK low time
T2, T3, T4, T5, T8, T9, T10 > 0.1µs
BIT TIME 18
BIT TIME 19
SCLK
T10
“1”
D1
“0”
“1”
DO
DO
DO PIN AS OUTPUT
Figure 14. Serial Interface Stop Sequence
SCLK frequency should be greater than 5kHz to avoid
automatic reset from internal circuitry.
Figure 16. All Bits D19 through D0 = 1
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From MSB to LSB (see Table 9):
D19 D18 D17 D16 D15 D14 D13 D12
0
1
0
0
1
1
0
0
D11 D10 D9
D8
1
D7
0
D6
1
D5
1
0
1
1
D4
0
D3
0
D2
0
D1
0
D0
0
Table 9. Auto-Poll Example Bit Sequence
Figure 17. D19 = D18 = 1, D17 = D0 = 0
Auto-Poll Programming Example
Auto-Poll example (see Figure 18):
D0 = D1 = D2 = 0, no desense
D3 = D4 = 0, demodulator bandwidth = 1712 hertz, 1
kHz baud rate, pulse = 500µsec.
Required demodulator bandwidth is 0.65/500usec =
1300 hertz
D5 = D6 = 1, Slice level = 50%
D7 = 0, D8 = 1, bit check = 4 bits.
This is the time the device is ON checking for four
consecutive valid windows.
Figure 18. Autopoll Example
D9 = D10 = 1, D11 = 0, data rate is 1 kHz, (500µsec
pulses), window set to 433µsec (< 500 usec)
D12 = D13 = 0, D14 = 1, sleep timer set to 160msec,
that is, 4 bit is ON and 160msec is OFF.
D15 = 1, device is placed in autopoll
D16 = 0, not used. Always set to 0.
D17 = 0, squelch is OFF
D18 = 1, watchdog timer is OFF
D19 = 0, no RSSI offset
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MICRF219
inductance. Ground plane should be solid and with no
sudden interruptions. Avoid using ground plane on top
layer next to the matching elements. It normally adds
additional stray capacitance which changes the
matching. Do not use Phenolic materials as they are
conductive above 200MHz. Typically, FR4 or better
materials are recommended. The RF path should be
as straight as possible to avoid loops and
unnecessary turns. Separate ground and VDD lines
from other digital or switching power circuits (such
microcontroller…etc). Known sources of noise should
be laid out as far as possible from the RF circuits.
Avoid unnecessary wide traces which would add more
distribution capacitance (between top trace to bottom
GND plane) and alter the RF parameters.
PCB Considerations and Layout
Figure 19 to Figure 23 show the QR219BPF PCB
layout. The Gerber files provided are downloadable
from Micrel Website and contain the remaining layers
needed to fabricate this board. When copying or
making one’s own boards, make the traces as short
as possible. Long traces alter the matching network
and the values suggested are no longer valid.
Suggested matching values may vary due to PCB
variations. A PCB trace 100 mills (2.5mm) long has
about 1.1nH inductance. Optimization should always
be done with exhaustive range tests. Make sure the
individual ground connection has a dedicated via
rather then sharing a few of ground points by a single
via. Sharing ground via will increase the ground path
Figure 19. QR219BPF Top Layer
Figure 20. QR219BPF Bottom Layer
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Figure 21. QR219BPF Top Silkscreen Layer
Figure 22. QR219BPF Bottom Silkscreen Layer
Figure 23. QR219BPF Dimensions (in inches)
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MICRF219
QR219BPF Bill of Materials, 433.92MHz
Item Reference
Part
Description
Qty.
1
1
2
ANT1
22AWG rigid wire
1.5pF 50V
4.7uF 6.3V
0.1uF 16V
5.6pF 50V
10pF 50V
0ohm
167mm (6.6”) 22AWG wire
0603 chip capacitor
0805 chip capacitor
0603 chip capacitor
0603 chip capacitor
0603 chip capacitor
0603 chip resistor
C3
1
3
C4
1
4
C6,C5
2
5
C8
1
6
C10,C9
2
7
JP1, JP2, R5, R6, R7
5
8
R1, R2, JP3, JP4
(np)
0603 chip resistor, not placed
7 pin connector
4
9
J1
J2
L1
L2
R3
U1
Y1
CON7
1
10
11
12
13
14
15
(np)
Edge mount SMA connector
5%, 0603 SMT inductor
5%, 0603 SMT inductor
0603 chip resistor
1
24nH 5%
39nH 5%
100kohm
MICRF219AYQS
13.52127MHz
1
1
2
MICRF219 chip
1
Crystal
1
Table 10. QR219BPF Bill of Materials, 433.92MHz
QR219BPF Bill of Materials, 315MHz
Item Reference
Part
Description
Qty.
1
1
2
ANT1
22AWG rigid wire
1.8pF 50V
4.7µF 6.3V
0.1µF 16V
6.8pF 50V
10pF 50V
0ꢀ
230mm (9.0”) 22AWG wire
0603 chip capacitor
0805 chip capacitor
0603 chip capacitor
0603 chip capacitor
0603 chip capacitor
0603 chip resistor
C3
1
3
C4
1
4
C6,C5
2
5
C8
1
6
C10,C9
2
7
JP1, JP2, R5, R6, R7
5
8
R1, R2, JP3, JP4
(np)
0603 chip resistor, not placed
7 pin connector
4
9
J1
J2
L1
L2
R3
U1
Y1
CON7
1
10
11
12
13
14
15
(np)
Edge mount SMA connector
5%, 0603 SMT inductor
5%, 0603 SMT inductor
0603 chip resistor
1
39nH 5%
68nH 5%
100kꢀ
1
1
2
MICRF219AYQS
9.81563MHz
MICRF219 chip
1
Crystal
1
Table 11. QR219BPF Bill of Materials, 315MHz
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MICRF219
Package Information
QSOP16 Package Type (AQS16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel
assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including
liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual
property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2009 Micrel, Incorporated.
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