PL123E-09HOI [MICREL]
Low Skew Zero Delay Buffer;
| 型号： | PL123E-09HOI |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Low Skew Zero Delay Buffer |
| 文件： | 总10页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
FEATURES
DESCRIPTION
The PL123E-09 (-09H for High Drive) is a high perfor-
mance, low skew, low jitter zero delay buffer designed
to distribute high speed clocks. It has two low-skew
output banks, of 4 outputs each, that are synchronized
with the input. Control of the two banks of outputs is
achieved by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
Frequency Range 10MHz to 220MHz
Zero input - output delay.
Low Output to Output Skew
Optional Drive Strength:
Standard (8mA) PL123E-09
High (12mA) PL123E-09H
2.5V or 3.3V, ±10% operation.
Available in 16-Pin SOP or TSSOP packages
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF
CLKOUT
CLKA1
CLKA2
PLL
Mux
REF
CLKA1
CLKA2
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
CLKA3
CLKA4
GND
GND
CLKB1
CLKB2
CLKB3
CLKB4
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
S1
S2
Selector
Inputs
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 1
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
PIN DESCRIPTIONS
Package Type
Name
Type
Description
TSSOP-16L
SOP-16L
REF[1]
1
2
1
2
I
Input reference frequency.
CLKA1[2]
CLKA2[2]
VDD
O
O
P
P
O
O
I
Buffered clock output, Bank A
Buffered clock output, Bank A
VDD connection
3
3
4,13
5,12
6
4,13
5,12
6
GND
GND connection
CLKB1[2]
CLKB2[2]
S2[3]
Buffered clock output, Bank B
Buffered clock output, Bank B
Selector input
7
7
8
8
S1[3]
9
9
I
Selector input
CLKB3[2]
CLKB4[2]
CLKA3[2]
CLKA4[2]
CLKOUT[2]
10
11
14
15
16
10
11
14
15
16
O
O
O
O
O
Buffered clock output, Bank B
Buffered clock output, Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output. Internal feedback on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION
CLOCK A1–A4
CLOCK B1–B4
S2
S1
CLKOUT
Output Source
PLL Shutdown
(Bank A)
(Bank B)
0
0
1
1
0
1
0
1
Three-state
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
PLL
PLL
N
N
Y
N
Driven
Reference
PLL
Driven
Driven
INPUT / OUTPUT SKEW CONTROL
The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 2
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this equals
ringing!
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Value of decoupling capacitor is frequency depend-
ant. Typical values to use are 0.1F for designs
using frequencies < 50MHz and 0.01F for designs
using frequencies > 50MHz.
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20
To CMOS Input
50 line
Connect a 33 series
resistor at each of the output
clocks to enhance the
stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 3
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage ............................VSS – 0.5V to 4.6V
Storage Temperature ..........................–65°C to 150°C
Junction Temperature ..................................... 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)……………..> 2000V
OPERATING CONDITIONS
Description
Parameter
Min
Max
3.63
30
Unit
V
Supply Voltage
VDD
2.25
–
[4]
Load Capacitance, <100 MHz, 3.3V
CL
pF
pF
pF
pF
pF
pF
pF
pF
MHz
MHz
Ω
Load Capacitance, <100 MHz, 2.5V with High Drive
Load Capacitance, <133.3 MHz, 3.3V
Load Capacitance, <133.3 MHz, 2.5V with High Drive
Load Capacitance, <133.3 MHz, 2.5V with Standard Drive
Load Capacitance, >133.3 MHz, 3.3V
Load Capacitance, >133.3 MHz, 2.5V with High Drive
Input Capacitance[5]
–
30
–
22
–
22
–
15
–
15
–
15
CIN
–
5
Closed-loop bandwidth (typical), 3.3V
Closed-loop bandwidth (typical), 2.5V
Output Impedance (typical), 3.3V High Drive
Output Impedance (typical), 3.3V Standard Drive
Output Impedance (typical), 2.5V High Drive
Output Impedance (typical), 2.5V Standard Drive
BW
1
0.5
23
33
26
39
ROUT
Ω
Ω
Ω
Power-up time for all VDD’s to reach minimum specified
voltage (power ramps must be monotonic)
tPU
0.01
250
ms
Notes:
4. Applies to Test Circuit #1.
5. Applies to both REF Clock and internal feedback path on CLKOUT.
6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 4
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
3.3V DC ELECTRICAL SPECIFICATIONS
Description
Parameter Test Conditions
Min
2.97
–
Max
3.63
Unit
V
Supply Voltage
VDD
VIL
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Input HIGH Current
0.8
V
VIH
2.5
–
VDD + 0.3
±10
V
IIL
0 < VIN < VIL
VIN = VDD
µA
µA
IIH
–
100
V
V
IOL = 8 mA (Standard Drive)
IOL = 12 mA (High Drive)
–
–
0.4
0.4
Output LOW Voltage
VOL
V
V
IOH = –8 mA (Standard Drive)
IOH = –12 mA (High Drive)
2.4
2.4
–
–
Output HIGH Voltage
Supply Current
VOH
IDD
Unloaded outputs, 66-MHz REF
–
45
mA
2.5V DC ELECTRICAL SPECIFICATIONS
Description
Parameter
Test Conditions
Min
2.25
–
Max
2.75
Unit
V
Supply Voltage
VDD
VIL
VIH
IIL
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Input HIGH Current
0.7
V
1.7
–
VDD + 0.3
±10
V
0<VIN < VIL
VIN = VDD
µA
µA
IIH
–
100
IOL = 8 mA (Standard Drive)
IOL = 12 mA (High Drive)
–
–
0.5
0.5
Output LOW Voltage
VOL
V
IOH = –8 mA (Standard Drive)
IOH = –12 mA (High Drive)
VDD – 0.6
VDD – 0.6
–
–
Output HIGH Voltage
Supply Current
VOH
IDD
V
Unloaded outputs, 66-MHz REF
–
30
mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 5
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS
Description
Parameter Test Conditions
Min
10
10
10
10
25
40
47
45
–
Typ
–
Max Unit
3.3V High Drive
220
167
200
134
75
60
53
55
–
MHz
MHz
MHz
MHz
%
Maximum Frequency[7]
(Input/Output)
3.3V Standard Drive
–
1/t1
2.5V High Drive
–
2.5V Standard Drive
–
<133.3 MHz
TIDC
–
Input Duty Cycle
(PLL Mode only)
>133.3 MHz
–
%
<133.3 MHz
t2 ÷ t1
–
%
Output Duty Cycle[8]
>133.3 MHz
–
%
Standard Drive, CL = 30 pF, <100 MHz
1.6
1.6
0.6
1.2
1.2
0.5
1.5
2.1
1.3
1.2
–
ns
Standard Drive, CL = 22 pF, <133.3 MHz
Standard Drive, CL = 15 pF, <167 MHz
High Drive, CL = 30 pF, <100 MHz
High Drive, CL = 22 pF, <133.3 MHz
High Drive, CL = 15 pF, >133.3 MHz
Standard Drive, CL = 15 pF, <133.33 MHz
High Drive, CL = 30 pF, <100 MHz
High Drive, CL = 22 pF, <133.3 MHz
High Drive, CL = 15 pF, >133.3 MHz
All outputs equally loaded
–
–
ns
–
–
ns
Rise, Fall Time (3.3V)[8]
t3,t4
–
–
ns
–
–
ns
–
–
ns
–
–
ns
–
–
ns
Rise, Fall Time (2.5V)[8]
t3, t4
–
–
ns
–
–
ns
[8]
Output to Output Skew
t5
t6
–
100
100
200
ps
PLL enabled @ 3.3V
–100
–200
–
ps
Delay, REF Rising Edge
to CLKOUT Rising Edge[8]
PLL enabled @2.5V
–
ps
Measured at VDD/2.
–
–
–
–
–
–
±150
±300
1.0
ps
ps
Any output to any output, 3.3V supply
Part to Part Skew[8]
PLL Lock Time[8]
t7
Measured at VDD/2.
Any output to any output, 2.5V supply
Stable power supply, valid clocks pre-
sented on REF and CLKOUT pins
tLOCK
ms
3.3V, >66 MHz, <15 pF
–
–
–
–
–
–
–
–
–
–
–
–
55
125
100
95
ps
ps
ps
ps
ps
ps
3.3V, >66 MHz, <30 pF, Standard. Drive
3.3V, >66 MHz, <30 pF, High Drive
2.5V, >66 MHz, <15 pF, Standard. Drive
2.5V, >66 MHz, <15 pF, High Drive
2.5V, >66 MHz, <30 pF, High Drive
Cycle-to-Cycle Jitter,
Peak[8, 9]
TJCC
65
145
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 6
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS (continued)
Description
Parameter Test Conditions
3.3V, 66–100 MHz, <15 pF
Min
–
Typ
–
Max
75
Unit
ps
3.3V, >100 MHz, <15 pF
–
–
45
ps
3.3V, >66 MHz, <30 pF, Standard Drive
3.3V, >66 MHz, <30 pF, High Drive
2.5V, >66 MHz, <15 pF, Standard. Drive
2.5V, 66–100 MHz, <15 pF, High Drive
2.5V, >100 MHz, <15 pF, High Drive
–
–
100
70
ps
Period Jitter, Peak[8,9]
TPER
–
–
ps
–
–
60
ps
–
–
60
ps
–
–
45
ps
Notes:
7. For the given maximum loading conditions. See CL in Operating Conditions Table.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
9. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 7
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
OUTPUT
All Outputs Rise/Fall Time
2.0V(1.8V)
0.8V(0.6V)
3.3V (2.5V)
0V
2.0V(1.8V)
0.8V(0.6V)
t3
t4
Output-Output Skew
OUTPUT
VDD/2
OUTPUT
VDD/2
t5
Input-Output Propagation Delay
INPUT
VDD/2
CLKOUT
VDD/2
t6
Device-Device Skew
Any Output, Part 1 or 2
Any Output, Part 1 or 2
VDD/2
VDD/2
t7
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 8
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
TEST CIRCUITS
Test Circuit #1
VDD
0.1 F
0.1 F
CLK
OUTPUTS
VDD
CLOAD
GND
GND
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
16 PIN Narrow SOP, TSSOP ( mm )
SOP
TSSOP
E
H
Symbol
Min.
Max.
Min.
Max.
A
A1
B
C
D
E
1.35
0.10
0.33
0.19
9.80
3.80
5.80
0.40
1.75
0.25
0.51
0.25
10.00
4.00
6.20
1.27
-
1.20
0.15
0.30
0.20
5.10
4.50
0.05
0.19
0.09
4.90
4.30
D
A
H
L
6.40 BSC
0.45
A1
0.75
C
e
0.65 BSC
1.27 BSC
L
B
e
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 9
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
2180 Fortune Drive, San Jose, CA 95131, USA
Tel: (408) 944-0800 Fax: (408) 474-1000
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL123E-09(H) X X - X
Part Number
H=High Drive
None=Tubes
R=Tape & Reel
None = Standard Drive
Package Type
O=TSSOP
S=SOP
Temperature Range
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Part/Order Number
Marking
Package Option
P123E09
OC
LLLLL
P123E09H
OC
LLLLL
P123E09
SC
LLLLL
P123E09H
SC
LLLLL
P123E09
OI
LLLLL
P123E09H
OI
LLLLL
P123E09
SI
LLLLL
P123E09H
SI
PL123E-09OC
PL123E-09OC-R
PL123E-09HOC
PL123E-09HOC-R
PL123E-09SC
16-Pin TSSOP Tube
16-Pin TSSOP (Tape and Reel)
16-Pin TSSOP Tube
16-Pin TSSOP (Tape and Reel)
16-Pin SOP Tube
PL123E-09SC-R
PL123E-09HSC
PL123E-09HSC-R
PL123E-09OI
16-Pin SOP (Tape and Reel)
16-Pin SOP Tube
16-Pin SOP (Tape and Reel)
16-Pin TSSOP Tube
PL123E-09OI-R
PL123E-09HOI
PL123E-09HOI-R
PL123E-09SI
16-Pin TSSOP (Tape and Reel)
16-Pin TSSOP Tube
16-Pin TSSOP (Tape and Reel)
16-Pin SOP Tube
PL123E-09SI-R
PL123E-09HSI
16-Pin SOP (Tape and Reel)
16-Pin SOP Tube
PL123E-09HSI-R
*Note: LLLLL designates lot number
16-Pin SOP (Tape and Reel)
LLLLL
Micrel Inc., reserves the right to make changes in its products or specifications, o r both at any time without notice. The information furnished by Micrel
is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express
written approval of the President of Micrel Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 10
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