SM844256 [MICREL]

10 Gigabit Ethernet and SONET, 6 Output, Ultra-Low Jitter LVDS Frequency Synthesizer; 10千兆以太网和SONET ， 6输出，超低抖动LVDS频率合成器


型号：	SM844256
厂家：	MICREL SEMICONDUCTOR
描述：	10 Gigabit Ethernet and SONET, 6 Output, Ultra-Low Jitter LVDS Frequency Synthesizer 10千兆以太网和SONET ， 6输出，超低抖动LVDS频率合成器以太网
文件：	总8页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SM844256

10 Gigabit Ethernet and SONET, 6 Output,

Ultra-Low Jitter LVDS Frequency

Synthesizer

General Description

Features

The SM844256 provides a low-noise timing solution for

high speed, high accuracy synthesis of clock signals.

Common applications include SONET, Gigabit Ethernet,

10 Gigabit Ethernet, and similar networking standards. It

includes a power reduction methodology, along with a

patented RotaryWave^TMarchitecture that provides a very

stable clock with very low noise.

• Generates six LVDS outputs

• 2.5V or 3.3V operating range

• Typical phase jitter @ 125MHz

(1.875MHz to 20MHz): 80 fs (typical) @ 3.3V

• 75MHz to 625MHz output frequencies

• Industrial temperature range

• Green, RoHS, and PFOS compliant

• Available in 24-pin TSSOP EPAD

• Operating supply modes:

Power supplies of either 3.3V or 2.5V are supported, with

superior jitter and phase noise performance. The device

synthesizes different low noise LVDS output frequencies

such as 125MHz, 156.25MHz, 312.5MHz, and 625MHz for

Ethernet applications; 77.76MHz, 155.52MHz, 311.04MHz,

and 622.08MHz for SONET applications. The crystal

reference frequencies used include 25MHz and 19.44Mhz

for Ethernet and SONET applications, respectively.

Core/Output

3.3V/3.3V, 3.3V/2.5V, 2.5V/2.5V

Applications

The SM844256 is an excellent replacement for IDT Femto-

clocks, with improved accuracy, power consumption,

waveform integrity, and jitter.

• SONET

• Gigabit Ethernet

• 10-Gigabit Ethernet

• Infiniband

Data sheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

________________________________________________________________________________________________________________________

Block Diagram

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

M9999-072110-B

July 2010

Micrel, Inc.

SM844256

Ordering Information^{(1, 2)}

Part Number

SM844256KA

Notes:

Marking

844256

Shipping

Junction Temperature Range

Package

24-Pin TSSOP EPAD

Tube, Tape & Reel

–40° to +85°C

1. Devices are Green, RoHS, and PFOS Compliant.

2. Lead finish is 100% matte tin.

Pin Configuration

24-Pin TSSOP EPAD

(Top View)

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July 2010

Micrel, Inc.

SM844256

Pin Description

Pin Number

1, 2

Pin Name

V_DDO

Pin Type

PWR

Pin Level

Pin Function

2.5V or 3.3V Power Supply

Differential Clock Output

3, 4

/Q2, Q2

/Q1, Q1

/Q0, Q0

O, (DIF)

LVDS

5, 6

7, 8

Pull-Up 45k, Single-Ended Input Select Pin.

Logic (0) = PLL Output

PLL_BYPASS

I, (SE)

LVCMOS

Logic (1) = Xtal Reference

V_DDA

V_DD

PWR

Analog 3.3V or 2.5V Power Supply

3.3V or 2.5V Power Supply

FB_SEL

XTAL_IN

XTAL_OUT

N_SEL0

GND

I, (SE)

O, (SE)

I, (SE)

PWR

LVCMOS

12pF crystal

LVCMOS

Pull-Down 45k, Single-Ended Input Select Pin

Crystal Reference Input, no load caps needed.

Crystal Reference Output, no load caps needed.

Pull-Up 45k, Single-Ended Input Select Pin

Ground

16, 17

N_SEL1

/Q5, Q5

/Q4, Q4

/Q3, Q3

I, (SE)

O, (DIF)

LVCMOS

LVDS

Pull-Up 45k, Single-Ended Input Select Pin

Differential Clock Output

19, 20

21, 22

23, 24

LVDS

Differential Clock Output

LVDS

Differential Clock Output

Input and Output Frequency Table

XTAL (MHz)

FB_SEL

N_SEL1

N_SEL0

Outputs (MHz)

Application

600

300

150

120

SAS/SATA

625

10 Gigabit Ethernet

312.50

156.25

Gigabit Ethernet/Infiniband/PCI/PCI-

E/PCI-X

125

18.75

600

300

150

SAS/SATA

19.44

622.08

311.04

155.52

77.76

10 Gigabit Ethernet/SONET

SONET

19.53125

625

10 Gigabit Ethernet

312.5

156.25

78.125

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July 2010

Micrel, Inc.

SM844256

Absolute Maximum Ratings⁽¹⁾

Operating Ratings⁽²⁾

Supply Voltage (V_DDA, V_DD, V_DDO)................................+4.6V

Input Voltage (V_IN)………………………-0.50V to V_DD+0.5V

LVDS Output Current (I_OUT)………………………… ±10mA

Lead Temperature (soldering, 20sec.)....................... 260°C

Case Temperature ..................................................... 115°C

Storage Temperature (T_s) ..........................-65°C to +150°C

Supply Voltage (V_DDO).......................... +2.375V to +3.465V

Supply Voltage (V_DD,V_DDA).................... +2.375V to +3.465V

Ambient Temperature (T_A) ..........................–40°C to +85°C

(3)

Junction Thermal Resistance

TSSOP (θ_JA).......................................................32°C/W

DC Electrical Characteristics⁽⁴⁾

V_DDA= V_DD= 3.3V ±5% or 2.5V ±5%, V_DDO= 2.5V ±5%, T_A= –40°C to +85°C, unless noted.

Symbol

Parameter

Condition

Min

Typ

2.5

3.3

Max

2.625

3.465

TBD

Units

V_DDO

2.5V Operating Voltage

2.375

V_DDA,V_DD3.3V Operating Voltage

I_DDA

Analog Supply Range

Core Supply Current

I/O Supply Range

F_OUT= 156.25 MHz

_OUT= 625.00 MHz

I_DD

F_OUT= 156.25 MHz

F_OUT= 625.00 MHz

F_OUT= 156.25 MHz

F_OUT= 625.00 MHz

TBD

I_DDO

195

200

V_DDA= V_DD= V_DDO= 3.3V ±5%, T_A= –40°C to +85°C, unless noted.

Symbol

Parameter

Condition

Min

Typ

Max

Units

V_DDA

3.3V Operating Voltage

3.135

3.3

3.465

V_DD

V_DDO

I_DDA

Analog Supply Range

Core Supply Current

I/O Supply Range

F_OUT= 156.25 MHz

F_OUT= 625.00 MHz

F_OUT= 156.25 MHz

F_OUT= 625.00 MHz

F_OUT= 156.25 MHz

F_OUT= 625.00 MHz

I_DD

I_DDO

195

200

234

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied

at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.

4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

M9999-072110-B

July 2010

Micrel, Inc.

SM844256

LVDS DC Electrical Characteristics^{(5, 6, 7)}

V_DDA= V_DD= 3.3V ±5% or 2.5V ±5%, V_DDO= 2.5V or 3.3V ±5%, T_A= –40°C to +85°C, unless noted.

Symbol

V_OD

Parameter

Condition

Min

Typ

Max

Units

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

Figure 1

275

350

475

ΔV_OD

V_OS

1.15

1.25

1.50

ΔV_OS

V_OSMagnitude Change

LVCMOS DC Electrical Characteristics⁽⁶⁾

V_DDA= V_DD= 3.3V ±5% or 2.5V ±5%, V_DDO= 2.5V or 3.3V ±5%, T_A= –40°C to +85°C, unless noted.

Symbol

Parameter

Condition

Min

Typ

Max

Units

V_IH

Input High Voltage

V_DD

+0.3

V_IL

I_IH

Input Low Voltage

-0.3

0.8

150

Input High Current (FB_SEL)

V_DD= V_IN= 3.465V

μA

Input High Current (PLL_BYPASS),

(N_SEL0), (NSEL1)

I_IL

Input Low Current (FB_SEL)

V_DD= 3.465V, V_IN= 0V

-5

μA

Input Low Current (PLL_BYPASS),

(N_SEL0), (NSEL1)

-150

AC Electrical Characteristics⁽⁸⁾

V_DDA= V_DD= 3.3V ±5% or 2.5V ±5%, V_DDO= 2.5V or 3.3V ±5%, T_A= –40°C to +85°C, unless noted.

Symbol

F_OUT

Parameter

Condition

Min

Typ

Max

Units

MHz

Output Frequency

RMS Phase Jitter (Random)

Refer to Frequency Table

125MHz, Integration Range:

(1.875MHz – 20MHz)

Note 9

625

T_jit(∅)

T_SKEW

T_R/T_F

ODC

Output-to-Output Skew

LVDS Output Rise/Fall Time

Output Duty Cycle

300

20% – 80%

100

160

T_LOCK

Notes:

PLL Lock Time

5. See Figure 4 for load test circuit example.

6. The circuit is designed to meet the DC specifications shown in the above table(s) after thermal equilibrium has been established.

7. Outputs terminated 100Ω between Q and /Q. All unused outputs must be terminated.

8. The circuit is designed to meet the AC specifications shown in the above table(s) after thermal equilibrium has been established.

9. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points.

M9999-072110-B

July 2010

Micrel, Inc.

SM844256

Phase Noise Plot: 125MHz @ 3.3V

Figure 1. Duty Cycle Timing

Figure 2. All Outputs Rise/Fall Time

M9999-072110-B

July 2010

Micrel, Inc.

SM844256

Figure 3. RMS Phase Noise/Jitter

Figure 4. LVDS Output Load and Test Circuit

Figure 5. Crystal Input Interface

M9999-072110-B

July 2010

Micrel, Inc.

SM844256

Package Information

24-pin Epad TSSOP

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its

use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product

can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant

into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully

indemnify Micrel for any damages resulting from such use or sale.

M9999-072110-B

July 2010

SM844256 [MICREL]

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