SY100E150JC [MICREL]

6-BIT D LATCH; 6位D锁存


型号：	SY100E150JC
厂家：	MICREL SEMICONDUCTOR
描述：	6-BIT D LATCH 6位D锁存
文件：	总4页 (文件大小：63K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

6-BIT D

LATCH

SY10E150

SY100E150

DESCRIPTION

FEATURES

■ 700ps max. propagation delay

■ Extended 100E VEE range of –4.2V to –5.5V

■ Differential outputs

The SY10/100E150 are 6-bit D latches with differential

outputs designed for use in new, high- performance ECL

systems. When both Latch Enables (LEN1, LEN2) are at a

logic LOW, the latch is in the transparent mode and input

data propagates through to the output. A logic HIGH on

either LEN1 or LEN2 (or both) latches the input data. The

Master Reset (MR) overrides all other signals to set the Q

outputs to a logic LOW.

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E150

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN CONFIGURATION

24 23 22 21 20 19

PLCC

TOP VIEW

J28-1

VEE

10 11

LEN

PIN NAMES

D0–D5

LEN1, LEN2

Function

Data Inputs

Latch Enables

Master Reset

True Outputs

Q0–Q5

VCCO

Inverting Outputs

VCC to Output

Rev.: D

Amendment: /0

Issue Date: November, 1998

SY10E150

SY100E150

Micrel

TRUTH TABLE⁽¹⁾

(Each Latch)

INPUTS

OUTPUTS

Operating

Mode

LEN1

LEN2

Latch

(2)

Latched

(2)

Latched

Asynchronous

NOTES:

1. H = HIGH state

L = LOW state

X = Don’t care

2. Retains Data that is present before the LEN positive transition.

DC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

IIH

Input HIGH Current

µA

—

200

150

—

200

150

—

200

150

LEN MR

IEE

Power Supply Current

—

10E

100E

—

SY10E150

SY100E150

Micrel

AC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

tPLH

tPHL

Propagation Delay to Output

LEN

—

250 375 550 250 375

375 500 700 375 500

450 625 750 450 625

550 250 375

700 375 500

750 450 625

550

700

750

Set-up Time, D

200

—

200

—

200

—

Hold Time, D

200 –50

tRR

tPW

tskew

Reset Recovery Time

Minimum Pulse Width, MR

Within-Device Skew

750 650

—

400

—

400

—

400

—

Rise/Fall Time

20% to 80%

300 450 650 300 450

650 300 450

650

—

NOTE:

1. Within-device skew is defined as identical transitions on similar paths through a device.

PRODUCT ORDERING CODE

Ordering

Code

Package

Type

Operating

Range

SY10E150JC

J28-1

Commercial

SY10E150JCTR

SY100E150JC

SY100E150JCTR

SY10E150

SY100E150

Micrel

28 LEAD PLCC (J28-1)

Rev. 03

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.