SY100E445JCTR [MICREL]

4-BIT SERIAL-to-PARALLEL CONVERTER; 4比特串行并行变换器


型号：	SY100E445JCTR
厂家：	MICREL SEMICONDUCTOR
描述：	4-BIT SERIAL-to-PARALLEL CONVERTER 4比特串行并行变换器移位寄存器触发器逻辑集成电路输出元件
文件：	总8页 (文件大小：84K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

4-BIT SERIAL-to-PARALLEL

CONVERTER

SY10E445

SY100E445

FEATURES

DESCRIPTION

■ On-chip clock ÷4 and ÷8

The SY10/100E445 are integrated 4-bit serial-to-parallel

data converters. The devices are designed to operate for

NRZ data rates of up to 2.5Gb/s. The chip generates a

divide-by-4 and a divide-by-8 clock for both 4-bit conversion

and a two-chip 8-bit conversion function. The conversion

sequence was chosen to convert the first serial bit to Q0,

the second to Q1, etc.

Two selectable serial inputs provide a loopback capability

for testing purposes when the device is used in conjunction

with the E446 parallel-to-serial converter.

The start bit for conversion can be moved using the

SYNC input. A single pulse, applied asynchronously for at

least two input clock cycles, shifts the start bit for conversion

from Qn to Qn-1 by one bit. For each additional shift required,

an additional pulse must be applied to the SYNC input.

Asserting the SYNC input will force the internal clock dividers

to "swallow" a clock pulse, effectively shifting a bit from the

Qn to the Qn-1 output (see Timing Diagram B).

■ Extended 100E VEE range of –4.2V to –5.5V

■ 2.5Gb/s data rate capability

■ Differential clock and serial inputs

■ VBB output for single-ended use

■ Asynchronous data synchronization

■ Mode select to expand to 8 bits

■ Internal 75kΩ input pull-down resistors

■ Fully compatible with Motorola MC10E/100E445

■ Available in 28-pin PLCC package

PIN CONFIGURATION

The MODE input is used to select the conversion mode

of the device. With the MODE input LOW (or open) the

device will function as a 4-bit converter. When the mode

input is driven HIGH, the data on the output will change on

every eighth clock cycle, thus allowing for an 8-bit conversion

scheme using two E445s. When cascaded in an 8-bit

conversion scheme, the devices will not operate at the

2.5Gb/s data rate of a single device. Refer to the applications

section of this data sheet for more information on cascading

the E445.

For lower data rate applications, a VBB reference voltage

is supplied for single-ended inputs. When operating at clock

rates above 500MHz, differential input signals are

recommended. For single-ended inputs, the VBB pin is tied

to the inverting differential input and bypassed via a 0.01µF

capacitor. The VBB provides the switching reference for the

input differential amplifier. The VBB can also be used to AC

couple an input signal.

24 23 22 21 20 19

INB

OUT

SEL

TOP VIEW

PLCC

J28-1

CLK

CCO

10 11

PIN NAMES

SINA, SINA

SINB, SINB

SEL

Function

Differential Serial Data Input A

Differential Serial Data Input B

Serial Input Select Pin

SOUT, SOUT

Q0–Q3

Differential Serial Data Output

Parallel Data Outputs

CLK, CLK

CL/4, CL/4

CL/8, CL/8

MODE

Differential Clock Inputs

Differential ÷4 Clock Output

Differential ÷8 Clock Output

Conversion Mode 4-bit/8-bit

Conversion Synchronizing Input

Input, Resets the Counters

VCC to Output

SYNC

RESET

VCCO

Rev.: D

Amendment:/0

Issue Date: October, 1998

SY10E445

Micrel

SY100E445

BLOCK DIAGRAM

SINB

SINA

SEL

SOUT

CL/4

÷4

CLK

CL/4

÷2

CL/8

MODE

RESET

SYNC

VBB

SY10E445

Micrel

SY100E445

TRUTH TABLES

LOGIC DIAGRAM

Mode

Conversion

4-Bit

SEL

Serial Input

8-Bit

DC CHARACTERISTICS

LOGIC DI GRAM

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

IIH

Parameter

Input HIGH Current

Output HIGH Voltage

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

—

150

—

150

—

150

µA

—

VOH

(SOUT only) 10E –1020

(SOUT only) 100E –1025

—

–790 –980

–830 –1025

—

–760 –910

–830 –1025

—

–670

–830

VBB

IEE

Output Reference Voltage

10E –1.38

100E –1.38

—

–1.27 –1.35

–1.26 –1.38

—

–1.25 –1.31

–1.26 –1.38

—

–1.19

–1.26

Power Supply Current

—

10E

100E

—

154

185

—

154

185

—

154

177

185

212

NOTE:

1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E

and 100E VOH levels.

AC CHARACTERISTICS

LOGIC DI GRAM

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

fMAX

Max. Conversion Frequency

2.0

2.5

—

2.0

2.5

—

2.0

2.5

—

Gb/s

NRZ

tPLH

tPHL

Propagation Delay to Output

CLK to Q

CLK to SOUT

—

1500 1800 2100 1500 1800 2100 1500 1800 2100

800 975 1150 800 975 1150 800 975 1150

CLK to CL/4

CLK to CL/8

1100 1325 1550 1100 1325 1550 1100 1325 1550

Set-up Time

SINA, SINB

SEL

—

–100 –250

—

–100 –250

—

–100 –250

—

–200

300

—

–200

300

—

–200

300

—

Hold Time, SINA, SINB, SEL

Reset Recovery Time

450

500

400

—

450

500

400

—

450

500

400

—

tRR

tPW

Minimum Pulse Width

CLK, MR

Rise/Fall Times

20% to 80%

SOUT

—

100

200

225

425

350

650

100

200

225

425

350

650

100

200

225

425

350

550

Other

NOTES:

1. Guaranteed for input clock amplitudes of 150mV to 800mV.

2. Guaranteed for input clock amplitudes of 150mV to 400mV.

SY10E445

Micrel

SY100E445

LAOPGPLICICDAITAIGORNASMINFORMATION

Clock

The SY10/100E are integrated 1:4 serial-to-parallel

converters. The chips are designed to work with the

E446 devices to provide both transmission and receiving

of a high-speed serial data path. The E445, under special

input conditions, can convert up to a 2.5Gb/s NRZ data

stream into 4-bit parallel data. The device also provides

a divide-by-four clock output to be used to synchronize

the parallel data with the rest of the system.

E445a

E445b

SIN

SOUT

SIN

Serial Input

Data

The E445 features multiplexed dual serial inputs to

provide test loop capability when used in conjunction

with the E446. Figure 1 illustrates the loop test

architecture. The architecture allows for the electrical

testing of the link without requiring actual transmission

over the serial data path medium. The SINA serial input

of the E445 has an extra buffer delay and, thus, should

be used as the loop back serial input.

Parallel Output Data

100ps

Clock

Tpd CLK

to SOUT

800ps

SOUT

To Serial

Medium

1050ps

SOUT

Parallel

Data

Figure 2. Cascaded 1:8 Converter Architecture

clock-to-serial-out would potentially cause a serial bit to

be swallowed (Figure 3). With a minimum delay of 800ps

on this output, the clock for the lower order E445 cannot

be delayed more than 800ps relative to the clock of the

first E445 without potentially missing a bit of information.

Because the set-up time on the serial input pin is

negative, coincident excursions on the data and clock

inputs of the E445 will result in correct operation.

SINA

Parallel

Data

SINB

From Serial

Medium

Figure 1. Loop Test Architecture

Clock a

Clock b

The E445 features a differential serial output and a

divide-by-8 clock output to facilitate the cascading of two

devices to build a 1:8 demultiplexer. Figure 2 illustrates

the architecture of a 1:8 demultiplexer using two E445s.

The timing diagram for this configuration can be found

on the following page. Notice the serial outputs (SOUT)

of the lower order converter feed the serial inputs of the

higher order device. This feedthrough of the serial inputs

bounds the upper end of the frequency of operation. The

clock-to-serial output propagation delay, plus the set-up

Tpd CLK

to SOUT

800ps

1050ps

Figure 3. Cascade Frequency Limitation

Perhaps the easiest way to delay the second clock

time of the serial input pins, must fit into a single clock relative to the first is to take advantage of the differential

period for the cascade architecture to function properly. clock inputs of the E445. By connecting the clock for the

Using the worst case values for these two parameters second E445 to the complimentary clock input pin, the

from the data sheet, tPD CLK to SOUT = 1150ps or a device will clock a half a clock period after the first E445

clock frequency of 950MHz.

(Figure 4). Utilizing this simple technique will raise the

The clock frequency is significantly lower than that of potential conversion frequency up to 1.5GHz. The divide-

a single converter. To increase this frequency, some by-eight clock of the second E445 should be used to

games can be played with the clock input of the higher synchronize the parallel data to the rest of the system as

order E445. By delaying the clock feeding the second the parallel data of the two E445s will no longer be

E445 relative to the clock of the first E445, the frequency synchronized. This skew problem between the outputs

of operation can be increased. The delay between the can be worked around as the parallel information will be

two clocks can be increased until the minimum delay of static for eight more clock pulses.

SY10E445

Micrel

SY100E445

TLIOMGINICGDDIIAAGGRRAAMMS

CLK

Dn–4

Dn–3

Dn–2

Dn–1

Dn+1

Dn+2

Dn+3

SIN

RESET

Dn–4

Dn–3

Dn–2

Dn–1

Dn+1

Dn+2

Dn+3

SOUT

CL/8

Dn–4

Dn–3

Dn–2

Dn–1

Dn+1

Dn+2

Dn+3

CL/4

Timing Diagram A. 1:4 Serial to Parallel Conversion

CLK

Dn–4

Dn–3

Dn–2

Dn–1

Dn+1

Dn+2

Dn+3

Dn+4

SIN

RESET

SYNC

Dn–4

Dn+1

Dn+2

Dn+3

Dn+4

Dn+3

Dn–3

Dn–2

Dn–1

Dn–2

SOUT

Dn–4

Dn–3

Dn–1

Dn+1

Dn+2

Dn+4

CL/4

CL/8

Timing Diagram B. 1:4 Serial to Parallel Conversion with SYNC Pulse

SY10E445

Micrel

SY100E445

667ps

(1.5GHz)

Clock

100ps

Clock a

Clock b

E445a

E445b

SIN

SOUT

SIN

Serial Input

Data

Tpd CLK

to SOUT

800ps

1050ps

Parallel Output Data

Figure 4. Extended Frequency 1:8 Demultiplexer

CLK

SINa

Dn–4

Dn–3

Dn–2

Dn–1

Dn+1

Dn+2

Dn+3

Dn+4

Dn–4

Dn–3

Dn–2

Dn–1

Q4 (Q0 a)

Q5 (Q1 a)

Dn+1

Dn+2

Dn+3

Q6 (Q2 a)

Q7 (Q3 a)

SOUTa

Dn–4

Dn–3

Dn–2

Dn–1

Dn–4

Dn–3

Dn+1

Dn+2

Dn–1

Dn+3

Dn–2

Dn+1

SOUTb

CL/4a

CL/4b

CL/8a

CL/8b

Timing Diagram

PRODUCT ORDERING CODE

Ordering

Code

Package

Type

Operating

Range

SY10E445JC

J28-1

Commercial

SY10E445JCTR

SY100E445JC

SY100E445JCTR

SY10E445

Micrel

SY100E445

28 LEAD PLCC (J28-1)

Rev. 03

SY10E445

Micrel

SY100E445

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

SY100E445JCTR [MICREL]

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