SY100H841ZC [MICREL]
SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE; 单电源四路PECL -TO -TTL W /输出锁存使能型号: | SY100H841ZC |
厂家: | MICREL SEMICONDUCTOR |
描述: | SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE |
文件: | 总6页 (文件大小:74K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ClockWorks™
SY10H841
SY100H841
FINAL
SINGLE SUPPLY QUAD
PECL-TO-TTLW/LATCHED
OUTPUT ENABLE
FEATURES
DESCRIPTION
■ Translates positive ECL to TTL (PECL-to-TTL)
■ 300ps pin-to-pin skew
The SY10/100H841 are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 50pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled low by the internal pull-
downs) the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
■ 500ps part-to-part skew
■ Differential internal design for increased noise
immunity and stable threshold inputs
■ VBB reference output
■ Single supply
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H841 solves several clock distribution
problems such as minimizing skew (300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
■ Enable input
■ Latch enable input
■ Extra TTL and ECL power/ground pins to reduce
cross-talk/noise
■ High drive capability: 24mA each output
■ Fully compatible with industry standard 10K, 100K
I/O levels
■ Available in 16-pin SOIC package
PIN CONFIGURATION
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
3
LEN
EN
Q
Q
Q
Q
0
1
2
3
G
T
2
GE
Q
VE
SOIC
Z16-1
V
T
T
D
V
Q
G
Q
1
T
0
D
VBB
GT
V
BB
D
D
D Q
PIN NAMES
LEN
EN
Pin
GT
Function
TTL Ground (0V)
VT
TTL VCC (+5.0V)
VE
ECL VCC (+5.0V)
GE
ECL Ground (0V)
D, D
VBB
Q0 - Q3
EN
Signal Input (PECL)
VBB Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Latch Enable Input
LEN
Rev.: F
Amendment:/0
Issue Date: May, 1999
1
ClockWorks™
SY10H841
Micrel
SY100H841
PIN DESCRIPTION
TRUTH TABLE
D
L
LEN
L
EN
L
Q
L
Pin
1
Symbol
LEN
EN
GE
VE
Description
Latch Enable Input
H
X
X
L
L
H
2
Enable Input (PECL)
ECL Ground (0V)
ECL VCC (+5.0V)
X
H
L
L
3
H
Latch
4
5
D
ECL Signal Input (Non-inverting)
ECL Signal Input (Inverting)
VBB Reference Output (PECL)
TTL Ground (0V)
(1)
ABSOLUTE MAXIMUM RATINGS
6
D
7
VBB
GT
Symbol
Rating
Value
Unit
8
VE (ECL)
VT (TTL)
Power Supply
Voltage
–0.5 to +7.0
–0.5 to +7.0
V
9
Q0
Signal Output (TTL)
TTL Ground (0V)
10
11
12
13
14
15
16
GT
VI (ECL)
VOUT (TTL)
Input Voltage
0.0 to VEE
0.0 to VT
V
Q1
Signal Output (TTL)
TTL VCC (+5.0V)
VT
Tstore
TA
Storage Temperature
Operating Temperature
–65 to +150
0 to +85
˚C
˚C
VT
TTL VCC (+5.0V)
Q2
Signal Output (TTL)
TTL Ground (0V)
NOTE:
1. PermanentdevicedamagemayoccurifABSOLUTEMAXIMUMRATINGS
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections
ofthisdatasheet. ExposuretoABSOLUTEMAXIMUMRATlNGconditions
for extended periods may affect device reliability.
GT
Q3
Signal Output (TTL)
VCC AND CLOAD
Ranges to meet duty cycle requirement: 0°C ≤ TA ≤ 85°C. Output duty cycle measured relative to 1.5V.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
All Outputs
PW
Ranges of VCC and CL to meet min.
pulse width (HIGH or LOW) at
fOUT ≤ 40MHz
VCC
CL
PW
4.75
10
11
5.0
—
—
5.25
50
—
V
pF
ns
PW
Ranges of VCC and CL to meet min.
pulse width (HIGH or LOW) at
fOUT ≤ 50MHz
VCC
CL
PW
4.875
15
9.0
5.0
—
—
5.125
27
—
V
pF
ns
All Outputs
DC CHARACTERISTICS
VT = VE = 5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IEE
Parameter
Min.
Max.
40
Min.
—
Max.
40
Min.
Max.
40
Unit
Condition
VE Pin
Total all VT pins
Power Supply Current
Power Supply Current
ECL
TTL
—
—
—
—
—
—
mA
mA
ICCH
20
—
20
20
ICCL
25
—
25
25
2
ClockWorks™
SY10H841
Micrel
SY100H841
TTL DC ELECTRICAL CHARACTERISTICS
VT = VE = +5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
VOH
Output HIGH Voltage
2.5
2.0
—
—
2.5
2.0
—
—
2.5
2.0
—
—
V
IOH = –3.0mA
IOH = –15mA
VOL
IOS
Output LOW Voltage
—
0.5
—
0.5
—
0.5
V
IOL = 24mA
VOUT = 0V
Output Short Circuit Current
–80
–200
–80
–200
–80
–200
mA
(1)
10H ECL DC ELECTRICAL CHARACTERISTICS
VT = VE = +5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IIH
Parameter
Input HIGH Current
Input LOW Current
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
Min.
Max.
225
Min.
—
Max.
Min.
—
Max.
175
Unit
µA
µA
V
Condition
—
—
175
—
IIL
0.5
—
0.5
0.5
—
—
VIH
3.830
3.050
3.620
4.160
3.520
3.730
3.870
3.050
3.650
4.190
3.520
3.750
3.940
3.050
3.690
4.280
3.555
3.810
VE = 5.0V
VE = 5.0V
VE = 5.0V
VIL
V
VBB
V
NOTE:
1. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = +5.0V.
(1)
100H ECL DC ELECTRICALCHARACTERISTICS
VT = VE = +5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IIH
Parameter
Input HIGH Current
Input LOW Current
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
Min.
Max.
225
Min.
Max.
175
Min.
Max.
175
Unit
µA
µA
V
Condition
—
—
—
—
IIL
0.5
—
0.5
—
0.5
—
—
VIH
3.835
3.190
3.620
4.120
3.525
3.740
3.835
3.190
3.620
4.120
3.525
3.740
3.835
3.190
3.620
4.120
3.525
3.740
VE = 5.0V
VE = 5.0V
VE = 5.0V
VIL
V
VBB
V
NOTE:
1. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = +5.0V.
3
ClockWorks™
SY10H841
Micrel
SY100H841
AC CHARACTERISTICS
VT = VE = 5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Propagation Delay
D to Output
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
tPLH
tPHL
Q0–Q3
2.7
3.7
2.7
3.7
2.7
3.7
ns
CL = 50pF
tskpp
Part-to-Part Skew(1,4)
Within-Device Skew(2,4)
Within-Device Skew(3,4)
Q0–Q3
Q0–Q3
Q0–Q3
Q0–Q3
—
—
0.5
0.3
0.3
3.7
—
—
0.5
0.3
0.3
3.7
—
—
0.5
0.3
0.3
3.7
ns
ns
ns
ns
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
tskew++
tskew– –
—
—
—
tPLH
tPHL
Propagation Delay
LEN to Q
2.7
2.7
2.7
tPLH
tPHL
Propagation Delay
EN to Output
Q0–Q3
Q0–Q3
2.7
—
3.7
1.5
2.7
—
3.7
1.5
2.7
—
3.7
1.5
ns
ns
CL = 50pF
CL = 50pF
tr
tf
Output Rise/Fall Time
1.0V to 2.0V
fMAX
—
Max. Input Frequency(5,6)
Pulse Width
Q0–Q3
Q0–Q3
Q0–Q3
Q0–Q3
Q0–Q3
160
1.5
—
—
—
—
—
160
1.5
—
—
—
—
—
160
1.5
—
—
—
—
—
MHz
ns
CL = 50pF
—
—
—
—
—
Recovery Time EN
Set-up Time D, EN
Hold Time D, EN
1.0
1.0
1.0
ns
tS
0.75
0.75
0.75
0.75
0.75
0.75
ns
tH
ns
NOTES:
1. Device-to-Device Skew considering HIGH-to-HIGH transitions at common VCC level.
2. Within-Device Skew considering HIGH-to-HIGH transitions at common VCC level.
3. Within-Device Skew considering LOW-to-LOW transitions at common VCC level.
4. All skew parameters are guaranteed but not tested.
5. Frequency at which output levels will meet at 0.8V to 2.0V minimum swing.
6. The fMAX value is specified as the minimum guaranteed maximum frequency. Actual operational maximum frequency may be greater.
PRODUCTORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY10H841ZC
Z16-1
Z16-1
Z16-1
Z16-1
Commercial
Commercial
Commercial
Commercial
SY10H841ZCTR
SY100H841ZC
SY100H841ZCTR
4
ClockWorks™
SY10H841
Micrel
SY100H841
TTL SWITCHING CIRCUIT
V
EE
V
CC & VCCO
USE 0.1µF CAPACITORS
FOR DECOUPLING.
PECL
IN
TTL
50Ω COAX
DEVICE
UNDER
TEST
OUT
PULSE
GENERATOR
450Ω
50Ω COAX
50Ω COAX
USE OSCILLOSCOPE
INTERNAL 50Ω LOAD
FOR TERMINATION.
CH A
CH B
OSCILLOSCOPE
ECL/TTL PROPAGATION DELAY — SINGLE ENDED
50%
VIN
Tpd++
Tpd– –
1.5V
VOUT
ECL/TTL WAVEFORMS: RISE AND FALL TIMES
2.0V
0.8V
V
OUT
T
rise
Tfall
5
ClockWorks™
SY10H841
Micrel
SY100H841
16 LEAD SOIC .300" WIDE (Z16-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
6
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