SY100S318JC [MICREL]
5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE; 5-宽5 ， 4,4 ， 4,2的OA / OAI门
| 型号： | SY100S318JC |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE |
| 文件： | 总5页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5-WIDE 5, 4, 4, 4, 2
OA/OAI GATE
SY100S318
DESCRIPTION
FEATURES
■ Max. propagation delay of 800ps
■ IEE min. of –55mA
The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/
AND gate with both true and complementary outputs,
designed for use in high-performance ECL systems. The
inputs on this device have 75KΩ pull-down resistors.
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for
PIN CONFIGURATIONS
improved noise immunity
■ Internal 75KΩ input pull-down resistors
■ 70% faster than Fairchild
■ 40% lower power than Fairchild
11 10 9
8 7 6 5
■ Function and pinout compatible with Fairchild F100K
D2b
D3b
12
13
14
15
16
17
18
4
3
O
■ Available in 24-pin CERPACK and 28-pin PLCC
O
packages
VEE
VEES
D4b
2
VCCA
VCC
VCC
D2e
D1e
Top View
PLCC
J28-1
1
28
27
26
D1c
D2c
19 20 21 22 23 24 25
BLOCK DIAGRAM
D
D
D
D
D
1a
2a
3a
4a
5a
24 23 22 21 20 19
1
2
3
4
5
6
18
17
16
15
14
13
D
D
D
D
3c
4c
1d
2d
D
D
D
D
D
D
1b
5a
4a
3a
2a
1a
Top View
Flatpack
F24-1
D
D
D
D
1b
2b
3b
4b
D
3d
4d
D
7
8 9 10 11 12
D
D
D
D
1c
2c
3c
4c
O
O
D
D
D
D
1d
2d
3d
4d
PIN NAMES
Pin
Dna – Dne
O – O
Function
D
D
1e
2e
Data Inputs (n = 1...5)
Data Outputs
VEES
VEE Substrate
VCCA
VCCO for ECL Outputs
Rev.: G
Amendment:/0
Issue Date: July, 1999
1
SY100S318
Micrel
LOGIC EQUATION
O = (D1a + D2a + D3a + D4a + D5a)
(D1b + D2b + D3b + D4b)
(D1c + D2c + D3c + D4c)
(D1d + D2d + D3d + D4d)
(D1e + D2e)
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol
IIH
Parameter
Input HIGH Current, All Inputs
Power Supply Current
Min.
—
Typ.
—
Max.
200
Unit
µA
Condition
VIN = VIH (Max.)
Inputs Open
IEE
–55
–41
–25
mA
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C TA = +25°C
TA = +85°C
Symbol
Parameter
Propagation Delay
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
tPLH
tPHL
300
900
300
900
300
900
ps
Data to Output
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
200
900
200
900
200
900
ps
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C TA = +25°C
TA = +85°C
Symbol
Parameter
Propagation Delay
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
tPLH
tPHL
300
800
300
800
300
800
ps
Data to Output
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
200
900
200
900
200
900
ps
2
SY100S318
Micrel
TIMING DIAGRAM
0.7 ± 0.1 ns
0.7 ± 0.1 ns
INPUT
–0.95V
–1.69V
80%
50%
20%
t
t
PHL
PLH
tPLH
TRUE
50%
OUTPUT
tPHL
80%
50%
20%
COMPLEMENT
t
TLH
tTHL
Propagation Delay and Transition Times
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100S318FC
SY100S318JC
SY100S318JCTR
F24-1
J28-1
J28-1
Commercial
Commercial
Commercial
3
SY100S318
Micrel
24 LEAD CERPACK (F24-1)
Rev. 03
4
SY100S318
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
5
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