SY100S336A [MICREL]
ENHANCED 4-STAGE COUNTER/SHIFT REGISTER; 强化4级计数器/移位寄存器
| 型号： | SY100S336A |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | ENHANCED 4-STAGE COUNTER/SHIFT REGISTER |
| 文件： | 总9页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ENHANCED 4-STAGE
COUNTER/SHIFT REGISTER
SY100S336A
FEATURES
DESCRIPTION
ꢀ Max. shift frequency of 700MHz
ꢀ Clock to Q delay max. of 1100ps
ꢀ Sn to TC speed improved by 50%
ꢀ Sn set-up and hold time reduced by more than 50%
ꢀ IEE min. of –170mA
The SY100S336A is functionally the same as the
SY100S336, but has Sn to TC speed and Sn set-up and
hold times significantly improved, allowing for higher clock
frequency when used as a cascaded multi-stage counter.
The SY100S336A functions either as a modulo-16 up/
down counter or as a 4-bit bidirectional shift register and is
designed for use in high-performance ECL systems. Three
Select inputs (Sn) are provided for determining the mode of
operation. The Function Table lists the available modes of
operation. In order to allow cascading for multistage
counters, two Count Enable controls (CEP, CET) are
ꢀ Industry standard 100K ECL levels
ꢀ Internal 75KΩ input pull-down resistors
ꢀ Extended supply voltage option:
VEE = –4.2V to –5.5V
ꢀ Voltage and temperature compensation for improved provided. The CET input also functions as the Serial Data
noise immunity
input (S0) for a shift-up operation, while the D3 input serves
as the Serial Data input for the shift-down operation.
When the device is in the counting mode, the Terminal
Count (TC) goes to a logical LOW when the count reaches
15 for count-up or reaches 0 for count-down. When in the
shift mode, the TC output simply repeats the Q3 output.
The flexiblity provided by the TC/Q3 output and the D0/
CET input allows these signals to be interconnected from
one stage to the next higher stage for multistage counting
or shift-up operations. The individual Presets (Pn) allow
initialization of the counter by entering data in parallel to
preset the counter. A logic HIGH on the Master Reset (MR)
overrides all other inputs and asynchronously clears the
flip-flops. An additional synchronous Clear is provided, as
well as a complement function which synchronously inverts
the contents of the flip-flops. All inputs have 75KΩ pull-
down resistors.
ꢀ 50% faster than Fairchild 300K at lower power
ꢀ Function and pinout compatible with Fairchild F100K
ꢀ Available in 24-pin CERPACK and 28-pin PLCC
packages
PIN CONFIGURATIONS
11 10 9
8 7 6 5
P
0
12
13
14
15
16
17
18
4
3
Q
Q
2
2
CP
VEE
2
V
V
V
CCA
Top View
PLCC
J28-1
V
EES
1
CC
MR
28
27
26
CC
PIN NAMES
S
0
1
Q
Q
1
1
S
19 20 21 22 23 24 25
Pin
Function
Clock Pulse Input
CP
CEP
Count Enable Parallel Input (Active LOW)
D0/CET
Serial Data Input/Count Enable Trickle
Input (Active LOW)
24 23 22 21 20 19
18
1
2
3
4
5
6
S2
CEP
D0/CET
TC
P1
P2
P3
D3
Q3
Q3
17
16
15
14
13
S0 — S2
MR
Select Inputs
Top View
Flatpack
F24-1
Master Reset Input
VEE Substrate
VEES
Q0
VCCA
VCCO for ECL Outputs
Preset Inputs
Q0
7
8 9 10 11 12
P0 – P3
D3
Serial Data Input
Terminal Count Output
Data Outputs
TC
Q0 — Q3
Q0 — Q3
Complementary Data Outputs
Rev.: G
Amendment:/0
Issue Date: July, 1999
1
SY100S336A
Micrel
BLOCK DIAGRAM
D3
D0/CET
S0
CEP
S
1
2
S
TC
T
T
T
Q
Q
0
0
Q
1
Q
2
Q3
T
T
T
T
T
T
T
T
R
T
Q1
Q
2
Q3
R
T
R
T
R
T C
T
C
T C
T C
CP
MR
P0 Q0 Q0
P1 Q1 Q1 P2 Q2 Q2 P3 Q3 Q3
2
SY100S336A
Micrel
TRUTH TABLE(1)
Inputs
Outputs
MR
L
S2
L
S1
L
S0
L
CEP
X
D0/CET
D3
X
CP
u
Q0
P0
Q0
Q1
D0
Q1
P1
Q1
Q2
Q0
Q2
Q3
P3
Q3
D3
Q2
TC
L
Mode
X
X
X
X
L
P2
Q2
Q3
Q1
Preset (Parallel Load)
Invert
L
L
L
H
L
X
X
u
L
L
L
H
H
L
X
X
u
D3
Q3*
ꢀ
ꢀ
Shift Left
L
L
H
L
X
X
u
Shift Right
L
H
H
L
X
u
(Q0–3) minus 1
Count Down
L
L
L
H
L
X
X
Q0
Q0
Q1
Q2
Q3
Q3
Count Down with CEP
Not Active
Count Down with CET
Not Active
L
H
L
L
X
H
X
X
Q1
Q2
H
L
L
L
H
H
H
L
H
H
H
L
L
X
L
X
L
L
X
X
X
u
u
X
L
L
L
L
H
≠
Clear
(Q0–3) plus 1
Count Up
H
Q0
Q0
Q1
Q2
Q3
Q3
≠
Count Up with CEP
Not Active
Count Up with CET
Not Active
L
H
H
L
X
H
X
X
Q1
Q2
H
L
H
H
H
X
X
X
X
Q0
Q1
Q2
Q3
H
Hold
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
L
L
H
H
L
H
L
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
Asynchronous Master
Reset
L
H
H
H
H
H
H
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
u = LOW-to-HIGH Transition
ꢀꢀ= L if Q0 – Q3 = LLLL
H if Q0 – Q3 ≠ LLLL
≠ ꢀ= L if Q0 – Q3 = HHHH
H if Q0 – Q3 ≠ HHHH
* Before the clock, TC is Q3; after the clock, TC is Q2
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol
IIH
Parameter
Min.
—
Typ.
—
Max.
200
Unit
µA
Condition
VIN = VIH (Max.)
Inputs Open
Input HIGH Current, All Inputs
Power Supply Current
IEE
–170
–120
–60
mA
3
SY100S336A
Micrel
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Shift Frequency
Min.
Max.
—
Min.
700
450
Max.
—
Min.
700
450
Max.
—
Unit
MHz
ps
Condition
fshift
700
450
tPLH
tPHL
Propagation Delay
CP to Qn, Qn
1200
1200
1200
tPLH
tPHL
Propagation Delay
CP to TC
600
500
600
400
400
300
1900
1400
1900
1200
1500
900
600
500
600
400
400
300
1900
1400
1900
1200
1500
900
600
500
600
400
400
300
1900
1400
1900
1200
1500
900
ps
ps
ps
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
MR to Qn, Qn
tPLH
tPHL
Propagation Delay
MR to TC
tPLH
tPHL
Propagation Delay
D0/CET to TC
tPLH
tPHL
Propagation Delay
Sn to TC
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
tS
Set-up Time
D3
Pn
800
800
700
1000
900
—
—
—
—
—
800
800
700
1000
900
—
—
—
—
—
800
800
700
1000
900
—
—
—
—
—
D0/CET to CEP
Sn
MR (Release Time)
tH
Hold Time
D3
Pn
D0/CET to CEP
Sn
ps
ps
200
200
200
-200
—
—
—
—
200
200
200
-200
—
—
—
—
200
200
200
-200
—
—
—
—
tpw (H)
Pulse Width HIGH, CP, MR
—
800
—
800
—
800
4
SY100S336A
Micrel
AC ELECTRICAL CHARACTERISTICS
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Shift Frequency
Min.
Max.
—
Min.
700
450
Max.
—
Min.
700
450
Max.
—
Unit
MHz
ps
Condition
fshift
700
450
tPLH
tPHL
Propagation Delay
CP to Qn, Qn
1100
1100
1100
tPLH
tPHL
Propagation Delay
CP to TC
600
500
600
400
400
900
1800
1300
1800
1100
1500
300
600
500
600
400
400
900
1800
1300
1800
1100
1500
300
600
500
600
400
400
900
1800
1300
1800
1100
1500
ps
ps
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
MR to Qn, Qn
tPLH
tPHL
Propagation Delay
MR to TC
tPLH
tPHL
Propagation Delay
D0/CET to TC
tPLH
tPHL
Propagation Delay
Sn to TC
tTLH
tTHL
Transition Time300
20% to 80%, 80% to 20%
tS
Set-up Time
ps
D3
Pn
800
800
700
1000
900
—
—
—
—
—
800
800
700
1000
900
—
—
—
—
—
800
800
700
1000
900
—
—
—
—
—
D0/CET to CEP
Sn
MR (Release Time)
tH
Hold Time
D3
Pn
D0/CET to CEP
Sn
ps
ps
200
200
200
-200
—
—
—
—
200
200
200
-200
—
—
—
—
200
200
200
-200
—
—
—
—
tpw (H)
Pulse Width HIGH, CP, MR
—
800
—
800
—
800
5
SY100S336A
Micrel
TIMING DIAGRAMS
DATA
0.7 ± 0.1 ns
0.7 ± 0.1 ns
–0.95V
80%
50%
20%
CLOCK
–1.69V
1/fshift
tpw (H)
t
t
PHL
PLH
tPLH
OUTPUT
OUTPUT
50%
t
PHL
t
TLH
tTHL
Propagation Delay (Clock) and Transition Times
0.7 ± 0.1 ns
0.7 ± 0.1 ns
–0.95V
–1.69V
80%
50%
20%
MR
t
S
(RELEASE TIME)
50%
tpw (H)
CLOCK
OUTPUT
OUTPUT
t
t
PHL
PLH
tPLH
50%
t
PHL
80%
50%
20%
Propagation Delay (Reset)
6
SY100S336A
Micrel
TIMING DIAGRAMS
0.7 ± 0.1 ns
0.7 ± 0.1 ns
INPUT
–0.95V
–1.69V
80%
50%
20%
t
PHL
tPLH
80%
50%
20%
OUTPUT
t
TLH
tTHL
Propagation Delay (Serial Data, Selects)
INHIBIT COUNT
–0.95V
–1.69V
CEP
50%
ENABLE COUNT
t
H
t
t
S
–0.95V
D3
, P
n
, S
n
50%
–1.69V
–0.95V
t
H
S
CLOCK
50%
–1.69V
Set-up and Hold Time
NOTES:
1. VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND.
2. tS is the minimum time before the transition of the clock that information
must be present at the data input.
3. tH is the minimum time after the transition of the clock that information must
remain unchanged at the data input.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100S336AFC
SY100S336AJC
SY100S336AJCTR
F24-1
J28-1
J28-1
Commercial
Commercial
Commercial
7
SY100S336A
Micrel
24 LEAD CERPACK (F24-1)
Rev. 03
8
SY100S336A
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
9
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