SY100S370JCTR [MICREL]
UNIVERSAL DEMULTIPLEXER/ DECODER; 通用复用/解码器
| 型号： | SY100S370JCTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | UNIVERSAL DEMULTIPLEXER/ DECODER |
| 文件： | 总7页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNIVERSAL
SY100S370
DEMULTIPLEXER/
DECODER
FEATURES
DESCRIPTION
■ Max. propagation delay of 1200ps
■ IEE min. of –92mA
The SY100S370 is a universal demultiplexer/decoder
that can be used as either a dual 1-of-4 decoder or as a
single 1-of-8 decoder and is designed for use in high-
performance ECL systems. The Mode control (M) input
determines the function. In the dual 1-of-4 mode, each 4-
input group has a pair of active-LOW Enable (E) inputs.
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved The Enable pins are assigned such that in the single 1-of-
noise immunity
8 mode they can be tied together in pairs to result in two
active-LOW Enable inputs. E1a will be tied to E1b and E2a
to E2b.
The auxiliary inputs (Hn) are used to determine whether
the outputs are active-HIGH or active-LOW. The address
■ Internal 75KΩ input pull-down resistors
■ 60% faster than National or Signetics
■ Approximately 40% lower power than Fairchild
■ Function and pinout compatible with Fairchild F100K inputs for the dual 1-of-4 mode are A0a, A1a, A0b. A2a is
unused. In the 1-of-8 mode, the address inputs are A0a,
A1a, A2a. The inputs on the device have 75KΩ pull-down
resistors.
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
PIN CONFIGURATIONS
PIN NAMES
11 10 9
8 7 6 5
Pin
Ana, Anb
Ena, Enb
M
Function
E
1a
1b
12
13
14
15
16
17
18
4
3
Z
Z
0a (Z
0
)
)
E
3a (Z
3
Address Inputs (n = 0,1,2)
Enable Inputs (n = 1,2)
V
EE
EES
2b
2a
2
V
V
V
CCA
Top View
PLCC
V
1
CC
J28-1
E
28
27
26
CC
Mode Control Input
Z
Z
1b (Z
5
)
)
E
Ha
Z0 – Z3 (Z0a – Z3a) Polarity Select Input
Z4 – Z7 (Z0b – Z3b) Polarity Select Input
Common Polarity Select Input
Single 1-of-8 Data Outputs
Dual 1-of-4 Data Outputs (n = 1...4)
VEE Substrate
2b (Z
6
H
a
19 20 21 22 23 24 25
Hb
Hc
Z0 – Z7
Zna, Znb
VEES
VCCA
24 23 22 21 20 19
18
VCCO for ECL Outputs
1
2
3
4
5
6
H
c
A2a
H
b
17
16
15
14
13
M
Top View
Flatpack
F24-1
A
0b
1b
A
1a
0a
1a (Z
2a (Z
A
A
Z
3b (Z
7
)
Z
Z
1
)
)
Z
0b (Z
4
)
2
7
8
9 10 11 12
Rev.: G
Amendment:/0
1
Issue Date: July, 1999
SY100S370
Micrel
BLOCK DIAGRAM
A0a
Z2a (Z2)
Z0a (Z0)
Z1a (Z1)
Z3a (Z3)
A1a
E1a
E2a
A2a
M
Z2b (Z6)
Z0b (Z4)
Z1b (Z5)
Z3b (Z7)
A0b
A1b
E1b
E2b
Ha
Hc
Hb
2
SY100S370
Micrel
TRUTH TABLES(1)
Dual 1-of-4 Mode (M = A2a = Hc = LOW)
Active HIGH Outputs
Active LOW Outputs
Inputs
(Ha and Hb Inputs HIGH)
(Ha and Hb Inputs LOW)
E1a,E1b E2a,E2b A1a,A1b
A0a,A0b
Z0a,Z0b
Z1a,Z1b
Z2a,Z2b
Z3a,Z3b
Z0a,Z0b Z1a,Z1b
Z2a,Z2b
Z3a,Z3b
H
X
L
X
H
L
X
X
L
L
X
X
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
L
L
H
H
L
H
L
L
L
L
H
L
L
H
H
H
H
H
L
H
H
L
Single 1-of-8 Mode (M = HIGH; A0b = A1b = Ha = Hb = LOW)
Active HIGH Outputs* (Hc Input HIGH)
Inputs
E1
E2
A2a
A1a
A0a
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
H
X
X
H
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
H
L
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
* for Hc = LOW, output states are complemented
E1 = E1a and E1b wired; E2 = E2a and E2b wired
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
Symbol
Parameter
Input HIGH Current
Min.
Typ.
Max.
Unit
Condition
IIH
µA
VIN = VIH (Max.)
Hc, A0a, A1a, A2a
All Others
—
—
—
—
310
250
IEE
Power Supply Current
–92
–73
–46
mA
Inputs Open
3
SY100S370
Micrel
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Propagation Delay
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
tPLH
tPHL
300
500
500
600
300
1300
300
1300
300
1300
ps
Ena, Enb to Output
tPLH
tPHL
Propagation Delay
Ana, Anb to Output
1600
1600
2100
900
500
500
600
300
1600
1600
2100
900
500
500
600
300
1600
1600
2100
900
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
Ha, Hb, Hc to Output
tPLH
tPHL
Propagation Delay
M to Output
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
PLCC
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
TA = 0°C TA = +25°C
TA = +85°C
Symbol
Parameter
Propagation Delay
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Condition
tPLH
tPHL
300
500
500
600
300
1200
300
1200
300
1200
ps
Ena, Enb to Output
tPLH
tPHL
Propagation Delay
Ana, Anb to Output
1500
1500
2100
900
500
500
600
300
1500
1500
2100
900
500
500
600
300
1500
1500
2100
900
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
Ha, Hb, Hc to Output
tPLH
tPHL
Propagation Delay
M to Output
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
4
SY100S370
Micrel
TIMING DIAGRAM
0.7 ± 0.1 ns
0.7 ± 0.1 ns
INPUT
–0.95V
–1.69V
80%
50%
20%
tPHL
tPLH
80%
50%
20%
OUTPUT
tTLH
tTHL
Propagation Delay and Transition Times
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100S370FC
SY100S370JC
SY100S370JCTR
F24-1
J28-1
J28-1
Commercial
Commercial
Commercial
5
SY100S370
Micrel
24 LEAD CERPACK (F24-1)
Rev. 03
6
SY100S370
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
7
相关型号：
SY100S371JC-TR
100S SERIES, TRIPLE 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PQCC28
MICROCHIP
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