SY100S815ZCTR [MICREL]
SINGLE SUPPLY QUAD PECL/TTL-TO-PECL; 单电源四路PECL / TTL - TO- PECL
| 型号： | SY100S815ZCTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | SINGLE SUPPLY QUAD PECL/TTL-TO-PECL |
| 文件： | 总4页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SINGLE SUPPLY QUAD
PECL/TTL-TO-PECL
ClockWorks™
SY100S815
FEATURES
DESCRIPTION
The SY100S815 is a low skew 1-to-4 PECL differential
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin TEN.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S815 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. In
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
to maintain minimum skew.
■ Quad PECL version of popular ECLinPS E111
■ Low skew
■ Guaranteed skew spec
■ TTL enable input
■ Selectable TTL or PECL clock input
■ Single +5V supply
■ Differential internal design
■ PECL I/O fully compatible with industry standard
■ Internal 75kΩ PECL input pull-down resistors
■ Available in 16-pin SOIC package
BLOCK DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
EIN
0
EIN
1
TIN
PIN CONFIGURATION
TEN
16
15
14
13
12
11
10
9
VCC
1
2
3
4
5
6
7
8
EIN
TEN
VEE
EIN
TIN
PIN NAMES
TOP VIEW
SOIC
Q3
Q3
Q0
Q0
Z16-1
Pin
EIN, EIN
TIN
Function
Differential PECL Input Pair
TTL Input
Q2
Q1
Q1
Q2
TEN
TTL Input Enable
VCCO
VCCO
Q0, Q0 – Q3, Q3
Differential PECL Outputs
PECL VCC (+5.0V)
PECL Ground (0V)
VCC
VEE
Rev.: F
Amendment: /0
Issue Date: October, 1998
1
ClockWorks™
SY100S815
Micrel
TRUTH TABLE
TEN
L
EIN
L
TIN
X
Q
L
L
H
X
H
L
H
X
L
H
X
H
H
PECL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = +5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IIH
Parameter
Min.
—
Typ.
—
Max.
150
Min.
—
Typ.
Max.
150
Min.
—
Typ.
Max.
150
Unit
µA
µA
V
Input HIGH Current
Input LOW Current
Input HIGH Voltage(1)
Input LOW Voltage(1)
—
—
—
—
—
—
—
—
IIL
0.5
—
—
0.5
—
0.5
—
VIH
3.835
3.190
—
4.120
3.525
3.835
3.190
4.120
3.525
3.835
3.190
4.120
3.525
VIL
—
V
VOH
VOL
ICC
Output HIGH Voltage(2) VCC –1025 VCC –955 VCC –870 VCC –1025 VCC –955 VCC –870 VCC –1025 VCC –955 VCC –870 mV
Output LOW Voltage(2) VCC –1890 VCC –1705 VCC –1620 VCC –1890 VCC –1705 VCC –1620 VCC –1890 VCC –1705VCC –1620 mV
Power Supply(3)
Current
—
53
65
—
53
65
—
60
74
mA
NOTES:
1. VCC = VCCO = 5.0V
2. VIN = VIH (Max.) or VIL (Min.) Loading with 50Ω to VCC –2V.
3. All inputs and outputs open.
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = +5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
VIH
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Condition
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current(1),(2)
2.0
—
—
—
2.0
—
—
—
2.0
—
—
—
V
V
VIL
—
0.8
—
0.8
—
0.8
IIH
—
—
—
—
20
100
—
—
—
—
20
100
—
—
—
—
20
100
µA
IIL
Input LOW Current(3)
Input Clamp Voltage(4)
—
—
—
—
–0.6
–1.2
—
—
—
—
–0.6
–1.2
—
—
—
—
–0.6
–1.2
mA
V
VIK
NOTES:
1. VIN=2.7V
2. VIN=5.0V
3. VIN=0.5V
4. IIN=-18mA
2
ClockWorks™
SY100S815
Micrel
AC ELECTRICAL CHARACTERISTICS(1–6)
VCC = VCCO = +5.0V ± 5%
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
tPLH
tPHL
Propagation Delay to Output(1)
EIN (differential)(2)
EIN (single-ended)(3)
TIN
ps
430
330
350
—
—
—
630
730
950
430
330
350
—
—
—
630
730
950
430
330
350
—
—
—
630
730
950
tskew
VPP
Within-Device skew(4)
—
25
50
—
25
50
—
25
50
ps
Minimum PECL(5)
Input Swing
250
—
—
250
—
—
250
—
—
mV
VCMR
PECL Common(6)
Mode Range
–1.6
—
–0.4
–1.6
—
–0.4
–1.6
—
–0.4
V
tr
tf
Output Rise/Fall Times
20% to 80%
275
375
600
275
375
600
275
375
600
ps
NOTES:
1. Part-to-part skew is defined as Max. — Min. value at the given temperature.
2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min.) is AC limited for
the S815, as a differential input as low as 50mV will still produce full PECL levels at the output.
6. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must
be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.).
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100S815ZC
Z16-1
Z16-1
Commercial
Commercial
SY100S815ZCTR
3
ClockWorks™
SY100S815
Micrel
16 LEAD SOIC .300" WIDE (Z16-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
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