SY100S838_06 [MICREL]
(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHIP; （±1 ， ± 2/3）或（ ±2 ， ± 4/6）时钟发生芯片
| 型号： | SY100S838_06 |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | (±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHIP |
| 文件： | 总5页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
PrecisionEdge
SY100S838
SY100S838L
(÷1, ÷2/3) OR (÷2, ÷4/6)
CLOCK GENERATION CHIP
FEATURES
■ 3.3V and 5V power supply options
■ 50ps output-to-output skew
®
Precision Edge
■ Synchronous enable/disable
DESCRIPTION
■ Master Reset for synchronization
■ Internal 75KΩ input pull-down resistors
■ Available in 20-pin SOIC package
The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/
6) clock generation chip designed explicitly for low skew
clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the VBB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor.
The VBB output is designed to act as the switching
reference for the input of the SY100S838/L under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
TRUTH TABLE
CLK
Z
EN
L
MR
L
Function
Divide
ZZ
X
H
L
Hold Q0–3
X
H
Reset Q0–3
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input
is LOW, SY100S838/L functions as a divide by 2 and by
4/6 clock generation chip. However, if FSEL input is HIGH,
it functions as a divide by 1 and by 2/3 clock chip.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
FSEL
L
DIVSEL
Q0, Q1 OUTPUTS
Divide by 2
Q2, Q3 OUTPUTS
Divide by 4
L
H
L
L
Divide by 2
Divide by 6
H
Divide by 1
Divide by 2
H
H
Divide by 1
Divide by 3
PIN NAMES
Pin
CLK
Function
Differential Clock Inputs
Function Select Input
Synchronous Enable
Master Reset
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S838/Ls in a system.
FSEL
EN
MR
VBB
Reference Output
Q0, Q1
Q2, Q3
DIVSEL
Differential ÷1 or ÷2 Outputs
Differential ÷2/3 or ÷4/6 Outputs
Frequency Select Input
Precision Edge is a registered trademark of Micrel, Inc.
Rev.: G
Amendment: /0
M9999-113006
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: November2006
Precision Edge®
SY100S838
SY100S838L
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information
Package Operating
Package
Marking
Lead
Finish
Part Number
Type
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Z20-1
Range
Commercial
Commercial
Commercial
Commercial
Industrial
SY100S838ZC
SY100S838ZC
SY100S838ZC
SY100S838LZC
SY100S838LZC
SY100S838ZI
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
NiPdAu
SY100S838ZCTR(1)
SY100S838LZC
SY100S838LZCTR(1)
SY100S838ZI
SY100S838ZITR(1)
SY100S838LZI
Industrial
SY100S838ZI
Industrial
SY100S838LZI
SY100S838LZI
SY100S838ZG with
SY100S838LZITR(1)
SY100S838ZG(2)
Industrial
Industrial
Pb-Free bar-line indicator Pb-Free
SY100S838ZG with NiPdAu
Pb-Free bar-line indicator Pb-Free
SY100S838LZG with NiPdAu
Pb-Free bar-line indicator Pb-Free
SY100S838LZG with NiPdAu
Pb-Free bar-line indicator Pb-Free
SY100S838ZGTR(1, 2)
SY100S838LZG(2)
Z20-1
Z20-1
Z20-1
Industrial
Industrial
Industrial
SY100S838LZGTR(1, 2)
20-Pin SOIC (Z20-1)
Notes:
1. Tape and Reel.
2. Pb-Free package is recommended for new designs.
M9999-113006
hbwhelp@micrel.com or (408) 955-1690
2
Precision Edge®
SY100S838
SY100S838L
Micrel, Inc.
BLOCK DIAGRAM
CLK
CLK
÷
÷
1
2
Q
Q
0
0
1
0
Q
Q
1
1
÷
÷
2
3
or
or
EN
R
Q
2
1
0
MR
FSEL
÷
÷
4
6
Q
Q
2
3
DIVSEL
Q
3
(1)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IEE
Parameter
Power Supply Current
Output Reference Voltage
Input High Current
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
35
-1.38
—
50
—
—
65
-1.26 -1.38
150
35
50
—
—
65
-1.26 -1.38
150
35
50
—
—
65
-1.26 -1.38
150
35
54
—
—
75
mA
V
VBB
-1.26
150
IIH
—
—
—
µA
Note:
1. Parametric values specified at:
5 volt Power Supply Range 100S838 Series:
-4.2V to -5.5V.
3 volt Power Supply Range 100S838L Series -3.0V to -3.8V.
M9999-113006
hbwhelp@micrel.com or (408) 955-1690
3
Precision Edge®
SY100S838
SY100S838L
Micrel, Inc.
(1)
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
fMAX
Maximum Toggle Frequency
Propagation Delay to Output
1000
—
—
1000
—
—
1000
—
—
1000
—
—
MHz
ps
tPLH
tPHL
CLK ➝ Output (Diff.) 950
CLK ➝ Output (S.E.) 900
MR ➝ Q 600
—
—
—
1150 950
1200 900
900 600
—
—
—
1150 970
1200 920
900 600
—
—
—
1170 1050
1220 1000
900 600
—
—
—
1250
1300
900
tskew
Within-Device Skew(2) Q0 — Q3
—
—
—
—
50
—
—
—
—
50
—
—
—
—
50
—
—
—
—
50
ps
Part-to-Part
Set-up Time
Q0 — Q3 (Diff.)
200
200
200
200
tS
tH
EN ➝ CLK 300 150
DIVSEL ➝ CLK 300
—
—
300 150
300
—
—
300 150
300
—
—
300 150
300
—
—
ps
ps
—
—
—
—
Hold Time
CLK ➝ EN 400 150
—
—
400 150
400 200
—
—
400 150
400 200
—
—
400 150
400 200
—
—
CLK ➝ DIVSEL 400 200
VPP
VCMR
tRR
Minimum Input Swing(3)
Common Mode Range(4)
Reset Recovery Time
Minimum Pulse Width
CLK 250
CLK (4)
—
—
—
—
—
250
—
—
—
—
250
—
—
—
—
250
—
—
—
—
mV
V
-0.55 (4)
-0.55 (4)
-0.55 (4)
-0.55
100
100
—
100
—
100
—
ps
ps
tPW
CLK 800
MR 700
—
—
—
—
800
700
—
—
—
—
800
700
—
—
—
—
800
700
—
—
—
—
tr
tf
Output Rise/Fall Times
(20% —80%)
Q
280
—
550 280
—
550 280
—
550 280
—
550
ps
Notes:
1. Parametric values specified at:
5 volt Power Supply Range 100S838 Series:
-4.2V to -5.5V.
3 volt Power Supply Range 100S838L Series -3.0V to -3.8V.
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. TheCMRrangeisreferencedtothemostpositivesideofthedifferentialinputsignal. Normaloperationisobtainedifthe HIGHlevelfallswithinthespecified
range and the peak-to-peak voltage lies between VPP (min) and 1.0V. The lower end of the CMR range is dependent on VEE and is equal to VEE +1.65V.
TIMING DIAGRAM
CLK
Q (÷1)
Q (÷2)
Q (÷3)
Q (÷4)
Q (÷6)
M9999-113006
hbwhelp@micrel.com or (408) 955-1690
4
Precision Edge®
SY100S838
SY100S838L
Micrel, Inc.
20-PIN SOIC .300" WIDE (Z20-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-113006
hbwhelp@micrel.com or (408) 955-1690
5
相关型号：
SY100S839VZC
Low Skew Clock Driver, 100S Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, 0.300 INCH, SOIC-20
MICROCHIP
SY100S839VZG-TR
100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
MICROCHIP
©2020 ICPDF网 联系我们和版权申明