SY10E016JI [MICREL]
8-BIT SYNCHRONOUS BINARY UP COUNTER; 8位同步二进制计数器
| 型号： | SY10E016JI |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 8-BIT SYNCHRONOUS BINARY UP COUNTER |
| 文件： | 总9页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY10E016
SY100E016
FINAL
8-BIT SYNCHRONOUS
BINARY UP COUNTER
DESCRIPTION
FEATURES
The SY10/100E016 are high-speed synchronous,
presettable and cascadable 8-bit binary counters designed
foruseinnew, high-performanceECLsystems. Architecture
and operation are the same as the Motorola MC10H016 in
the MECL 10KH family, extended to 8 bits, as shown in the
logic diagram.
■ 700MHz min. count frequency
■ Extended 100E VEE range of –4.2V to –5.5V
■ 1000ps CLK to Q, TC
■ Internal, gated TC feedback
■ 8 bits wide
The counters feature internal feedback of TC, gated by
the TCLD (terminal count load) pin. When TCLD is LOW,
the TC feedback is disabled and counting proceeds
continuously, with TC going LOW to indicate an all-HlGH
state. When TCLD is HIGH, the TC feedback causes the
counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter.
■ Fully synchronous counting and TC generation
■ Asynchronous Master Reset
■ Fully compatible with industry standard 10KH,
100K I/O levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E016
■ Available in 28-pin PLCC package
PIN NAMES
PIN CONFIGURATION
Pin
P0-P7
Q0-Q7
CE
Function
Parallel Data (Preset) Inputs
Data outputs
25 24 23 22 21 20 19
Count Enable Control Input
Parallel Load Enable Control Input
Master Reset
MR
CLK
TCLD
VEE
NC
26
27
28
1
18
17
16
15
14
13
12
Q7
Q6
PE
VCC
Q5
MR
PLCC
TOP VIEW
J28-1
CLK
TC
Clock
2
VCCO
Q4
Terminal Count Output
TC-Load Control Input
VCC to Output
P0
3
TCLD
VCCO
P1
4
Q3
5
6
7
8
9
10 11
Rev.: D
Amendment: /2
Issue Date: May, 1998
1
SY10E016
SY100E016
Micrel
BLOCK DIAGRAM
TC
Q7
BIT 7
P7
CE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q2
– Q
6
5
5
5
BIT 2 – BIT 6
BIT 1
5
5
5
Q1
P1
CE
Q0
Q0
SLAVE
Q0M
Q0M
MASTER
BIT 0
PE
CE
TCLD
P0
MR CLK
2
SY10E016
SY100E016
Micrel
TRUTH TABLE(1)
CE
PE
L
TCLD
MR
L
CLK
Z
Function
Load Parallel (Pn to Qn)
Continuous Count
X
L
X
L
H
H
H
X
L
Z
L
H
X
X
X
L
Z
Count; Load Parallel on TC = LOW
Hold
H
X
X
L
Z
L
ZZ
Z
Master respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
X
H
NOTE:
1. Z = Clock Pulse (LOW-to-HIGH), ZZ = Clock Pulse (HIGH-to-LOW)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IIH
Parameter
Input HIGH Current
Power Supply Current
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
µA
—
—
150
—
—
150
—
—
150
—
—
150
IEE
mA
10E
100E
—
—
151 181
151 181
—
—
151
151
181
181
—
—
151 181
151 181
—
—
151 181
174 208
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°C
TA = 0°C
TA = 25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
700 900 700 900 700 900 700 900
Unit
MHz
ps
fCOUNT
Max. Count Frequency
—
—
—
—
tPLH
tPHL
Propagation Delay to Output
CLK to Q
600 725 1000 600 725 1000 600 725 1000 600 725 1000
600 775 1000 600 775 1000 600 775 1000 600 775 1000
550 775 1050 550 775 1050 550 775 1050 550 775 1050
MR to Q
CLK to TC (Qs loaded)(1)
CLK to TC (Qs unloaded)(1)
MR to TC
550 700 900
550 700 900
550 700 900 550 700 900
625 775 1000 625 775 1000 625 775 1000 625 775 1000
tS
tH
Set-up Time
Pn
CE
PE
ps
ps
150 –30
600 400
600 400
500 300
—
—
—
—
150 –30
600 400
600 400
500 300
—
—
—
—
150 –30
600 400
600 400
500 300
—
—
—
—
150 –30
600 400
600 400
500 300
—
—
—
—
TCLD
Hold Time
Pn
CE
PE
TCLD
250
0
0
30
–400
–400
—
—
—
—
250
0
0
30
–400
–400
—
—
—
—
250
0
0
30
–400
–400
—
—
—
—
250
0
0
30
–400
–400
—
—
—
—
100 –300
100 –300
100 –300
100 –300
tRR
tWP
Reset Recovery Time
900 700
—
—
900 700
—
—
900 700
—
—
900 700
—
—
ps
ps
Minimum Pulse Width
CLK, MR
400
—
400
—
400
—
400
—
tr
tf
Rise/Fall Times
20% to 80%
300 510 800
300 510 800
300 510 800 300 510 800
ps
NOTE:
1. CLK to TC propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded, the noise generated in going from a IIII IIII
state to a 0000 0000 state causes the CLk to TC+ delay to increase.
3
SY10E016
SY100E016
Micrel
FUNCTION TABLE
Function
Load
PE
L
CE
X
L
MR TCLD CLK
P7–P4
H
P3
H
X
X
X
X
H
X
X
L
P2
H
X
X
X
X
H
X
X
H
H
H
H
H
H
X
P1
L
P0 Q7–Q4 Q3
Q2
H
H
H
H
L
Q1
L
Q0
L
TC
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
L
X
X
X
X
L
X
X
L
L
L
L
L
L
X
H
H
H
H
L
H
H
H
H
L
Count
H
H
H
H
L
X
X
X
X
X
L
L
H
L
L
L
X
H
H
L
L
L
X
H
L
L
L
X
H
H
H
H
H
H
L
Load
Hold
X
H
H
L
X
X
X
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
X
X
X
X
H
H
H
H
H
H
X
L
L
X
L
L
Load On
Terminal
Count
H
L
H
L
L
H
L
H
H
H
H
L
L
H
L
H
L
L
H
L
H
H
H
H
L
H
L
L
H
L
L
H
L
H
L
Reset
X
X
X
L
L
L
4
SY10E016
SY100E016
Micrel
APPLICATIONS INFORMATION
Cascading Multiple E016 Devices
E016 in the chain to count all of the lower order terminal count
outputs, itmustbeinthelowstate. Thebitwidthofthecounter
canbeincreasedordecreasedbysimplyaddingorsubtracting
E016 devices from Figure 1 and maintaining the logic pattern
illustrated in the same figure.
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output and
count enable input (CE) greatly facilitate the cascading of
E016 devices. Two E016s can be cascaded without the need
for external gating; however, for counters wider than 16 bits,
externalORgatesarenecessaryforcascadeimplementations.
Figure 1, below, pictorially illustrates the cascading of 4
E016s to build a 32-bit high frequency counter. Note the E101
gates used to OR the terminal count outputs of the lower order
E016s to control the counting operation of the higher order
bits. When the terminal count of the preceding device (or
devices) goes low (the counter reaches an all 1s state), the
more significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition. In
addition, the preceding devices will also count one bit, thus
sending their terminal count outputs back to a high state,
disabling the count operation of the more significant counters
and placing them back into hold modes. Therefore, for an
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary set-up time of the CE input and the
propagation delay through the OR gate controlling it (for 16-
bitcountersthelimitationisonlytheTCpropagationdelayand
the CE set-up time). Figure 1 shows E101 gates used to
control the count enable inputs; however, if the frequency of
operation is lower, a slower ECL OR gate can be used. Using
the worst case guarantees for these parameters from the
ECLinPS data book, the maximum count frequency for a
greater than 16-bit counter is 475MHz and that for a 16-bit
counter is 625MHz. Note that this assumes the trace delay
between the TC outputs and the CE inputs are negligible. If
this is not the case, estimates of these delays need to be
added to the calculations.
LOAD
Q
0–Q
7
Q
0–Q
7
Q0–Q
7
Q0–Q7
"LO"
CE
PE
CE
PE
CE
PE
CE
PE
E016
LSB
E016
E016
E016
MSB
CLK
TC
CLK
TC
CLK
TC
CLK
TC
P
0–P
7
P
0–P
7
P
0–P
7
P0–P7
E101
E101
CLOCK
Figure 1. 32-Bit Cascaded E016 Counter
5
SY10E016
SY100E016
Micrel
Programmable Divider
Todeterminewhatvaluetoloadintothedevicetoaccomplish
the desired division, the designer simply subtracts the binary
equivalent of the desired divide ratio for the binary value for
256. As an example for a divide ration of 113:
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLDpin(loadonterminalcount),whenasserted,reloadsthe
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 2
PN's = 256 – 113 = 8F16 = 1000 1111
where
P0 = LSB and P7 = MSB
below illustrates the input conditions necessary for utilizing Forcing this input condition, as per the set-up in Figure 2, will
the E016 as a programmable divider set up to divide by 113. result in the waveforms of Figure 3. Note that the TC output
H
L
L
L
H
H
H
H
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
H
PE
CE
L
H
TCLD
CLK
TC
Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
Figure 2. Mod 2 to 256 Programmable Divider
LOAD
1001 0000
1001 0001
1111 1100
1111 1101
1111 1110
1111 1111
LOAD
CLOCK
PE
TC
Divide by 113
Figure 3. Divide by 113 E016 Programmable Divider Waveforms
6
SY10E016
SY100E016
Micrel
Divide
Preset Data Inputs
Ratio
P7
P6
P5
P4
P3
P2
P1
P0
2
3
4
5
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
L
L
H
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
112
113
114
H
H
H
L
L
L
L
L
L
H
L
L
L
H
H
L
H
H
L
H
H
L
H
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
254
255
256
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
Table 1. Preset Values for Various Divide Ratios
is used as the divide output and the pulse duration is equal to two TC outputs were OR tied, the cascaded count operation
a full clock period. For even divide ratios twice the desired would not operate properly. Because in the cascaded form
divideratiocanbeloadedintotheE016andtheTC outputcan the PE feedback is external and requires external gating, the
feed the clock input of a toggle flip-flop to create a signal maximumfrequencyofoperationwillbesignificantlylessthan
divided as desired with a 50% duty cycle.
the same operation in a single device.
A single E016 can be used to divide by any ratio from 2 to
256, inclusive. If divide ratios of greater than 256 are needed,
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers, the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reachedterminalcount, externalgatingoftheTCpinsmustbe
used for multiple E016 divider chains.
Figure 4 on the following page shows a typical block
diagram of a 32-bit divider chain. Once again, the maximize
the frequency of operation, E101 OR gates were used. For
lower frequency applications, a slower OR gate could replace
the E101. Note that for a 16-bit divider, the OR function
feeding the PE (program enable) input CANNOT be replaced
by a wire OR tie as the TC output of the least significant E016
mustalsofeedtheCEinputofthemostsignificantE016. Ifthe
Maximizing E016 Count Frequency
The E016 device produces nine fast transitioning single-
ended outputs; thus, VCC noise can become significant in
situationswherealloftheoutputsswitchsimultaneouslyinthe
same direction. This VCC noise can negatively impact the
maximum frequency of operation of the device. Since the
device does not need to have the Q outputs terminated to
count properly, it is recommended that, if the outputs are not
going to be used in the rest of the system, they should be left
unterminated. In addition, if only a subset of the Q outputs are
used in the system, only those outputs should be terminated.
Not terminating the unused outputs will not only cut down the
VCC noise generated, but will also save in total system power
dissipation. Following these guidelines will allow designers to
either be more aggressive in their designs, or provide them
7
SY10E016
SY100E016
Micrel
E101
Q0–Q
7
Q
0–Q
7
Q0–Q7
Q0–Q7
"LO"
CE
PE
CE
PE
CE
PE
CE
PE
E016
E016
E016
MSB
E016
LSB
CLK
TC
CLK
TC
CLK
TC
CLK
TC
P0–P7
P0–P
7
P
0–P7
P0–P7
E101
E101
CLOCK
Figure 4. 32-Bit Cascaded E016 Programmable Divider
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
Ordering
Code
Package
Type
Operating
Range
SY10E016JI
J28-1
J28-1
J28-1
J28-1
Industiral
Industrial
Industrial
Industrial
SY10E016JC
J28-1
J28-1
J28-1
J28-1
Commercial
Commercial
Commercial
Commercial
SY10E016JITR
SY100E016JI
SY100E016JITR
SY10E016JCTR
SY100E016JC
SY100E016JCTR
8
SY10E016
SY100E016
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
9
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