SY10E137 [MICREL]

8-BIT RIPPLE COUNTER; 8位异步计数器


型号：	SY10E137
厂家：	MICREL SEMICONDUCTOR
描述：	8-BIT RIPPLE COUNTER 8位异步计数器计数器
文件：	总4页 (文件大小：79K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8-BIT RIPPLE

COUNTER

SY10E137

SY100E137

FEATURES

DESCRIPTION

■ 1.8GHz min. count frequency

The SY10/100E137 are very high speed binary ripple

counters. The two least significant bits were designed

with very fast edge rates, while the more significant bits

maintain standard ECLinPS output edge rates. This allows

the counters to operate at very high frequencies, while

maintaining a moderate power dissipation level.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Synchronous and asynchronous enable pins

■ Differential clock input and data output pins

■ VBB output for single-ended use

The devices are ideally suited for multiple frequency

clock generation, as well as for counters in high-

performance ATE time measurement boards.

■ Asynchronous Master Reset

■ Internal 75KΩ input pull-down resistors

■ Available in 28-pin PLCC packge

Both asynchronous and synchronous enables are

available to maximize the device's flexibility for various

applications. The asynchronous enable input, A_Start,

when asserted, enables the counter while overriding any

synchronous enable signals. The E137 features XOR'ed

enable inputs, EN1 and EN2, which are synchronous to

the CLK input. When only one synchronous enable is

asserted, the counter becomes disabled on the next CLK

transition. All outputs remain in the previous state poised

for the other synchronous enable or A_Start to be

asserted in order to re-enable the counter. Asserting

both synchronous enables causes the counter to become

enabled on the next transition of the CLK. EN1 (or EN2)

and CLK edges are coincident. Sufficient delay has been

inserted in the CLK path (to compensate for the XOR

gate delay and the internal D-flip-flop set-up time) to

ensure that the synchronous enable signal is clocked

correctly; hence, the counter is disabled.

PIN CONFIGURATION

25 24 23 22 21 20 19

A_Start

VCC

PLCC

TOP VIEW

J28-1

VEE

CLK

VBB

10 11

The E137 can also be driven single-endedly utilizing

the VBB output supply as the voltage reference for the

CLK input signal. If a single-ended signal is to be used,

the VBB pin should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. VBB can

only source/sink 0.5mA; therefore, it should be used as

a switching reference for the E137 only.

All input pins left open will be pulled LOW via an input

pull-down resistor. Therefore, do not leave the differential

CLK inputs open. Doing so causes the current source

transistor of the input clock gate to become saturated,

thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

PIN NAMES

CLK, CLK

Q0–Q7, Q0–Q7

A_Start

EN1, EN2

Function

The asynchronous Master Reset resets the counter to

an all zero state upon assertion.

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Reference Output

VCC to Output

VBB

VCCO

Rev.: C

Amendment:/1

Issue Date: February, 1998

SY10E137

Micrel

SY100E137

BLOCK DIAGRAM

A_Start

EN1

EN2

Q7 Q7

CLK

VBB

(1)

SEQUENTIAL TRUTH TABLE

Function

Reset

EN1

EN2 A_Start MR

CLK

Count

Stop

Async. Start

Count

Stop

Sync. Start

Stop

Count

Reset

NOTE:

1. Z = LOW-to-HIGH transition

SY10E137

Micrel

SY100E137

DC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

VBB

Output Reference

Voltage

—

10E –1.38

100E –1.38

—

–1.27 –1.35

–1.26 –1.38

—

–1.25 –1.31

–1.26 –1.38

—

–1.19

–1.26

IIH

Input HIGH Current

—

150

—

150

—

150

µA

—

IEE

Power Supply

Current

10E

100E

—

121 145

—

121

145

—

121

139

145

167

AC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

fCOUNT

Max. Count Frequency

1800 2200

—

1800 2200

—

1800 2200

—

MHz

—

tPLH

tPHL

Propagation Delay to Output

CLK to Q0

CLK to Q1

CLK to Q2

CLK to Q3

CLK to Q4

CLK to Q5

CLK to Q6

CLK to Q7

1300 1700 2150 1300 1700 2150 1350 1750 2200

1600 2025 2500 1600 2050 2500 1650 2100 2550

1950 2425 2925 1950 2450 2925 2025 2500 3000

2275 2750 3350 2275 2775 3350 2350 2850 3425

2625 3125 3750 2625 3150 3750 2700 3225 3625

2950 3450 4150 2950 3475 4150 3050 3550 4250

3250 3775 4450 3250 3800 4450 3375 3925 4600

3575 4075 4800 3575 4125 4800 3700 4250 4950

950 1325 1700 950 1325 1700 950 1325 1700

700 1000 1300 700 1000 1300 700 1000 1300

A_Start to Q0

MR to Q0

Set-up Time (EN1, EN2)

Hold Time (EN1, EN2)

–150

—

–150

—

–150

—

300 150

400 200

300 150

400 200

300 150

400 200

tRR

Reset Recovery Time

MR, A_Start

tPW

Minimum Pulse Width

CLK, MR, A_Start

400

—

400

—

400

—

VPP

Minimum Input Swing (CLK) 0.25

—

1.0 0.25

—

1.0 0.25

—

1.0

VCMR

Com. Mode Range (CLK)

–0.4

–2.0 –0.4

–2.0

—

Rise/Fall Time, 20% to 80%

Q0, Q1

Q2–Q7

150

275

—

400 150

600 275

—

400 150

600 275

—

400

600

NOTE:

1. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50mV input swings.

PRODUCT ORDERING CODE

Ordering

Code

Package

Type

Operating

Range

SY10E137JC

J28-1

Commercial

SY10E137JCTR

SY100E137JC

SY100E137JCTR

SY10E137

Micrel

SY100E137

28 LEAD PLCC (J28-1)

Rev. 03

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

SY10E137 [MICREL]

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