SY10EL16VFZC_技术文档

ENHANCED

DIFFERENTIAL

RECEIVER

SY10EL16VA-VF

SY100EL16VA-VF

FEATURES

DESCRIPTION

■ 3.3V and 5V power supply options

■ 250ps propagation delay

The SY10/100EL16VA-VF are differential receivers.

The devices are equivalent to SY10/100EL16 or SY10/

100EL16V with enhanced capabilities. The QHG, /QHG

outputs have a DC gain several times larger than the DC

gain of the Q output.

The SY10/100EL16VA have an identical pinout to the

SY10/100EL16 or SY10/100EL16V. It provides a VBB

output for either single-ended application or as a DC

bias for AC coupling to the device.

■ Very high voltage gain vs. standard EL16 or EL16V

■ Ideal for Pulse Amplifier and Limiting Amplifier

applications

■ Data synchronous Enable/Disable (/EN) on QHG and

/QHG provides for complete glitchless gating of the

outputs

The SY10/100EL16VB are very similar to the SY10/

100EL16VA. The /Q output is provided for feedback

purposes.

■ Ideal for gating timing signals

■ Complete solution for high quality, high frequency

crystal oscillator applications

The SY10/100EL16VC provides an /EN input which is

synchronized with the data input (D) signal in a way that

providesglitchlessgatingoftheQHG and/QHG outputs. When

the /EN signal is LOW, the input is passed to the outputs and

the data output equals the data input. When the data input is

HIGH and the /EN goes HIGH, it will force the QHG LOW and

the /QHG HIGH on the next negative transition of the data

input. If the data input is LOW when the /EN goes HIGH, the

next data transition to a HIGH is ignored and QHG remains

LOW and /QHG remains HIGH. The next positive transition of

the data input is not passed on to the data outputs under these

conditions. The QHG and /QHG outputs remain in their dis-

abled state as long as the /EN input is held HIGH. The /EN

input has no influence on the /Q output and the data input is

passed on (inverted) to this output whether /EN is HIGH or

LOW. This configuration is ideal for crystal oscillator applica-

tions, where the oscillator can be free running and gated on

and off synchronously without adding extra counts to the

output.

■ Internal 75K Ohm input pull-down resistors

■ Available in both 8 and 16-pin SOIC package; 8 and

10-pin (3mm) MSOP and in DIE form

PIN NAMES

D

Function

Data Inputs

Q

Data Outputs

QHG

VBB

/EN

Data Outputs w/High Gain

Reference Voltage Output

Enable Input

The SY10/100EL16VD provides the flexibility of all the

combinations in DIE form, in 16-pin 150mil SOIC package or

in 10-pin MSOP package. The 16-pin SOIC and 10-pin MSOP

packages are ideal for prototyping DIE applications.

TheSY10/100EL16VEaresimilar totheSY10/100EL16VB

where the Q, /Q output is made available differently. In this

package option, VBB is no longer provided.

TRUTH TABLE

/EN

0

QHG Output

Data

TheSY10/100EL16VFaresimilar totheSY10/100EL16VC,

offering the D, /D inputs rather than the VBB output.

1

Logic Low

Rev.: L

Amendment:/1

Issue Date: July 2000

1

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

PIN CONFIGURATION/BLOCK DIAGRAM

8

1

2

VCC

QHG

/QHG

VEE

NC

D

7

6

5

/D

3

4

VBB

SY10/100EL16VA

5V/3.3V Differential Receiver w/High Gain

8

1

2

VCC

QHG

/QHG

VEE

Q

/Q

D

(Available in 8-pin SOIC or 8-pin MSOP)

7

6

5

3

4

/D

8

1

2

VCC

QHG

/QHG

VEE

/Q

D

7

6

5

SY10/100EL16VE

EL16VB w/Differential Q, QB output (no VBB)

/D

3

4

(Available in 8-pin SOIC or 8-pin MSOP)

VBB

SY10/100EL16VB

EL16VA w/Extra QB output

V

CC

1

2

3

8

7

6

5

/Q

D

Q

HG

(Available in 8-pin SOIC or 8-pin MSOP)

/D

/QHG

OE

LEN

Q

BB

LATCH

/EN

VEE

4

D

V

CC

1

2

3

8

7

6

5

/Q

D

Q

HG

SY10/100EL16VF

EL16VC w/Differential Data Input

V

BB

/QHG

(Available in 8-pin SOIC or 8-pin MSOP)

OE

LEN

Q

VBB

LATCH

/EN

V

EE

4

D

SY10/100EL16VC

EL16VB w/Enable Input

(Available in 8-pin SOIC or 8-pin MSOP)

2

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

PIN CONFIGURATION/BLOCK DIAGRAM

1

2

NC

Q

16

15

V

CC

Q

HG

3

4

/Q

D

14

13

12

11

/QHG

EE

SOIC

Z16-2

10 VCC

Q

/Q

D

1

2

V

/D

5

6

QHG

9

V

BB

NC

/EN

MSOP

K10-1

3

4

5

/QHG

VEE

/EN

8

7

6

7

8

10 NC

NC

/D

9

VBB

SY10/100EL16VDZC

SY10/100EL16VDKC

EL16VDXC packaged in 16-pin SOIC

EL16VDXC packaged in 10-pin MSOP

DIE LAYOUT

All options in DIE form w/Extra Q output and VBB output

Die Size (mils) 39. X 52. X 14.5

Q

VCC

/Q

Q

HG

D

/D

BB

OE

LEN

Q

LATCH

D

V

BB

V

/QHG

/EN

VEE

SY10/100EL16VDXC

DIE

TOP VIEW

3

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

(1)

DC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min) to VEE (Max), VCC = GND

TA = –40°C

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Power Supply

Current

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

IEE

mA

10EL

—

40

—

40

—

40

—

40

46

100EL

VBB

Output Reference

V

Voltage

10EL –1.43

100EL –1.38

—

–1.30 –1.38

–1.26 –1.38

—

–1.27 –1.35

–1.26 –1.38

—

–1.25 –1.31

–1.26 –1.38

—

–1.19

–1.26

IIH

Input HIGH Current

—

150

—

150

—

150

—

150

µA

NOTE:

1. Parametric values specified at: 10/100EL16VA-VF Series:

-3.0V to -5.5V.

(4)

AC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min) to VEE (Max), VCC = GND

TA = –40°C

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

tPLH

tPHL

Propagation Delay to

ps

Q, /Q Output

D (Diff)

D (SE)

—

350

400

—

350

400

—

350

400

—

380

430

QHG, /QHG Output

D (Diff)

D (SE)

—

650

700

—

650

700

—

650

700

—

730

780

tS

Setup Time

Hold Time

/EN

—

150

—

150

—

150

—

150

—

ps

tH

tskew

Duty Cycle Skew⁽¹⁾

(Diff)

—

5

—

5

—

20

—

5

—

20

—

5

—

20

—

ps

mV

V

VPP

Minimum Input Swing⁽²⁾

150

VCMR

Common Mode Range⁽³⁾–1.3

—

–0.4 –1.4

350 100

—

–0.4 –1.4

350 100

—

–0.4 –1.4

350 100

—

–0.4

350

tr

tf

Output Q

100

225

ps

Rise/Fall Time

(20% TO 80%)

NOTES:

1. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.

2. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈ 40 to Q, /Q outputs and a DC gain of ≈ 200 or higher to

/QHG/QHG outputs.

3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified

range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table

assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – |VCMR (min)|.

4. Parametric values specified at: 10/100EL16VA-VF Series:

-3.0V to -5.5V.

4

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

TIMING DIAGRAM

D

t

S

tH

EN

Q

HG

PRODUCT ORDERING CODE

Ordering

Code

Package

Type

Operating VEE Range

Range (V)

Ordering

Code

Package

Type

Operating

Range

VEE Range

(V)

SY10EL16VAZC

Z8-1

Z16-2

Z8-1

Commercial -3.0 to -5.5

SY10EL16VAKCTR

SY100EL16VAKCTR

SY10EL16VBKCTR

SY100EL16VBKCTR

SY10EL16VCKCTR

SY100EL16VCKCTR

SY10EL16VDKCTR

SY100EL16VDKCTR

SY10EL16VEKCTR

SY100EL16VEKCTR

SY10EL16VFKCTR

SY100EL16VFKCTR

SY10EL16VDXC

K8-1

K10-1

K8-1

DIE

Commercial

-3.0 to -5.5

SY10EL16VAZCTR

SY100EL16VAZC

SY100EL16VAZCTR

SY10EL16VBZC

SY10EL16VBZCTR

SY100EL16VBZC

SY100EL16VBZCTR

SY10EL16VCZC

SY10EL16VCZCTR

SY100EL16VCZC

SY100EL16VCZCTR

SY10EL16VDZC

SY10EL16VDZCTR

SY100EL16VDZC

SY100EL16VDZCTR

SY10EL16VEZC

SY100EL16VDXC

DIE

SY10EL16VEZCTR

SY100EL16VEZC

SY100EL16VEZCTR

SY10EL16VFZC

SY10EL16VFZCTR

SY100EL16VFZC

SY100EL16VFZCTR

5

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

8 LEAD MSOP (K8-1)

Rev. 01

6

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

10 LEAD MSOP (K10-1)

Rev. 00

7

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

8 LEAD SOIC .150" WIDE (Z8-1)

Rev. 03

8

SY10EL16VA-VF

SY100EL16VA-VF

Micrel

16 LEAD SOIC .150" WIDE (Z16-2)

Rev. 02

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

9


型号：	SY10EL16VFZC
厂家：	MICREL SEMICONDUCTOR
描述：	ENHANCED DIFFERENTIAL RECEIVER 增强差分接收器
文件：	总9页 (文件大小：161K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SY10EL16VFZC [MICREL]

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