SY54017R
更新时间：2024-09-18 12:13:05
品牌：MICREL
描述：Low Voltage 1.2V/1.8V CML 2:1 MUX with Fail Safe Inputs, 3.2Gbps, 2.5GHz
概述
数据手册SY54017R 概述
Low Voltage 1.2V/1.8V CML 2:1 MUX with Fail Safe Inputs, 3.2Gbps, 2.5GHz 低电压1.2V / 1.8V CML 2 ： 1多路复用器与故障安全输入， 3.2Gbps的， 2.5GHz的
SY54017R 数据手册
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PDF下载SY54017R
Low Voltage 1.2V/1.8V CML 2:1 MUX
with Fail Safe Inputs, 3.2Gbps, 2.5GHz
General Description
Precision Edge®
The SY54017R is a fully differential, low voltage
1.2V/1.8V CML 2:1 MUX with Fail Safe Inputs. The
SY54017R can process clock signals as fast as 2.5GHz
or data patterns up to 3.2Gbps.
Features
• 1.2V/1.8V CML 2:1 MUX with Fail Safe Inputs
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled
from a 2.5V driver) as small as 100mV (200mVPP)
without any level-shifting or termination resistor
networks in the signal path. For AC-coupled input
interface applications, an internal voltage reference is
provided to bias the VT pin. The outputs are CML, with
extremely fast rise/fall times guaranteed to be less than
95ps.
• Guaranteed AC performance over temperature and
voltage:
– DC-to- > 3.2Gbps throughput
– <390ps propagation delay (IN-to-Q)
– <20ps Input-to-Input skew
– <95ps rise/fall times
• Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
The SY54017R operates from a 2.5V ±5% core supply
and a 1.8V or 1.2V ±5% output supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY54017R is part of Micrel’s
high-speed, Precision Edge® product line.
– <1psRMS random jitter
– <10psPP deterministic jitter
• High-speed CML outputs
• 2.5V ±5% , 1.8/1.2V ±5% power supply operation
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) MLF® package
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Applications
Functional Block Diagram
• Data Distribution: OC-48, OC-48+FEC
• SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
Markets
• Storage
• ATE
• Test and measurement
• Enterprise networking equipment
• High-end servers
• Access
• Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
MLF is a registered trademark of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
M9999-033108-A
hbwhelp@micrel.com or (408) 955-1690
March 2008
Micrel, Inc.
SY54017R
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY54017RMG
SY54017RMGTR(2)
Notes:
MLF-16
Industrial
017R with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
MLF-16
Industrial
017R with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin MLF® (MLF-16)
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SY54017R
Pin Description
Pin Number
16,1
Pin Name
IN0, /IN0
IN1,/IN1
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device.
They accept differential signals as small as 100mV (200mVPP). Each input pin
internally terminates with 50Ω to the VT pin. If the input swing falls below a certain
threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable
output by latching the output to its last valid state.
4,5
2
3
VT0
VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. An internal high impedance resistor divider biases VT to allow
input AC coupling. For AC-coupling, bypass VT with a 0.1µF low ESR capacitor to
VCC. See “Interface Applications” subsection and Figure 2a.
15
SEL
This single-ended TTL/CMOS compatible input selects the inputs to the multiplexer.
Note that this input is internally connected to a 25k ohm pull-up resistor and will
default to a logic HIGH state if left open.
7
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the VCC pin as possible. Supplies input and core circuitry.
8,13
14
VCCO
Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCCO
pins as possible. Supplies the output buffer.
GND,
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
Exposed pad
11,10
Q, /Q
CML Differential Output Pair: Differential buffered copy of the input signal. The
output swing is typically 390mV. See “Interface Applications” subsection for
termination information.
Truth Table
SEL
0
OUTPUT
IN0 Input Selected
IN1 Input Selected
1
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Micrel, Inc.
SY54017R
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC)............................... –0.5V to +3.0V
Supply Voltage (VCCO)............................. –0.5V to +2.7V
VCC – VCCO ........................................................<1.8V
VCCO – VCC ........................................................<0.5V
Input Voltage (VIN).......................................–0.5V to VCC
CML Output Voltage (VOUT)............... 0.6V to VCCO+0.5V
Current (VT)
Supply Voltage (VCC)..........................2.375V to 2.625V
(VCCO)………………...…..1.14V to 1.9V
Ambient Temperature (TA) ................... –40°C to +85°C
Package Thermal Resistance(3)
MLF®
Still-air (θJA)............................................ 75°C/W
Junction-to-board (ψJB) .......................... 33°C/W
Source or sink current on VT pin.................±100mA
Input Current
Source or sink current on (IN, /IN).................±50mA
Maximum operating Junction Temperature ..........125°C
Lead Temperature (soldering, 20sec.)..................260°C
Storage Temperature (Ts) ....................–65°C to +150°C
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
VCC
Min
2.375
1.14
1.7
Typ
2.5
1.2
1.8
22
Max
2.625
1.26
1.9
Units
V
VCC
Power Supply Voltage Range
VCCO
V
VCCO
V
ICC
Power Supply Current
Power Supply Current
Max. VCC
No Load. Max VCCO
32
mA
mA
ICCO
RIN
16
21
Input Resistance
(IN-to-VT, /IN-to-VT )
45
90
50
55
ꢀ
ꢀ
RDIFF_IN
VIH
Differential Input Resistance
(IN-to-/IN)
100
110
Input HIGH Voltage
(IN, /IN)
IN, /IN
1.2
0.2
VCC
V
V
Input LOW Voltage
(IN, /IN)
VIH–0.1
VIL
VIH
VIL with VIH = 1.2V
IN, /IN
Input HIGH Voltage
(IN, /IN)
1.14
0.66
VCC
V
V
Input LOW Voltage
(IN, /IN)
VIH–0.1
VIL
VIN
VIL with VIH = 1.14V, (1.2V-5%)
see Figure 3a
Input Voltage Swing
(IN, /IN)
0.1
0.2
1.0
2.0
V
V
VDIFF_IN
VIN_FSI
Differential Input Voltage Swing
(|IN - /IN|)
see Figure 3b
Input Voltage Threshold that
Triggers FSI
30
100
mV
V
VT_IN
Voltage from Input to VT
1.28
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
M9999-033108-A
hbwhelp@micrel.com or (408) 955-1690
March 2008
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Micrel, Inc.
SY54017R
CML Outputs DC Electrical Characteristics(5)
VCCO = 1.14V to 1.26V RL = 50ꢀ to VCCO, VCCO = 1.7V to 1.9V, RL = 50ꢀ to VCCO or 100ꢀ across the outputs,
CC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.
V
Symbol
Parameter
Condition
Min
VCCO-0.020
300
Typ
VCCO-0.010
390
Max
VCCO
475
950
55
Units
V
VOH
Output HIGH Voltage
Output Voltage Swing
RL = 50ꢀ to VCCO
See Figure 3a
VOUT
mV
mV
ꢀ
VDIFF_OUT
ROUT
Differential Output Voltage Swing See Figure 3b
Output Source Impedance
600
780
45
50
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = 2.5V ±5%; VCCO = +1.14V to +1.26V or +1.7V to +1.9V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
VIH
Parameter
Condition
Min
Typ
Max
VCC
0.8
30
Units
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
VIL
V
IIH
-125
-300
µA
µA
IIL
Note:
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
M9999-033108-A
hbwhelp@micrel.com or (408) 955-1690
March 2008
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Micrel, Inc.
SY54017R
AC Electrical Characteristics
VCCO = 1.14V to 1.26V RL = 50ꢀ to VCCO, VCCO = 1.7V to 1.9V, RL = 50ꢀ to VCCO or 100ꢀ across the outputs,
CC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.
V
Symbol
fMAX
Parameter
Condition
Min
3.2
2.5
Typ
Max
Units
Gbps
GHz
ps
Maximum Frequency
NRZ Data
VOUT > 200mV
Clock
tPD
Propagation Delay
IN-to-Q VIN: 100mV-200mV, Note 6, Figure 1a
VIN: >200mV, Note 6, Figure 1a
220
190
90
320
270
200
5
470
390
350
20
75
1
ps
SEL-to-Q
See Figure 1a
Note 8
ps
tSkew
Input-to-Input Skew
Part-to-Part Skew
ps
Note 9
ps
tJitter
Data
Random Jitter Note 10
psRMS
psPP
psRMS
psPP
psPP
Deterministic Jitter
Note 11
10
1
Clock
Cycle-to-Cycle Jitter Note 12
Total Jitter
Crosstalk Induced Jitter
(Adjacent Channel)
Note 13
Note 14
10
0.7
tR tF
Output Rise/Fall Times
(20% to 80%)
At full output swing.
Differential I/O
30
47
60
95
53
ps
%
Duty Cycle
Notes:
6. Propagation delay is measured with input tr/tf ≤300ps (20% to 80%).
8. Input-to-Input skew is the difference in time between both inputs and the output for the same temperature, voltage and transition.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs. Vin >200mV with input tr/tf ≤300ps (20% to 80%).
10. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX
.
11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
12. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER
where T is the time between rising edges of the output signal.
_CC = Tn –Tn+1,
13. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
14. Crosstalk induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while
applying a similar, differential clock frequencies that are asynchronous with respect to each other at the adjacent input.
M9999-033108-A
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March 2008
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Micrel, Inc.
SY54017R
Functional Description
CML Output Termination with VCCO 1.8V
Fail-Safe Input (FSI)
For VCCO of 1.8V, Figure 5a and Figure b, terminate
with either 50ꢀ-to-1.8V or 100ꢀ differentially across
the outputs. AC- or DC-coupling is fine.
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
output when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below 100mVPK (200mVPP), typically 30mVPK.
Maximum frequency of the SY54017R is limited by
the FSI function.
Input AC-Coupling
The SY54017R input can accept AC-coupling from
any driver. Bypass VT with a 0.1µF low ESR capacitor
to VCC as shown in Figures 4c and 4d. VT has an
internal high impedance resistor divider as shown in
Figure 2a, to provide a bias voltage for AC-coupling.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output.
No ringing and no undetermined state will occur at the
output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal close to the FSI threshold. Due
to the FSI function, the propagation delay will depend
on rise and fall time of the input signal and on its
amplitude. Refer to “Typical Characteristics” for
detailed information
Interface Applications
For Input Interface Applications, see Figures 4a-f and
for CML Output Termination, see Figures 5a-d.
CML Output Termination with VCCO 1.2V
For VCCO of 1.2V, Figure 5a, terminate the output
with 50ꢀ-to-1.2V, DC-coupled, not 100ꢀ differentially
across the outputs.
If AC-coupling is used, Figure 5d, terminate into 50ꢀ
to 1.2V before the coupling capacitor and then
connect to a high value resistor to a reference
voltage.
Do not AC couple with internally terminated receiver.
For example, 50ꢀ ANY-IN input. AC-coupling will
offset the output voltage by 200mV and this offset
voltage will be too low for proper driver operation.
M9999-033108-A
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March 2008
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Micrel, Inc.
SY54017R
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail Safe Feature
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March 2008
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Micrel, Inc.
SY54017R
Typical Characteristics
VCC = 2.5V, VCCO =1.2V GND = 0V, VIN = 100mV, RL = 50ꢀ to 1.2V, TA = 25°C, unless otherwise stated.
M9999-033108-A
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March 2008
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Micrel, Inc.
SY54017R
Functional Characteristics
VCC = 2.5V, VCCO =1.2V GND = 0V, VIN = 400mV, RL = 50ꢀ to 1.2V, Data Pattern: 223-1, TA = 25°C, unless otherwise
stated.
M9999-033108-A
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March 2008
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Micrel, Inc.
SY54017R
Functional Characteristics
VCC = 2.5V, VCCO =1.2V GND = 0V, VIN = 400mV, RL = 50ꢀ to 1.2V, TA = 25°C, unless otherwise stated.
M9999-033108-A
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Micrel, Inc.
SY54017R
Input and Output Stage
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified CML Output Buffer
Single-Ended and Differential Swings
Figure 3a. Single-Ended Swing
Figure 3b. Differential Swing
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Micrel, Inc.
SY54017R
Input Interface Applications
Figure 4b. CML Interface
(DC-Coupled, 1.2V)
Figure 4a. CML Interface
(DC-Coupled, 1.8V, 2.5V)
Figure 4c. CML Interface
(AC-Coupled)
Figure 4f. LVDS Interface
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVPECL Interface
(DC-Coupled)
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Micrel, Inc.
SY54017R
CML Output Termination
Figure 5a. 1.2V or 1.8V CML DC-Coupled Termination
Figure 5b. 1.8V CML DC-Coupled Termination
Figure 5d. CML AC-Coupled Termination
(VCCO 1.2V only)
Figure 5c. CML AC-Coupled Termination
(VCCO 1.8V only)
Related Product and Support Documents
Part Number
Function
Datasheet Link
SY54017AR
3.2Gbps Precision, 2:1 Low Voltage CML Mux with
Internal Termination
http://www.micrel.com/page.do?page=/product-
info/products/sy54017ar.shtml
HBW Solutions
New Products and Termination Application Notes
http://www.micrel.com/page.do?page=/product-
info/as/HBWsolutions.shtml
M9999-033108-A
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Micrel, Inc.
SY54017R
Package Information
16-Pin MLF® (3mm x3mm) (MLF-16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2008 Micrel, Incorporated.
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