SY55856UHI [MICREL]
2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE; 2.5V / 3.3V 2.5GHz的差分双通道精密CML延迟线
| 型号： | SY55856UHI |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE |
| 文件： | 总9页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SuperLite™
SY55856U
2.5V/3.3V 2.5GHz
DIFFERENTIAL 2-CHANNEL
PRECISION CML DELAY LINE
FEATURES
■ Guaranteed AC parameters over temp and voltage
SuperLite™
• > 2.5GHz f
MAX
• < 384ps prop delay
DESCRIPTION
• < 120ps t /t
r f
■ Delay either clock or data
The SY55856U is a 2.5GHz, two-channel, fully differential
CML (Current Mode Logic) delay line. The device is
optimized to adjust the relative delay between two channels,
such as clock and data, in 50ps increments. Both inputs
may be adjusted in either direction in 7 increments of 50ps,
for a total adjustment range of ±350ps. In addition, the
clock input maybe inverted through the CINV control pin.
The SY55856U inputs are designed to accept single-
ended or differential CML signals. The differential CML
outputs are optimized for 50Ω loads (50Ω source terminated),
thus only requires a single 100Ω resistor across the output
pair. Output rise and fall time is an extremely fast 110ps(max)
and the differential swing is 400mV. The maximum
throughput of the SY55856U is guaranteed to exceed
2.5GHz (5Gbps).
■ 50ps increments
■ ± 350ps total delay
■ Source terminated CML outputs
■ Full differential I/O
■ Wide supply voltage spectrum: 2.3V to 3.6V
■ Available in a tiny 32-pin EPAD-TQFP package
APPLICATIONS
■ Data communications systems
■ Telecom systems
■ High-speed backplanes
■ Signal de-skewing
■ Pulse alignment
■ Digitally controlled delay lines
SuperLite is a trademarks of Micrel, Inc.
Rev.: E
Amendment: /0
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: January 2007
SuperLite™
SY55856U
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating
Package
Marking
Lead
Finish
Part Number
Type
H32-1
H32-1
H32-1
Range
32 31 30 29 28 27 26 25
SY55856UHI
Industrial
Industrial
Industrial
55856U
55856U
Sn-Pb
Sn-Pb
/DATA_IN
GND
1
24
23
/DATA_OUT
2
3
GND
SY55856UHITR(2)
SY55856UHG(3)
DATA_IN
GND
22
21
20
DATA_OUT
GND
55856U with
NiPdAu
Top View
EPAD-TQFP
4
5
6
7
8
Pb-Free bar line indicator Pb-Free
55856U with NiPdAu
Pb-Free bar line indicator Pb-Free
GND
CLK_IN
GND
GND
SY55856UHGTR(2, 3) H32-1
Industrial
H32-1
19
18
CLK_OUT
GND
/CLK_IN
/CLK_OUT
17
Notes:
9
10 11 12 13 14 15 16
1. Contact factory for die availability. Dice are guaranteed at T = 25°C, DC Electricals only.
A
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
32-Pin EPAD-TQFP (H32-1)
PIN DESCRIPTION
Pin Number
Pin Name
Pin Function
1, 3
/DATA_IN,
DATA_IN
CML Input (Differential). This is one of the CML inputs, the data in signal. A delayed
version of this signal appears at DATA_OUT, /DATA_OUT.
2, 4, 5, 7,
GND
Ground.
18, 20. 21, 23
22, 24
6, 8
DATA_OUT,
/DATA_OUT
CML Output (Differential). This is one of the CML outputs, the data output. It is a delayed
version of DATA_IN , /DATA_IN.
CLK_IN,
/CLK_IN
CML Input (Differential). This is one of the differential CML inputs, the clock in signal. A
delayed version of this input appears at CLK_OUT, /CLK_OUT.
17, 19
/CLK_OUT,
CLK_OUT
CML Output (Differential). This is one of the CML outputs, the clock output. It is a delayed,
copy of CLK_IN, /CLK_IN.
9, 10, 15, 16
VCC
Power Supply.
25, 26, 31, 32
11
CINV
VT Input (Single Ended). This is the clock inversion select signal. This input optionally
inverts the CLK_IN, /CLK_IN signal which results in an inverted CLK_OUT, /CLK_OUT. A
voltage below the VT threshold results in no inversion. A voltage above the threshold value
results in an inversion from the clock input to the clock output. Refer to the “VT input”
section below.
14
LVL
Analog Input. This input determines what level differentiates logic high from logic low. This
input affects the behavior of the CINV, S0, S1 and S2 inputs. Please refer to the “VT input“
section below for more details. For the control interface, see Figure 3a. For TTL control
interface, see Figure 3b.
30
DELAY_SEL
S0, S1, S2
VT Input (Single Ended). CML compatible control logic. This is the delay path control input.
Logic high delays the clock signal with respect to the data signal. A logic low delays the
data signal with respect to the clock signal. Inputs S2, S1 and S0 control amount of delay.
27, 28, 29
VT Input (Single Ended). CML compatible control logic. This is the delay selection control
input. These three bits define how much relative delay will occur between the data and
clock signals, as per the truth table shown in Table 2. For the control logic interface, see
Figure 3a. For TTL control interface, see Figure 3b. S0=LSB.
12, 13
NC
No Connect.
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
2
SuperLite™
SY55856U
Micrel, Inc.
BLOCK DIAGRAM
A0
A1
A3
A2
A4
A5
A6
DATA_OUT
/DATA_OUT
VCC
DATA_IN
S2
INPUT
BUFFER
A7
S1
/DATA_IN
S0
S2
S1
5k
5k
S0
LVL
VREF = 1.3V
DEL_SEL
A0
A1
A3
A2
A4
A5
A6
CLK_OUT
/CLK_OUT
CLK_IN
/CLK_IN
S2
INPUT
BUFFER
A7
S1
S0
CINV
GND
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
3
SuperLite™
SY55856U
Micrel, Inc.
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs
the Voltage threshold that differentiates logic high from logic
The true pin of a CML input pair is internally biased to low for these five inputs only. If LVL is left unconnected, the
ground through a 75kΩ resistor. The complement pin of a
V
+ GND
CC
VT inputs will switch at about
or V
,
TCL
CML input pair is internally biased halfway between V
CC
2
and ground by a voltage divider consisting of two 75kΩ
resistors. To keep a CML input at static logic zero at V
whichever is higher. To obtain a logic switching threshold
different from this, the LVL input must be driven with the
actual desired threshold voltage. The user may drive the
>
CC
3.0V, leave both inputs unconnected. For V
≤ 3.0V,
CC
connect the complement input to V
and leave the true
CC
LVL pin with any voltage between V – 0.1V and ground.
CC
input unconnected. To make an input static logic one,
For example, driving LVL with a voltage set at Vcc – 1.3V
causes the VT inputs to accept single ended PECL outputs
and switch appropriately.
Note that VT inputs are internally clamped so that the
threshold will not fall below VTCL Volts. Since driving the
LVL input to ground causes the threshold to be somewhere
(max), it is expected that the
user will keep the Voltage at the LVL pin at or above V
(max). Please refer to Figure 3 for clarification.
connect the true input to V , and leave the complement
CC
input unconnected. These are the only safe ways to cause
CML inputs to be at a static value. In particular, no CML
input should be directly connected to ground. All NC pins in
the figures below should be left unconnected.
VT (Variable Threshold) Inputs
Five inputs to SY55856U, CINV, DELAY_SEL, S0, S1, and
S2, are variable threshold inputs. The LVL input determines
between V
(min) and V
TCL
TCL
TCL
NC
NC
IN
/IN
VCC
NC
IN
/IN
VCC > 3.0V
(1)
Figure 1. Hard Wiring a Logic "1"
NC
IN
VCC
/IN
Logic
Switching
Threshold
VCC ≤ 3.0V
VCC
(1)
VCC — 0.1V
Figure 2. Hard Wiring a Logic "0"
VCC
3.0V ≤ VCC ≤ 3.6V
VCC
VTCL
Operating
1.10k
3
SY55856
Range
TTL
Driver
S0, S1, S2
VTCL
VCC — 0.1V VCC
LVL
Input
LVL
909Ω
Figure 3a. Logic Switching Threshold
Note 1. IN is either the DATA_IN or the CLK_IN input. /IN is either the /
Figure 3b. Interfacing TTL-to-CML Select
(CINV, DELAY_SEL, S0, S1, S2)
DATA_IN or the /CLK_IN input.
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
4
SuperLite™
SY55856U
Micrel, Inc.
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Value
–0.5 to +6.0
–0.5 to VCC+5.0
–0.5 to VCC+5.0
–40 to +85
260
Unit
V
VCC
VIN
Power Supply Voltage
Input Voltage
V
VOUT
TA
CML Output Voltage
V
Operating Temperature Range
LeadcTemperature (soldering, 20sec.)
Storage Temperature Range
°C
°C
°C
TLEAD
Tstore
θJA
–55 to +125
Package Thermal Resistance
(Junction-to-Ambient)
– Still Air
– 500lfpm
28
20
°C/W
°C/W
Exposed pad soldered to PCB GND pin
θJC
Package Thermal Resistance
(Junction-to-Case)
4
°C/W
Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions
for extended periods may affect device reliability.
CML TERMINATION
SY55856U inputs are designed to accept a termination
resistor between the true and complement inputs of a CML
differential input pair, as shown in Figure 4.
All CML inputs accept a CML output from any other
member of this family. All CML outputs are source
terminated 50Ω differential drivers as shown in Figure 4.
SY55856U expects its inputs to be externally terminated.
VCC
50Ω
50Ω
50Ω
100Ω
50Ω
16mA
SY55856U
Figure 4. 50Ω Load CML Output
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
5
SuperLite™
SY55856U
Micrel, Inc.
TRUTH TABLES
DATA_IN CLK_IN CINV DATA_OUT /DATA_OUT CLK_OUT /CLK_OUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
Table 1. Input to Output Connectivity
S2
S1
S0
DATA_OUT
CLK_OUT
(D_SEL=0) (ps)
(D_SEL=1) (ps)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
350
300
250
200
150
100
50
0
50
100
150
200
250
300
350
0
Table 2. Nominal Differential Delay Values
Note:
1. Table 2 defines the approximate relative delay between the two paths. For example, if S2, S1, S0 = 000, and an edge appears at CLK_IN at the
same instant as an edge appears at DATA_IN, then an edge at CLK_OUT will appear about 350ps earlier than an edge at DATA_OUT. That is,
negative values imply CLK_OUT being shifted early with respect to DATA_OUT. Likewise, a positive value in the third column implies that
CLK_OUT is shifted late with respect to DATA_OUT. Please consult the “AC ELECTRICAL CHARACTERISTICS” section for more precise delay
values.
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
6
SuperLite™
SY55856U
Micrel, Inc.
DC ELECTRICAL CHARACTERISTICS
TA = –40°C
Typ.
TA = +25°C
Typ.
TA = +85°C
Typ.
Symbol
VCC
Parameter
Min.
2.3
—
Max.
3.6
Min.
2.3
—
Max.
3.6
Min.
2.3
—
Max. Unit Condition
Power Supply Voltage
Power Supply Current
—
—
—
3.6
V
ICC
—
140
115
140
—
140
mA
No Load
VT INPUTS DC ELECTRICAL CHARACTERISTICS
(1)
VCC = 2.3V to 3.6V; GND = 0V; T = –40°C to +85°C
A
Symbol
VILVL
Parameter
Analog Input(2)
Min.
VTCL
Typ.
—
Max.
VCC - 0.1
VCC
Unit
V
V
VIHVT
VILVT
VIST
VT Input High Voltage(3,4)
VT Input High Voltage(3,4)
VSW + 0.1
0.0
—
—
VSW – 0.1
—
V
Input Switching Threshold
Differential Voltage(5)
100
50
mV
VTCL
Threshold Clamp Voltage
1.2
—
1.4
V
Note 1. DC parameters are guaranteed after thermal equilibrium has been established.
Note 2. The LVL input determines the voltage switching threshold that differentiates logic high from logic low for the V inputs S0, S1, S2,
T
DELAY_SEL, and CINV. LVL may be driven to V , but this is not useful, as the V inputs could then not get high enough to reliably indicate
CC
T
logic high. Also, as shown in Figure 3, the LVL input internally clamps at V
. If LVL is left unconnected, the V inputs will switch at about the
TCL
T
maximum of
VCC + GND
VCC
2
=
and V
.
TCL
2
Note 3.
Note 4.
V
V
inputs are S0, S1, S2, DELAY_SEL, and CINV.
T
is the threshold switching voltage. It is equal to the voltage at the LVL pin, when this voltage is above V
(max). V
is some value
SW
SW
TCL
between V
(min) and V
(max) when the Voltage at the LVL pin is below V
(max).
TCL
TCL
TCL
Note 5.
V
V
is the voltage difference needed to guarantee a stable logic level. Logic high must be at least V
above V . Logic low must be at most
IST SW
IST
IST
below V . Thus, the minimum input swing on a given V input pin, that is, |V
- V
|, must be at least 2×V
.
SW
T
IHVT
ILVT
IST
CML DC ELECTRICAL CHARACTERISTICS
VCC = 2.3V to 3.6V; GND = 0V; T = –40°C to +85°C
A
Symbol
VID
Parameter
Min.
100
Typ.
Max.
—
Unit Condition
Differential Input Voltage
Input HIGH Voltage
Input LOW Voltage
—
—
mV
V
VIH
1.6
VCC
VIL
1.5
—
VCC –0.1
VCC
V
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing(6)
VCC –0.040
VCC –1.00
VCC –0.010
VCC –0.800
V
V
V
No Load
No Load
VCC –0.65
VOUT
(Swing)
0.650
—
0.800
0.400
1.00
—
No Load
50Ω Environment
ROUT
Output Source Impedance
(CLK_OUT, /CLK_OUT and
DATA_OUT, /DATA_OUT)
40
50
60
Ω
Note 6.
V
is defined as the swing on one output of a differential pair, that is |V - V | on one pin. The swing for common mode noise
OUT(SWING) OH OL
immunity purposes is 2 × V
. Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a
OUT(SWING)
400mV swing is available in a 50Ω environment. Refer to “CML Termination” figures for more details.
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
7
SuperLite™
SY55856U
Micrel, Inc.
(7)
AC ELECTRICAL CHARACTERISTICS
VCC = 2.3V to 3.6V; GND = 0V
TA = –40°C
TA = +25°C
TA = +85°C
Symbol
fMAX
∆t
Parameter
Maximum Frequency
Delay step size
Min.
2.5
Max.
—
Min.
Max.
—
Min.
Max.
—
Unit
GHz
ps
2.5
36
2.5
36
36
52
52
52
tPLH
tPHL
Delay line insertion delay(8)
232
384
232
384
232
384
ps
tDELAY Delay line range
tJITTER Output jitter
250
—
365
<1
290
—
420
<1
335
—
465
<1
ps
psRMS
ps
tSKEW
DC
Delay line duty cycle skew (ItPLH–tPHLI)
—
50
—
50
—
50
Duty cycle
45
—
55
45
—
55
45
—
55
%
tr/tf
CML Output rise/fall time
(20% to 80%)
100
110
120
ps
Note 7. Tested using the 50W load, as shown in Figure 4.
Note 8. Delay line insertion delay is the minimum input-to-output delay with select control set to S2:S0 = 0 for CLK_OUT and S2:S0 = 7 for
DATA_OUT. This resulting delay is the inherent propagation delay.
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
8
SuperLite™
SY55856U
Micrel, Inc.
32-PIN EPAD-TQFP (DIE UP) (H32-1)
Rev. 01
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
M9999-011207
hbwhelp@micrel.com or (408) 955-1690
9
相关型号：
©2020 ICPDF网 联系我们和版权申明