SY87700LHGTR [MICREL]
3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY; 3.3V 32-175Mbps AnyRate时钟和数据恢复
| 型号： | SY87700LHGTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| 文件： | 总14页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 32-175Mbps AnyRate®
CLOCK AND DATA RECOVERY
SY87700L
FEATURES
DESCRIPTION
■ Industrial temperature range (–40°C to +85°C)
■ 3.3V power supply
The SY87700L is a complete Clock Recovery and Data
Retiming integrated circuit for data rates from 32Mbps
up to 175Mbps NRZ. The device is ideally suited for
SONET/SDH/ATM applications and other high-speed data
transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
■ SONET/SDH/ATM compatible
■ Clock and data recovery from 32Mbps up to
175Mbps NRZ data stream, clock generation from
32Mbps to 175Mbps
■ Two on-chip PLLs: one for clock generation and
another for clock recovery
■ Selectable reference frequencies
■ Differential PECL high-speed serial I/O
■ Line receiver input: no external buffering needed
■ Link Fault indication
The SY87700L also includes a link fault detection
circuit.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
■ 100k ECL compatible I/O
■ Complies with Bellcore, ITU/CCITT and ANSI
specifications for applications such as OC-1 and
OC-3 as well as proprietary applications
APPLICATIONS
■ Available in 32-pin EPAD-TQFP and 28-pin SOIC
packages (28-pin SOIC is available, but is not
recommended for new designs.)
■ SONET/SDH/ATM OC-1 and OC-3
■ Fast Ethernet, SMPTE 259
■ Proprietary architecture up to 175Mbps
BLOCK DIAGRAM
PLLR P/N
RDOUTP
(PECL)
RDINP
(PECL)
RDINN
PHASE
DETECTOR
RDOUTN
RCLKP
(PECL)
0
1
CHARGE
PUMP
VCO
RCLKN
PHASE/
FREQUENCY
DETECTOR
LINK
FAULT
DETECTOR
CD
LFIN
(TTL)
(PECL)
REFCLK
(TTL)
PHASE/
FREQUENCY
DETECTOR
CHARGE
PUMP
VCO
TCLKP
(PECL)
1
0
TCLKN
VCC
DIVIDER
VCCA
BY 8, 10, 16, 20
VCCO
SY87700L
GND
DIVSEL 1/2
PLLS P/N
(TTL)
FREQSEL 1/2/3
(TTL)
CLKSEL
(TTL)
AnyRate is a registered trademark of Micrel, Inc.
Rev.: H
Amendment: /0
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
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Issue Date: September2006
Micrel, Inc.
SY87700L
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
VCCA
LFIN
1
2
3
4
5
6
7
8
9
28 VCC
Package Operating
Package
Marking
Lead
Finish
27 CD
Part Number
Type
Z28-1
Z28-1
H32-1
H32-1
Z28-1
Range
DIVSEL1
RDINP
26 DIVSEL2
25 RDOUTP
24 RDOUTN
23 VCCO
22 RCLKP
21 RCLKN
20 VCCO
19 TCLKP
18 TCLKN
17 CLKSEL
16 PLLRP
15 PLLRN
SY87700LZI
Industrial
Industrial
Industrial
Industrial
Industrial
SY87700LZI
SY87700LZI
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
NiPdAu
SY87700LZITR(2)
RDINN
SY87700LHI
SY87700LHITR(2)
SY87700LZG(3)
SY87700LHI
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
SY87700LHI
SY87700LZG with
Pb-Free bar line indicator Pb-Free
SY87700LZG with NiPdAu
Pb-Free bar line indicator Pb-Free
SY87700LHG with NiPdAu
Pb-Free bar line indicator Pb-Free
SY87700LHG with NiPdAu
Pb-Free bar line indicator Pb-Free
SY87700LZGTR(2, 3)
SY87700LHG
Z28-1
H32-1
Industrial
Industrial
Industrial
N/C 10
PLLSP 11
PLLSN 12
GND 13
SY87700LHGTR(2, 3) H32-1
GND 14
Notes:
28-Pin SOIC (Z28-1)
1. Contact factory for die availability. Dice are guaranteed at T = 25°C, DC Electricals only.
A
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
32 31 30 29 28 27 26 25
RDOUTP
NC
RDINP
RDINN
1
2
3
4
5
6
24
23
22
21
20
19
RDOUTN
VCCO
RCLKP
RCLKN
VCCO
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
NC
TCLKP
TCLKN
7
8
18
17
9 10 11 12 13 14 15 16
32-Pin EPAD TQFP (H32-1)
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SY87700L
PIN DESCRIPTIONS
Pin Number
SOIC
Pin Number
TQFP
Pin Name
Pin Function
4
5
2
3
RDINP,
RDINN
Serial Data Input (Differential PECL): These built-in line receiver inputs are
connected to the differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data (RDOUT) information.
The incoming data rate can be within one of five frequency ranges depend-
ing on the state of the FREQSEL pins. See “Frequency Selection” table.
7
5
REFCLK
CD
Reference Clock (TTL Inputs): This input is used as the reference for the
internal frequency synthesizer and the “training” frequency for the receiver
PLL to keep it centered in the absence of data coming in on the RDIN inputs.
27
26
Carrier Detect (PECL Input): This input controls the recovery function of the
Receive PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When this input is
HIGH the input data stream (RDIN) is recovered normally by the Receive
PLL. When this input is LOW the data on the inputs RDIN will be internally
forced to a constant LOW, the data outputs RDOUT will remain LOW, the
Link Fault Indicator output LFIN forced LOW and the clock recovery PLL
forced to look onto the clock frequency generated from REFCLK.
6
8
9
4
6
7
FREQSEL1,
FREQSEL2,
FREQSEL3
Frequency Select (TTL Inputs): These inputs select the output clock
frequency range as shown in the “Frequency Selection” table.
3
26
32
25
DIVSEL1,
DIVSEL2
Divider Select (TTL Inputs): These inputs select the ratio between the
output clock frequency (RCLK/TCLK) and the REFCLK input frequency as
shown in the “Reference Frequency Selection” table.
17
2
16
31
CLKSEL
LFIN
Clock Select (TTL Inputs): This input is used to select either the recovered
clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency
synthesizer (CLKSEL = LOW) to the TCLK outputs.
Link Fault Indicator (TTL Output): This output indicates the status of the
input data stream RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range of the Receive
PLL (1000ppm). LFIN is an asynchronous output.
25
24
24
23
RDOUTP,
RDOUTN
Receive Data Output (Differential PECL): These ECL 100k outputs
represent the recovered data from the input data stream (RDIN). This
recovered data is specified against the rising edge of RCLK.
22
21
21
20
RCLKP,
RCLKN
Clock Output (Differential PECL): These ECL 100k outputs represent the
recovered clock used to sample the recovered data (RDOUT).
19
18
18
17
TCLKP,
TCLKN
Clock Output (Differential PECL): These ECL 100k outputs represent
either the recovered clock (CLKSEL = HIGH) used to sample the recovered
data (RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
11
12
9
10
PLLSP,
PLLSN
Clock Synthesis PLL Loop Filter. External loop filter pins for the clock
synthesis PLL.
16
15
15
14
PLLRP,
PLLRN
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver
PLL.
27, 28,
29, 30
19, 22
12, 13
1, 8
VCC
VCCA
VCCO
GND
NC
Supply Voltage(1)
Analog Supply Voltage(1)
Output Supply Voltage(1)
Ground
1
20, 23
13, 14
10
No Connect
Note:
1.
V
, V
, V
must be the same value.
CC
CCA
CCO
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Micrel, Inc.
SY87700L
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram generates
Lock Detect
The SY87700L contains a link fault indication circuit which
a clock that is at the same frequency as the incoming data monitors the integrity of the serial data inputs. If the received
bit rate at the Serial Data input. The clock is phase aligned serial data fails the frequency test, the PLL will be forced to
by a PLL so that it samples the data in the center of the lock to the local reference clock. This will maintain the correct
data eye pattern.
frequency of the recovered clock output under loss of signal
The phase relationship between the edge transitions of or loss of lock conditions. If the recovered clock frequency
the data and those of the generated clock are compared by deviates from the local reference clock frequency by more
a phase/frequency detector. Output pulses from the detector than approximately 1000ppm, the PLL will be declared out
indicate the required direction of phase correction. These of lock. The lock detect circuit will poll the input data stream
pulses are smoothed by an integral loop filter. The output of in an attempt to reacquire lock to data. If the recovered
the loop filter controls the frequency of the Voltage Controlled clock frequency is determined to be within approximately
Oscillator (VCO), which generates the recovered clock.
1000ppm, the PLL will be declared in lock and the lock
Frequency stability without incoming data is guaranteed detect output will go active.
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30µs data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
M9999-111406
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Micrel, Inc.
SY87700L
CHARACTERISTICS
Jitter Transfer
Performance
Jitter transfer function is defined as the ratio of jitter on
the output OC-N/STS-N signal to the jitter applied on the
input OC-N/STS-N signal versus frequency. Jitter transfer
requirements are shown in Figure 2.
The SY87700L PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the Bellcore
Specifications: GR-253-CORE, Issue 2, December 1995 and
ITU-T Recommendations: G.958 document, when used with
differential inputs and outputs.
Jitter Generation
The jitter of the serial clock and serial data outputs shall
not exceed .01 U.I. rms when a serial data input with no
jitter is presented to the serial data inputs.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak
amplitude of sinusoidal jitter applied on the input signal that
causes an equivalent 1dB optical/electrical power penalty.
SONET input jitter tolerance requirement condition is the
input jitter amplitude which causes an equivalent of 1dB
power penalty.
A
Jitter Transfer (dB)
0.1
-20dB/decade
15
-20dB/decade
1.5
-20dB/decade
Acceptable
Range
-20
0.40
f0
f1
f2
f4
ft
fc
Frequency
Frequency
OC/STS-N
Level
f0
(Hz)
f1
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
OC/STS-N
Level
fc
(kHz)
P
(dB)
3
10
30
300
6.5
65
3
130
0.1
Figure 1. Input Jitter Tolerance
Figure 2. Jitter Transfer
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SY87700L
FREQUENCY SELECTION TABLE
fVCO/fRCLK
f
RCLK Data Rates (Mbps)
FREQSEL1
FREQSEL2
FREQSEL3
0
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
6
125 - 175
94 - 157
63 - 104
47 - 78
8
1
12
16
24
—
—
0
1
32 - 52
0
undefined
undefined
X(2)
Notes:
1. SY87700L operates from 32-175MHz. For higher speed applications, the SY87701L operates from 32MHz to 1250MHz.
2. X is a DON'T CARE.
(1)
REFERENCE FREQUENCY SELECTION
LOOP FILTER COMPONENTS
fRCLK/fREFCLK
DIVSEL1
DIVSEL2
R5
C3
0
0
1
1
0
1
0
1
8
10
16
20
PLLSP
PLLSN
Wide Range
R5 = 350Ω
C3 = 1.0µF (X7R Dielectric)
R6
C4
PLLRP
PLLRN
Wide Range
R6 = 680Ω
C4 = 1.0µF (X7R Dielectric)
Note:
1. Suggested Values. Values may vary for different applications.
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Micrel, Inc.
SY87700L
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (V ) .................................. –0.5V to +4.0V Supply Voltage (V ) .............................. +3.15V to +3.45V
CC
CC
Input Voltage (V ) ......................................... –0.5V to V
Ambient Temperature (T ) ......................... –40°C to +85°C
(3)
Package Thermal Resistance
IN
CC
A
Output Current (I
)
Continuous ............................................................. 50mA
OUT
(4)
SOIC (θ ) ..................................................................... 80°C/W
JA
(5)
EPAD TQFP (θ )
JA
Surge....................................................................100mA
Lead Temperature (soldering, 20 sec.) ..................... 260°C
0lfpm airflow .................................................27.6°C/W
200lfpm airflow .............................................22.6°C/W
500lfpm airflow .............................................20.7°C/W
Storage Temperature (T ) ....................... –65°C to +150°C
S
DC ELECTRICAL CHARACTERISTICS
Symbol
VCC
Parameter
Condition
Min
Typ
3.3
Max
3.45
230
Units
V
Power Supply Voltage
Power Supply Current
3.15
ICC
170
mA
PECL 100K DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C; unless noted.
Symbol
VIH
Parameter
Condition
Min
Typ
—
Max
Units
V
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input LOW Current
VCC –1.165
VCC –1.810
VCC –1.075
VCC –1.860
0.5
VCC –0.880
VCC –1.475
VCC –0.830
VCC –1.570
—
VIL
—
V
VOH
VOL
IIL
50Ω to VCC –2V
50Ω to VCC –2V
VIN = VIL(min)
—
V
—
V
—
µA
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C; unless noted.
Symbol
VIH
Parameter
Condition
Min
2.0
—
Typ
Max
VCC
0.8
—
Units
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
—
—
—
—
V
V
V
V
VIL
VOH
VOL
IIH
IOH = –0.4mA
IOL = 4mA
2.0
—
0.5
VIN = 2.7V, VCC = max.
VIN = VCC, VCC = max.
–125
—
—
—
—
+100
µA
µA
IIL
Input LOW Current
VIN = 0.5V, VCC = max.
–300
–15
—
—
—
µA
IOS
Output Short Circuit Current
VOUT = 0V (maximum 1 sec)
–100
mA
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Airflow of 500lfpm recommended for 28-pin SOIC.
4. 28-pin SOIC package is NOT recommended for new designs.
5. Using JEDEC standard test boards with die attach pad soldered to PCB. See www.amkor.com for additional package details.
M9999-111406
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Micrel, Inc.
SY87700L
AC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C; unless noted.
Symbol
fVCO
∆fVCO
tACQ
tCPWH
tCPWL
tir
Parameter
Condition
Min
750
—
Typ
—
5
Max
1250
—
Units
MHz
%
VCO Center Frequency
VCO Center Frequency Tolerance
Acquisition Lock Time
fREFCLK × Byte Rate
Nominal
—
—
—
—
0.5
—
—
15
µs
REFCLK Pulse Width HIGH
REFCLK Pulse Width LOW
REFCLK Input Rise Time
Output Duty Cycle (RCLK/TCLK)
4
—
ns
4
—
ns
—
2
ns
tODC
tr, tf
45
100
55
% of UI
ps
ECL Output Rise/Fall Time
(20% to 80%)
50Ω to VCC –2V
500
tSKEW
tDV
Recovered Clock Skew
Data Valid
–200
—
—
—
+200
—
ps
ps
ps
1/(2 × fRCLK) – 200
1/(2 × fRCLK) – 200
tDH
Data Hold
—
TIMING WAVEFORMS
t
t
CPWH
CPWL
REFCLK
t
t
ODC
ODC
RCLK
t
SKEW
t
tDH
DV
RDOUT
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SY87700L
32-PIN APPLICATION EXAMPLE
R13
VCC
LED
D2
R12
Q1
2N2222A
VEE
DIODE
D1
32 31
30 29 28 27 26 25
VCC
RDOUTP
RDOUTN
VCCO
NC
24
23
22
1
2
3
4
5
6
7
8
1N4148
R10
RDINP
RDINN
FREQSEL1
REFCLK
1
2
3
RCLKP
RCLKN
VCCO
21
20
19
18
FREQSEL2
FREQSEL3
CLKSEL
DIVSEL1
DIVSEL2
4
5
6
7
TCLKP
TCLKN
NC
17
9
10
11 12 13 14 15 16
CD
VEE R11
SW1
1kΩ
C3
C4
GND
R1
R2
C2
C1
Ferrite Bead
BLM21A102
V
(+2V)
V
CCO
VCC
L3
L2
L1
(+2V)
CC
V
(+2V)
CCA
C5
22µF
C6
0.1µF
C7
6.8µF
C11
0.1µF
C12
0.01µF
C8
6.8µF
C13
0.1µF
C14
0.01µF
C9
6.8µF
C15
0.1µF
C16
0.01µF
GND
C10
6.8µF
C17
0.1µF
C18
0.01µF
V
(–1.3V)
EE
VEE
C21
0.01µF
C19
1.0µF
C20
0.1µF
V
(–1.3V)
EEA
Note:
C3, C4 are optional.
C1 = C2 = 1.0µF
R1 = 350Ω
R2 = 680Ω
R3 through R10 = 5kΩ
R12 = 12kΩ
R13 = 130Ω
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Micrel, Inc.
SY87700L
28-PIN APPLICATION EXAMPLE
VCC
(R17 - R22)
5kΩ x 6
1
2
3
4
5
6
VCC
Ferrite Bead
BLM21A102
Stand Off
LED
R8
D2
FB1
0.1µF
130Ω
0.1µF
22µF
22µF
C9
C8
C7
C6
GND
1
2
3
VCCA
LFIN
VCC 28
J1
VCC
Capacitor Pads
(1206 format)
27
26
25
VCC
CD
R7
1kΩ
Diode D1
1N4148
R1
R2
R4
DIVSEL1
RDINP
DIVSEL2
RDOUTP
RDOUTN
VCCO
0.1µF
0.1µF
C1
C2
4
5
C14
C15
RDIN
RDINN
24
23
22
R3
6
7
8
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
N/C
0.1µF
0.1µF
See Table 1
RCLKP
RCLKN
C16
C17
GND
21
9
VCCO 20
0.1µF
0.1µF
19
10
11
TCLKP
C18
C19
R5
80Ω
18
PLLSP
TCLKN
LOOP FILTER
NETWORK
C3
12
13
14
17
PLLSN
CLKSEL
1.5µF
R6 50Ω
16
15
PLLRP
PLLRN
GND
GND
If VCC = +3.3V:
R9 through R14 = 220Ω
C4
1.0µF
REFCLK
(TTL)
VCC
GND
NC
C5
Pin 1 (VCCA)
Pin 28 (VCC)
XTAL
Oscillator
0.1µF
0.1µF
0.1µF
0.1µF
C10
C11
C12
14
1
7
ꢀ
C13
0.1µF
Pin 23 (VCCO)
Pin 20 (VCCO)
8
VCC
120Ω
R21
For AC-Coupling Only
C1 = C2 = 0.1µF
R1 = R2 = 680Ω
R3 = R4 = 1kΩ
For DC Mode Only
C1 = C2 = Shorted
R1 = R2 = 130Ω
R3 = R4 = 82Ω
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
SY87700L
BILL OF MATERIALS (32-PIN EPAD-TQFP)
Item
Part Number
Manufacturer
Description
Qty
C1, C2
VJ0603Y105JXJAT
Vishay
1.0µF Ceramic Capacitor, Size 0603
X7R Dielectric, Loop Filter, Critical
2
C3, C4
VJ0603Y105JXJAT
Vishay
1.0µF Ceramic Capacitor, Size 0603
X7R Dielectric, Loop Filter, Optional
2
C5
C6
ECS-T1ED226R
Panasonic
Panasonic
22µF Tantalum Electrolytic Capacitor, Size D
1
1
ECU-V1H104KBW
0.1µF Ceramic Capacitor, Size 1206
X7R Dielectric, Power Supply Decoupling
C7, C8, C9, C10
C19
ECS-T1EC685R
ECJ-3YB1E105K
Panasonic
Panasonic
6.8µF Tantalum Electrolytic Capacitor, Size C
4
1
1.0µF Ceramic Capacitor, Size 1206
X7R Dielectric, VEEA Decoupling
C11, C13
C15, C17
C20
ECU-V1H104KBW
ECU-V1H104KBW
ECU-V1H104KBW
ECU-V1H103KBW
ECU-V1H103KBW
ECU-V1H103KBW
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
0.1µF Ceramic Capacitor, Size 1206
X7R Dielectric, VCCO/VCC Decoupling
1
1
1
1
1
1
0.1µF Ceramic Capacitor, Size 1206
X7R Dielectric, VCCA/VEEA Decoupling
0.1µF Ceramic Capacitor, Size 1206
X7R Dielectric, VEEA Decoupling
C12, C14
C16, C18
C21
0.01µF Ceramic Capacitor, Size 1206
X7R Dielectric, VCCO/VCC Decoupling
0.01µF Ceramic Capacitor, Size 1206
X7R Dielectric, VCCA/VEEA Decoupling
0.01µF Ceramic Capacitor, Size 1206
X7R Dielectric, VEEA Decoupling
D1
D2
1N4148
Diode
1
1
P300-ND/P301-ND
Panasonic
T-1 3/4 Red LED
J1, J2, J3, J4, J5 142-0701-851
J6, J7, J8, J9,
J10, J11, J12
Johnson
Components
Gold Plated, Jack, SMA, PCB Mount
12
L1, L2, L3
Q1
BLM21A102F
NTE123A
Murata
NTE
Ferrite Beads, Power Noise Suppression
2N2222A Buffer/Driver Transistor, NPN
3
1
1
R1
350Ω Resistor, 2%, Size 0402
Loop Filter Component, Critical
R2
680Ω Resistor, 2%, Size 0402
Loop Filter Component, Critical
1
8
R3, R4, R5, R6
R7, R8, R9, R10
5kΩ Pull-up Resistors, 2%, Size 1206
R11
R12
R13
SW1
1kΩ Pull-down Resistor, 2%, Size 1206
12kΩ Resistor, 2%, Size 1206
1
1
1
1
130Ω Pull-up Resistor, 2%, Size 1206
SPST, Gold Finish, Sealed Dip Switch
206-7
CTS
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
11
Micrel, Inc.
SY87700L
28 LEAD SOIC .300" WIDE (Z28-1)
Rev. 02
Note:
The 28 Lead SOIC package is NOT recommended for new designs.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
12
Micrel, Inc.
SY87700L
32 LEAD EPAD TQFP (DIE UP) (H32-1)
Rev. 01
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
Heavy Copper Plane
VEE
PCB Thermal Consideration for 32-Pin EPAD-TQFP Package
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
13
Micrel, Inc.
SY87700L
APPENDIX A
Layout and General Suggestions
1. Establish controlled impedance stripline, microstrip, or co-planar construction techniques.
2. Signal paths should have, approximately, the same width as the device pads.
3. All differential paths are critical timing paths, where skew should be matched to within ±10ps.
4. Signal trace impedance should not vary more than ±5%. If in doubt, perform TDR analysis of all high-speed signal
traces.
5. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to
reduce stray capacitance. Be careful of crosstalk coupling into the filter network.
6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately
decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals.
7. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based
oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter.
8. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1kΩ
resistor to V
.
EE
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
14
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