SY89295UMITR [MICREL]
2.5V / 3.3V 1.5 GHZ PRECISION LVPECL PROGRAMMABLE DELAY; 2.5V / 3.3V 1.5 GHz的LVPECL精密可编程延迟
| 型号： | SY89295UMITR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 2.5V / 3.3V 1.5 GHZ PRECISION LVPECL PROGRAMMABLE DELAY |
| 文件： | 总15页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Edge™
SY89295U
2.5V/3.3V 1.5GHz PRECISION
LVPECL PROGRAMMABLE DELAY
FEATURES
■ Precision LVPECL programmable delay line
■ Guaranteed AC performance over temperature and
Precision Edge™
voltage:
• > 1.5GHz f
DESCRIPTION
MAX
• < 160ps rise/fall times
■ Low-jitter design:
The SY89295U is a programmable delay line that delays
the input signal using a digital control signal. The delay can
vary from 3.2ns to 14.8ns in 10ps increments. In addition,
the input signal is LVPECL, uses either a 2.5V ±5% or 3.3V
±10% power supply, and is guaranteed over the full industrial
temperature range (–40°C to +85°C).
• < 10ps total jitter
pp
• < 2ps
• < 1ps
cycle-to-cycle jitter
random jitter
rms
rms
■ Programmable delay range: 3.2ns to 14.8ns in 10ps
The delay varies in discrete steps based on a control
word. The control word is 10-bits long and controls the
delay in 10ps increments. The eleventh bit is D[10] and is
used to simultaneously cascade the SY89295U which allows
for a larger delay range. In addition, the input pins IN and
/IN default to an equivalent low state when left floating.
Further, for maximum flexibility, the control register interface
accepts CMOS or TTL level signals.
increments
■ Increased monotonicity over the MIC100EP195
■ ±10% of LSB INL
■ V output reference voltage
BB
■ Parallel inputs accepts LVPECL or CMOS/LVTTL
■ Low voltage operation: 2.5V ±5% and 3.3V ±10%
■ Industrial –40°C to +85°C temperature range
For applications that requires an analog delay input, see
the SY89296L which is a programmable delay chip with
fine tune control. The SY89295U and SY89296U are part
of Micrel’s high-speed, Precision Edge™ product line.
■ Available in 32-pin (5mm × 5mm) MLF™ and 32-pin
TQFP packages
All support documentation can be found on Micrel’s
website at www.micrel.com.
APPLICATIONS
■ Clock de-skewing
■ Timing adjustments
■ Aperture centering
Precision Edge is a trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
Rev.: A
Amendment: /0
M9999-031604
hbwhelp@micrel.com or (408) 955-1690
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Issue Date: March 2004
Precision Edge™
SY89295U
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package
Operating
Range
Package
Marking
32 3130 29 28 27 26 25
1
2
3
4
5
6
7
8
D8
24 GND
Part Number
Type
MLF-32
MLF-32
T32-1
23
22
21
20
19
18
D9
D10
IN
D0
VCC
Q
/Q
VCC
VCC
SY89295UMI
SY89295UMITR(2)
Industrial
Industrial
Industrial
Industrial
SY89295U
SY89295U
SY89295U
SY89295U
/IN
SY89295UTI
SY89295UTITR(2)
VBB
VEF
VCF
T32-1
17 NC
9 10 11 12 13 14 15 16
Notes:
1. Contact factory for die availability. Dice are guaranteed at T = 25°C,
A
DC electricals only.
2. Tape and Reel.
32-Pin MLF™ (MLF-32)
32 31 30 29 28 27 26 25
D8
D9
D10
IN
1
2
3
4
5
6
24
23
22
21
20
19
GND
D0
VCC
Q
/Q
/IN
VCC
VCC
NC
VBB
VEF
VCF
7
8
18
17
9 10 1112 13 14 15 16
32-Pin TQFP (T32-1)
TRUTH TABLES
Input/Output
Inputs
Digital Control Latch
Outputs
LEN
Latch Action
Pass Through D[10:0]
Latched D[10:0]
IN
0
/IN
1
OUT
/OUT
0
1
0
1
1
0
1
0
Input Enable
/EN
Q, /Q
0
1
IN, /IN Delayed
Latched D[10:0]
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Precision Edge™
SY89295U
Micrel
FUNCTIONAL BLOCK DIAGRAM
IN
0
1
0
1
0
1
0
1
0
1
/IN
512
GD
256
GD
128
GD
64
GD
32
GD
/EN
0
1
0
1
0
1
0
1
0
1
16
GD
8
GD
4
GD
2
GD
1
GD
D[9:0]
LEN
10-bit
Latch
SETMIN
Q
0
1
SETMAX
/Q
1
GD
CASCADE
/CASCADE
D[10]
Latch
VBB
VCF
VEF
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Precision Edge™
SY89295U
Micrel
PIN DESCRIPTION
Pin Number
Pin Name
Pin Function
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
D[9:0]
CMOS, ECL, or TTL Control Bits: These control signals adjust the delay from IN to Q.
See “AC Electrical Characteristics” for delay values. In addition, see “Interface Applications”
section which illustrates the proper interfacing techniques for different logic standards.
D[9:0] contains pull-downs and defaults LOW when left floating. D0 (LSB), and D9 (MSB).
See “Typical Operating Characteristics” for delay information.
3
D10
CMOS, ECL, or TTL Control Bit: This bit is used to cascade devices for an extended delay
range. In addition, it drives CASCADE, and /CASCADE. Further, D[10] contains a pull-
down and defaults LOW when left floating.
4, 5
6
IN, /IN
VBB(1)
LVPECL/ECL Signal Input: Input signal to be delayed. IN contains a 75kΩ pull-down and
will default to a logic LOW if left floating.
Reference Voltage Output: When using a single-ended input signal source to IN or /IN,
connect the unused input of the differential pair to this pin. This pin can also be used to
rebias AC-coupled inputs to IN and /IN. When used, de-couple to VCC using a 0.01µF
capacitor, otherwise leave floating if not used. Maximum sink/source is ±0.5mA.
7
VEF
Reference Voltage Output: Connect this pin to VCF when D[9:0], and D[10] is ECL.
Logic Standard
LVPECL
CMOS
VCF Connects to
(1)
VEF
,
No Connect
1.5V Source
TTL
8
9, 24, 28
10
VCF
Reference Voltage Input: The voltage driven on VCF sets the logic transition threshold for
D[9:0], and D[10].
GND,
Exposed Pad(2)
Negative Supply: For MLF™ package, exposed pad must be connected to a ground plane
that is the same potential as the ground pin.
LEN
ECL Control Input: When HIGH latches the D[9:0] and D[10] bits. When LOW, the D[9:0]
and D[10] latches are transparent.
11
SETMIN
ECL Control Input: When HIGH, D[9:0] registers are reset. When LOW, the delay is set
by SETMAX or D[9:0] and D[10]. SETMIN contains a pull-down and defaults LOW when
left floating.
12
SETMAX
VCC
ECL Control Input: When SETMAX is set HIGH and SETMIN is set LOW, D[9:0] =
10’b1111111111. When SETMAX is LOW, the delay is set by SETMIN or D[9:0] and
D[10]. SETMAX contains a pull-down and defaults LOW when left floating.
13, 18, 19, 22
14, 15
Positive Power Supply: Bypass with 0.1µF and 0.01µF low ESR capacitors.
/Cascade,
Cascade
LVPECL Differential Output: The outputs are used when cascading two or more
SY89295U to extend the delay range.
16
20, 21
17
/EN
/Q, Q
NC
LVPECL Single-Ended Control Input: When LOW, Q is delayed from IN. When HIGH,
Q is a differential LOW. /EN contains a pull-down and defaults LOW when left floating.
LVPECL Differential Output: Q is a delayed version of IN. Always terminate the
output with 50Ω to VCC – 2V. See “Output Interface Applications” section.
No Connect.
Notes:
1. Single-ended operation is only functional at 3.3V.
2. MLF™ package only.
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SY89295U
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Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (V ) .................................. –0.5V to +4.0V Supply Voltage (V ) .............................. +2.375V to +3.6V
CC
CC
Input Voltage (V ) ......................................... –0.5V to V
Ambient Temperature (T ) ......................... –40°C to +85°C
IN
CC
A
(3)
LVPECL Output Current (I
)
Package Thermal Resistance
OUT
Continuous .........................................................50mA
MLF™ (θ )
JA
Surge ................................................................100mA
Still-Air .............................................................35°C/W
MLF™ (ψ
)
Lead Temperature (soldering, 10 sec.) ................... +220°C
JB
Junction-to-Board ............................................28°C/W
Storage Temperature Range (T ) ............ –65°C to +150°C
S
TQFP (θ
)
JA
Still-Air .............................................................28°C/W
TQFP (ψ
)
JB
Junction-to-Board ............................................20°C/W
(4)
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC
Power Supply
VCC = 2.5V
VCC = 3.3V
2.375
3
2.5
3.3
2.625
3.6
V
V
IEE
Power Supply Current
No load, max VCC
See Figure 1a.
See Figure 1b.
220
1200
2400
mA
mV
mV
VIN
Input Voltage Swing (IN, /IN)
150
300
VDIFF_IN
Differential Input Voltage
Swing (IN, /IN)
VIHCMR
Input High Common Mode Range
IN, INB
VEE+1.2
VCC
V
VCC = 3.3V, TA = –40°C to 85°C, unless otherwise stated.
Symbol
VIH
Parameter
Condition
Min
Typ
Max
2.420
1.675
Units
Input High Voltage (IN, /IN)
Input Low High Voltage (IN, /IN)
Output Voltage Reference
Mode Connection
2.075
1.355
V
V
V
V
V
VIL
VBB
Ground Reference
Ground Reference
1.325 1.425 1.525
VEF
1.20
1.55
1.30
1.65
1.4
VCF
Input Select Voltage
1.75
VCC = 2.5V, TA = –40°C to 85°C, unless otherwise stated.
Symbol
VIH
Parameter
Condition
Min
Typ
Max
2.42
Units
Input High Voltage (IN, /IN)
Input Low High Voltage (IN, /IN)
Output Voltage Reference
Mode Connection
2.075
1.355
V
V
V
V
V
VIL
1.675
VBB
Ground Reference
Ground Reference
1.325 1.425 1.525
VEF
1.20
1.15
1.30
1.25
1.40
1.35
VCF
Input Select Voltage
Notes:
1. Permanent device damage may occur if the ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and
functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance on MLF™ packages assumes exposed pad is soldered (or equivalent) to the device most negative potential (GND).
4. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. Input and output
parameters vary 1:1 with V
.
CC
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5
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SY89295U
Micrel
(5)
LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS
VCC = 2.5V ±5% or 3.3V ±10%; RLOAD = 50Ω to VCC–2V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
VOH
Parameter
Condition
Min
Typ
Max
Units
V
Output HIGH Voltage (Q, /Q)
Output LOW Voltage (Q, /Q)
Output Voltage Swing (Q, /Q)
2.155 2.280 2.405
1.355 1.480 1.605
VOL
V
VOUT
See Figure 1a.
See Figure 1b.
550
1.1
800
1.6
mV
V
VDIFF_OUT
Differential Output Voltage Swing
(Q, /Q)
(6)
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C, unless otherwise stated.
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Units
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
VIL
0.8
40
V
IIH
µA
µA
IIL
-300
Notes:
5. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. All input and output
parameters vary 1:1 with V , however, the values are referenced to 3.3V.
CC
6. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established.
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SY89295U
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(7)
AC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C; unless otherwise stated.
Symbol
fMAX
Parameter
Condition
Min
Typ
Max
Units
Maximum Operating Frequency
Clock
VOUT ≥ 400mV
1.5
GHz
tpd
Propagation Delay
IN to Q; D[0–10]=0
IN to Q; D[0–10]=1023
/EN to Q: D[0–10]=0
D10 to CASCADE
3200
11500
3400
350
4200
14800
4400
670
ps
ps
ps
ps
tRANGE
Programmable Range
tpd (max) – tpd (min)
8300
ps
ps
tSKEW
Duty Cycle Skew
Note 8
25
∆t
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
D0-D9 High
10
15
35
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
70
145
290
575
1150
2300
4610
9220
INL
tS
Integral Non-Linearity
Setup Time
Note 9
–10
+10
%LSB
D to LEN
200
350
300
ps
ps
ps
D to IN Note 10
/EN to IN Note 11
tH
tR
Hold Time
LEN to D
IN to /EN Note 12
200
400
ps
ps
Release Time
/EN to IN
SETMAX to LEN
SETMIN to LEN
500
500
450
ps
ps
ps
tJITTER
Cycle-to-Cycle Jitter
Total Jitter
Random Jitter
Note 13
Note 14
Note 15
2
10
1
psrms
psp-p
psrms
tr, tf
Output Rise/Fall Time
20% to 80% (Q)
20% to 80% (CASCADE)
50
90
85
160
300
ps
ps
Duty Cycle
45
55
%
Notes:
7. High frequency AC electricals are guaranteed by design and characterization.
8. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output.
9. INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The
maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1024. INL = measured
delay – measured minimum delay + (step number × TIL).
10. This setup time defines the amount of time prior to the input signal. The delay tap of the device must be set.
11. This setup time defines the amount of the time that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater
than ±75mV to the IN, /IN transition.
12. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than ±75mV to the IN, /IN transition.
13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs.
T
= T – T +1, where T is the time between rising edges of the output signal.
jitter_cc
n n
12
14. Total jitter definition: With an ideal clock input, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-
peak jitter value.
15. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean.
Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps.
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SY89295U
Micrel
TYPICAL OPERATING CHARACTERISTICS
V
= 3.3V, GND = 0, D = 100mV, T = 25°C, unless otherwise stated.
IN A
CC
Amplitude vs. Frequency
Delay vs. D[9:0]
900
800
700
600
500
400
300
200
100
0
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
500 1000 1500 2000 2500
FREQUENCY (MHz)
0
500
1000
D[9:0]
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SY89295U
TIMING DIAGRAM
/IN
IN
tpd
/Q
Q
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VDIFF_IN
,
VIN,
VOUT
VDIFF_OUT 1.6V (Typ.)
800mV (Typ.)
Figure 1b. Differential Voltage Swing
Figure 1a. Single-Ended Voltage Swing
INPUT AND OUTPUT STAGES
Figure 2a. Differential
Input Stage
Figure 2b. Single-Ended
Input Stage
Figure 3. LVPECL
Output Stage
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SY89295U
OUTPUT INTERFACE APPLICATIONS
+3.3V
+3.3V
R1
130Ω
R1
130Ω
Z0 = 50Ω
Z0 = 50Ω
Q
+3.3V
+3.3V
Z0 = 50Ω
Z0 = 50Ω
Q
/Q
50Ω
50Ω
/Q
R2
82Ω
R2
82Ω
VCC
For +2.5V systems
R1 = 19Ω
VT = VCC
—2V
C (optional)
For +2.5V systems
R1 = 250Ω, R2 = 62.5Ω
50Ω
R1
0.01µF
Figure 4. Parallel Termination
Figure 5. Y-Termination
+3.3V
+3.3V
R1
130Ω
R1
1kΩ
R3
1kΩ
+3.3V
Q
+3.3V
Z0 = 50Ω
/Q
R2
82Ω
R2
82Ω
R4
1.6kΩ
For +2.5V systems
R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ
Figure 6. Terminating Unused I/O
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SY89295U
APPLICATIONS INFORMATION
For best performance, use good high-frequency layout
In all cases, V
current sinking or sourcing must be
BB
techniques, filter V supplies, and keep ground connections
limited to 0.5mA or less.
CC
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the SY89295U
data inputs and outputs.
Setting D Input Logic Thresholds
In all designs where the SY89295U GND supply is at
zero volts, the D inputs can accommodate CMOS and TTL
level signals, as well as PECL or LVPECL. Figures 11, 12
and 14 show how to connect V and V for all possible
V
Reference
BB
The VBB pin is an internally generated reference and is
CF
EF
available for use only by the SY89295U. When unused, this
cases.
pin should be left unconnected. Two common uses for V
are to handle a single-ended PECL input, and to re-bias
inputs for AC-coupling applications.
BB
Cascading
Two or more SY89295U may be cascaded in order to
extend the range of delays permitted. Each additional
SY89295U adds about 3.2ns to the minimum delay and
adds another 10240ps to the delay range.
If either IN or /IN are driven by a single-ended output,
V
is used to bias the unused input. Please refer to Figure
BB
10. The PECL signal driving the SY89295U may optionally
be inverted in this case.
Internal cascade circuitry has been included in the
SY89295U. Using this internal circuitry, the SY89295U may
be cascaded without any external gating.
When the signal is AC-coupled, V is used, as shown
BB
in Figure 13, to re-bias IN and/or /IN. This ensures that
SY89295U inputs are within acceptable common mode
range.
Examples of cascading 2, 3, or 4 SY89295U appear in
Figures 7, 8, and 9.
Control Word (11bits)
C[10]
D[10]
D[9:0]
IN
C[9:0]
#1
#2
IN
Q
Q
/IN
/Q
/IN
/Q
SETMIN
SETMAX
/CASCADE
CASCADE
Figure 7. Cascading Two SY89295U
Control Word (12bits)
C[11]
C[10]
D[10]
D[10]
D[9:0]
IN
C[9:0]
#1
#2
#3
IN
Q
IN
Q
Q
/IN
/Q
/IN
/Q
/IN
/Q
SETMIN
/CASCADE
/CASCADE
SETMIN
SETMAX
SETMAX
CASCADE
CASCADE
Figure 8. Cascading Three SY89295U
11
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SY89295U
Control Word (12bits)
C[11]
C[10]
D[10]
D[10]
D[9:0]
IN
#1
#2
#3
#4
C[9:0]
IN
Q
IN
Q
IN
Q
Q
/IN
/Q
/IN
/Q
/IN
/Q
/IN
/Q
SETMIN
/CASCADE
/CASCADE
SETMIN
SETMAX
SETMIN
SETMAX
SETMAX
CASCADE
CASCADE
Figure 9. Cascading Four SY89295U
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SY89295U
INTERFACE APPLICATIONS
VCC = +3.3V
D[0:10]
LVPECL
Signals
VCF
VEF
Figure 11. V /V Biasing for
Figure 10. Interfacing to a
CF EF
LVPECL Control (D) Input
Single-Ended LVPECL Signal
To invert the signal, connect the LVPECL
input to /IN and connect VCC to IN.
VCC = +3.3V
VCC = +3.3V
TTL
Inputs
D[0:10]
VCF
CMOS
Inputs
D[0:10]
IN
NC VCF
NC VEF
NC VEF
VCC
/IN
1.5kΩ
50Ω
0.01µF
50Ω
VBB
0V
Figure 13. Re-Biasing an
AC-Coupled Signal
Figure 14. V /V Biasing for
Figure 12. V /V Biasing for
CF EF
CF EF
LVTTL Control (D) Input
CMOS Control (D) Input
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number
Function
Data Sheet Link
SY89295U
2.5/3.3V 1.5GHz Precision LVPECL
Programmable Delay
www.micrel.com/product-info/products/sy89295u.shtml
www.micrel.com/product-info/products/sy89296u.shtml
www.amkor.com/products/notes_papers/MLF_appnote_0902.pdf
http://www.micrel.com/product-info/as/solutions.shtml
SY89296U
2.5/3.3V 1.5GHz Precision LVPECL
Programmable Delay with Fine Tune Control
16-MLF Manufacturing Guidelines
Exposed Pad Application Note
HBW Solutions
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Precision Edge™
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SY89295U
32 LEAD MicroLeadFrame™ (MLF-32)
Rev. 01
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
Heavy Copper Plane
VEE
PCB Thermal Consideration for 32-Pin MLF™ Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.
M9999-031604
hbwhelp@micrel.com or (408) 955-1690
14
Precision Edge™
Micrel
SY89295U
32 LEAD TQFP (T32-1)
Rev. 01
MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2004 Micrel, Incorporated.
M9999-031604
hbwhelp@micrel.com or (408) 955-1690
15
相关型号：
SY89295UTI
Active Delay Line, Programmable, 1-Func, 1023-Tap, Complementary Output, PQFP32, TQFP-32
MICROCHIP
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