SY89542UMI [MICREL]
2.5V, 3.2Gbps DUAL, DIFFERENTIAL 2:1 LVDS MULTIPLEXER WITH INTERNAL TERMINATION; 2.5V , 3.2Gbps的双差分2 : 1 LVDS与内部终端复用器型号: | SY89542UMI |
厂家: | MICREL SEMICONDUCTOR |
描述: | 2.5V, 3.2Gbps DUAL, DIFFERENTIAL 2:1 LVDS MULTIPLEXER WITH INTERNAL TERMINATION |
文件: | 总10页 (文件大小:340K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2.5V, 3.2Gbps DUAL, DIFFERENTIAL
2:1 LVDS MULTIPLEXER WITH
INTERNAL TERMINATION
®
Precision Edge
SY89542U
FEATURES
■ Dual 2:1 multiplexer
®
Precision Edge
■ Guaranteed AC performance over temp and voltage:
• DC-to > 3.2Gbps data rate throughput
DESCRIPTION
• < 600ps In-to-Out t
pd
• < 150ps t /t
r f
The SY89542U includes two precision, high-speed 2:1
differential Muxes with LVDS (350mV) compatible outputs
with a guaranteed data rate throughput of 3.2Gbps over
temperature and voltage.
■ Ultra-low jitter design:
• < 1ps
random jitter
RMS
• < 10ps deterministic jitter
PP
• < 10ps total jitter (clock)
PP
The SY89542U differential inputs include a unique, 3-pin
internal termination that allows access to the termination
• < 0.7ps
crosstalk-induced jitter
RMS
■ Unique input isolation design minimizes crosstalk
■ Internal input termination
network through a V pin. This feature allows the device to
T
easily interface to different logic standards, both AC- and
DC-coupled without external resistor-bias and termination
networks. The result is a clean, stub-free, low jitter interface
solution.
■ Unique input termination and V pin accepts
T
DC-Coupled and AC-coupled inputs (LVDS, LVPECL,
CML)
The SY89542U operates from a single 2.5V supply, and
is guaranteed over the full industrial temperature range
(–40°C to +85°C). For applications that require a 3.3V supply,
consider the SY89543L. The SY89542U is part of Micrel’s
■ 350mV LVDS output swing
■ CMOS/TTL compatible MUX select
■ Power supply 2.5V ±5%
®
■ –40°C to +85°C temperature range
Precision Edge product family.
®
■ Available in 32-pin (5mm x 5mm) MLF package
All support documentation can be found on Micrel’s web
site at www.micrel.com.
APPLICATIONS
■ Redundant clock/data switchover
■ SONET/SDH multi-channel select applications
■ Fibre Channel applications
■ GigE applications
FUNCTIONAL BLOCK DIAGRAM
INA0
INB0
50Ω
50Ω
VTA0
VTB0
50Ω
50Ω
2:1 MUX
2:1 MUX
/INA0
/INB0
0
0
LVDS
LVDS
QA
/QA
QB
MUX A
MUX B
/QB
1
1
S
S
INA1
VTA1
INB1
VTB1
50Ω
50Ω
50Ω
50Ω
/INA1
/INB1
SELA (CMOS/TTL)
SELB (CMOS/TTL)
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Rev.: D
Amendment: /0
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: August 2007
Precision Edge®
SY89542U
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating
Package
Marking
Lead
Finish
32 31 30 29 28 27 26 25
Part Number
Type
Range
1
24
23
VCC
VCC
/INA0
VTA0
INA0
VCC
SELA
GND
VCC
SY89542UMI
MLF-32
MLF-32
MLF-32
Industrial
Industrial
Industrial
SY89542U
SY89542U
Sn-Pb
Sn-Pb
2
3
4
5
6
7
INB1
VTB 1
/INB1
VCC
SELB
GND
VCC
22
21
20
19
18
SY89542UMITR(2)
SY89542UMG(3)
SY89542U with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY89542UMGTR(2,3) MLF-32
Industrial
SY89542U with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
8
17
9
10 11 12 13 14 15 16
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
®
32-Pin MLF
3. Recommended for new designs.
PIN DESCRIPTION
Pin Number
Pin Name
Pin Function
4, 2, 32, 30,
27, 25, 23, 21
INA0, /INA0,
INA1, /INA1,
INB0, /INB0,
INB1, /INB1
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate
state if left open. Unused differential input pairs can be terminated by connecting one input
to VCC and the complementary input to GND through a 1kΩ resistor. The VT pin is to be
left open in this configuration. Please refer to the “Input Interface Applications” section for
more details.
3, 31, 26, 22
6, 19
VTA0 , VTA1,
VTB0, VTB1
Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT
pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more details.
SELA, SELB
VCC
These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers.
Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default
to logic HIGH state if left open. Input switching threshold is VCC/2.
1, 5, 8, 17, 20,
24, 28, 29
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors. The 0.01µF
capacitor should be as close to VCC pin as possible.
10, 11, 14, 15
QA, /QA,
QB, /QB
Differential Outputs: This differential LVDS output pair provides a copy of the selected
input. It is a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs.
Please refer to the “Truth Table” for details. Unused output pairs must be terminated with
100Ω across the differential pair.
7, 9, 12, 13, 16, 18
GND,
Ground: Ground pin and exposed pad must be connected to the same ground plane.
Exposed pad
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hbwhelp@micrel.com or (408) 955-1690
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®
Precision Edge
SY89542U
Micrel, Inc.
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (V ) ................................. –0.5V to +4.0V
Supply Voltage (V ) ............................. 2.375V to 2.625V
CC
CC
Input Voltage (V ) ........................................ –0.5V to V
Ambient Temperature (T ) ........................ –40°C to +85°C
IN
CC
A
(3)
(4)
Termination Current
Package Thermal Resistance
®
MLF (θ )
JA
Source or sink current on V ..................................... ±100mA
T
Input Current
Still-Air ................................................................ 35°C/W
Source or sink current on IN, /IN .......................... ±50mA
500lfpm .............................................................. 28°C/W
®
Lead Temperature (soldering, 20 sec.) ................... +260°C
MLF (ψ )
JB
Storage Temperature (T ) ....................... –65°C to +150°C
Junction-to-Board ................................................20°C/W
S
(5)
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C; Unless otherwise stated.
Symbol
VCC
Parameter
Condition
Min
Typ
2.5
70
Max
2.625
95
Units
V
Power Supply
2.375
(6)
ICC
Power Supply Current
No Load, Max. VCC
mA
Ω
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
80
40
100
120
RIN
Input Resistance
50
60
Ω
(IN-to-VT, /IN-to-VT)
VIH
Input High Voltage (IN, /IN)
Input Low Voltage (IN, /IN)
Input Voltage Swing (IN, /IN)
1.2
0
VCC
VIH–0.1
VCC
V
V
V
V
VIL
VIN
Notes 7
Notes 7
0.1
0.2
VDIFF_IN
Differential Input Voltage Swing
|IN - /IN|
IN-to-VT
Voltage from Input to VT
1.8
V
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. Ψ uses 4-layer
JB
θ
in still-air unless otherwise stated.
JA
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50Ω pull-ups.
7. See “Single-Ended and Differential Swings” section for V and V
definition.
IN
DIFF_IN
M9999-082407
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Precision Edge®
SY89542U
Micrel, Inc.
(9)
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across Q and /Q, unless otherwise stated.
Symbol
VOH
Parameter
Condition
Min
Typ
Max
Units
V
Output HIGH Voltage (Q, /Q)
Output LOW Voltage (Q, /Q)
Output Voltage Swing (Q, /Q)
See Figure 5a
See Figure 5a
See Figures 1a, 5a
See Figure 1b
1.475
VOL
0.925
250
V
VOUT
350
700
mV
mV
VDIFF-OUT
Differential Output Voltage Swing
|Q - /Q|
500
VOCM
Output Common Mode Voltage
(Q, /Q)
See Figure 5b
See Figure 5b
1.125
–50
1.275
+50
V
∆VOCM
Change in Common Mode Voltage
(Q, /Q)
mV
(9)
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
VCC = 2.5V ±5%; TA = –40°C to +85°C; unless otherwise stated.
Symbol
VIH
Parameter
Condition
Min
Typ
Max
VCC
0.8
Units
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
VIL
V
IIH
40
µA
µA
IIL
–300
Note:
9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
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®
Precision Edge
SY89542U
Micrel, Inc.
(10)
AC ELECTRICAL CHARACTERISTICS
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
Gbps
GHz
ps
fMAX
Maximum Operating Frequency
NRZ Data
Clock
3.2
VOUT > 200mV
IN-to-Q
4
tpd
Differential Propagation Delay
250
200
350
350
450
600
20
SEL-to-Q
Note 11
ps
tSKEW
Input-to-Input Skew
Bank-to-Bank Skew
Part-to-Part Skew
ps
Note 12
25
ps
Note 13
200
1
ps
tJITTER
Data
Random Jitter (RJ) Note 14
Deterministic Jitter (DJ) Note 15
psRMS
psPP
psPP
psRMS
psRMS
ps
10
Clock
Total Jitter (TJ ) Note 16
Cycle-to-Cycle Jitter Note 17
Crosstalk-Induced Jitter Note 18
10
1
0.7
150
tr, tf
Output Rise / Fall Time
(20% to 80%)
At full output swing
35
80
Notes:
10. Measured with 100mV input swing. See “Timing Diagrams ” section for definition of parameters. High frequency AC-parameters are guaranteed by
design and characterization.
11. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew
does not include the output skew.
12. Bank-to-bank skew is the difference in time from input to the output between banks.
13. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
14. Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
23
15. Deterministic jitter is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 2 –1 PRBS pattern.
12
16. Total jitter definition: with an ideal clock input of frequency ≤ f
, no more than one output edge in 10 output edges will deviate by more than the
MAX
specified peak-to-peak jitter value.
17. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T -T where T is the time between rising edges of the output signal.
n
n-1
18. Crosstalk is measured at the output while applying two similar frequencies to adjacent inputs that are asynchronous with respect to each other at the
inputs.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89542U
Micrel, Inc.
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VDIFF_IN
,
VIN,
VOUT
VDIFF_OUT 700mV (Typ.)
350mV (Typ.)
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
TIMING DIAGRAM
IN
/IN
tpd
Q
/Q
SEL
SEL-to-Q
tpd
Q
/Q
Figure 2. Timing Diagram
TRUTH TABLE
IN0
0
IN1
X
SEL
Q
0
1
0
1
/Q
1
0
0
1
1
1
X
0
X
0
1
X
1
0
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®
Precision Edge
SY89542U
Micrel, Inc.
FUNCTIONAL CHARACTERISTICS
V
= 2.5V, T = 25°C.
CC
A
200MHz Output
1.6GHz Output
Q
Q
/Q
/Q
TIME (600ps/div.)
2.5GHz Output
TIME (80ps/div.)
3.2GHz Output
Q
Q
/Q
/Q
TIME (50ps/div.)
TIME (40ps/div.)
OC-12 Mask (223–1 PRBS)
2xGBE Mask (223–1 PRBS)
TIME (270ps/div.)
TIME (67ps/div.)
3.2Gbps Data Output (223-1 PRBS)
Output Amplitude
vs. Frequency
400
350
300
250
200
150
100
50
0
0
1
2
3
4
5
6
FREQUENCY (GHz)
TIME (80ps/div.)
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Precision Edge®
SY89542U
Micrel, Inc.
INPUT AND OUTPUT STAGE INTERNAL TERMINATION
VCC
IN
50Ω
VT
GND
50Ω
/IN
Figure 3. Simplified Differential Input Stage
INPUT INTERFACE APPLICATIONS
VCC
VCC
VCC
IN
LVPECL
IN
/IN
CML
IN
VCC
0.01µF
SY89542U
/IN
CML
/IN
SY89542U
GND
GND
VT
SY89542U
VCC –1.4V
Rp
GND
VT
NC
VT
For VCC = 2.5V, Rp = 19Ω
GND
Figure 4c. LVPECL
Interface (DC-Coupled)
Figure 4a. CML
Interface (DC-Coupled)
Figure 4b. CML
Interface (AC-Coupled)
VCC
VCC
IN
LVPECL
IN
/IN
LVDS
/IN
Rp
Rp
VCC
SY89542U
GND
–
1.4V
SY89542U
VT
GND
GND
NC
VT
GND
For VCC = 2.5V, Rp = 50Ω
Figure 4e. LVDS Interface
Figure 4d. LVPECL
Interface (AC-Coupled)
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
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®
Precision Edge
SY89542U
Micrel, Inc.
OUTPUT INTERFACE APPLICATIONS
ground between an LVDS driver and receiver. Also, change
in common mode voltage, as a function of data input, is
kept to a minimum, to keep EMI low.
LVDS specifies a small swing of 350mV typical, on a
nominal 1.25V common mode above ground. The common
mode voltage has tight limits to permit large variations in
50Ω
50Ω
VOCM
,
VOCM
,
∆VOCM
∆VOCM
50Ω
50Ω
GND
GND
Figure 5a. LVDS Differential Measurement
Figure 5b. LVDS Common Mode Measurement
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number
Function
Data Sheet Link
SY89543L
3.3V, 3.2Gbps Dual, Differential 2:1 LVDS
Multiplexer with Internal Input Termination
http://www.micrel.com/_pdf/HBW/sy89543l.pdf
SY89544U
SY89545L
SY89546U
SY89547L
2.5V, 3.2Gbps 4:1 LVDS Multiplexer with Internal http://www.micrel.com/_pdf/HBW/sy89544u.pdf
Input Termination
3.3V, 3.2Gbps 4:1 LVDS Multiplexer with Internal http://www.micrel.com/_pdf/HBW/sy89545l.pdf
Input Termination
2.5V 3.2Gbps, Differential 4:1 LVDS Multiplexer
with 1:2 Fanout and Internal Input Termination
http://www.micrel.com/_pdf/HBW/sy89546u.pdf
3.3V 3.2Gbps, Differential 4:1 LVDS Multiplexer
with 1:2 Fanout and Internal Input Termination
http://www.micrel.com/_pdf/HBW/sy89547l.pdf
MLF® Application Note
www.amkor.com/products/notes_papers/LF_AppNote_0902.pdf
www.micrel.com/product-info/products/solutions.shtml
HBW Solutions
New Products and Applications
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
9
Precision Edge®
SY89542U
Micrel, Inc.
®
32-PIN MicroLeadFrame (MLF-32)
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
Heavy Copper Plane
®
VEE
PCB Thermal Consideration for 32-Pin MLF Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-082407
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