ML65F16244 [MICRO-LINEAR]
16-Bit Buffer/Line Driver with 3-State Outputs; 16位与3态输出缓冲器/线路驱动器
| 型号： | ML65F16244 |
| 厂家： | 
MICRO LINEAR CORPORATION |
| 描述： | 16-Bit Buffer/Line Driver with 3-State Outputs |
| 文件： | 总10页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1998
PRELIMINARY
ML65F16244*
16-Bit Buffer/Line Driver with 3-State Outputs
GENERAL DESCRIPTION
FEATURES
The ML65F16244 is a BiCMOS, 16-bit buffer/line driver
with 3-state outputs. This device was specifically designed
for high speed bus applications. Its 16 channels support
propagation delay of 2ns maximum, and fast output
enable and disable times of 5ns or less to minimize
datapath delay.
■ Low propagation delays — 2ns maximum for 3.3V,
2.5ns maximum for 2.7V
■ Fast output enable/disable times of 5ns maximum
■ FastBus Charge current to minimize the bus settling
time during active capacitive loading
This device is designed to minimize undershoot,
overshoot, and ground bounce to decrease noise delays.
These transceivers implement a unique digital and analog
implementation to eliminate the delays and noise
inherent in traditional digital designs. The device offers a
new method for quickly charging up a bus load capacitor
to minimize bus settling times, or FastBus™ Charge.
FastBus Charge is a transition current, (specified as
■ 2.7 to 3.6V V supply operation;
CC
LV-TTL compatible input and output levels with 3-state
capability
■ Industry standard pinout compatible to FCT, ALV, LCX,
LVT, and other low voltage logic families
I
) that injects between 60 to 200mA (depending
■ ESD protection exceeds 2000V
DYNAMIC
on output load) of current during the rise time and fall
time. This current is used to reduce the amount of time it
takes to charge up a heavily-capacitive loaded bus,
effectively reducing the bus settling times, and
■ Full output swing for increased noise margin
■ Undershoot and overshoot protection to 400mV
improving data/clock margins in tight timing budgets.
typically
Micro Linear’s solution is intended for applications for
critical bus timing designs that include minimizing
device propagation delay, bus settling time, and time
delays due to noise. Applications include; high speed
memory arrays, bus or backplane isolation, bus to bus
bridging, and sub-2ns propagation delay schemes.
■ Low ground bounce design
The ML65F16244 follows the pinout and functionality of
the industry standard 2.7V to 3.6V-logic families.
* This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
V
CC
OE
A0
A1
A2
A3
B0
B1
B2
B3
GND
1 of 4
1
ML65F16244
PIN CONFIGURATION
ML65F16244
48-Pin SSOP (R48)
48-Pin TSSOP (T48)
1OE
1B0
1B1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2OE
1A0
1A1
GND
1A2
1A3
3
GND
1B2
4
5
1B3
6
V
7
V
CC
CC
2B0
2B1
8
2A0
2A1
GND
2A2
2A3
3A0
3A1
GND
3A2
3A3
9
GND
2B2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2B3
3B0
3B1
GND
3B2
3B3
V
V
CC
CC
4B0
4B1
4A0
4A1
GND
4A2
4A3
3OE
GND
4B2
4B3
4OE
TOP VIEW
FUNCTION TABLE
(Each 4-bit section)
INPUTS
OUTPUTS
OE
1Ai, 2Ai, 3Ai, 4Ai
1Bi, 2Bi, 3Bi, 4Bi
L
L
H
L
H
L
H
X
Z
L = Logic Low, H = Logic High, X = Don’t Care, Z = High Impedance
2
ML65F16244
PIN DESCRIPTION
PIN NAME
FUNCTION
PIN NAME
FUNCTION
Output Enable
Data Input
1
2
1OE
1B0
1B1
GND
1B2
1B3
Output Enable
Data Output
Data Output
Signal Ground
Data Output
Data Output
2.7V to 3.6V Supply
Data Output
Data Output
Signal Ground
Data Output
Data Output
Data Output
Data Output
Signal Ground
Data Output
Data Output
2.7V to 3.6V Supply
Data Output
Data Output
Signal Ground
Data Output
Data Output
Output Enable
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
3OE
4A3
4A2
GND
4A1
4A0
3
Data Input
4
Signal Ground
Data Input
5
6
Data Input
7
V
CC
V
CC
2.7V to 3.6V Supply
Data Input
8
2B0
2B1
GND
2B2
2B3
3B0
3B1
GND
3B2
3B3
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
9
Data Input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal Ground
Data Input
Data Input
Data Input
Data Input
Signal Ground
Data Input
Data Input
V
CC
V
CC
2.7V to 3.6V Supply
Data Input
4B0
4B1
GND
4B2
4B3
4OE
1A3
1A2
GND
1A1
1A0
2OE
Data Input
Signal Ground
Data Input
Data Input
Output Enable
3
ML65F16244
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Storage Temperature Range ..................... –65°C to 150°C
Junction Temperature..............................................150°C
Lead Temperature (Soldering, 10sec) ...................... 150°C
Thermal Impedance (q ) ..................................... 76°C/W
JA
V
............................................................................. 7V
CC
OPERATING CONDITIONS
DC InputVoltage .............................. –0.3V to V + 0.3V
CC
AC InputVoltage (PW < 20ns)................................. –3.0V
DC Output Voltage ...................................–0.3V to 7VDC
Output Current, Source or Sink ............................. 180mA
Temperature Range........................................0°C to 70°C
V
Operating Range ...................................2.7V to 3.6V
IN
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V = 3.3V, T = Operating Temperature Range (Note 1).
IN
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF)
tPHL, tPLH Propagation Delay
Ai to Bi
3.3V
2.7V
3.3V
2.7V
3.3V
2.7V
3.3V
2.7V
3.3V
2.7V
1.35
1.25
1.7
1.9
2
2.5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
pF
tOE
Output Enable Time
Output Disable Time
OE to Ai/Bi
DIRtoAi/Bi
OE to Ai/Bi
DIRtoAi/Bi
6
5
6
tOD
5
6
5
6
TOS
CIN
Output-to-Output Skew
Input Capacitance
300
5
DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = Open)
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Logic high
2.0
V
V
Logic low
0.8
300
300
5
Input High Current
Input Low Current
Per pin, VIN = 3V
Per pin, VIN = 0V
VCC = 3.6V, 0 < VIN < VCC
VCC = 3.6V, IIN = 18mA
Low to high transitions
High to low transitions
mA
mA
mA
V
IIL
IHI-Z
VIC
Three-State Output Current
Input Clamp Voltage
–0.7
80
–0.2
IDYNAMIC Dynamic Transition Current
(FastBus Charge)
mA
mA
V
80
VOH
Output High Voltage
VCC = 3.6V
VCC = 2.7V
2.4
3.4
2.35
2.25
V
VOL
ICC
Output LowVoltage
VCC = 2.7V and 3.6V
0.6
3
V
Quiescent Power Supply Current
VCC = 3.6V, f = 0Hz,
Inputs = VCC or 0V
µA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
4
ML65F16244
100
80
60
40
20
0
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
0.4
0.8
1.2
(V)
1.6
2
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
OL
V
(V)
OH
Figure 1a. Typical V vs. I for 3.3V V
.
Figure 1b. Typical V
vs. I
for 3.3V V
.
OL
OL
CC
OH
OH
CC
One Buffer Output
One Buffer Output
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
V = 2.7V
CC
V
= 2.7V
CC
V
= 3.3V
V
= 3.3V
CC
CC
0
25
50
75
0
25
50
75
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 2a. Propagation Delay vs. Load Capacitance:
3.3V, 50MHZ
Figure 2b. Propagation Delay vs. Load Capacitance:
2.7V, 50MHZ
60
50
60
50
75pF
75pF
40
30
20
10
0
40
30
50pF
30pF
50pF
20
30pF
10
0
0
20
40
60
80
100
0
20
40
60
80
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3a. I vs. Frequency: V = V = 3.3V.
Figure 3b. I vs. Frequency: V = V = 2.7V.
CC CC IN
CC
CC
IN
One Buffer Output
One Buffer Output
5
ML65F16244
FUNCTIONAL DESCRIPTION
1OE
1A0
1A1
1A2
1A3
1B0
1B1
1B2
1B3
2OE
2A0
2A1
2A2
2A3
2B0
2B1
2B2
2B3
3OE
3A0
3A1
3A2
3A3
3B0
3B1
3B2
3B3
4OE
4A0
4A1
4A2
4A3
4B0
4B1
4B2
4B3
Figure 4. Logic Diagram
1A0 1A1
1A2 1A3 2A0
2A1
2A2
2A3 3A0 3A1 3A2 3A3 4A0 4A1 4A2 4A3
2OE
1OE
3OE
4OE
2B0
2B1
2B2
2B3 3B0
3B1
3B2
3B3
4B0
4B1
4B2
4B3
1B0 1B1
1B2 1B3
Figure 5. Logic Symbol
6
ML65F16244
ARCHITECTURAL DESCRIPTION
One path sources current to the load capacitance where
the signal is asserted, and the other path sinks current
from the output when the signal is negated.
The ML65F16244 is a 16-bit buffer/line driver with 3-state
outputs designed for 2.7V to 3.6V V operation. This
CC
device is designed for Quad-Nibble, Dual-Byte or single
16-bit word memory interleaving operations. Each bank
has an independently controlled 3-state output enable pin
with output enable/disable access times of less than 5ns.
Each bank is configured to have four independent buffer/
line drivers.
The assertion path is the Darlington pair consisting of
transistors Q1 and Q2. The effect of transistor Q1 is to
increase the current gain through the stage from input to
output, to increase the input resistance and to reduce
input capacitance. During an input low-to-high transition,
the output transistor Q2 sources large amount of current to
quickly charge up a highly capacitive load which in
effect reduces the bus settling time. This current is
Until now, these buffer/line drivers were typically
implemented in CMOS logic and made to be TTL
compatible by sizing the input devices appropriately. In
order to buffer large capacitances with CMOS logic, it is
necessary to cascade an even number of inverters, each
successive inverter larger than the preceding, eventually
leading to an inverter that will drive the required load
capacitance at the required frequency. Each inverter
stage represents an additional delay in the gating process
because in order for a single gate to switch, the input
must slew more than half of the supply voltage. The best
of these 16-bit CMOS buffers has managed to drive 50pF
load capacitance with a delay of 3ns.
specified as I
.
DYNAMIC
The negation path is also the Darlington pair consisting of
transistor Q3 and transistor Q4. With M1 connecting to
the input of the Darlington pair, Transistor Q4 then sinks a
large amount of current during the input transition from
high-to-low.
Inverter X2 is a helpful buffer that not only drives the
output toward the upper rail but also pulls the output to
the lower rail.
Micro Linear has produced a 16-bit buffer/line driver with
a delay less than 2ns (at 3.3V) by using a unique circuit
architecture that does not require cascade logic gates.
There are a number of MOSFETs not shown in Figure 6.
These MOSFETs are used to 3-state the buffers.
The basic architecture of the ML65F16244 is shown in
Figure 6. In this circuit, there are two paths to the output.
V
CC
OE
Q1
Q2
X1
X2
IN
OUT
M1
Q3
Q4
Figure 6. One Buffer Cell of the ML65F16244
7
ML65F16244
CIRCUITS AND WAVE FORMS
V
CC
= 3V
1.5V
ML65F16244
DUT
INPUT
0V
3V
t
PLH
V
V
IN
OUT
1.5V
50pF
OUTPUT
0V
I
OUT
t
PHL
t
AND t INPUT = 2ns
FALL
RISE
Figure 7. Test Circuits for All Outputs
Figure 8. Propagation Delay
ENABLE
DISABLE
1.5V
V
= 3V
CC
1.5V
INPUT
CONTROL
INPUT
t
t
t
OD
OE
OE
3V
1.5V
OUTPUT1
OUTPUT
LOW
V
V
+ 0.3V
OL
OL
V
V
OH
OUTPUTi
i = 1 to 16
1.5V
– 0.3V
OUTPUT
HIGH
OH
0V
t
OS
t
OD
Figure 9. Enable and Disable Times
Figure 10. Output Skew
8
ML65F16244
PHYSICAL DIMENSIONS inches (millimeters)
Package: R48
48-Pin SSOP
0.620 - 0.630
(15.75 - 16.00)
48
0.291 - 0.301 0.402 - 0.410
(7.39 - 7.65) (10.21 - 10.41)
PIN 1 ID
1
0.015 - 0.025
(0.38 - 0.64)
(4 PLACES)
0.025 BSC
(0.63 BSC)
0.094 - 0.110
(2.39 - 2.79)
0º - 8º
0.006 - 0.014
(0.15 - 0.36)
0.024 - 0.040
(0.61 - 1.02)
0.005 - 0.010
(0.13 - 0.26)
0.088 - 0.092
(2.24 - 2.34)
0.008 - 0.016
(0.20 - 0.41)
SEATING PLANE
Package: T48
48-Pin TSSOP
0.487 - 0.497
(12.37 - 12.63)
0.236 - 0.244
(6.00 - 6.20)
0.319 BSC
(8.1 BSC)
PIN 1 ID
0.020 BSC
(0.50 BSC)
0.047 MAX
(1.20 MAX)
0º - 8º
0.007 - 0.011
(0.17 - 0.27)
0.020 - 0.028
(0.50 - 0.70)
0.004 - 0.008
(0.10 - 0.20)
0.031 - 0.039
(0.80 - 1.00)
0.002 - 0.006
(0.05 - 0.15)
SEATING PLANE
9
ML65F16244
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
0°C to 70°C
PACKAGE
ML65F16244CR (EOL)
ML65F16244CT (EOL)
48-Pin SSOP (R48)
48-Pin TSSOP (T48)
0°C to 70°C
© Micro Linear 2000.
is a registered trademark of Micro Linear Corporation. All other trademarks are the
property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property
right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications.
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
www.microlinear.com
DS65F16244-01
10
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