11LC010-E/SN 概述
1K-16K UNI/O® Serial EEPROM Family Data Sheet 1K - 16K UNI / O ?串行EEPROM系列数据手册 EEPROM
11LC010-E/SN 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Active | 零件包装代码: | SOIC |
包装说明: | 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8 | 针数: | 8 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.32.00.51 | Factory Lead Time: | 9 weeks |
风险等级: | 5.52 | Is Samacsys: | N |
最大时钟频率 (fCLK): | 1 MHz | 数据保留时间-最小值: | 200 |
耐久性: | 1000000 Write/Erase Cycles | JESD-30 代码: | R-PDSO-G8 |
JESD-609代码: | e3 | 长度: | 4.9 mm |
内存密度: | 1024 bit | 内存集成电路类型: | EEPROM |
内存宽度: | 8 | 湿度敏感等级: | 3 |
功能数量: | 1 | 端子数量: | 8 |
字数: | 128 words | 字数代码: | 128 |
工作模式: | SYNCHRONOUS | 最高工作温度: | 125 °C |
最低工作温度: | -40 °C | 组织: | 128X8 |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | SOP |
封装等效代码: | SOP8,.25 | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 并行/串行: | SERIAL |
峰值回流温度(摄氏度): | 260 | 电源: | 3/5 V |
认证状态: | Not Qualified | 座面最大高度: | 1.75 mm |
串行总线类型: | 1-WIRE | 最大待机电流: | 0.000005 A |
子类别: | EEPROMs | 最大压摆率: | 0.005 mA |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 2.5 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | AUTOMOTIVE |
端子面层: | Matte Tin (Sn) - annealed | 端子形式: | GULL WING |
端子节距: | 1.27 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | 40 | 宽度: | 3.9 mm |
最长写入周期时间 (tWC): | 10 ms | 写保护: | SOFTWARE |
Base Number Matches: | 1 |
11LC010-E/SN 数据手册
通过下载11LC010-E/SN数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载11AA010/11LC010
11AA020/11LC020
11AA040/11LC040
11AA080/11LC080
11AA160/11LC160
1K-16K UNI/O® Serial EEPROM Family Data Sheet
Features:
Description:
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology
The Microchip Technology Inc. 11AAXXX/11LCXXX
(11XX*) devices are a family of 1 Kbit through 16 Kbit
Serial Electrically Erasable PROMs. The devices are
organized in blocks of x8-bit memory and support the
patented** single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
- 1 mA active current, typical
- 1 µA standby current (max.) (I-temp)
• 128 x 8 through 2,048 x 8 Bit Organizations
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz
Clock Frequency
Low-voltage design permits operation down to 1.8V (for
11AAXXX devices), with standby and active currents of
only 1 uA and 1 mA, respectively.
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write enable latch bit
The 11XX family is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 3-lead SOT-23, 8-lead TDFN,
and 8-lead MSOP.
- Write-In-Progress bit
• Block Write Protection
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection
Package Types (not to scale)
MSOP
(MS)
PDIP/SOIC
(P, SN)
- Power-on/off data protection circuitry
- Write enable latch
NC
NC
1
2
3
4
8
7
6
5
VCC
NC
• High Reliability
1
2
3
4
8
7
6
5
NC
NC
NC
V
NC
NC
SCIO
CC
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4,000V
NC
NC
VSS
VSS
SCIO
• 3-lead SOT-23 Package
SOT23
TDFN
(MN)
• 8-lead PDIP, SOIC, MSOP, TDFN Packages
• Pb-Free and RoHS Compliant
• Available Temperature Ranges:
(TT)
1
2
3
4
NC
8
7
6
5
VCC
NC
VCC
2
1
NC
NC
VSS
3
- Industrial (I):
- Automotive (E):
-40°C to +85°C
-40°C to +125°C
NC
SCIO
VSS
SCIO
Pin Function Table
Name
Function
SCIO
VSS
Serial Clock, Data Input/Output
Ground
VCC
Supply Voltage
* 11XX is used in this document as a generic part number for the 11 series devices.
®
** Microchip’s UNI/O Bus products are covered by the following patent issued in the U.S.A.: 7,376,020.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 1
11AAXXX/11LCXXX
DEVICE SELECTION TABLE
Density
(bits)
Page Size
(Bytes)
Temp.
Ranges
Part Number
Organization VCC Range
Packages
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
P, SN, MS, MN, TT
11LC010
11AA010
11LC020
11AA020
11LC040
11AA040
11LC080
11AA080
11LC160
11AA160
1K
1K
128 x 8
128 x 8
2.5-5.5V
1.8-5.5V
2.5-5.5V
1.8-5.5V
2.5-5.5V
1.8-5.5V
2.5-5.5V
1.8-5.5V
2.5-5.5V
1.8-5.5V
16
16
16
16
16
16
16
16
16
16
I,E
I
2K
256 x 8
I,E
I
2K
256 x 8
4K
512 x 8
I,E
I
4K
512 x 8
8K
1,024 x 8
1,024 x 8
2,048 x 8
2,048 x 8
I,E
I
8K
16K
16K
I,E
I
DS22067E-page 2
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
SCIO w.r.t. VSS.....................................................................................................................................-0.6V to VCC+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
Automotive (E):
Min.
VCC = 2.5V to 5.5V
VCC = 1.8V to 2.5V
VCC = 2.5V to 5.5V
TA = -40°C to +85°C
TA = -20°C to +85°C
TA = -40°C to +125°C
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Max.
VCC+1
Units
Test Conditions
D1
VIH
High-level input
voltage
0.7*VCC
V
D2
D3
D4
D5
D6
D7
D8
VIL
VHYS
VOH
VOL
IO
Low-level input
voltage
-0.3
-0.3
0.3*VCC
0.2*VCC
V
V
VCC ≥ 2.5V
VCC < 2.5V
Hysteresis of Schmitt 0.05*Vcc
Trigger inputs (SCIO)
—
V
VCC ≥ 2.5V (Note 1)
High-level output
voltage
VCC -0.5
VCC -0.5
—
—
V
V
IOH = -300 μA, VCC = 5.5V
IOH = -200 μA, Vcc = 2.5V
Low-level output
voltage
—
—
0.4
0.4
V
V
IOI = 300 μA, VCC = 5.5V
IOI = 200 μA, Vcc = 2.5V
Output current limit
(Note 2)
—
—
±4
±3
mA
mA
VCC = 5.5V (Note 1)
Vcc = 2.5V (Note 1)
ILI
Input leakage current
(SCIO)
—
±1
μA
VIN = VSS or VCC
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TA = 25°C, FCLK = 1 MHz,
VCC = 5.0V (Note 1)
D9
ICC Read Read Operating
Current
—
—
3
1
mA
mA
VCC=5.5V; FBUS=100 kHz, CB=100 pF
VCC=2.5V; FBUS=100 kHz, CB=100 pF
D10 ICC Write Write Operating
Current
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
D11
Iccs
Standby Current
—
5
μA
VCC = 5.5V
TA = 125°C
—
—
1
μA
μA
VCC = 5.5V
TA = 85°C
D12
ICCI
Idle Mode Current
50
VCC = 5.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: The SCIO output driver impedance will vary to ensure IO is not exceeded.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 3
11AAXXX/11LCXXX
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = 2.5V to 5.5V
VCC = 1.8V to 2.5V
VCC = 2.5V to 5.5V
TA = -40°C to +85°C
TA = -20°C to +85°C
TA = -40°C to +125°C
AC CHARACTERISTICS
Automotive (E):
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1
2
3
4
FBUS Serial bus frequency
10
10
—
—
100
100
kHz
µs
—
TE
Bit period
—
TIJIT Input edge jitter tolerance
±0.08
±0.75
UI
(Note 3)
FDRIFT Serial bus frequency drift
rate tolerance
% per byte —
5
FDEV Serial bus frequency drift
limit
—
±5
% per
command
—
6
7
TOJIT Output edge jitter
—
—
±0.25
100
UI
ns
(Note 3)
TR
SCIO input rise time
—
(Note 1)
8
TF
SCIO input fall time
—
100
ns
—
(Note 1)
9
TSTBY Standby pulse time
600
10
5
—
—
—
µs
µs
µs
—
—
—
10
11
TSS Start header setup time
THDR Start header low pulse
time
12
13
14
TSP Input filter spike
suppression (SCIO)
—
50
ns
(Note 1)
TWC Write cycle time
(byte or page)
—
—
5
10
ms
ms
Write, WRSR commands
ERAL, SETAL commands
—
Endurance (per page)
1M
—
cycles
25°C, VCC = 5.5V (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site:
www.microchip.com.
3: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
CL = 100 pF
Timing Measurement Reference Level
Input
0.5 VCC
0.5 VCC
Output
DS22067E-page 4
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
FIGURE 1-1:
BUS TIMING – START HEADER
10
11
2
SCIO
Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit
FIGURE 1-2:
BUS TIMING – DATA
2
7
8
12
SCIO
Data ‘0’
Data ‘1’
Data ‘1’
Data ‘0’
FIGURE 1-3:
BUS TIMING – STANDBY PULSE
9
SCIO
Standby
Mode
FIGURE 1-4:
BUS TIMING – JITTER
2
2
3
3
6
6
6
6
Ideal Edge
from Master
Ideal Edge
from Master
Ideal Edge
from Slave
Ideal Edge
from Slave
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 5
11AAXXX/11LCXXX
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
The 11XX family of serial EEPROMs support the
UNI/O® protocol. They can be interfaced with
microcontrollers, including Microchip’s PIC® microcon-
trollers, ASICs, or any other device with an available
discrete I/O line that can be configured properly to
match the UNI/O protocol.
The 11XX devices contain an 8-bit instruction register.
The devices are accessed via the SCIO pin.
Table 4-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb
last.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a
master device which determines the clock period, con-
trols the bus access and initiates all operations, while
the 11XX works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is active.
FIGURE 2-1:
BLOCK DIAGRAM
STATUS
Register
HV Generator
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
Dec
Page Latches
Y Decoder
Current-
Limited
Slope
Control
SCIO
Sense Amp.
R/W Control
Vcc
Vss
DS22067E-page 6
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
If a command is terminated in any manner other than a
NoMAK/SAK combination, then the master must per-
form a standby pulse before beginning a new com-
mand, regardless of which device is to be selected.
3.0
3.1
BUS CHARACTERISTICS
Standby Pulse
When the master has control of SCIO, a standby pulse
can be generated by holding SCIO high for TSTBY. At
this time, the 11XX will reset and return to Standby
mode. Subsequently, a high-to-low transition on SCIO
(the first low pulse of the header) will return the device
to the active state.
Note: After a POR/BOR event occurs, a low-
to-high transition on SCIO must be gen-
erated before proceeding with communi-
cation, including a standby pulse.
An example of two consecutive commands is shown in
Figure 3-1. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the previ-
ous command. However, a period of TSS must be
observed after the end of the command and before the
beginning of the start header. After TSS, the start
header (including THDR low pulse) can be transmitted
in order to begin the new command.
A standby pulse cannot be generated while the slave
has control of SCIO. In this situation, the master must
wait for the slave to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command, an error is detected
by the master, a standby pulse should be generated
and the command should be performed again.
FIGURE 3-1:
CONSECUTIVE COMMANDS EXAMPLE
Standby Pulse(1)
Device Address
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Device Address
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
3.2
Start Data Transfer
All operations must be preceded by a start header. The
start header consists of holding SCIO low for a period
of THDR, followed by transmitting an 8-bit ‘01010101’
code. This code is used to synchronize the slave’s
internal clock period with the master’s clock period, so
accurate timing is very important.
TSS must be observed after the end of the command
and before the beginning of the start header.
Figure 3-2 shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
FIGURE 3-2:
START HEADER
SCIO
TSS
THDR Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’
MAK
NoSAK
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 7
11AAXXX/11LCXXX
FIGURE 3-4:
MAK (‘1’)
ACKNOWLEDGE BITS
3.3
Acknowledge
SAK (‘1’)
An Acknowledge routine occurs after each byte is
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
master, and the second bit is transmitted by the slave.
Note: A MAK must always be transmitted
NoMAK (‘0’)
NoSAK(1)
following the start header.
The Master Acknowledge, or MAK, is signified by trans-
mitting a ‘1’, and informs the slave that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a
‘0’, and is used to end the current operation (and initiate
the write cycle for write operations).
Note 1: A NoSAK is defined as any sequence that is not a
valid SAK.
3.4
Device Addressing
Note: When a NoMAK is used to end a WRITE
or WRSR instruction, the write cycle is
not initiated if no bytes of data have
been received.
A device address byte is the first byte received from the
master device following the start header. The device
address byte consists of a four-bit family code, for the
11XX this is set as ‘1010’. The last four bits of the
device address byte are the device code, which is
hardwired to ‘0000’.
The slave Acknowledge, or SAK, is also signified by
transmitting a ‘1’, and confirms proper communication.
However, unlike the NoMAK, the NoSAK is signified by
the lack of a middle edge during the bit period.
FIGURE 3-5:
DEVICE ADDRESS BYTE
ALLOCATION
Note: In order to guard against bus contention,
a NoSAK will occur after the start
header.
MAKSAK
SLAVE ADDRESS
A NoSAK will occur for the following events:
• Following the start header
• Following the device address, if no slave on the
bus matches the transmitted address
0
0
0
0
1
0
1
0
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL, and ERAL during a write cycle.
3.5
Bus Conflict Protection
• If the slave becomes out of sync with the master
To help guard against high current conditions arising
from bus conflicts, the 11XX features a current-limited
output driver. The IOL and IOH specifications describe
the maximum current that can be sunk or sourced,
respectively, by the SCIO pin. The 11XX will vary the
output driver impedance to ensure that the maximum
current level is not exceeded.
• If a command is terminated prematurely by using
a NoMAK, with the exception of immediately after
the device address.
See Figure 3.3 and Figure 3-4 for details.
If a NoSAK is received from the slave after any byte
(except the start header), an error has occurred. The
master should then perform a standby pulse and begin
the desired command again.
FIGURE 3-3:
Master
ACKNOWLEDGE
ROUTINE
Slave
SAK
MAK
DS22067E-page 8
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
3.8.1
FREQUENCY DRIFT
3.6
Device Standby
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some toler-
ance for such frequency drift. The tolerance range is
specified by two parameters, FDRIFT and FDEV. FDRIFT
specifies the maximum tolerable change in bus fre-
quency per byte. FDEV specifies the overall limit in fre-
quency deviation within an operation (i.e., from the end
of the start header until communication is terminated
for that operation). The start header at the beginning of
the next operation will reset the re-synchronization cir-
cuitry and allow for another FDEV amount of frequency
drift.
The 11XX features a low-power Standby mode during
which the device is waiting to begin a new command.
A high-to-low transition on SCIO will exit low-power
mode and prepare the device for receiving the start
header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK (i.e., valid termina-
tion of a command)
• Reception of a standby pulse
Note: In the case of the WRITE, WRSR, SETAL, or
ERALcommands, the write cycle is initiated
upon receipt of the NoMAK, assuming all
other write requirements have been met.
3.8.2
EDGE JITTER
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization cir-
cuitry is designed to provide some tolerance for edge
jitter.
3.7
Device Idle
The 11XX features an Idle mode during which all serial
data is ignored until a standby pulse occurs. Idle mode
will be entered upon the following conditions:
The 11XX adjusts its phase every MAK bit, so TIJIT
specifies the maximum allowable peak-to-peak jitter
relative to the previous MAK bit. Since the position of
the previous MAK bit would be difficult to measure by
the master, the minimum and maximum jitter values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle.
• Missed edge transition
• Reception of a MAK following a WREN, WRDI,
SETAL, or ERALcommand byte
• Reception of a MAK following the data byte of a
The difference between the minimum and maximum
values, as a percentage of the bit period, should be cal-
culated and then compared against TIJIT to determine
jitter compliance.
WRSRcommand
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, an edge transition will be missed, thus causing
the device to enter Idle mode.
Note: Because the 11XX only re-synchronizes
during the MAK bit, the overall ability to
remain synchronized depends on a combi-
nation of frequency drift and edge jitter (i.e.,
if the MAK bit edge is experiencing the max-
imum allowable edge jitter, then there is no
room for frequency drift). Conversely, if the
frequency has drifted to the maximum
amount tolerable within a byte, then no edge
jitter can be present.
3.8
Synchronization
At the beginning of every command, the 11XX utilizes
the start header to determine the master’s bus clock
period. This period is then used as a reference for all
subsequent communication within that command.
The 11XX features re-synchronization circuitry which
will monitor the position of the middle data edge during
each MAK bit and subsequently adjust the internal time
reference in order to remain synchronized with the
master.
There are two variables which can cause the 11XX to
lose synchronization. The first is frequency drift,
defined as a change in the bit period, TE. The second is
edge jitter, which is a single occurrence change in the
position of an edge within a bit period, while the bit
period itself remains constant.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 9
11AAXXX/11LCXXX
4.0
DEVICE COMMANDS
After the device address byte, a command byte must
be sent by the master to indicate the type of operation
to be performed. The code for each instruction is listed
in Table 4-1.
TABLE 4-1:
INSTRUCTION SET
Instruction Name Instruction Code Hex Code
Description
READ
CRRD
WRITE
WREN
WRDI
RDSR
WRSR
ERAL
SETAL
0000 0011
0000 0110
0110 1100
1001 0110
1001 0001
0000 0101
0110 1110
0110 1101
0110 0111
0x03
0x06
0x6C
0x96
0x91
0x05
0x6E
0x6D
0x67
Read data from memory array beginning at specified address
Read data from current location in memory array
Write data to memory array beginning at specified address
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read STATUS register
Write STATUS register
Write ‘0x00’ to entire array
Write ‘0xFF’ to entire array
that the slave should output the next data byte. This
continues until the master sends a NoMAK, which ends
the operation.
4.1
Read Instruction
The Read command allows the master to access any
memory location in a random manner. After the READ
instruction has been sent to the slave, the two bytes of
the Word Address are transmitted, with an Acknowl-
edge sequence being performed after each byte. Then,
the slave sends the first data byte to the master. If more
data is to be read, the master sends a MAK, indicating
To provide sequential reads in this manner, the 11XX
contains an internal Address Pointer which is incre-
mented by one after the transmission of each byte. This
Address Pointer allows the entire memory contents to
be serially read during one operation. When the highest
address is reached, the Address Pointer rolls over to
address ‘0x000’ if the master chooses to continue the
operation by providing a MAK.
FIGURE 4-1:
READ COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Word Address LSB
Command
Word Address MSB
7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8
SCIO
SCIO
0 0 0 0 0 0 1 1
Data Byte n
Data Byte 2
Data Byte 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
DS22067E-page 10
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
TABLE 4-2:
INTERNAL ADDRESS
COUNTER
4.2
Current Address Read (CRRD)
Instruction
Command
Event
Action
The internal address counter featured on the 11XX
maintains the address of the last memory array loca-
tion accessed. The CRRDinstruction allows the mas-
ter to read data back beginning from this current
location. Consequently, no word address is provided
upon issuing this command.
—
Power-on Reset Counter is undefined
READor
WRITE
MAK edge fol-
lowing each
Address byte
Counter is updated
with newly received
value
READ,
MAK/NoMAK
Counter is incre-
mented by 1
Note that, except for the initial word address, the
READ and CRRD instructions are identical, including
the ability to continue requesting data through the use
of MAKs in order to sequentially read from the array.
WRITE, or edge following
CRRD each data byte
Note: If, following each data byte in a READ,
WRITE, or CRRD instruction, neither a
MAK nor a NoMAK edge is received
(i.e., if a standby pulse occurs instead),
the internal address counter will not be
incremented.
As with the READinstruction, the CRRDinstruction is
terminated by transmitting a NoMAK.
Table 4-2 lists the events upon which the internal
address counter is modified.
Note: During a Write command, once the last
data byte for a page has been loaded,
the internal Address Pointer will rollover
to the beginning of the selected page.
FIGURE 4-2:
CRRD COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Command
Data Byte 1
Data Byte 2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SCIO
SCIO
0 0 0 0 0 1 1 0
Data Byte n
7 6 5 4 3 2 1 0
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 11
11AAXXX/11LCXXX
Upon receipt of each word, the four lower-order
Address Pointer bits are internally incremented by one.
The higher-order bits of the word address remain con-
stant. If the master should transmit data past the end of
the page, the address counter will roll over to the begin-
ning of the page, where further received data will be
written.
4.3
Write Instruction
Prior to any attempt to write data to the 11XX, the write
enable latch must be set by issuing the WREN
instruction (see Section 4.4).
Once the write enable latch is set, the user may pro-
ceed with issuing a WRITE instruction (including the
header and device address bytes) followed by the MSB
and LSB of the Word Address. Once the last Acknowl-
edge sequence has been performed, the master
transmits the data byte to be written.
Note: Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes actu-
ally being written. Physical page bound-
aries start at addresses that are integer
multiples of the page size (16 bytes) and
end at addresses that are integer multi-
ples of the page size minus 1. As an
example, the page that begins at
address 0x30 ends at address 0x3F. If a
page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to
the beginning of the current page (over-
writing data previously stored there),
instead of being written to the next page
as might be expected. It is therefore
necessary for the application software to
prevent page write operations that
would attempt to cross a page bound-
ary.
The 11XX features a 16-byte page buffer, meaning that
up to 16 bytes can be written at one time. To utilize this
feature, the master can transmit up to 16 data bytes to
the 11XX, which are temporarily stored in the page buf-
fer. After each data byte, the master sends a MAK, indi-
cating whether or not another data byte is to follow. A
NoMAK indicates that no more data is to follow, and as
such will initiate the internal write cycle.
Note: If a NoMAK is generated before any data
has been provided, or if a standby pulse
occurs before the NoMAK is generated,
the 11XX will be reset, and the write
cycle will not be initiated.
FIGURE 4-3:
WRITE COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Word Address LSB
Command
Word Address MSB
7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8
SCIO
0 1 1 0 1 1 0 0
Data Byte n
Data Byte 2
Data Byte 1
7 6 5 4 3 2 1 0
SCIO
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Twc
DS22067E-page 12
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
The following is a list of conditions under which the
write enable latch will be reset:
4.4
Write Enable (WREN) and Write
Disable (WRDI) Instructions
• Power-up
The 11XX contains a write enable latch. See Table 6-1
for the Write-Protect Functionality Matrix. This latch
must be set before any write operation will be com-
pleted internally. The WREN instruction will set the
latch, and the WRDIinstruction will reset the latch.
• WRDIinstruction successfully executed
• WRSRinstruction successfully executed
• WRITEinstruction successfully executed
• ERALinstruction successfully executed
• SETALinstruction successfully executed
Note: The WRENand WRDIinstructions must
be terminated with a NoMAK following
the command byte. If a NoMAK is not
received at this point, the command will
be considered invalid, and the device
will go into Idle mode without responding
with a SAK or executing the command.
FIGURE 4-4:
WRITE ENABLE COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Command
SCIO
1 0 0 1 0 1 1 0
FIGURE 4-5:
WRITE DISABLE COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Command
1 0 0 1 0 0 0 1
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 13
11AAXXX/11LCXXX
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user through the WRSR instruction.
These bits are nonvolatile.
4.5
Read Status Register (RDSR)
Instruction
The RDSRinstruction provides access to the STATUS
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
Note: If Read Status Register command is
initiated while the 11XX is currently
executing an internal write cycle on the
STATUS register, the new Block
Protection bit values will be read during
the entire command.
7
6
5
4
3
2
1
0
X
X
X
X
BP1
BP0
WEL
WIP
Note: Bits 4-7 are don’t cares, and will read as ‘0’.
The WIP and WEL bits will update dynamically (asyn-
chronous to issuing the RDSR instruction). Further-
more, after the STATUS register data is received, the
master can provide a MAK during the Acknowledge
sequence to request that the data be transmitted again.
This allows the master to continuously monitor the WIP
and WEL bits without the need to issue another full
command.
The Write-In-Process (WIP) bit indicates whether the
11XX is busy with a write operation. When set to a ‘1’,
a write is in progress, when set to a ‘0’, no write is in
progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘0’, the latch
prohibits writes to the array. This bit is set and cleared
using the WREN and WRDI instructions, respectively.
This bit is read-only for any other instruction.
Once the master is finished, it provides a NoMAK to
end the operation.
Note: The current drawn for a Read Status
Register command during a write cycle
is a combination of the ICC Read and ICC
Write operating currents.
FIGURE 4-6:
READ STATUS REGISTER COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Command
STATUS Register Data
3 2 1 0
SCIO
0 0 0 0 0 1 0 1
0 0 0 0
Note: The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.
DS22067E-page 14
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
After transmitting the STATUS register data, the master
must transmit a NoMAK during the Acknowledge
sequence in order to initiate the internal write cycle.
4.6
Write Status Register (WRSR)
Instruction
The WRSRinstruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the STATUS register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Table 4-3.
Note: The WRSR instruction must be termi-
nated with a NoMAK following the data
byte. If a NoMAK is not received at this
point, the command will be considered
invalid, and the device will go into Idle
mode without responding with a SAK or
executing the command.
TABLE 4-3:
BP1
ARRAY PROTECTION
BP0
Address Ranges Write-Protected
Address Ranges Unprotected
0
0
1
1
0
1
0
1
None
Upper 1/4
Upper 1/2
All
All
Lower 3/4
Lower 1/2
None
TABLE 4-4:
PROTECTED ARRAY ADDRESS LOCATIONS
Density
Upper 1/4
Upper 1/2
All Sectors
1K
2K
4K
8K
60h-7Fh
C0h-FFh
40h-7Fh
80h-FFh
00h-7Fh
00h-FFh
180h-1FFh
300h-3FFh
600h-7FFh
100h-1FFh
200h-3FFh
400h-7FFh
000h-1FFh
000h-3FFh
000h-7FFh
16K
FIGURE 4-7:
WRITE STATUS REGISTER COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Command
Status Register Data
7 6 5 4 3 2 1 0
Twc
0 1 1 0 1 1 1 0
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 15
11AAXXX/11LCXXX
The ERAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or
all of the array is protected.
4.7
Erase All (ERAL) Instruction
The ERALinstruction allows the user to write ‘0x00’ to
the entire memory array with one command. Note that
the write enable latch (WEL) must first be set by issuing
the WRENinstruction.
Note: The ERAL instruction must be termi-
nated with a NoMAK following the com-
mand byte. If a NoMAK is not received at
this point, the command will be consid-
ered invalid, and the device will go into
Idle mode without responding with a
SAK or executing the command.
Once the write enable latch is set, the user may pro-
ceed with issuing a ERAL instruction (including the
header and device address bytes). Immediately after
the NoMAK bit has been transmitted by the master, the
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0x00’.
FIGURE 4-8:
ERASE ALL COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Command
SCIO
0 1 1 0 1 1 0 1
Twc
The SETAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or
all of the array is protected.
4.8
Set All (SETAL) Instruction
The SETALinstruction allows the user to write ‘0xFF’
to the entire memory array with one command. Note
that the write enable latch (WEL) must first be set by
issuing the WRENinstruction.
Note: The SETAL instruction must be termi-
nated with a NoMAK following the com-
mand byte. If a NoMAK is not received at
this point, the command will be consid-
ered invalid, and the device will go into
Idle mode without responding with a
SAK or executing the command.
Once the write enable latch is set, the user may pro-
ceed with issuing a SETAL instruction (including the
header and device address bytes). Immediately after
the NoMAK bit has been transmitted by the master, the
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0xFF’.
FIGURE 4-9:
SET ALL COMMAND SEQUENCE
Device Address
Standby Pulse
Start Header
SCIO
0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 0
Command
SCIO
0 1 1 0 0 1 1 1
Twc
DS22067E-page 16
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
5.0
DATA PROTECTION
6.0
POWER-ON STATE
The following protection has been implemented to
prevent inadvertent writes to the array:
The 11XX powers on in the following state:
• The device is in low-power Shutdown mode,
requiring a low-to-high transition on SCIO to enter
Idle mode
• The Write Enable Latch (WEL) is reset on power-
up
• A Write Enable (WREN) instruction must be issued
to set the write enable latch
• The Write Enable Latch (WEL) is reset
• The internal Address Pointer is undefined
• After a write, ERAL, SETAL, or WRSR command,
the write enable latch is reset
• A low-to-high transition, standby pulse and subse-
quent high-to-low transition on SCIO (the first low
pulse of the header) are required to enter the
active state
• Commands to access the array or write to the
status register are ignored during an internal write
cycle and programming is not affected
.
TABLE 6-1:
WEL
WRITE PROTECT FUNCTIONALITY MATRIX
Protected Blocks
Unprotected Blocks
Status Register
0
1
Protected
Protected
Protected
Writable
Protected
Writable
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 17
11AAXXX/11LCXXX
7.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 7-1.
TABLE 7-1:
Name
PIN FUNCTION TABLE
3-pin SOT-23
8-pin PDIP/SOIC/
MSOP/TDFN
Description
SCIO
VCC
VSS
NC
1
2
5
Serial Clock, Data Input/Output
Supply Voltage
8
4
3
Ground
—
1,2,3,6,7
No Internal Connection
7.1
Serial Clock, Data Input/Output
(SCIO)
SCIO is a bidirectional pin used to transfer commands
and addresses into, as well as data into and out of, the
device. The serial clock is embedded into the data
stream through Manchester encoding. Each bit is rep-
resented by a signal transition at the middle of the bit
period.
DS22067E-page 18
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP
Example:
11AA160
XXXXXXXX
T/XXXNNN
e
3
I/P
1L7
0828
YYWW
8-Lead PDIP Package Marking (Pb-Free)
Device
Line 1 Marking
Device
Line 1 Marking
11AA010
11AA020
11AA040
11AA080
11AA160
11AA010
11AA020
11AA040
11AA080
11AA160
11LC010
11LC020
11LC040
11LC080
11LC160
11LC010
11LC020
11LC040
11LC080
11LC160
Note:
T = Temperature Grade (I, E)
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 19
11AAXXX/11LCXXX
Example:
11AA160I
8-Lead SOIC
XXXXXXXT
e
3
SN
0828
XXXXYYWW
1L7
NNN
8-Lead SOIC Package Marking (Pb-Free)
Device
Line 1 Marking
Device
Line 1 Marking
11AA010
11AA020
11AA040
11AA080
11AA160
11AA010T
11AA020T
11AA040T
11AA080T
11AA160T
11LC010
11LC020
11LC040
11LC080
11LC160
11LC010T
11LC020T
11LC040T
11LC080T
11LC160T
Note:
T = Temperature Grade (I, E)
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS22067E-page 20
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
8-Lead MSOP (150 mil)
Example:
11A01I
XXXXXXT
YWWNNN
8281L7
8-Lead MSOP Package Marking (Pb-Free)
Device
Line 1 Marking
Device
Line 1 Marking
11AA010
11AA020
11AA040
11AA080
11AA160
11A01T
11A02T
11A04T
11A08T
11AAT
11LC010
11LC020
11LC040
11LC080
11LC160
11L01T
11L02T
11L04T
11L08T
11LAT
Note:
T = Temperature Grade (I, E)
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 21
11AAXXX/11LCXXX
8-Lead 2x3 TDFN
Example:
XXX
YWW
NN
D51
828
17
8-Lead 2x3 TDFN Package Marking (Pb-Free)
Device
I-Temp Marking
Device
I-Temp Marking
E-Temp Marking
11AA010
11AA020
11AA040
11AA080
11AA160
D11
D21
D31
D41
D51
11LC010
11LC020
11LC040
11LC080
11LC160
D14
D24
D34
D44
D54
D15
D25
D35
D45
D55
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
YY
WW
NN
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS22067E-page 22
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
3-Lead SOT-23
Example:
XXNN
B517
3-Lead SOT-23 Package Marking (Pb-Free)
Device
I-Temp Marking
Device
I-Temp Marking
E-Temp Marking
11AA010
11AA020
11AA040
11AA080
11AA160
B1NN
B2NN
B3NN
B4NN
B5NN
11LC010
11LC020
11LC040
11LC080
11LC160
M1NN
M2NN
M3NN
M4NN
M5NN
N1NN
N2NN
N3NN
N4NN
N5NN
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 23
11AAXXX/11LCXXX
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ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
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M
ꢁꢎꢀꢕ
ꢁꢀꢛꢘ
M
ꢁꢀꢀꢘ
ꢁꢕꢀꢘ
ꢁꢎꢛꢕ
ꢁꢎꢖꢕ
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ꢁꢀꢀꢘ
ꢁꢕꢕ<
ꢁꢕꢖꢕ
ꢁꢕꢀꢖ
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ꢁ-ꢎꢘ
ꢁꢎ<ꢕ
ꢁꢖꢕꢕ
ꢁꢀꢘꢕ
ꢁꢕꢀꢘ
ꢁꢕꢜꢕ
ꢁꢕꢎꢎ
ꢁꢖ-ꢕ
ꢙꢃꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
6ꢓꢓꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
9ꢋ*ꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅꢝꢋ*ꢅꢐꢓꢆꢌꢃꢄꢑꢅꢅꢏ
ꢛꢗꢊꢃꢉꢜ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢁꢕꢀꢕ/ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2ꢅ1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢀ<1
DS22067E-page 24
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
c
φ
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A
L
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L1
β
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
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ꢂꢃ&ꢌꢍ
7
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ꢀꢁꢎꢜꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅꢅꢏ
ꢗ
M
ꢀꢁꢎꢘ
ꢕꢁꢀꢕ
M
M
M
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.
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
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: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
,ꢍꢆ'%ꢈꢉꢅ@ꢋꢓ&ꢃꢋꢄꢆꢇA
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M
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9
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3ꢋꢋ&ꢅꢗꢄꢑꢇꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅ1ꢋ&&ꢋ'
9ꢀ
ꢀ
ꢀꢁꢕꢖꢅꢝ.3
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ꢕꢁꢀꢜ
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ꢘꢟ
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ꢁ
ꢕꢁꢎꢘ
ꢕꢁꢘꢀ
ꢀꢘꢟ
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ꢘꢟ
ꢀꢘꢟ
ꢛꢗꢊꢃꢉꢜ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢜ1
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 25
11AAXXX/11LCXXX
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS22067E-page 26
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ(ꢋꢌ"ꢗꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌ)ꢄ*ꢃꢆꢑ( ꢒꢆꢙ( !ꢇꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
N
E
E1
NOTE 1
2
b
1
e
c
φ
A2
A
L
L1
A1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
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ꢕꢁ?ꢘꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅ
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
ꢗ
M
ꢕꢁꢜꢘ
ꢕꢁꢕꢕ
M
ꢕꢁ<ꢘ
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ꢗꢀ
.
.ꢀ
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M
ꢖꢁꢛꢕꢅ1ꢐ,
-ꢁꢕꢕꢅ1ꢐ,
-ꢁꢕꢕꢅ1ꢐ,
ꢕꢁ?ꢕ
9
ꢕꢁꢖꢕ
ꢕꢁ<ꢕ
3ꢋꢋ&ꢓꢉꢃꢄ&
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈ
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ꢀ
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ꢕꢟ
<ꢟ
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9ꢈꢆ#ꢅ>ꢃ#&ꢍ
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)
ꢕꢁꢕ<
ꢕꢁꢎꢎ
M
M
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ꢕꢁꢖꢕ
ꢛꢗꢊꢃꢉꢜ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢀꢀ1
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 27
11AAXXX/11LCXXX
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ+ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ)ꢄ*ꢃꢆꢑ(ꢛꢒꢆMꢆ,-ꢓ-ꢔ%./ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ0ꢍ+ꢛꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS22067E-page 28
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ+ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ)ꢄ*ꢃꢆꢑ(ꢛꢒꢆMꢆ,-ꢓ-ꢔ%./ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ0ꢍ+ꢛꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 29
11AAXXX/11LCXXX
ꢓꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆ0"ꢄꢐꢉꢋꢉꢊꢗ"ꢆꢑ00ꢒꢆꢙ !0ꢁ,ꢓꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
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ꢎꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕꢖ1
DS22067E-page 30
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
APPENDIX A: REVISION HISTORY
Revision A (10/07)
Original release of this document.
Revision B (01/08)
Revised SOT-23 Package Type; Revised DFN
package to TDFN; Section 3.3 (added new bullet item);
Section 4.5 note; Table 7-1.
Revision C (03/08)
Removed patent pending notice; Revised Tables 1-1
and 1-2; Section 3.3 (bullet 3) and 3.7 (bullet 2);
Product ID System.
Revision D (04/08)
Revised document status to Preliminary; General
updates.
Revision E (09/08)
Updated UNI/O trademark; Revised Table 1-2,
parameters 3 and 5; Updated package drawings.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 31
11AAXXX/11LCXXX
NOTES:
DS22067E-page 32
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 33
11AAXXX/11LCXXX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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Reader Response
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RE:
From:
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Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
11AAXXX/11LCXXX
DS22067E
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22067E-page 34
Preliminary
© 2008 Microchip Technology Inc.
11AAXXX/11LCXXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
X
/XXX
Examples:
Tape & Reel Temperature Package
Range
a)
b)
11AA010-I/P = 1 Kbit, 1.8V Serial EEPROM,
Industrial temp., PDIP package
11LC160T-E/TT = 16 Kbit, 2.5V Serial
EEPROM, Extended temp., Tape & Reel,
SOT-23 package
Device:
11AA010 = 1 Kbit, 1.8V UNI/O Serial EEPROM
11LC010 = 1 Kbit, 2.5V UNI/O Serial EEPROM
11AA020 = 2 Kbit, 1.8V UNI/O Serial EEPROM
11LC020 = 2 Kbit, 2.5V UNI/O Serial EEPROM
11AA040 = 4 Kbit, 1.8V UNI/O Serial EEPROM
11LC040 = 4 Kbit, 2.5V UNI/O Serial EEPROM
11AA080 = 8 Kbit, 1.8V UNI/O Serial EEPROM
11LC080 = 8 Kbit, 2.5V UNI/O Serial EEPROM
11AA160 = 16 Kbit, 1.8V UNI/O Serial EEPROM
11LC160 = 16 Kbit, 2.5V UNI/O Serial EEPROM
c)
11AA080-I/MS = 8 Kbit, 1.8V Serial EEPROM,
Industrial temp., MSOP package
d)
e)
11LC020T-I/SN = 2 Kbit, 2.5V Serial EEPROM,
Industrial temp., Tape & Reel, SOIC package
11AA040T-I/MNY
=
4
Kbit, 1.8V Serial
EEPROM, Industrial temp., Tape and Reel,
2x3 mm TDFN package, Nickel Palladium Gold
finish
Tape & Reel:
T
=
=
Tape and Reel
Tube
Blank
Temperature
Range:
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package:
P
=
=
=
=
=
8-lead Plastic DIP (300 mil body)
8-lead Plastic SOIC (3.90 mm body)
8-lead Plastic Micro Small Outline (MSOP)
8-lead 2x3 mm TDFN
SN
MS
MNY(1)
TT
3-lead SOT 23 (Tape and Reel only)
Note 1:
“Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 35
11AAXXX/11LCXXX
NOTES:
DS22067E-page 36
Preliminary
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
32
PICDEM.net, PICtail, PIC logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
Preliminary
DS22067E-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
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Tel: 60-4-227-8870
Fax: 60-4-227-4068
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Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
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Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS22067E-page 38
Preliminary
© 2008 Microchip Technology Inc.
11LC010-E/SN 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
11LC010-E/TO | MICROCHIP | 128 X 8 1-WIRE SERIAL EEPROM, PBCY3, ROHS COMPLIANT, PLASTIC, TO-92, 3 PIN | 获取价格 | |
11LC010-E/TT | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-ECS16K | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-EMNY | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-EMS | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-EP | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-ESN | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-ETO | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-ETT | MICROCHIP | 1K-16K UNI/O® Serial EEPROM Family Data Sheet | 获取价格 | |
11LC010-I/MN | MICROCHIP | 128 X 8 1-WIRE SERIAL EEPROM, PDSO8, 2 X 3 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TDFN-8 | 获取价格 |
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