23LCV1024-IST [MICROCHIP]

1 Mbit SPI Serial SRAM with Battery Backup and SDI Interface; 1兆位的SPI串行SRAM ,带有备用电池和SDI接口
23LCV1024-IST
型号: 23LCV1024-IST
厂家: MICROCHIP    MICROCHIP
描述:

1 Mbit SPI Serial SRAM with Battery Backup and SDI Interface
1兆位的SPI串行SRAM ,带有备用电池和SDI接口

电池 静态存储器
文件: 总30页 (文件大小:700K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
23LCV1024  
1 Mbit SPI Serial SRAM with Battery Backup and SDI Interface  
Device Selection Table  
Part  
Number  
Dual I/O  
(SDI)  
Battery  
Backup  
Max. Clock  
Frequency  
VCC Range  
Packages  
SN, ST, P  
23LCV1024  
2.5-5.5V  
Yes  
Yes  
20 MHz  
Features:  
Description:  
• SPI-Compatible Bus Interface:  
- 20 MHz Clock rate  
The Microchip Technology Inc. 23LCV1024 is a 1 Mbit  
Serial SRAM device. The memory is accessed via a  
simple Serial Peripheral Interface (SPI) compatible  
serial bus. The bus signals required are a clock input  
(SCK) plus separate data in (SI) and data out (SO)  
lines. Access to the device is controlled through a Chip  
Select (CS) input. Additionally, SDI (Serial Dual Inter-  
face) is supported if your application needs faster data  
rates.  
- SPI/SDI mode  
• Low-Power CMOS Technology:  
- Read Current: 3 mA at 5.5V, 20 MHz  
- Standby Current: 4 A at +85°C  
• Unlimited Read and Write Cycles  
• External Battery Backup Support  
• Zero Write Time  
This device also supports unlimited reads and writes to  
the memory array, and supports data backup via an  
external battery/coin cell connected to VBAT (pin 7).  
• 128K x 8-bit Organization:  
- 32-byte page  
The 23LCV1024 is available in standard packages  
including 8-lead SOIC, PDIP and advanced 8-lead  
TSSOP.  
• Byte, Page and Sequential mode for Reads and  
Writes  
• High Reliability  
Temperature Range Supported:  
Package Types (not to scale)  
- Industrial (I):  
-40C to +85C  
• Pb-Free and RoHS Compliant, Halogen Free  
• 8-Lead SOIC, TSSOP and PDIP Packages  
Pin Function Table  
SOIC/TSSOP/PDIP  
Name  
Function  
CS  
1
8
Vcc  
CS  
Chip Select Input  
SO/SIO1  
NC  
2
3
4
7
6
5
VBAT  
SO/SIO1  
Vss  
Serial Output/SDI Pin  
Ground  
SCK  
Vss  
SI/SIO0  
SI/SIO0  
SCK  
Serial Input/SDI Pin  
Serial Clock  
VBAT  
External Backup Supply Input  
Power Supply  
Vcc  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 1  
23LCV1024  
1.0  
ELECTRICAL CHARACTERISTICS  
(†)  
Absolute Maximum Ratings  
VCC.............................................................................................................................................................................6.5V  
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V  
Storage temperature ...............................................................................................................................-65°C to +150°C  
Ambient temperature under bias...............................................................................................................-40°C to +85°C  
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at those or any other conditions above those  
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an  
extended period of time may affect device reliability.  
TABLE 1-1:  
DC CHARACTERISTICS  
Industrial (I):  
TA = -40°C to +85°C  
DC CHARACTERISTICS  
Param.  
No.  
Sym.  
Characteristic  
Min.  
Typ.(1)  
Max.  
Units  
Test Conditions  
23LCV1024  
D001  
D002  
VCC  
Supply voltage  
2.5  
5.5  
V
V
VIH  
VIL  
VOL  
VOH  
ILI  
High-level input  
voltage  
.7 VCC  
VCC +0.3  
D003  
D004  
D005  
D006  
D007  
Low-level input  
voltage  
-0.3  
0.10xVCC  
V
V
23LCV1024  
Low-level output  
voltage  
0.2  
IOL = 1 mA  
High-level output  
voltage  
VCC -0.5  
V
IOH = -400 A  
Input leakage  
current  
±1  
±1  
A  
A  
CS = VCC, VIN = VSS OR VCC  
CS = VCC, VOUT = VSS OR VCC  
ILO  
Output leakage  
current  
D008  
D009  
ICC Read Operating current  
3
4
10  
10  
mA FCLK = 20 MHz; SO = O, 5.5V  
ICCS  
Standby current  
A CS = VCC = 5.5V, Inputs tied to  
VCC or VSS  
D010  
D011  
D012  
CINT  
VDR  
Input capacitance  
7
pF VCC = 0V, f = 1 MHz, Ta = 25°C  
(Note 1)  
RAM data retention  
voltage  
1.0  
1.8  
V
V
V
(Note 2)  
VTRIP  
VBAT Change Over  
1.6  
2.0  
Typical at Ta = 25°C  
(Note 1)  
D013  
D014  
VBAT  
IBAT  
VBAT Voltage Range  
VBAT Current  
1.4  
1
3.6  
(Note 1)  
A Typical at 2.5V, Ta = 25°C  
(Note 1)  
Note 1: This parameter is periodically sampled and not 100% tested. Typical measurements taken at room  
temperature (25°C).  
2: This is the limit to which VDD can be lowered without losing RAM data. This parameter is periodically  
sampled and not 100% tested.  
DS25156A-page 2  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
TABLE 1-2:  
AC CHARACTERISTICS  
AC CHARACTERISTICS  
Param.  
Industrial (I):  
TA = -40°C to +85°C  
Sym.  
Characteristic  
Min.  
Max.  
Units  
Test Conditions  
No.  
1
2
3
4
5
6
7
8
9
FCLK Clock frequency  
TCSS CS setup time  
TCSH CS hold time  
TCSD CS disable time  
25  
50  
25  
10  
10  
25  
25  
25  
0
20  
20  
20  
25  
20  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Tsu  
THD  
TR  
Data setup time  
Data hold time  
CLK rise time  
CLK fall time  
Note 1  
Note 1  
TF  
THI  
TLO  
Clock high time  
Clock low time  
10  
11  
12  
13  
14  
TCLD Clock delay time  
TV  
Output valid from clock low  
THO  
TDIS  
Output hold time  
Note 1  
Output disable time  
Note 1: This parameter is periodically sampled and not 100% tested.  
TABLE 1-3:  
AC TEST CONDITIONS  
AC Waveform:  
Input pulse level  
Input rise/fall time  
0.1 VCC to 0.9 VCC  
5 ns  
-40°C to +85°C  
Operating temperature  
CL = 30 pF  
Timing Measurement Reference Level:  
Input  
0.5 VCC  
0.5 VCC  
Output  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 3  
23LCV1024  
FIGURE 1-1: SERIAL INPUT TIMING (SPI MODE)  
4
CS  
2
11  
7
3
8
SCK  
5
6
SI  
MSB in  
LSB in  
High-Impedance  
SO  
FIGURE 1-2: SERIAL OUTPUT TIMING (SPI MODE)  
CS  
3
9
10  
SCK  
12  
14  
13  
MSB out  
LSB out  
SO  
SI  
Don’t Care  
DS25156A-page 4  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
If operating in Sequential mode, the data stored in the  
memory at the next address can be read sequentially  
by continuing to provide clock pulses. The internal  
Address Pointer is automatically incremented to the  
next higher address after each byte of data is shifted  
out. When the highest address is reached (1FFFFh),  
the address counter rolls over to address 00000h,  
allowing the read cycle to be continued indefinitely.  
The read operation is terminated by raising the CS  
pin.  
2.0  
2.1  
FUNCTIONAL DESCRIPTION  
Principles of Operation  
The 23LCV1024 is an 1 Mbit Serial SRAM designed to  
interface directly with the Serial Peripheral Interface  
(SPI) port of many of today’s popular microcontroller  
families, including Microchip’s PIC® microcontrollers. It  
may also interface with microcontrollers that do not  
have a built-in SPI port by using discrete I/O lines  
programmed properly in firmware to match the SPI  
protocol. In addition, the 23LCV1024 is also capable of  
operating in SDI (or dual SPI) mode.  
2.4  
Write Sequence  
Prior to any attempt to write data to the 23LCV1024, the  
device must be selected by bringing CS low.  
The 23LCV1024 contains an 8-bit instruction register.  
The device is accessed via the SI pin, with data being  
clocked in on the rising edge of SCK. The CS pin must  
be low for the entire operation.  
Once the device is selected, the Write command can  
be started by issuing a WRITE instruction, followed by  
the 24-bit address, with the first seven MSB’s of the  
address being a “don’t care” bit, and then the data to be  
written. A write is terminated by the CS being brought  
high.  
Table 2-1 contains a list of the possible instruction  
bytes and format for device operation. All instructions,  
addresses and data are transferred MSB first, LSB last.  
If operating in Page mode, after the initial data byte is  
shifted in, additional bytes can be shifted into the  
device. The Address Pointer is automatically  
incremented. This operation can continue for the entire  
page (32 bytes) before data will start to be overwritten.  
2.2  
Modes of Operation  
The 23LCV1024 has three modes of operation that are  
selected by setting bits 7 and 6 in the MODE register.  
The modes of operation are Byte, Page and Burst.  
If operating in Sequential mode, after the initial data  
byte is shifted in, additional bytes can be clocked into  
the device. The internal Address Pointer is automati-  
cally incremented. When the Address Pointer reaches  
the highest address (1FFFFh), the address counter  
rolls over to (00000h). This allows the operation to  
continue indefinitely, however, previous data will be  
overwritten.  
Byte Operation – is selected when bits 7 and 6 in the  
MODE register are set to 00. In this mode, the read/  
write operations are limited to only one byte. The  
command followed by the 24-bit address is clocked into  
the device and the data to/from the device is transferred  
on the next eight clocks (Figure 2-1, Figure 2-2).  
Page Operation – is selected when bits 7 and 6 in the  
MODE register are set to 10. The 23LCV1024 has 4096  
pages of 32 bytes. In this mode, the read and write oper-  
ations are limited to within the addressed page (the  
address is automatically incremented internally). If the  
data being read or written reaches the page boundary,  
then the internal address counter will increment to the  
start of the page (Figure 2-3, Figure 2-4).  
Sequential Operation – is selected when bits 7 and 6  
in the MODE register are set to 01. Sequential opera-  
tion allows the entire array to be written to and read  
from. The internal address counter is automatically  
incremented and page boundaries are ignored. When  
the internal address counter reaches the end of the  
array, the address counter will roll over to 0x00000  
(Figure 2-5, Figure 2-6).  
2.3  
Read Sequence  
The device is selected by pulling CS low. The 8-bit  
READ instruction is transmitted to the 23LCV1024  
followed by the 24-bit address, with the first seven  
MSB’s of the address being a “don’t care” bit. After the  
correct READinstruction and address are sent, the data  
stored in the memory at the selected address is shifted  
out on the SO pin.  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 5  
23LCV1024  
TABLE 2-1:  
INSTRUCTION SET  
Hex  
Code  
Instruction Name Instruction Format  
Description  
READ  
WRITE  
EDIO  
RSTIO  
RDMR  
WRMR  
0000 0011  
0000 0010  
0011 1011  
1111 1111  
0000 0101  
0000 0001  
0x03  
0x02  
0x3B  
0xFF  
0x05  
0x01  
Read data from memory array beginning at selected address  
Write data to memory array beginning at selected address  
Enter Dual I/O access  
Reset Dual I/O access  
Read Mode Register  
Write Mode Register  
FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE)  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
SI  
Instruction  
24-bit Address  
0 0 0 0 0 0 1 1 23 22 21 20  
2
1
0
Data Out  
High-Impedance  
7
6
5
4
3
2
1
0
SO  
FIGURE 2-2: BYTE WRITE SEQUENCE (SPI MODE)  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
SI  
Instruction  
24-bit Address Data Byte  
0 0 0 0 0 0 1 0 23 22 21 20  
2
1
0
7
6
5
4
3
2
1
0
High-Impedance  
SO  
DS25156A-page 6  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE)  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
SI  
Instruction  
0 0 0 0 0 0 1 1 23 22 21 20  
Page X, Word Y  
24-bit Address  
2
1
0
Page X, Word Y  
High-Impedance  
SO  
7
6
5
4
3
2
1
0
CS  
40 41 42 43 44 45 46 47  
SCK  
SI  
Page X, Word Y+1  
Page X, Word 31  
Page X, Word 0  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO  
FIGURE 2-4:  
PAGE WRITE SEQUENCE (SPI MODE)  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
Instruction  
0 0 0 0 0 0 1 0 23 22 21 20  
Page X, Word Y  
24-bit Address  
Page X, Word Y  
2
1
0
7
6
5
4
3
2
1
0
SI  
CS  
SCK  
SI  
40 41 42 43 44 45 46 47  
Page X, Word Y+1  
Page X, Word 31  
Page X, Word 0  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 7  
23LCV1024  
FIGURE 2-5:  
SEQUENTIAL READ SEQUENCE (SPI MODE)  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
Instruction  
24-bit Address  
23 22 21 20  
0 0 0 0 0 0 1 1  
2
1
0
SI  
Page X, Word Y  
7
6
5
4
3
2
1
0
SO  
CS  
SCK  
SI  
Page X, Word 31  
Page X+1, Word 0  
Page X+1, Word 1  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO  
CS  
SCK  
SI  
Page X+1, Word 31  
Page X+n, Word 1  
Page X+n, Word 31  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO  
DS25156A-page 8  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
FIGURE 2-6:  
SEQUENTIAL WRITE SEQUENCE (SPI MODE)  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
Instruction  
24-bit Address  
Data Byte 1  
5
0 0 0 0 0 0 1 0 23 22 21 20  
2
1
0
7
6
4
3
2
1
0
SI  
CS  
40 41 42 43 44 45 46 47  
Data Byte 2  
49 50 51 52 53 54 55  
Data Byte 3  
48  
7
SCK  
SI  
Data Byte n  
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 9  
23LCV1024  
The mode bits indicate the operating mode of the  
SRAM. The possible modes of operation are:  
2.5  
Read Mode Register Instruction  
(RDMR)  
0 0= Byte mode  
The Read Mode Register instruction (RDMR) provides  
access to the MODE register. The MODE register may  
be read at any time. The MODE register is formatted as  
follows:  
1 0= Page mode  
0 1= Sequential mode (default operation)  
1 1= Reserved  
Bits 0 through 5 are reserved and should always be set  
to ‘0’.  
TABLE 2-2:  
MODE REGISTER  
7
6
5
4
3
2
1
0
0
See Figure 2-7 for the RDMRtiming sequence.  
W/R  
W/R  
MODE MODE 0 0 0 0 0  
W/R = writable/readable  
FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR)  
CS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
SCK  
Instruction  
0
0
0
0
0
1
0
1
SI  
Data from MODE Register  
High-Impedance  
7
6
5
4
3
2
1
0
SO  
DS25156A-page 10  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
2.6  
Write Mode Register Instruction  
(WRMR)  
The Write Mode Register instruction (WRMR) allows the  
user to write to the bits in the MODE register as shown  
in Table 2-2. This allows for setting of the Device  
operating mode. Several of the bits in the MODE  
register must be cleared to ‘0’. See Figure 2-8 for the  
WRMRtiming sequence.  
FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR)  
CS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
1
15  
0
SCK  
SI  
Instruction  
Data to MODE Register  
7
6
5
4
3
2
0
0
0
0
0
0
0
1
High-Impedance  
SO  
2.7  
Power-On State  
The 23LCV1024 powers on in the following state:  
• The device is in low-power Standby mode  
(CS= 1)  
• A high-to-low-level transition on CS is required to  
enter active state  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 11  
23LCV1024  
3.6  
VBAT Supply Input  
3.0  
PIN DESCRIPTIONS  
The descriptions of the pins are listed in Table 3-1.  
The VBAT pin is used as an input for external backup  
supply to maintain SRAM data when VCC is below the  
VTRIP point. If the VBAT function is not being used it is  
recommended to connect this pin to VSS.  
TABLE 3-1:  
Name  
PIN FUNCTION TABLE  
SOIC/  
PDIP  
Function  
3.7  
SPI and SDI Pin Designations  
TSSOP  
CS  
1
2
3
4
5
6
7
8
Chip Select Input  
SPI Mode:  
SO/SIO1  
NC  
Serial Data Output/SDI Pin  
No Connect  
CS  
1
8
Vcc  
VSS  
Ground  
SO  
NC  
2
3
4
7
6
5
VBAT  
SCK  
SI  
SI/SIO0  
SCK  
Serial Data Input/SDI Pin  
Serial Clock Input  
External Backup Supply  
Power Supply  
Vss  
VBAT  
VCC  
SDI Mode:  
3.1  
Chip Select (CS)  
CS  
1
8
Vcc  
A low level on this pin selects the device. A high level  
deselects the device and forces it into Standby mode.  
When the device is deselected, SO goes to the high-  
impedance state, allowing multiple parts to share the  
same SPI bus. After power-up, a low level on CS is  
required, prior to any sequence being initiated.  
SIO1  
NC  
2
3
7
6
VBAT  
SCK  
Vss  
4
5
SIO0  
3.2  
Serial Output (SO)  
The SO pin is used to transfer data out of the  
23LCV1024. During a read cycle, data is shifted out on  
this pin after the falling edge of the serial clock.  
3.3  
Serial Input (SI)  
The SI pin is used to transfer data into the device. It  
receives instructions, addresses, and data. Data is  
latched on the rising edge of the serial clock.  
3.4  
Serial Dual Interface Pins(SIO0,  
SIO1)  
The SIO0 and SIO1 pins are used for SDI mode of  
operation. Functionality of these I/O pins is shared with  
SO and SI.  
3.5  
Serial Clock (SCK)  
The SCK is used to synchronize the communication  
between a master and the 23LCV1024. Instructions,  
addresses or data present on the SI pin are latched on  
the rising edge of the clock input, while data on the SO  
pin is updated after the falling edge of the clock input.  
DS25156A-page 12  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
4.1  
Dual Interface Mode  
4.0  
DUAL SERIAL MODE  
The 23LCV1024 supports SDI (Serial Dual) mode of  
operation. To enter SDI mode the EDIO command must  
be clocked in (Figure 4-1). It should be noted that if the  
MCU resets before the SRAM, the user will need to  
determine the serial mode of operation of the SRAM  
and reset it accordingly. Byte read and write sequence  
in SDI mode is shown in Figure 4-2 and Figure 4-3.  
The 23LCV1024 also supports SDI (Serial Dual) mode  
of operation when used with compatible master  
devices. As a convention for SDI mode of operation,  
two bits are entered per clock using the SIO0 and SIO1  
pins. Bits are clocked MSB first.  
FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE  
CS  
0
1
2
3
4
5
6
7
SCK  
SI  
0
0
1
1
1
0
1
1
High-Impedance  
SO  
FIGURE 4-2:  
BYTE READ MODE SDI  
CS  
0
2
4
5
13  
14 15  
1
3
6
18  
20 21 22 23  
19  
16 17  
SCK  
0
1
0
0
0
0
1
6
7
4
2
22 20 18  
4
2
3
0
1
SIO0  
Dummy Byte  
Data Out  
Instruction  
24-Bit Address  
0
0
1
5
3
23 21 19  
5
SIO1  
Note:  
Note:  
Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high.  
The first byte read after the address will be a dummy byte.  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 13  
23LCV1024  
FIGURE 4-3:  
BYTE WRITE MODE SDI  
CS  
5
0
1
2
3
4
6
13 14 15 16  
19  
17 18  
SCK  
SIO0  
0
0
0
0
0
0
1
22 20 18  
4
2
3
0
6
7
4
2
Data In  
Instruction  
24-Bit Address  
0
0
1
23 21 19  
5
1
5
3
SIO1  
Note:  
Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high.  
4.2  
Exit SDI Mode  
To exit from SDI mode, the RSTIO command must be  
issued. The command must be entered in the current  
device configuration see (Figure 4-4)  
FIGURE 4-4:  
RESET SDI MODE (RSTIO) – FROM SDI MODE  
CS  
3
2
0
1
SCK  
1 1 1 1  
SIO0  
SIO1  
1 1 1 1  
DS25156A-page 14  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
The VBAT trip point is the point at which the internal  
switch operates the device from the VBAT supply and  
is typically 1.8V (VTRIP specification D012). When VCC  
falls below the VTRIP point the system will continue to  
maintain the SRAM contents.  
5.0  
VBAT  
The 23LCV1024 features an internal switch that will  
maintain the SRAM contents. In the event that the VCC  
supply is not available, the voltage applied to the VBAT  
pin serves as the backup supply.  
The following conditions apply:  
Supply Condition  
Read/Write Access  
Powered By  
VCC < VTRIP, VCC < VBAT  
VCC > VTRIP, VCC < VBAT  
VCC > VTRIP, VCC > VBAT  
No  
Yes  
Yes  
VBAT  
VCC  
VCC  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 15  
23LCV1024  
6.0  
6.1  
PACKAGING INFORMATION  
Package Marking Information  
8-Lead PDIP (300 mil)  
Example  
23LCVB  
I/P 1L7  
XXXXXXXX  
XXXXXNNN  
e
3
0528  
YYWW  
8-Lead SOIC (3.90 mm)  
Example:  
23LCVBI  
XXXXXXXT  
XXXXYYWW  
SN  
0528  
e
3
NNN  
1L7  
Example:  
3LVB  
8-Lead TSSOP  
XXXX  
TYWW  
I837  
1L7  
NNN  
Legend: XX...X Part number or part number code  
T
Temperature (I, E)  
Y
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code (2 characters for small packages)  
Pb-free JEDEC designator for Matte Tin (Sn)  
YY  
WW  
NNN  
e
3
Note: For very small packages with no room for the Pb-free JEDEC designator  
, the marking will only appear on the outer carton or reel label.  
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
DS25156A-page 16  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢐꢁꢂꢋꢐꢃꢆꢑꢇꢒꢆꢓꢆꢔꢕꢕꢆꢖꢋꢈꢆꢗꢘꢅꢙꢆꢚꢇꢍꢏꢇꢛ  
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ  
N
NOTE 1  
E1  
3
1
2
D
E
A2  
A
L
A1  
c
e
eB  
b1  
b
ꢯꢄꢃꢏꢇ  
ꢰꢱꢝꢲꢠꢛ  
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ  
ꢢꢰꢱ  
ꢱꢴꢢ  
ꢁꢀꢣꢣꢅꢩꢛꢝ  
ꢁꢀꢞꢣ  
ꢁꢞꢀꢣ  
ꢁꢙꢨꢣ  
ꢁꢞꢺꢨ  
ꢁꢀꢞꢣ  
ꢁꢣꢀꢣ  
ꢁꢣꢺꢣ  
ꢁꢣꢀꢶ  
ꢢꢦꢵ  
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ  
ꢂꢃꢏꢖꢘ  
ꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ  
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ  
ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ  
ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢹꢃꢋꢏꢘ  
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ  
ꢦꢙ  
ꢦꢀ  
ꢠꢀ  
ꢔꢀ  
ꢌꢩ  
ꢁꢙꢀꢣ  
ꢁꢀꢸꢨ  
ꢁꢀꢀꢨ  
ꢁꢣꢀꢨ  
ꢁꢙꢸꢣ  
ꢁꢙꢥꢣ  
ꢁꢞꢥꢶ  
ꢁꢀꢀꢨ  
ꢁꢣꢣꢶ  
ꢁꢣꢥꢣ  
ꢁꢣꢀꢥ  
ꢁꢞꢙꢨ  
ꢁꢙꢶꢣ  
ꢁꢥꢣꢣ  
ꢁꢀꢨꢣ  
ꢁꢣꢀꢨ  
ꢁꢣꢻꢣ  
ꢁꢣꢙꢙ  
ꢁꢥꢞꢣ  
ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ  
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ  
ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ  
ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ  
ꢜꢘꢊꢃꢉꢝ  
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ  
ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ  
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ  
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ  
ꢩꢛꢝꢪꢅꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ  
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢶꢩ  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 17  
23LCV1024  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS25156A-page 18  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 19  
23LCV1024  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ  
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ  
DS25156A-page 20  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢦꢧꢋꢐꢆꢞꢧꢠꢋꢐꢨꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢦꢒꢆꢓꢆꢩꢣꢩꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢦꢞꢞꢟꢇꢛ  
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ  
D
N
E
E1  
NOTE 1  
1
2
b
e
c
φ
A
A2  
A1  
L
L1  
ꢯꢄꢃꢏꢇ  
ꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ  
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ  
ꢢꢰꢱ  
ꢱꢴꢢ  
ꢢꢦꢵ  
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ  
ꢂꢃꢏꢖꢘ  
ꢣꢁꢺꢨꢅꢩꢛꢝ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ  
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ  
ꢛꢏꢉꢄꢋꢕꢎꢎꢅ  
ꢣꢁꢶꢣ  
ꢣꢁꢣꢨ  
ꢀꢁꢣꢣ  
ꢀꢁꢙꢣ  
ꢀꢁꢣꢨ  
ꢣꢁꢀꢨ  
ꢦꢙ  
ꢦꢀ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ  
ꢺꢁꢥꢣꢅꢩꢛꢝ  
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ  
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢳꢌꢄꢜꢏꢘ  
ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ  
ꢠꢀ  
ꢥꢁꢞꢣ  
ꢙꢁꢸꢣ  
ꢣꢁꢥꢨ  
ꢥꢁꢥꢣ  
ꢞꢁꢣꢣ  
ꢣꢁꢺꢣ  
ꢥꢁꢨꢣ  
ꢞꢁꢀꢣ  
ꢣꢁꢻꢨ  
ꢬꢕꢕꢏꢡꢐꢃꢄꢏ  
ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ  
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ  
ꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ  
ꢳꢀ  
ꢀꢁꢣꢣꢅꢼꢠꢬ  
ꢣꢾ  
ꢣꢁꢣꢸ  
ꢣꢁꢀꢸ  
ꢶꢾ  
ꢣꢁꢙꢣ  
ꢣꢁꢞꢣ  
ꢜꢘꢊꢃꢉꢝ  
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ  
ꢙꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢀꢨꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ  
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ  
ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ  
ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ  
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢶꢺꢩ  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 21  
23LCV1024  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS25156A-page 22  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
APPENDIX A: REVISION HISTORY  
Revision A (09/2012)  
Initial release.  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 23  
23LCV1024  
NOTES:  
DS25156A-page 24  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
THE MICROCHIP WEB SITE  
CUSTOMER SUPPORT  
Microchip provides online support via our WWW site at  
www.microchip.com. This web site is used as a means  
to make files and information easily available to  
customers. Accessible by using your favorite Internet  
browser, the web site contains the following  
information:  
Users of Microchip products can receive assistance  
through several channels:  
• Distributor or Representative  
• Local Sales Office  
• Field Application Engineer (FAE)  
Technical Support  
Product Support – Data sheets and errata,  
application notes and sample programs, design  
resources, user’s guides and hardware support  
documents, latest software releases and archived  
software  
• Development Systems Information Line  
Customers  
should  
contact  
their  
distributor,  
representative or field application engineer (FAE) for  
support. Local sales offices are also available to help  
customers. A listing of sales offices and locations is  
included in the back of this document.  
General Technical Support – Frequently Asked  
Questions (FAQ), technical support requests,  
online discussion groups, Microchip consultant  
program member listing  
Technical support is available through the web site  
at: http://microchip.com/support  
Business of Microchip – Product selector and  
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CUSTOMER CHANGE NOTIFICATION  
SERVICE  
Microchip’s customer notification service helps keep  
customers current on Microchip products. Subscribers  
will receive e-mail notification whenever there are  
changes, updates, revisions or errata related to a  
specified product family or development tool of interest.  
To register, access the Microchip web site at  
www.microchip.com. Under “Support”, click on  
“Customer Change Notification” and follow the  
registration instructions.  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 25  
23LCV1024  
READER RESPONSE  
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip  
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our  
documentation can better serve you, please FAX your comments to the Technical Publications Manager at  
(480) 792-4150.  
Please list the following information, and use this outline to provide us with your comments about this document.  
TO:  
RE:  
Technical Publications Manager  
Reader Response  
Total Pages Sent ________  
From:  
Name  
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Address  
City / State / ZIP / Country  
Telephone: (_______) _________ - _________  
FAX: (______) _________ - _________  
Literature Number: DS25156A  
Application (optional):  
Would you like a reply?  
Y
N
Device: 23LCV1024  
Questions:  
1. What are the best features of this document?  
2. How does this document meet your hardware and software development needs?  
3. Do you find the organization of this document easy to follow? If not, why?  
4. What additions to the document do you think would enhance the structure and subject?  
5. What deletions from the document could be made without affecting the overall usefulness?  
6. Is there any incorrect or misleading information (what and where)?  
7. How would you improve this document?  
DS25156A-page 26  
Preliminary  
2012 Microchip Technology Inc.  
23LCV1024  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options  
are shown below..  
PART NO.  
Device  
X
/XX  
X
Examples:  
Tape & Reel  
Package  
Temp Range  
a)  
b)  
c)  
23LCV1024-I/ST = 1 Mbit, 2.5 - 5.5V Serial  
SRAM, Industrial temp., TSSOP package  
23LCV1024-I/SN = 1 Mbit, 2.5 - 5.5V Serial  
SRAM, Industrial temp., SOIC package  
23LCV1024-I/P = 1 Mbit, 2.5 - 5.5V Serial  
SRAM, Industrial temp., PDIP package  
Device:  
23LCV1024=  
1 Mbit, 2.5 - 5.5V, SPI Serial SRAM  
Tape & Reel: Blank  
=
=
Standard packaging (tube)  
Tape & Reel  
T
Temperature  
Range:  
I
=
-40C to+85C  
Package:  
SN  
ST  
P
=
=
=
Plastic SOIC (3.90 mm body), 8-lead  
Plastic TSSOP (4.4 mm body), 8-lead  
Plastic PDIP (300 mil body), 8-lead  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 27  
23LCV1024  
NOTES:  
DS25156A-page 28  
Preliminary  
2012 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,  
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash  
and UNI/O are registered trademarks of Microchip Technology  
Incorporated in the U.S.A. and other countries.  
32  
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  
MTP, SEEVAL and The Embedded Control Solutions  
Company are registered trademarks of Microchip Technology  
Incorporated in the U.S.A.  
Silicon Storage Technology is a registered trademark of  
Microchip Technology Inc. in other countries.  
Analog-for-the-Digital Age, Application Maestro, BodyCom,  
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,  
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,  
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial  
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB  
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code  
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,  
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,  
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA  
and Z-Scale are trademarks of Microchip Technology  
Incorporated in the U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
GestIC and ULPP are registered trademarks of Microchip  
Technology Germany II GmbH & Co. & KG, a subsidiary of  
Microchip Technology Inc., in other countries.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2012, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
ISBN: 9781620765999  
QUALITY MANAGEMENT SYSTEM  
CERTIFIED BY DNV  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
== ISO/TS 16949 ==  
2012 Microchip Technology Inc.  
Preliminary  
DS25156A-page 29  
Worldwide Sales and Service  
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Tel: 43-7242-2244-39  
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Tel: 45-4450-2828  
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Tel: 91-11-4160-8631  
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Toronto  
Mississauga, Ontario,  
Canada  
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Fax: 86-756-3210049  
11/29/11  
DS25156A-page 30  
Preliminary  
2012 Microchip Technology Inc.  

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