24AA00TE/SN
更新时间：2024-09-18 19:08:20
品牌：MICROCHIP
描述：16 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8
概述
规格参数
数据手册24AA00TE/SN 概述
16 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8 EEPROM
24AA00TE/SN 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8 | 针数： | 8 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.32.00.51 | 风险等级： | 5.2 |
| 最大时钟频率 (fCLK)： | 0.4 MHz | 数据保留时间-最小值： | 200 |
| 耐久性： | 1000000 Write/Erase Cycles | I2C控制字节： | 1010XXXR |
| JESD-30 代码： | R-PDSO-G8 | JESD-609代码： | e3 |
| 长度： | 4.9 mm | 内存密度： | 128 bit |
| 内存集成电路类型： | EEPROM | 内存宽度： | 8 |
| 湿度敏感等级： | 1 | 功能数量： | 1 |
| 端子数量： | 8 | 字数： | 16 words |
| 字数代码： | 16 | 工作模式： | SYNCHRONOUS |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 组织： | 16X8 | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP8,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 并行/串行： | SERIAL | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 2/5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.75 mm | 串行总线类型： | I2C |
| 最大待机电流： | 0.000001 A | 子类别： | EEPROMs |
| 最大压摆率： | 0.002 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 1.7 V | 标称供电电压 (Vsup)： | 2.5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Matte Tin (Sn) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 40 |
| 宽度： | 3.9 mm | 最长写入周期时间 (tWC)： | 4 ms |
| Base Number Matches： | 1 |
24AA00TE/SN 数据手册
通过下载24AA00TE/SN数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载24LCS61/24LCS62
1K/2K Software Addressable I2C™ Serial EEPROM
PRODUCT OFFERING
PACKAGE TYPES
PDIP
Array
Size
Voltage SoftwareWrite
Device
Range
Protection
NC
1
8
Vcc
24LCS61
24LCS62
1K bits 2.5V-5.5V
2K bits 2.5V-5.5V
Entire Array
Lower Half
NC
2
3
7
6
NC
EDS
SCL
FEATURES
Vss
4
5
SDA
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• Software addressability allows up to 255 devices
on the same bus
SOIC
8
1
• 2-wire serial interface bus, I2C compatible
• Automatic bus arbitration
NC
NC
VCC
NC
7
6
5
2
3
4
• Wakes up to control code 0110
• General purpose output pin can be used to enable
other circuitry
SCL
SDA
EDS
Vss
• 100 kHz and 400 kHz compatibility
• Page-write buffer for up to 16 bytes
• 10 ms max write cycle time for byte or page write
• 1,000,000 erase/write cycles guaranteed
• 8-pin PDIP, SOIC or TSSOP packages
• Temperature ranges supported:
TSSOP
1
8
NC
NC
Vcc
2
3
4
7
6
5
NC
EDS
VSS
SCL
SDA
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LCS61/62 is a 1K/2K
bit Serial EEPROM developed for applications that
require many devices on the same bus but do not have
the I/O pins required to address each one individually.
These devices contain an 8 bit address register that is
set upon power-up and allows the connection of up to
255 devices on the same bus. When the process of
assigning ID values to each device is in progress, the
device will automatically handle bus arbitration if more
than one device is operating on the bus. In addition, an
external open drain output pin is available that can be
used to enable other circuitry associated with each indi-
vidual system. Low current design permits operation
with typical standby and active currents of only 10 µA
and 1 mA respectively. The device has a page-write
capability for up to 16 bytes of data. The device is avail-
able in the standard 8-pin PDIP, SOIC (150 mil), and
TSSOP packages.
BLOCK DIAGRAM
EDS
HV Generator
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
ID Register
Serial Number
SDA
SCL
YDEC
Vcc
Vss
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 1
24LCS61/62
TABLE 1-1:
Name
PIN FUNCTION TABLE
1.0
ELECTRICAL
CHARACTERISTICS
Function
1.1
Maximum Ratings*
VSS
SDA
SCL
VCC
NC
Ground
Serial Data
VCC........................................................................7.0V
All inputs and outputs w.r.t. VSS .....-0.6V to VCC +1.0V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) ..+300°C
ESD protection on all pins ..................................... ≥ 4 kV
Serial Clock
+2.5V to 5.5V Power Supply
No Internal Connection
External Device Select Output
EDS
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
All parameters apply across the speci-
VCC = +2.5V to +5.5V
fied operating ranges unless otherwise Industrial (I):
noted.
Tamb = -40°C to +85°C
Parameter
SCL and SDA pins:
Symbol
Min.
Max.
Units
Conditions
VIH
0.7 VCC
V
High level input voltage
Low level input voltage
VIL
VHYS
VOL
.3 VCC
—
V
V
V
Hysteresis of Schmitt trigger inputs
0.05 VCC
Low level output voltage
(SDA and EDS pins)
.40
IOL = 12 mA, VCC = 4.5V
IOL = 8 mA, VCC = 2.5V
Input leakage current
ILI
-10
-10
—
10
10
10
µA
µA
pF
VIN = Vss or Vcc
Output leakage current
ILO
VOUT = Vss or Vcc
Pin capacitance (all inputs/outputs)
CIN,
VCC = 5.0V (Note)
COUT
Tamb = 25°C, f = 1 MHz
Operating current
Standby current
ICC Write
ICC Read
ICCS
—
—
—
4
1
mA
mA
µA
VCC = 5.5V
VCC = 5.5V, SCL = 400 kHz
50
VCC = 5.5V, SDA = SCL = VCC
EDS = VCC
Note: This parameter is periodically sampled and not 100% tested.
DS21226C-page 2
Preliminary
1999 Microchip Technology Inc.
24LCS61/62
TABLE 1-3:
AC CHARACTERISTICS
All parameters apply across the specified
operating ranges unless otherwise noted.
Vcc = +2.5V to 5.5V
Industrial (I):
Tamb = -40°C to +85°C
VCC = 2.5V - 5.5V Vcc = 4.5V - 5.5V
STD MODE
FAST MODE
Parameter
Symbol
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
From VIL to VIH (Note 1)
From VIL to VIH (Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup time TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
250
4000
—
100
600
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time
(from 0.7 VCC to 0.3 VCC)
TOF
TSP
TWC
—
—
250
50
20 +0.1
CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
—
(Notes 1, 3)
Write cycle time
Endurance
—
10
—
—
10
—
ms Byte or Page mode
1M
1M
cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-1: BUS TIMING DATA
THIGH
TF
TR
SCL
Tsu:sta
TLOW
THD:DAT
TSU:DAT
TSU:STO
SDA
IN
THD:STA
TSP
TBUF
TAA
SDA
OUT
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 3
24LCS61/62
2.0
PIN DESCRIPTIONS
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
2.1
SDA (Serial Data)
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions. The SDA pin has Schmitt trigger and filter circuits
which suppress noise spikes to assure proper device
operation even on a noisy bus
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
Bus not Busy (A)
2.2
SCL (Serial Clock)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
This input is used to synchronize the data transfer from
and to the device. The SCL pin has Schmitt trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
2.3
EDS (External Device Select)
The External Device Select (EDS) pin is an open drain
output that is controlled by using the OE bit in the con-
trol byte. It can be used to enable other circuitry when
the device is selected. A pull-up resistor must be added
to this pin for proper operation. This pin should not be
pulled up to a voltage higher than Vcc+1V. See
Section 9.0 for more details.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between the START and STOP
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
DATA OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
DS21226C-page 4
Preliminary
1999 Microchip Technology Inc.
24LCS61/62
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 3-2).
3.5
Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24LCS61/62 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 5
24LCS61/62
FIGURE 4-1: CONTROL BYTE FORMAT
4.0
FUNCTIONAL DESCRIPTION
The 24LCS61/62 supports a bi-directional 2-wire bus
and data transmission protocol compatible with the I2C
protocol. The device is configured to reside on a com-
mon I2C bus with up to 255 total 24LCS61/62 devices
on the bus. Each device has a unique serial number
assigned to it when delivered from the factory. In an
actual system, this serial number will be used to assign
a separate 8-bit ID byte to each device in the system.
After an ID byte is assigned to each device in the sys-
tem, standard read and write commands can be sent to
each device individually.
Output Enable
Bit
Command Select
Control Code
Bits
S
0
1
1
0
OE C2 C1 C0 ACK
Start Bit
Acknowledge Bit
4.1
Device Serial Number
TABLE 4-1:
COMMAND CODES
The device serial number is stored in a 48-bit (6 byte)
register that is separate from the data array. The serial
number register is non-volatile and cannot be changed
by the user. Before shipment from the factory, this reg-
ister is programmed with a unique value for every
device. The 48 bit register allows for 2.8•1014 different
combinations. The serial number is used at power-up to
assign the device an ID byte which is then used for all
standard read and write commands sent to that specific
device.
Command Select Bits
(C2 C1 C0)
Command
Set Write Protection Fuse
Read
000
001
010
100
110
Write (Byte or Page)
Assign Address
Clear Address
4.2
Device ID Byte
The Device ID byte is an 8-bit value that provides the
means for every device on the bus to be accessed indi-
vidually. The ID byte is stored in a RAM register sepa-
rate from the data array. The ID byte register will always
default to address 00 upon power-up.
4.3
Device Addressing
Each command to the device must begin with a start
bit. A control byte is the first byte received following the
start condition from the master device (Figure 4-1). The
control byte consists of a four-bit control code, the OE
bit, and three command select bits. For the 24LCS61/
62, the control code is set to 0110 binary for all opera-
tions. The device will not acknowledge any commands
sent with any other control code. The next bit is the Out-
put Enable (OE) bit. This bit controls the operation of
the EDS pin. See Section 9.0 for more details. The last
three bits of the control byte are the command select
bits (C0-C2). The command select bits determine
which command will be executed. See Table 4-1. Fol-
lowing a valid control byte, the 24LCS61/62 will
acknowledge the command.
DS21226C-page 6
Preliminary
1999 Microchip Technology Inc.
24LCS61/62
the device ID byte, and the master must acknowledge
each byte of the serial number transmitted by the
device. As each bit is clocked out, each device will mon-
itor the bus to detect if another device is also transmit-
ting. If any device is outputting a logic ‘1’ on the bus and
it detects that the bus is at a logic ‘0’, then it assumes
that another device is controlling the bus. As soon as
any device detects that it is not controlling the bus it will
immediately stop transmitting data and return to
standby mode. The master must end the command by
sending a no ack after all 6 bytes of the serial number
have been transmitted, followed by a Stop bit. Sending
the Stop bit in any other position of the command will
result in the command aborting and all devices releas-
ing the bus with no address assigned. If a device trans-
mits its entire 48 bit serial number without releasing the
bus to another device, then the ID byte transmitted
within the command is transferred to the internal ID
byte register upon receipt of the Stop bit and it will now
respond only to commands that contain this ID byte (or
the Clear Address command). Once a device has been
assigned an ID byte, it will no longer respond to Assign
Address commands until power is cycled or the Clear
Address command is sent.
5.0
ASSIGNING THE ID BYTE
The 24LCS61/62 device contains a special register
which holds an 8-bit ID byte that is used as an address
to communicate with a specific device on the bus. All
read and write commands to the device must include
this ID address byte. Upon power-up, the ID byte will
default to 00h. Communicating with the device using
the default address is typically done only at testing or
programming time and not when it is connected to a
bus with more than one device. Before the device can
be used on a common bus with other devices, a unique
ID byte address must be assigned to every device.
5.1
Assign Address Command
The ID byte is assigned by sending the Assign Address
command. This command queries any device con-
nected to the bus and utilizing the automatic bus arbi-
tration feature, assigns an ID byte to the device that
remains on the bus after arbitration is complete. Once
a device has been assigned an ID byte, it will no longer
respond to Assign Address commands until power is
cycled or the Clear Address command is sent. The
Assign Address command must be repeated for each
device on the bus until all devices have been assigned
an ID byte.
This process of assigning ID bytes is repeated by the
controller until no more devices respond to the Assign
Address command. At this point, all devices on the bus
have been assigned an ID byte and standard read and
write commands can be executed to each individual
device.
The format for the Assign Address command is shown
in Figure 5-1. The command consists of the control
byte, the ID byte to be assigned to the device remaining
when the arbitration is complete, and 48 bits of data
being transmitted by devices on the bus. If the OE bit is
set to a 1, then any device who has not been assigned
an address will assert their respective EDS pin after the
acknowledge bit following the Device ID byte. After the
control byte and ID byte are sent, each device will begin
to transmit its unique 48-bit serial number. The
24LCS61/62 must acknowledge the control byte and
The ID byte is stored in a volatile SRAM register, and if
power is removed from the device or the Clear Address
command is sent, then the ID byte will default to
address 00 and the process of assigning an ID value
must be repeated.
FIGURE 5-1: ASSIGN ADDRESS COMMAND
STOP bit must occur here
or command will abort
A unique address must be assigned to each
device on the bus
S
T
A
R
T
6 Bytes (48 Bits) of Device Serial Number
with each byte separated by an ack bit
S
T
O
P
CONTROL
BYTE
Device ID Byte
O
P
0 1 1 0 1 0 0
E
S
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 7
24LCS61/62
after 8 don’t care bits have been transmitted, followed
by a Stop bit. Sending the Stop bit in any other position
of the command will result in the command aborting
and the device releasing the bus.
5.2
Clear Address Command
The clear address command will clear the device ID
byte from all devices on the bus and will enable all
devices to respond to the Assign Address command.
The master must end the command by sending an ack
FIGURE 5-2: CLEAR ADDRESS COMMAND
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
Device ID Byte
O
X X X X X X X X
P
0 1 1 0 1 1 0
E
S
A
C
K
A
C
K
DS21226C-page 8
Preliminary
1999 Microchip Technology Inc.
24LCS61/62
5.3
Operation State Diagram
The diagram below shows the state diagram for basic
operation of the 24LCS61/62. This diagram shows pos-
sible states and operational flow once power is applied
to the device. Table 5-1 summarizes operation of each
command for the assigned and unassigned states.
FIGURE 5-3: OPERATIONAL STATE DIAGRAM
Power Off
Clear Address
Command
Power Off
Power On
Assigned
State
(ID byte has been assigned)
Unassigned
State
Power
Off
(ID byte not assigned yet)
Assign Address Command:
Device wins Arbitration
Assign Address Command:
Device loses Arbitration
TABLE 5-1:
Command
COMMAND SUMMARY TABLE
Result if Device Has Not Yet
Been Assigned an ID Byte
Result if Device Has Already Been
Assigned an ID Byte
Assign Address
command
If device wins arbitration, then ID
byte will become xxh. If device
loses arbitration, then ID byte will
revert back to 00h.
Device will not acknowledge command.
Clear Address
command
Device will remain with ID byte set Device ID byte will revert back to 00h and will then
to 00h.
acknowledge Assign Address commands.
Read or Write
command with
ID byte set to 00h
Since the default ID byte for the
device is 00h, the device will exe-
cute the command.
Device will acknowledge the control byte, but it will not
acknowledge any further bytes and will not respond to
the command.
Read or Write
Device will acknowledge the control If the device ID byte matches the ID byte in the command
command with
ID byte set to xxh
(other than 00h)
byte, but it will not acknowledge
any further bytes and will not
respond to the command.
(xxh), the device will execute the command. If the device
ID byte does not match the ID byte in the command, then
the device will acknowledge the control byte, but it will not
acknowledge any further bytes and will not respond to
the command.
Set Write Protect
command with
ID byte set to 00h
Since the default ID address for the Device will acknowledge the control byte, but it will not
device is 00h, the device will exe-
cute the command.
acknowledge any further bytes and will not respond to
the command.
Set Write Protection Device will acknowledge the control If the device ID byte matches the ID byte in the command
command with
ID byte set to xxh
(other than 00h)
byte, but it will not acknowledge
any further bytes and will not
respond to the command.
(xxh), the device will execute the command. If the device
ID byte does not match the ID byte in the command, then
the device will acknowledge the control byte, but it will not
acknowledge any further bytes and will not respond to
the command. Note: Once this command has been exe-
cuted successfully for a device, the device will no longer
acknowledge any part of this command again.
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 9
24LCS61/62
6.0
WRITE OPERATIONS
Note: Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
6.1
Byte Write
Following the start signal from the master, the control
byte for a write command is sent by the master trans-
mitter. The device will acknowledge this control byte
during the ninth clock pulse. The next byte transmitted
by the master is the ID byte for the device. After receiv-
ing another acknowledge signal from the 24LCS61/62,
the master device will transmit the address and then
the data word to be written into the addressed memory
location. The 24LCS61/62 acknowledges between
each byte, and the master then generates a stop con-
dition. This initiates the internal write cycle, and during
this time the 24LCS61/62 will not generate acknowl-
edge signals (Figure 6-1).
6.2
Page Write
6.3
Low Voltage Write Protection
The control byte, ID byte, word address, and the first
data byte are transmitted to the 24LCS61/62 in the
same way as in a byte write. But, instead of generating
a stop condition, the master transmits up to 15 addi-
tional data bytes to the 24LCS61/62, which are tempo-
rarily stored in the on-chip page buffer and will be
written into the memory after the master has transmit-
ted a stop condition. If the master should transmit more
than 16 bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 6-2) and the 24LCS61/
62 will not generate acknowledge.
The 24LCS61/62 employs a VCC threshold detector cir-
cuit which disables the internal erase/write logic, if the
VCC is below 1.5 volts at nominal conditions.
6.4
Set Write Protection Command
The Set Write Protection command allows the user to
write protect a portion of the array. For the 24LCS61
this command will write protect the entire array. For the
24LCS62 this command will protect the lower half of the
array. This command is illustrated in Figure 6-3. This is
a one time only command and cannot be reversed
once the protection fuse has been set. Once the
Write protect feature has been set, the device will no
longer acknowledge the control byte (or any of the
other bytes) of this command. The STOP bit of this
command initiates an internal write cycle, and during
this time the 24LCS61/62 will not generate acknowl-
edge signals.
FIGURE 6-1: BYTE WRITE
S
S
T
A
R
T
BUS ACTIVITY
MASTER
T
CONTROL
BYTE
ADDRESS
O
DEVICE
ID BYTE
BYTE
DATA
P
SDA LINE
O
P
0 1 1 0 0 1 0
E
S
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
A
C
K
OE Bit = EDS Pin Output Enable; see Section 9.0
DS21226C-page 10
Preliminary
1999 Microchip Technology Inc.
24LCS61/62
FIGURE 6-2: PAGE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DEVICE
ID BYTE
ADDRESS
BYTE
DATA BYTE 0
DATA BYTE 15
SDA LINE
O
0 1 1 0 0 1 0
E
P
S
A
C
K
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 6-3: SET WRITE PROTECTION COMMAND
S
T
A
R
T
S
T
O
P
ADDRESS
BYTE
DEVICE
ID BYTE
CONTROL
BYTE
DATA BYTE
O
X X X X X X X X
P
X X X X X X X X
0 1 1 0 0 0 0
E
S
A
C
K
A
C
K
A
C
K
A
C
K
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 11
24LCS61/62
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command and then sending the Device ID byte for
that particular device. If the device is still busy with the
write cycle, then no ACK will be returned after the
Device ID byte. If no ACK is returned, then the start bit,
control byte and ID byte must be re-sent. If the cycle is
complete, then the device will return the ACK and the
master can then proceed with the next command. See
Figure 7-1 for flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control byte and
Device ID byte
Did Device
Acknowledge
Device ID
NO
(ACK = 0)?
YES
Next
Operation
DS21226C-page 12
Preliminary
1999 Microchip Technology Inc.
24LCS61/62
a start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master sends the con-
trol byte and ID byte for a read command. The
24LCS61/62 will then issue an acknowledge and trans-
mits the eight bit data word. The master will not
acknowledge the transfer but does generate a stop
condition and the 24LCS61/62 discontinues transmis-
sion (Figure 8-2).
8.0
READ OPERATIONS
Read operations are initiated in a similar way as the
write operations. There are three basic types of read
operations: current address read, random read, and
sequential read.
8.1
Current Address Read
The 24LCS61/62 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
read access was to address n, the next current address
read operation would access data from address n + 1.
Upon receipt of the correct control byte and ID byte, the
24LCS61/62 issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LCS61/62 discontinues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LCS61/62 transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LCS61/62 to transmit the next sequen-
tially addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24LCS61/62 contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation. The internal address pointer
will automatically roll over from address 7Fh
(24LCS61) or FFh (24LCS62) to address 00h.
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS61/62 as part of a write operation. After the ID
byte and word address are sent, the master generates
FIGURE 8-1: CURRENT ADDRESS READ
S
T
S
DEVICE
ID BYTE
BUS ACTIVITY
MASTER
CONTROL
BYTE
A
R
T
T
DATA
O
P
O
SDA LINE
1 1 0 0 0 1
P
S 0
E
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
OE Bit = EDS Pin Output Enable; see Section 9.0
K
FIGURE 8-2: RANDOM READ
S
T
A
R
T
S
ADDRESS
BYTE
DEVICE
ID BYTE
CONTROL
BYTE
DATA
BYTE
CONTROL
T
DEVICE
ID BYTE
S
T
A
R
T
BYTE
O
P
O
O
0 1 1 0 0 0 1
S
1 1 0 0 1 0
E
S 0
E
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 8-3: SEQUENTIAL READ
S
T
BUS ACTIVITY
ID
DATA n
DATA n + 1
DATA n + 2
DATA n + X
MASTER
O
P
BYTE
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 13
24LCS61/62
write commands, the EDS pin will pull low (providing
that the OE bit is set high) on the rising clock edge after
the ack bit following the ID byte. See Figure 9-1. For
commands such as the Clear Address command, the
EDS pin will change states at the rising clock edge just
before the Stop bit. It is also possible to control the EDS
pin by sending a partial command such as the control
byte and ID byte for a write command followed by the
Stop bit. The EDS pin would change states just before
the Stop bit as shown in the lower portion of Figure 9-
1. When the EDS pin has changed states, it is latched
and will remain in a given state until another command
is sent to the device with the OE bit set to change the
state of the pin, or power to the device is removed.
9.0
EXTERNAL DEVICE SELECT
(EDS) PIN AND OUTPUT
ENABLE (OE) BIT
The External Device Select (EDS) pin is an open drain,
low active output and may be used by the system
designer for functions such as enabling other circuitry
when the 24LCS61/62 is being accessed. Because the
pin is an open drain output, a pull-up resistor is required
for proper operation of this pin. When the device is pow-
ered up, the EDS pin will always be in the high imped-
ance state (off). The EDS pin function is controlled by
using the output enable (OE) bit in the control byte of
each command. If the OE bit is high, the EDS pin is
enabled and if the OE bit is low the pin is disabled. For
the Assign Address command and standard read or
FIGURE 9-1: EDS PIN OPERATION
ACK
BIT
ACK
BIT
Control
Byte
Start
Bit
ID Byte
SCL
SDA
1
0
2
1
3
1
4
0
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
EDS
For commands such as the Assign Address command or standard read and
writes, the EDS pin will be asserted on this rising clock edge if the OE bit was set
to a one in the control byte. If the OE bit is a zero and the previous command
asserted it, then the EDS pin will be released by the device on this clock edge.
ACK
BIT
ACK STOP
Control
Byte
Start
Bit
BIT
BIT
ID Byte
SCL
1
2
1
3
1
4
0
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SDA
EDS
0
For commands such as the Clear Address command, the command is ter-
minated at this point with a STOP bit. The EDS pin will be asserted on this
rising clock edge if the OE bit was set to a one in the control byte. If the OE
bit is a zero and the previous command asserted it, then the EDS pin will be
released by the device at this point.
DS21226C-page 14
Preliminary
1999 Microchip Technology Inc.
24LCS61/62
24LCS61/62 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office..
24LCS61/62 /P
—
Package:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body)
ST = TSSOP, 8-lead
OT = SOT-23, 5 lead
Temperature
Range:
Blank = 0°C to +70°C
I = –40°C to +85°C
E = –40°C to +125°C
24AA00
Device:
128 bit 1.8V I2C Serial EEPROM
128 bit 1.8V K I2C Serial EEPROM (Tape and Reel)
128 bit 2.5V I2C Serial EEPROM
24AA00T
24LC00
24LC00T
24C00
128 bit 2.5V K I2C Serial EEPROM (Tape and Reel)
128 bit 5.0V I2C Serial EEPROM
128 bit 5.0V K I2C Serial EEPROM (Tape and Reel)
24C00T
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 15
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
M
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2002 Microchip Technology Inc.
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