24AA02UID [MICROCHIP]

2K I2C™ Serial EEPROMs with Unique 32-bit Serial Number; 2K I2Câ ?? ¢串行EEPROM ,具有唯一的32位序列号
24AA02UID
型号: 24AA02UID
厂家: MICROCHIP    MICROCHIP
描述:

2K I2C™ Serial EEPROMs with Unique 32-bit Serial Number
2K I2Câ ?? ¢串行EEPROM ,具有唯一的32位序列号

可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器
文件: 总30页 (文件大小:631K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
24AA02UID/24AA025UID  
2
2K I C™ Serial EEPROMs with Unique 32-bit Serial Number  
Device Selection Table  
VCC  
Range  
Max. Clock  
Frequency  
Temp.  
Ranges  
Unique ID  
Length  
Part Number  
Cascadable  
Page Size  
24AA02UID  
1.7-5.5V  
1.7-5.5V  
400 kHz(1)  
400 kHz(1)  
I
I
No  
8-Byte  
32-Bit  
32-Bit  
24AA025UID  
Yes  
16-Byte  
Note 1: 100 kHz for VCC <2.5V  
Features:  
Description:  
• Preprogrammed 32-Bit Serial Number:  
- Unique across all UID-family EEPROMs  
The Microchip Technology Inc. 24AA02UID/  
24AA025UID (24AA02XUID*) is a 2 Kbit Electrically  
Erasable PROM with a preprogrammed, 32-bit  
unique ID. The device is organized as two blocks of  
128 x 8-bit memory with a 2-wire serial interface.  
Low-voltage design permits operation down to 1.7V,  
with maximum standby and active currents of only  
1 A and 1 mA, respectively. The 24AA02XUID also  
has a page write capability for up to eight bytes of  
data (16 bytes on the 24AA025UID). The  
24AA02XUID is available in the standard 8-pin PDIP,  
8-pin SOIC, 5-lead SOT-23, and 6-lead SOT-23  
packages.  
- Scalable to 48-bit, 64-bit, 128-bit, 256-bit,  
and other lengths  
• Single Supply with Operation Down to 1.7V  
• Low-Power CMOS Technology:  
- Read current 1 mA, max.  
- Standby current 1 A, max.  
• 2-Wire Serial Interface, I2C™ Compatible  
• Schmitt Trigger Inputs for Noise Suppression  
• Output Slope Control to Eliminate Ground Bounce  
• 100 kHz and 400 kHz Clock Compatibility  
• Page Write Time 3 ms, typical  
• Self-Timed Erase/Write Cycle  
• Page Write Buffer:  
Package Types (24AA02UID)  
SOT-23  
PDIP/SOIC  
1
2
3
4
8
NC  
NC  
VCC  
NC  
- 8-byte page (24AA02UID)  
NC  
1
2
3
5
4
SCL  
7
6
5
- 16-byte page (24AA025UID)  
Vss  
• ESD Protection >4,000V  
NC  
SCL  
SDA  
• More than 1 Million Erase/Write Cycles  
• Data Retention >200 Years  
Vcc  
SDA  
VSS  
• Factory Programming Available  
• Available Packages:  
Package Types (24AA025UID)  
- 8-lead PDIP, 8-lead SOIC, and 5-lead  
SOT-23 (24AA02UID)  
SOT-23  
PDIP/SOIC  
1
8
- 8-lead PDIP, 8-lead SOIC, and 6-lead  
SOT-23 (24AA025UID)  
A0  
A1  
VCC  
NC  
VCC  
A0  
SCL  
VSS  
6
1
2
3
2
3
4
7
6
5
5
4
• RoHS Compliant  
A2  
SCL  
SDA  
Temperature Ranges:  
- Industrial (I): -40°C to +85°C  
A1  
SDA  
VSS  
*24AA02XUID is used in this document as a generic  
part number for the 24AA02UID/24AA025UID devices.  
2013 Microchip Technology Inc.  
DS20005202A-page 1  
24AA02UID/24AA025UID  
Block Diagram  
(1)  
(1)  
(1)  
A0  
A2  
A1  
HV Generator  
I/O  
Control  
Logic  
Memory  
Control  
Logic  
EEPROM  
Array  
XDEC  
SDA  
SCL  
Write-Protect  
Circuitry  
VCC  
VSS  
YDEC  
Sense Amp.  
R/W Control  
Note 1: Pins A0, A1 and A2 are not available on  
the 24AA02UID.  
DS20005202A-page 2  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
1.0  
ELECTRICAL CHARACTERISTICS  
(†)  
Absolute Maximum Ratings  
VCC.............................................................................................................................................................................6.5V  
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V  
Storage temperature ...............................................................................................................................-65°C to +150°C  
Ambient temperature with power applied..................................................................................................-40°C to +85°C  
ESD protection on all pins  4 kV  
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at those or any other conditions above those  
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for  
extended periods may affect device reliability.  
TABLE 1-1:  
DC CHARACTERISTICS  
Industrial (I):  
TA = -40°C to +85°C, VCC = +1.7V to +5.5V  
DC CHARACTERISTICS  
Param.  
Sym.  
No.  
Characteristic  
Min.  
Typ.  
Max.  
Units  
Conditions  
SCL, SDA, A0, A1, and  
A2 pins  
D1  
D2  
D3  
VIH  
High-level Input Voltage  
Low-level Input Voltage  
0.7 VCC  
0.3 VCC  
V
V
V
VIL  
VHYS  
Hysteresis of Schmitt  
Trigger inputs  
0.05 VCC  
(Note)  
D4  
D5  
D6  
D7  
VOL  
ILI  
Low-level Output Voltage  
Input Leakage Current  
Output Leakage Current  
0.40  
±1  
V
IOL = 3.0 mA, VCC = 2.5V  
VIN = VSS or VCC  
A  
A  
pF  
ILO  
±1  
VOUT = VSS or VCC  
CIN,  
Pin Capacitance  
10  
VCC = 5.0V (Note)  
COUT  
(all inputs/outputs)  
TA = 25°C, FCLK = 1 MHz  
D8  
ICC write Operating Current  
0.1  
3
1
1
mA  
mA  
  
VCC = 5.5V, SCL = 400 kHz  
D9  
ICC read  
0.05  
0.01  
D10  
ICCS  
Standby Current  
Industrial  
SDA = SCL = VCC  
A0, A1, A2 = VSS  
Note:  
This parameter is periodically sampled and not 100% tested.  
2013 Microchip Technology Inc.  
DS20005202A-page 3  
24AA02UID/24AA025UID  
TABLE 1-2:  
AC CHARACTERISTICS  
Industrial (I):  
TA = -40°C to +85°C, VCC = +1.7V to +5.5V  
AC CHARACTERISTICS  
Param.  
Sym.  
No.  
Characteristic  
Clock frequency  
Min.  
Typ.  
Max.  
Units  
Conditions  
1
FCLK  
THIGH  
TLOW  
TR  
400  
100  
kHz 2.5V VCC 5.5V  
1.7V VCC 2.5V  
2
Clock high time  
Clock low time  
600  
4000  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
3
1300  
4700  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
4
SDA and SCL rise time  
(Note 1)  
300  
1000  
2.5V VCC 5.5V (Note 1)  
1.7V VCC 2.5V (Note 1)  
5
TF  
SDA and SCL fall time  
300  
(Note 1)  
6
THD:STA Start condition hold time  
600  
4000  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
7
TSU:STA Start condition setup  
time  
600  
4700  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
8
THD:DAT Data input hold time  
0
(Note 2)  
9
TSU:DAT Data input setup time  
100  
250  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
10  
11  
12  
TSU:STO Stop condition setup  
time  
600  
4000  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
TAA  
Output valid from clock  
(Note 2)  
900  
3500  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
TBUF  
Bus free time: Time the  
bus must be free before  
a new transmission can  
start  
1300  
4700  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
13  
14  
TOF  
TSP  
Output fall time from VIH  
minimum to VIL  
maximum  
250  
250  
ns  
ns  
2.5V VCC 5.5V  
1.7V VCC 2.5V  
Input filter spike  
suppression  
50  
(Notes 1 and 3)  
(SDA and SCL pins)  
15  
16  
TWC  
Write cycle time (byte or  
page)  
5
ms  
Endurance  
1M  
cycles 25°C (Note 4)  
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.  
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region  
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.  
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved  
noise spike suppression. This eliminates the need for a TI specification for standard operation.  
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific  
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site  
at www.microchip.com.  
DS20005202A-page 4  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
FIGURE 1-1:  
BUS TIMING DATA  
5
4
2
3
SCL  
7
8
9
10  
6
SDA  
IN  
14  
12  
11  
SDA  
OUT  
FIGURE 1-2:  
BUS TIMING START/STOP  
D3  
SCL  
SDA  
6
7
10  
Start  
Stop  
2013 Microchip Technology Inc.  
DS20005202A-page 5  
24AA02UID/24AA025UID  
2.0  
PIN DESCRIPTIONS  
The descriptions of the pins are listed in Table 2-1.  
TABLE 2-1:  
Name  
PIN FUNCTION TABLE  
PDIP  
SOIC  
5-Pin SOT-23  
6-Pin SOT-23  
Description  
A0  
A1  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
5
4
Chip Address Input(1)  
Chip Address Input(1)  
Chip Address Input(1)  
Ground  
A2  
2
VSS  
SDA  
SCL  
NC  
3
3
Serial Address/Data I/O  
Serial Clock  
1
1
5
6
Not Connected  
VCC  
4
+1.7V to 5.5V Power Supply  
Note 1: Chip address inputs A0, A1 and A2 are not connected on the 24AA02UID.  
2.1  
Serial Address/Data Input/Output  
(SDA)  
SDA is a bidirectional pin used to transfer addresses  
and data into and out of the device. Since it is an open-  
drain terminal, the SDA bus requires a pull-up resistor  
to VCC (typical 10 kfor 100 kHz, 2 kfor 400 kHz).  
For normal data transfer, SDA is allowed to change  
only during SCL low. Changes during SCL high are  
reserved for indicating Start and Stop conditions.  
2.2  
Serial Clock (SCL)  
The SCL input is used to synchronize the data transfer  
to and from the device.  
2.3  
A0, A1, A2 Chip Address Inputs  
The A0, A1 and A2 pins are not used by the  
24AA02UID. They may be left floating or tied to either  
VSS or VCC.  
For the 24AA025UID, the levels on the A0, A1 and A2  
inputs are compared with the corresponding bits in the  
slave address. The chip is selected if the compare is  
true. For the 6-lead SOT-23 package, pin A2 is not con-  
nected and its corresponding bit in the slave address  
should always be set to ‘0’.  
Up to eight 24AA025UID devices (four for the SOT-23  
package) may be connected to the same bus by using  
different Chip Select bit combinations. These inputs  
must be connected to either VSS or VCC.  
DS20005202A-page 6  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
4.4  
Data Valid (D)  
3.0  
FUNCTIONAL DESCRIPTION  
The state of the data line represents valid data when,  
after a Start condition, the data line is stable for the  
duration of the high period of the clock signal.  
The 24AA02XUID supports a bidirectional, 2-wire bus  
and data transmission protocol. A device that sends  
data onto the bus is defined as transmitter, while a  
device receiving data is defined as a receiver. The bus  
has to be controlled by a master device which gener-  
ates the Serial Clock (SCL), controls the bus access  
and generates the Start and Stop conditions, while the  
24AA02XUID works as slave. Both master and slave  
can operate as transmitter or receiver, but the master  
device determines which mode is activated.  
The data on the line must be changed during the low  
period of the clock signal. There is one clock pulse per  
bit of data.  
Each data transfer is initiated with a Start condition and  
terminated with a Stop condition. The number of data  
bytes transferred between Start and Stop conditions is  
determined by the master device and is, theoretically,  
unlimited (although only the last sixteen will be stored  
when doing a write operation). When an overwrite does  
occur, it will replace data in a first-in first-out (FIFO)  
fashion.  
4.0  
BUS CHARACTERISTICS  
The following bus protocol has been defined:  
• Data transfer may be initiated only when the bus  
is not busy.  
4.5  
Acknowledge  
• During data transfer, the data line must remain  
stable whenever the clock line is high. Changes in  
the data line while the clock line is high will be  
interpreted as a Start or Stop condition.  
Each receiving device, when addressed, is obliged to  
generate an acknowledge after the reception of each  
byte. The master device must generate an extra clock  
pulse which is associated with this Acknowledge bit.  
Accordingly, the following bus conditions have been  
defined (Figure 4-1).  
Note:  
The 24AA02XUID does not generate any  
Acknowledge bits if an internal  
programming cycle is in progress.  
4.1  
Bus Not Busy (A)  
The device that acknowledges has to pull down the  
SDA line during the acknowledge clock pulse in such a  
way that the SDA line is stable-low during the high  
period of the acknowledge related clock pulse. Of  
course, setup and hold times must be taken into  
account. During reads, a master must signal an end of  
data to the slave by not generating an Acknowledge bit  
on the last byte that has been clocked out of the slave.  
In this case, the slave (24AA02XUID) will leave the  
data line high to enable the master to generate the Stop  
condition.  
Both data and clock lines remain high.  
4.2  
Start Data Transfer (B)  
A high-to-low transition of the SDA line while the clock  
(SCL) is high determines a Start condition. All  
commands must be preceded by a Start condition.  
4.3  
Stop Data Transfer (C)  
A low-to-high transition of the SDA line while the clock  
(SCL) is high determines a Stop condition. All  
operations must be ended with a Stop condition.  
FIGURE 4-1:  
DATA TRANSFER SEQUENCE ON THE SERIAL BUS  
(A)  
(B)  
(D)  
(D)  
(C) (A)  
SCL  
SDA  
Start  
Condition  
Stop  
Condition  
Address or  
Acknowledge  
Valid  
Data  
Allowed  
to Change  
2013 Microchip Technology Inc.  
DS20005202A-page 7  
24AA02UID/24AA025UID  
FIGURE 5-1:  
CONTROL BYTE  
ALLOCATION  
5.0  
DEVICE ADDRESSING  
A control byte is the first byte received following the  
Start condition from the master device. The control byte  
consists of a 4-bit control code. For the 24AA02XUID,  
this is set as ‘1010binary for read and write  
operations. For the 24AA02UID the next three bits of  
the control byte are “don’t cares”.  
Read/Write Bit  
Chip  
Select  
Bits  
Control Code  
S 1 0 1 0  
For the 24AA025UID, the next three bits of the control  
byte are the Chip Select bits (A2, A1, A0). The Chip  
Select bits allow the use of up to eight 24AA025UID  
devices on the same bus and are used to select which  
device is accessed. The Chip Select bits in the control  
byte must correspond to the logic levels on the corre-  
sponding A2, A1 and A0 pins for the device to respond.  
These bits are in effect the three Most Significant bits of  
the word address.  
A2*A1*A0*R/W ACK  
Slave Address  
Acknowledge Bit  
Start Bit  
Note:  
* Bits A0, A1 and A2 are “don’t cares” for  
the 24AA02UID.  
For the 6-pin SOT-23 package, the A2 address pin is  
not available. During device addressing, the A2 Chip  
Select bit should be set to ‘0’.  
5.1  
Contiguous Addressing Across  
Multiple Devices  
The last bit of the control byte defines the operation to  
be performed. When set to ‘1’, a read operation is  
selected. When set to ‘0’, a write operation is selected.  
Following the Start condition, the 24AA02XUID moni-  
tors the SDA bus, checking the device type identifier  
being transmitted and, upon a 1010code, the slave  
device outputs an Acknowledge signal on the SDA line.  
Depending on the state of the R/W bit, the  
24AA02XUID will select a read or write operation.  
The Chip Select bits A2, A1 and A0 can be used to  
expand the contiguous address space for up to 16K bits  
by adding up to eight 24AA025UID devices on the  
same bus. In this case, software can use A0 of the con-  
trol byte as address bit A8, A1 as address bit A9 and  
A2 as address bit A10. It is not possible to sequentially  
read across device boundaries.  
For the SOT-23 package, up to four 24AA025UID  
devices can be added for up to 8K bits of address  
space. In this case, software can use A0 of the control  
byte as address bit A8, and A1 as address bit A9. It is  
not possible to sequentially read across device  
boundaries.  
Control  
Code  
Operation  
Chip Select  
R/W  
Read  
Write  
Chip Address  
Chip Address  
1010  
1010  
1
0
FIGURE 5-2:  
ADDRESS SEQUENCE BIT ASSIGNMENTS  
Control Byte  
Address Low Byte  
A
7
A
0
A2*  
A1*  
A0*  
1
0
1
0
R/W  
Control  
Code  
Chip  
Select  
bits  
Note:  
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02UID.  
DS20005202A-page 8  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
constant. If the master should transmit more than eight  
words (16 for the 24AA025UID) prior to generating the  
Stop condition, the address counter will roll over and the  
previously received data will be overwritten. As with the  
byte write operation, once the Stop condition is received  
an internal write cycle will begin (Figure 6-2).  
6.0  
6.1  
WRITE OPERATION  
Byte Write  
Following the Start condition from the master, the  
device code (4 bits), the chip address (3 bits) and the  
R/W bit which is a logic-low, is placed onto the bus by  
the master transmitter. This indicates to the addressed  
slave receiver that a byte with a word address will  
follow once it has generated an Acknowledge bit during  
the ninth clock cycle. Therefore, the next byte transmit-  
ted by the master is the word address and will be  
written into the Address Pointer of the 24AA02XUID.  
After receiving another Acknowledge signal from the  
24AA02XUID, the master device will transmit the data  
word to be written into the addressed memory location.  
The 24AA02XUID acknowledges again and the master  
generates a Stop condition. This initiates the internal  
write cycle and, during this time, the 24AA02XUID will  
not generate Acknowledge signals (Figure 6-1).  
Note:  
Page write operations are limited to writ-  
ing bytes within a single physical page  
regardless of the number of bytes  
actually being written. Physical page  
boundaries start at addresses that are  
integer multiples of the page buffer size  
(or ‘page size’) and end at addresses that  
are integer multiples of [page size – 1]. If  
a page Write command attempts to write  
across a physical page boundary, the  
result is that the data wraps around to the  
beginning of the current page (overwriting  
data previously stored there), instead of  
being written to the next page, as might be  
expected. It is therefore necessary for the  
application software to prevent page write  
operations that would attempt to cross a  
page boundary.  
6.2  
Page Write  
The write-control byte, word address and the first data  
byte are transmitted to the 24AA02XUID in the same  
way as in a byte write. However, instead of generating  
a Stop condition, the master transmits up to eight data  
bytes to the 24AA02XUID, which are temporarily stored  
in the on-chip page buffer and will be written into mem-  
ory once the master has transmitted a Stop condition.  
Upon receipt of each word, the three lower-order  
Address Pointer bits (four for the 24AA025UID) are  
internally incremented by ‘1’. The higher-order five bits  
(four for the 24AA025UID) of the word address remain  
6.3  
Write Protection  
The upper half of the array (80h-FFh) is permanently  
write-protected. Write operations to this address range  
are inhibited. Read operations are not affected.  
The remaining half of the array (00h-7Fh) can be  
written to and read from normally.  
FIGURE 6-1:  
BYTE WRITE  
S
T
A
R
T
S
Bus Activity  
Master  
Control  
Byte  
Word  
Address  
T
O
P
Data  
0
0
SDA Line  
A2*A1*A0*  
1
0
1
S
P
A
C
K
A
C
K
A
C
K
Bus Activity  
Chip  
Select  
Bits  
Note:  
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02UID.  
FIGURE 6-2:  
PAGE WRITE  
S
S
T
O
P
T
Bus Activity  
Master  
Control  
Byte  
Word  
Address (n)  
A
Data (n)  
Data (n + 1)  
Data (n + 7)  
R
T
*
*
*
10 10A2 A00  
A1  
SDA Line  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity  
Chip  
Select  
Bits  
Note:  
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02UID.  
2013 Microchip Technology Inc.  
DS20005202A-page 9  
24AA02UID/24AA025UID  
7.0  
ACKNOWLEDGE POLLING  
Since the device will not acknowledge during a write  
cycle, this can be used to determine when the cycle is  
complete (this feature can be used to maximize bus  
throughput). Once the Stop condition for a Write  
command has been issued from the master, the device  
initiates the internally-timed write cycle and ACK polling  
can then be initiated immediately. This involves the  
master sending a Start condition followed by the control  
byte for a Write command (R/W = 0). If the device is still  
busy with the write cycle, no ACK will be returned. If the  
cycle is complete, the device will return the ACK and  
the master can then proceed with the next Read or  
Write command. See Figure 7-1 for a flow diagram of  
this operation.  
FIGURE 7-1:  
ACKNOWLEDGE POLLING  
FLOW  
Send  
Write Command  
Send Stop  
Condition to  
Initiate Write Cycle  
Send Start  
Send Control Byte  
with R/W = 0  
Did Device  
Acknowledge  
(ACK = 0)?  
No  
Yes  
Next  
Operation  
DS20005202A-page 10  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
8.3  
Sequential Read  
8.0  
READ OPERATION  
Sequential reads are initiated in the same way as a  
random read, except that once the 24AA02XUID  
transmits the first data byte, the master issues an  
acknowledge as opposed to a Stop condition in a ran-  
dom read. This directs the 24AA02XUID to transmit the  
next sequentially-addressed 8-bit word (Figure 8-3).  
Read operations are initiated in the same way as write  
operations, with the exception that the R/W bit of the  
slave address is set to ‘1’. There are three basic types  
of read operations: current address read, random read  
and sequential read.  
8.1  
Current Address Read  
To provide sequential reads, the 24AA02XUID contains  
an internal Address Pointer that is incremented by one  
upon completion of each operation. This Address  
Pointer allows the entire memory contents to be serially  
read during one operation.  
The 24AA02XUID contains an address counter that  
maintains the address of the last word accessed, inter-  
nally incremented by ‘1’. Therefore, if the previous  
access (either a read or write operation) was to address  
n, the next current address read operation would  
access data from address n + 1. Upon receipt of the  
slave address with R/W bit set to ‘1’, the 24AA02XUID  
issues an acknowledge and transmits the 8-bit data  
word. The master will not acknowledge the transfer, but  
does generate a Stop condition, and the 24AA02XUID  
discontinues transmission (Figure 8-1).  
8.4  
Noise Protection  
The 24AA02XUID employs a VCC threshold detector  
circuit which disables the internal erase/write logic if the  
VCC is below 1.5V at nominal conditions.  
The SCL and SDA inputs have Schmitt Trigger and  
filter circuits which suppress noise spikes to assure  
proper device operation, even on a noisy bus.  
8.2  
Random Read  
Random read operations allow the master to access  
any memory location in a random manner. To perform  
this type of read operation, the word address must first  
be set. This is accomplished by sending the word  
address to the 24AA02XUID as part of a write  
operation. Once the word address is sent, the master  
generates a Start condition following the acknowledge.  
This terminates the write operation, but not before the  
internal Address Pointer is set. The master then issues  
the control byte again, but with the R/W bit set to a ‘1’.  
The 24AA02XUID will then issue an acknowledge and  
transmit the 8-bit data word. The master will not  
acknowledge the transfer, but does generate a Stop  
condition, and the 24AA02XUID will discontinue  
transmission (Figure 8-2).  
FIGURE 8-1:  
CURRENT ADDRESS READ  
S
Bus Activity  
Master  
T
A
R
Control  
Byte  
S
T
Data (n)  
O
P
T
1
0
A0*  
0
1
A2*A1*  
SDA Line  
1
S
P
A
C
K
N
o
Bus Activity  
Chip  
Select  
Bits  
A
C
K
Note:  
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02UID.  
2013 Microchip Technology Inc.  
DS20005202A-page 11  
24AA02UID/24AA025UID  
FIGURE 8-2:  
RANDOM READ  
S
S
T
A
R
T
T
A
R
T
S
T
Bus Activity  
Master  
Control  
Byte  
Word  
Address (n)  
Control  
Byte  
Data (n)  
O
P
* * *  
* * *  
A2A1A0  
0
0
A2 A01  
1 0  
1
1 0  
0
A1  
1
S
P
S
SDA Line  
A
C
K
A
C
K
A
C
K
N
o
Chip  
Select  
Bits  
Chip  
Select  
Bits  
Bus Activity  
A
C
K
Note:  
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02UID.  
FIGURE 8-3:  
SEQUENTIAL READ  
S
T
O
P
Bus Activity  
Master  
Control  
Byte  
Data (n)  
Data (n + 1)  
Data (n + 2)  
Data (n + x)  
1
P
SDA Line  
A
C
K
A
C
K
A
C
K
A
C
K
N
o
Bus Activity  
A
C
K
DS20005202A-page 12  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
9.2  
Extending the 32-bit Serial  
Number  
9.0  
PREPROGRAMMED UNIQUE  
32-BIT SERIAL NUMBER  
For applications that require serial numbers larger than  
32 bits, additional data bytes can be used to pad the  
provided serial number to meet the required length.  
Any data byte values can be used for padding as the  
32-bit serial number ensures the extended serial num-  
ber remains unique.  
The 24AA02XUID is programmed at the factory with a  
unique 32-bit serial number stored in the upper half of  
the array and permanently write-protected. The  
remaining 1,024 bits are available for application use.  
Note:  
The 32-bit serial number is unique across  
all Microchip UID-family serial EEPROM  
devices.  
The padding can be performed in two ways. The first  
method is to pad the data in software by combining the  
32-bit serial number from the 24AA02XUID with fixed  
data. The second method is to extend the number of  
bytes read from the 24AA02XUID to meet the required  
length. Table 9-1 shows example address ranges and  
their corresponding serial number lengths.  
FIGURE 9-1:  
MEMORY ORGANIZATION  
00h  
Standard  
EEPROM  
80h  
TABLE 9-1:  
EXTENDED READ EXAMPLES  
Write-Protected  
Serial Number Block  
Serial Number  
End Address  
Start Address  
Length  
FFh  
0xFC  
0xFA  
0xF8  
0xF0  
0xE0  
0xFF  
0xFF  
0xFF  
0xFF  
0xFF  
32 bits  
48 bits  
64 bits  
128 bits  
256 bits  
The 4-byte serial number is stored in array locations  
0xFC through 0xFF, as shown in Figure 9-2.  
9.1  
Manufacturer and Device Codes  
In addition to the serial number, a manufacturer code is  
stored at location 0xFA and a device identifier is stored  
at 0xFB. The manufacturer code is fixed as 0x29. For  
the 24AA02XUID, the device identifier is 0x41. The ‘4’  
indicates the I2C™ family and the ‘1’ indicates a 2 Kbit  
memory density.  
FIGURE 9-2:  
SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE  
Manufacturer  
Code  
Device  
Code  
Description  
32-bit Serial Number  
29h  
41h  
12h  
34h  
56h  
78h  
Data  
Type  
Fixed  
Serialized  
Array  
Address  
FAh  
FBh  
FCh  
FDh  
FEh  
FFh  
2013 Microchip Technology Inc.  
DS20005202A-page 13  
24AA02UID/24AA025UID  
10.0 PACKAGING INFORMATION  
10.1 Package Marking Information  
8-Lead PDIP (300 mil)  
Example:  
XXXXXXXX  
TXXXXNNN  
24AA02ID  
I/P 1L7  
e
3
YYWW  
1327  
8-Lead SOIC (3.90 mm)  
Example:  
24A2UIDI  
XXXXXXXT  
XXXXYYWW  
e
3
SN 1327  
NNN  
1L7  
5-Lead SOT-23  
Example:  
XXXXY  
WWNNN  
AAAF3  
271L7  
6-Lead SOT-23  
Example:  
XXXXY  
WWNNN  
AAAE3  
271L7  
1st Line Marking Code  
Part Number  
SOT-23  
I Temp.  
SOIC  
PDIP  
I Temp.  
I Temp.  
24AA02UID  
AAAFY  
AAAEY  
24A2UIDT  
4A25UIDT  
24AA02ID  
24A25UID  
24AA025UID  
Note:  
NN = Alphanumeric traceability code  
DS20005202A-page 14  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
Legend: XX...X Part number or part number code  
T
Temperature (I, E)  
Y
Year code (last digit of calendar year)  
YY  
WW  
NNN  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code (2 characters for small packages)  
Pb-free JEDEC designator for Matte Tin (Sn)  
e
3
Note:  
For very small packages with no room for the Pb-free JEDEC designator  
, the marking will only appear on the outer carton or reel label.  
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  
2013 Microchip Technology Inc.  
DS20005202A-page 15  
24AA02UID/24AA025UID  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS20005202A-page 16  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2013 Microchip Technology Inc.  
DS20005202A-page 17  
24AA02UID/24AA025UID  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢍꢓꢔꢆꢕꢆꢓꢄꢖꢖꢗꢘꢙꢆꢚꢛꢜꢝꢆꢎꢎꢆꢞꢗꢅꢟꢆꢠꢍꢏꢡꢢꢣ  
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ  
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ  
DS20005202A-page 18  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
ꢥꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢦꢖꢄꢑꢉꢋꢉꢊꢗꢖꢆꢒꢏꢦꢔꢆꢠꢍꢏꢦꢁꢧꢚꢣ  
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ  
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ  
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ꢎꢁꢍ%ꢆ%ꢃ(ꢊꢇ$ꢊꢋꢆꢃꢗꢅꢌꢇ$ꢈꢆ""  
ꢏꢄꢊꢈ%ꢁ))  
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ꢀꢁꢁꢄꢃꢕꢈꢋꢍꢆ  
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ꢓꢐꢓꢒ  
3ꢐ1ꢒ  
ꢓꢐꢔꢒ  
ꢒꢐ3ꢒ  
ꢒꢐ1;  
ꢒꢞ  
3ꢐꢖ;  
3ꢐ1ꢒ  
ꢒꢐ3;  
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ꢓꢐ ꢑꢌ!ꢆꢈ"ꢌꢁꢈꢌꢈꢋꢃꢊꢈ%ꢃꢄꢁꢍꢆꢂꢊꢈꢇꢌꢈꢋꢃꢉꢆꢂꢃꢕꢏꢎ6ꢃ83ꢖꢐ;ꢎꢐ  
<ꢏ=* <ꢊ"ꢌꢇꢃꢑꢌ!ꢆꢈ"ꢌꢁꢈꢐꢃꢗꢅꢆꢁꢂꢆꢄꢌꢇꢊꢍꢍꢘꢃꢆ7ꢊꢇꢄꢃ>ꢊꢍ#ꢆꢃ"ꢅꢁ&ꢈꢃ&ꢌꢄꢅꢁ#ꢄꢃꢄꢁꢍꢆꢂꢊꢈꢇꢆ"ꢐ  
ꢎꢌꢇꢂꢁꢇꢅꢌꢉ ꢇꢅꢈꢁꢍꢁꢋꢘ ꢑꢂꢊ&ꢌꢈꢋ =ꢒꢖꢟꢒꢛ3<  
2013 Microchip Technology Inc.  
DS20005202A-page 19  
24AA02UID/24AA025UID  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS20005202A-page 20  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
ꢨꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢦꢖꢄꢑꢉꢋꢉꢊꢗꢖꢆꢒꢏꢦꢔꢆꢠꢍꢏꢦꢁꢧꢚꢣ  
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ  
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ  
b
4
N
E
E1  
PIN 1 ID BY  
LASER MARK  
1
2
3
e
e1  
D
c
A
φ
A2  
L
A1  
L1  
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ꢎꢁꢍ%ꢆ%ꢃ(ꢊꢇ$ꢊꢋꢆꢃꢗꢅꢌꢇ$ꢈꢆ""  
ꢏꢄꢊꢈ%ꢁ))  
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ꢀꢁꢁꢄꢃ@ꢆꢈꢋꢄꢅ  
ꢀꢁꢁꢄꢉꢂꢌꢈꢄ  
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@ꢆꢊ%ꢃLꢌ%ꢄꢅ  
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3ꢐ1ꢒ  
ꢓꢐꢔꢒ  
ꢒꢐ3ꢒ  
ꢒꢐ1;  
ꢒꢞ  
3ꢐꢖ;  
3ꢐ1ꢒ  
ꢒꢐ3;  
1ꢐꢓꢒ  
3ꢐꢝꢒ  
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ꢒꢐNꢒ  
ꢒꢐꢝꢒ  
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ꢒꢐ;3  
ꢓꢗꢊꢃꢉꢤ  
3ꢐ ꢑꢌ!ꢆꢈ"ꢌꢁꢈ"ꢃꢑꢃꢊꢈ%ꢃ63ꢃ%ꢁꢃꢈꢁꢄꢃꢌꢈꢇꢍ#%ꢆꢃ!ꢁꢍ%ꢃ)ꢍꢊ"ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ#"ꢌꢁꢈ"ꢐꢃꢎꢁꢍ%ꢃ)ꢍꢊ"ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ#"ꢌꢁꢈ"ꢃ"ꢅꢊꢍꢍꢃꢈꢁꢄꢃꢆ7ꢇꢆꢆ%ꢃꢒꢐ3ꢓꢔꢃ!!ꢃꢉꢆꢂꢃ"ꢌ%ꢆꢐ  
ꢓꢐ ꢑꢌ!ꢆꢈ"ꢌꢁꢈꢌꢈꢋꢃꢊꢈ%ꢃꢄꢁꢍꢆꢂꢊꢈꢇꢌꢈꢋꢃꢉꢆꢂꢃꢕꢏꢎ6ꢃ83ꢖꢐ;ꢎꢐ  
<ꢏ=* <ꢊ"ꢌꢇꢃꢑꢌ!ꢆꢈ"ꢌꢁꢈꢐꢃꢗꢅꢆꢁꢂꢆꢄꢌꢇꢊꢍꢍꢘꢃꢆ7ꢊꢇꢄꢃ>ꢊꢍ#ꢆꢃ"ꢅꢁ&ꢈꢃ&ꢌꢄꢅꢁ#ꢄꢃꢄꢁꢍꢆꢂꢊꢈꢇꢆ"ꢐ  
ꢎꢌꢇꢂꢁꢇꢅꢌꢉ ꢇꢅꢈꢁꢍꢁꢋꢘ ꢑꢂꢊ&ꢌꢈꢋ =ꢒꢖꢟꢒꢓꢝ<  
2013 Microchip Technology Inc.  
DS20005202A-page 21  
24AA02UID/24AA025UID  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS20005202A-page 22  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
APPENDIX A: REVISION HISTORY  
Revision A (05/13)  
Initial release.  
2013 Microchip Technology Inc.  
DS20005202A-page 23  
24AA02UID/24AA025UID  
NOTES:  
DS20005202A-page 24  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
THE MICROCHIP WEB SITE  
CUSTOMER SUPPORT  
Microchip provides online support via our WWW site at  
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To register, access the Microchip web site at  
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Notification and follow the registration instructions.  
2013 Microchip Technology Inc.  
DS20005202A-page 25  
24AA02UID/24AA025UID  
READER RESPONSE  
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-  
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation  
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DS20005202A  
Literature Number:  
24AA02UID/24AA025UID  
Device:  
Questions:  
1. What are the best features of this document?  
2. How does this document meet your hardware and software development needs?  
3. Do you find the organization of this document easy to follow? If not, why?  
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DS20005202A-page 26  
2013 Microchip Technology Inc.  
24AA02UID/24AA025UID  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
PART NO.  
Device  
X
/XX  
Examples:  
Temperature Package  
Range  
a) 24AA02UID-I/SN: 2k-bit, 8-byte page,  
Serial EEPROM with 32-bit Serial  
Number, Industrial Temperature, 1.7V,  
SOIC package  
2
Device:  
24AA02UID  
=
=
1.7V, 2 Kbit I C™ Serial EEPROM  
with 32-bit Serial Number  
1.7V, 2 Kbit I C Serial EEPROM  
with 32-bit Serial Number (Tape  
and Reel)  
1.7V, 2 Kbit I C Serial EEPROM with  
b) 24AA02UIDT-I/OT: 2k-bit, 8-byte page,  
Serial EEPROM with 32-bit Serial  
Number, Industrial Temperature, 1.7V,  
SOT-23 package, tape and reel  
2
24AA02UIDT  
24AA025UID  
2
c)  
24AA025UID-I/SN: 2k-bit, 16-byte page,  
Serial EEPROM with 32-bit Serial  
Number, Industrial Temperature, 1.7V,  
Cascadable, SOIC package  
=
32-bit Serial Number and Address  
Pins  
2
24AA025UIDT = 1.7V, 2 Kbit I C Serial EEPROM with  
32-bit Serial Number and Address  
Pins (Tape and Reel)  
d) 24AA025UID-I/P: 2k-bit, 16-byte page,  
Serial EEPROM with 32-bit Serial  
Number, Industrial Temperature, 1.7V,  
Cascadable, PDIP package  
Temperature  
Range:  
I
=
-40°C to +85°C  
Package:  
P
SN  
OT  
=
=
=
Plastic DIP (300 mil body), 8-lead  
Plastic SOIC (3.90 mm body), 8-lead  
SOT-23 (Tape and Reel only)  
2013 Microchip Technology Inc.  
DS20005202A-page27  
24AA02UID/24AA025UID  
NOTES:  
DS20005202A-page 28  
2013 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
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Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,  
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash  
and UNI/O are registered trademarks of Microchip Technology  
Incorporated in the U.S.A. and other countries.  
32  
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  
MTP, SEEVAL and The Embedded Control Solutions  
Company are registered trademarks of Microchip Technology  
Incorporated in the U.S.A.  
Silicon Storage Technology is a registered trademark of  
Microchip Technology Inc. in other countries.  
Analog-for-the-Digital Age, Application Maestro, BodyCom,  
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,  
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,  
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial  
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB  
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code  
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,  
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,  
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA  
and Z-Scale are trademarks of Microchip Technology  
Incorporated in the U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
GestIC and ULPP are registered trademarks of Microchip  
Technology Germany II GmbH & Co. KG, a subsidiary of  
Microchip Technology Inc., in other countries.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2013, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
ISBN: 9781620772300  
QUALITY MANAGEMENT SYSTEM  
CERTIFIED BY DNV  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
== ISO/TS 16949 ==  
2013 Microchip Technology Inc.  
DS20005202A-page 29  
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11/29/12  
DS20005202A-page 30  
2013 Microchip Technology Inc.  

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