24AA1026TI/SN [MICROCHIP]
1024K I2C�� Serial EEPROM;
| 型号： | 24AA1026TI/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 1024K I2C�� Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总30页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24AA1026/24LC1026/24FC1026
1024K I2C Serial EEPROM
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
Device Selection Table
Part
VCC
Max. Clock
Temp.
Ranges
Number
Range
Frequency
24AA1026 1.7V-5.5V
24LC1026 2.5V-5.5V
24FC1026 1.8V-5.5V
400 kHz(1)
400 kHz(2)
1 MHz(3)
I
I, E
I
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
Note 1: 100 kHz for VCC < 2.5V
2: 100 kHz for VCC < 4.5V (E-temp)
3: 400 kHz for VCC < 2.5V
Features
Package Type
• Low-Power CMOS Technology:
- Read current 450 µA, maximum
- Standby current 5 µA, maximum
• 2-Wire Serial Interface, I2C Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
8-Lead PDIP
8-Lead SOIC/SOIJ
NC
1
8
VCC
1
2
3
4
8
7
6
5
NC
A1
VCC
WP
A1
A2
2
3
7
6
WP
SCL
A2
SCL
SDA
VSS
4
5
SDA
VSS
• Page Write Time 3 ms, typical
Block Diagram
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
A1A2
WP
HV Generator
• Hardware Write-Protect
• Electrostatic Discharge (ESD) Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 Years
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
Page Latches
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC and SOIJ
• RoHS Compliant
I/O
SCL
YDEC
• Temperature Ranges:
SDA
- Industrial (I):
-40C to +85C
- Automotive (E): -40C to +125C
VCC
VSS
Sense AMP
R/W Control
Description
The
Microchip
Technology
Incorporated
24AA1026/24LC1026/24FC1026 (24XX1026*) is a
128K x 8 (1024 Kbit) Serial Electrically Erasable
PROM, capable of operation across a broad voltage
range (1.7V to 5.5V).
*24XX1026 is used in this document as a generic part
number for the 24AA1026/24LC1026/24FC1026
devices.
2011-2015 Microchip Technology Inc.
DS20002270E-page 1
24AA1026/24LC1026/24FC1026
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS .......................................................................................................... -0.6V to VCC+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
DC CHARACTERISTICS
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Conditions
D1
D2
VIH
VIL
High-Level Input Voltage
Low-Level Input Voltage
0.7 VCC
—
—
V
V
V
V
0.3 VCC
0.2 VCC
—
VCC 2.5V
VCC < 2.5V
D3
VHYS
Hysteresis of Schmitt
Trigger Inputs
0.05 VCC
VCC 2.5V (Note)
(SDA, SCL pins)
D4
D5
VOL
ILI
Low-Level Output Voltage
Input Leakage Current
Output Leakage Current
—
—
0.40
±1
V
IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
µA
VIN = VSS or VCC
VIN = VSS or VCC
D6
D7
ILO
—
—
±1
10
µA
pF
VOUT = VSS or VCC
CIN,
Pin Capacitance
VCC = 5.0V (Note)
COUT
(all inputs/outputs)
TA = 25°C, FCLK = 1 MHz
D8
D9
ICCREAD Operating Current
ICCWRITE
—
—
—
450
5
µA
mA
µA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V
ICCS
Standby Current
5
SCL = SDA = VCC = 5.5V
A1 = A2 = WP = VSS
Note:
This parameter is periodically sampled and not 100% tested.
DS20002270E-page 2
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
2
3
4
FCLK Clock Frequency
—
—
100
100
400
400
1000
—
kHz 1.7V VCC 2.5V
kHz 2.5V VCC 4.5V, E-temp
kHz 2.5V VCC 5.5V
—
—
kHz 1.8V VCC 2.5V (24FC1026)
kHz 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
THIGH Clock High Time
TLOW Clock Low Time
4000
4000
600
600
500
4700
4700
1300
1300
500
—
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
—
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
TR
SDA and SCL Rise Time
1000
1000
300
300
300
300
100
—
(Note 1)
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns All except 24FC1026
—
5
6
TF
SDA and SCL Fall Time
—
(Note 1)
—
ns 1.8V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
THD:STA Start Condition Hold Time
4000
4000
600
600
250
4700
4700
600
600
250
0
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
7
8
TSU:STA Start Condition Setup
Time
—
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns (Note 2)
—
THD:DAT Data Input Hold Time
—
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2011-2015 Microchip Technology Inc.
DS20002270E-page 3
24AA1026/24LC1026/24FC1026
Electrical Characteristics:
AC CHARACTERISTICS (Continued)
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
9
TSU:DAT Data Input Setup Time
250
250
100
100
100
4000
4000
600
600
250
4000
4000
600
600
600
4700
4700
1300
1300
1300
—
—
—
ns 1.7V VCC 2.5V
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
10
11
12
13
TSU:STO Stop Condition Setup
Time
—
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
TSU:WP WP Setup Time
THD:WP WP Hold Time
—
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
—
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
ns 1.7V VCC 2.5V
—
TAA Output Valid from Clock
3500
3500
900
900
400
—
(Note 2)
—
ns 2.5V VCC 4.5V, E-temp
ns 2.5V VCC 5.5V
—
—
ns 1.8V VCC 2.5V (24FC1026)
ns 2.5V VCC 5.5V (24FC1026)
—
14
Bus Free Time: bus time
must be free before a new
transmission can start
4700
4700
1300
1300
500
ns
ns
ns
ns
ns
1.7V VCC 2.5V
TBUF
—
2.5V VCC 4.5V, E-temp
2.5V VCC 5.5V
—
—
1.8V VCC 2.5V (24FC1026)
2.5V VCC 5.5V (24FC1026)
—
15
TSP Input Filter Spike
Suppression
—
50
ns All except 24FC1026 (Notes 1 and 3)
(SDA and SCL pins)
16
17
TWC Write Cycle Time (byte or
page)
—
5
ms
Endurance
1,000,000
—
cycles Page mode, 25°C, VCC = 5.5V (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
DS20002270E-page 4
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
FIGURE 1-1:
BUS TIMING DATA
5
4
D3
2
SCL
7
3
10
8
9
SDA
IN
6
15
14
12
13
SDA
OUT
(protected)
WP
11
(unprotected)
2011-2015 Microchip Technology Inc.
DS20002270E-page 5
24AA1026/24LC1026/24FC1026
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
PDIP
SOIC
SOIJ
Function
NC
A1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Not Connected
User Configurable Chip Select
User Configurable Chip Select
Ground
A2
VSS
SDA
SCL
WP
VCC
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1026)
+2.5 to 5.5V (24LC1026)
+1.8 to 5.5V (24FC1026)
2.1
A1, A2 Chip Address Inputs
3.0
FUNCTIONAL DESCRIPTION
The A1 and A2 inputs are used by the 24XX1026 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
The 24XX1026 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1026 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A1 and A2 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an
open-drain terminal, therefore, the SDA bus requires a
pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k
for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4
Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited, but read operations are
not affected.
DS20002270E-page 6
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
4.5
Acknowledge
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
Note:
The 24XX1026 does not generate any
Acknowledge bits if an internal
4.2
Start Data Transfer (B)
programming cycle is in progress,
however, the control byte that is being
polled must match the control byte used to
initiate the write cycle.
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
A device that acknowledges must pull-down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX1026) will leave the data line high to enable
the master to generate the Stop condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
The transmitter must release the SDA line at this
point allowing the receiver to pull the SDA line low
to acknowledge the previous eight bits of data.
The receiver must release the SDA line at
this point so the transmitter can continue
sending data.
2011-2015 Microchip Technology Inc.
DS20002270E-page 7
24AA1026/24LC1026/24FC1026
FIGURE 5-1:
CONTROL BYTE
FORMAT
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX1026, this is set as ‘1010’ binary for read and
write operations. The next two bits of the control byte
are the Chip Select bits (A2, A1). The Chip Select bits
allow the use of up to four 24XX1026 devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2
and A1 pins for the device to respond. These bits are in
effect the two Most Significant bits (MSb) of the word
address. The next bit of the control byte is the block
select bit (B0). This bit acts as the A16 address bit for
accessing the entire array.
Read/Write Bit
Chip Block
Select
Bit
Select
Bits
Control Code
S
1
0
1
0
A2 A1 B0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
5.1
Contiguous Addressing Across
Multiple Devices
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). The upper
address bits are transferred first, followed by the Least
Significant bits (LSb).
The Chip Select bits A2 and A1 can be used to expand
the contiguous address space for up to 4 Mbit by
adding up to four 24XX1026’s on the same bus. In this
case, software can use A1 of the control byte as
address bit A17 and A2 as address bit A18. It is not
possible to sequentially read across device
boundaries.
Following the Start condition, the 24XX1026 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX1026 will select a read
or write operation.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
512K bits. The block select bit ‘B0’ controls access to
each “half”.
Sequential read operations are limited to 512K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
This device has an internal addressing boundary
limitation that is divided into two segments of 512K bits.
Block select bit ‘B0’ is used to control access to each
segment.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Address High Byte
Control Byte
Address Low Byte
A
A
A
A
A
2
A
1
B
0
A
A
A
9
A
8
A
7
A
0
•
•
•
•
•
•
1
0
1
0
R/W
12 11 10
15 14 13
Block
Select
Bit
Chip
Select
Bits
Control
Code
DS20002270E-page 8
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
6.2
Page Write
6.0
6.1
WRITE OPERATIONS
Byte Write
The write control byte, word address and the first data
byte are transmitted to the 24XX1026 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are
internally incremented by one. If the master should
transmit more than 128 bytes prior to generating the
Stop condition, the address counter will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received, an internal write cycle will begin (Figure 6-2).
If an attempt is made to write to the array with the WP
pin held high, the device will acknowledge the
command, but no write cycle will occur, no data will be
written and the device will immediately accept a new
command.
Following the Start condition from the master, the
control code (four bits), the Chip Select (two bits), the
block select (one bit), and the R/W bit (which is a logic
low) are clocked onto the bus by the master transmitter.
This indicates to the addressed slave receiver that the
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the high-order byte of the word address and will be
written into the Address Pointer of the 24XX1026. The
next byte is the Least Significant Address Byte. After
receiving another Acknowledge signal from the
24XX1026, the master device will transmit the data
word to be written into the addressed memory location.
The 24XX1026 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and during this time, the 24XX1026 will not
generate Acknowledge signals as long as the control
byte being polled matches the control byte that was
used to initiate the write (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (00000-1FFFF) when the pin is tied to VCC. If tied
to VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Note:
When doing a write of less than 128 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
2011-2015 Microchip Technology Inc.
DS20002270E-page 9
24AA1026/24LC1026/24FC1026
FIGURE 6-1:
BYTE WRITE
S
T
A
R
T
Bus Activity
Master
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
Data
A A B
SDA LINE
S 1 0 1 0
0
P
2 1 0
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 6-2:
PAGE WRITE
S
T
A
R
T
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
Bus Activity
Master
Data Byte 0
Data Byte 127
A A B
SDA Line
P
S 1 0 1 0
0
2 1 0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
DS20002270E-page 10
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete. (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be resent. If the cycle is complete, then the device
will return the ACK and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Note:
Care must be taken when polling the
24XX1026. The control byte that was
used to initiate the write needs to match
the control byte used for polling.
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
2011-2015 Microchip Technology Inc.
DS20002270E-page 11
24AA1026/24LC1026/24FC1026
8.3
Sequential Read
8.0
READ OPERATION
Sequential reads are initiated in the same way as a
random read except that after the 24XX1026 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX1026 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide
sequential reads, the 24XX1026 contains an internal
Address Pointer which is incremented by one at the
completion of each operation. This Address Pointer
allows half the memory contents to be serially read
during one operation. Sequential read address
boundaries are 00000h to 0FFFFh and 10000h to
1FFFFh. The internal Address Pointer will
automatically roll over from address 0FFFFh to
address 00000h if the master acknowledges the byte
received from the array address, 0FFFFh. The internal
address counter will automatically roll over from
address 1FFFFh to address 10000h if the master
acknowledges the byte received from the array
address 1FFFFh.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX1026 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n (n is any legal
address), the next current address read operation
would access data from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX1026 issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX1026 discontinues transmission (Figure 8-1).
FIGURE 8-1:
CURRENT ADDRESS
READ
S
T
A
R
T
S
T
O
P
Bus Activity
Master
Control
Byte
Data
Byte
A A B
2 1 0
SDA Line
S 1 0 1 0
1
P
A
C
K
N
O
Bus Activity
A
C
K
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX1026 as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again, but with the R/W bit set to a one.
The 24XX1026 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition which causes the 24XX1026 to discontinue
transmission (Figure 8-2). After
a random Read
command, the internal address counter will point to the
address location following the one that was just read.
DS20002270E-page 12
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
FIGURE 8-2:
RANDOM READ
S
T
A
R
T
S
T
A
R
T
Bus Activity
Master
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
Control
Byte
Data
Byte
A A B
2 1 0
A A B
2 1 0
SDA Line
S 1 0 1 0
0
S 1 0 1 0
1
P
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
FIGURE 8-3:
SEQUENTIAL READ
S
T
O
P
Control
Byte
Bus Activity
Master
Data (n)
Data (n + 1)
Data (n + x)
Data (n + 2)
P
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
N
O
Bus Activity
A
C
K
2011-2015 Microchip Technology Inc.
DS20002270E-page 13
24AA1026/24LC1026/24FC1026
9.0
9.1
PACKAGING INFORMATION
Package Marking Information*
8-Lead PDIP (300 mil)
Example:
24LC1026
XXXXXXXX
TXXXXNNN
I/P
13F
3
e
YYWW
1544
8-Lead SOIC (3.90 mm)
Example
:
XXXXXXXT
XXXXYYWW
NNN
24L1026I
SN
1544
13F
e
3
8-Lead SOIJ (5.28 mm)
Example
:
24FC1026
XXXXXXXX
TXXXXXXX
YYWWNNN
I/SM
e
3
154513F
Legend: XX...X Part number or part number code
T
Temperature (I, E)
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
YY
WW
NNN
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
e
3
* Standard device marking consists of Microchip part number, year code, week code,
and traceability code (facility code, mask rev#, and assembly code). For device
marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office.
Note:
Note:
For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
e
3
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20002270E-page 14
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2011-2015 Microchip Technology Inc.
DS20002270E-page 15
24AA1026/24LC1026/24FC1026
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS20002270E-page 16
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2015 Microchip Technology Inc.
DS20002270E-page 17
24AA1026/24LC1026/24FC1026
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002270E-page 18
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢍꢓꢔꢆꢕꢆꢓꢄꢖꢖꢗꢘꢙꢆꢚꢛꢜꢝꢆꢎꢎꢆꢞꢗꢅꢟꢆꢠꢍꢏꢡꢢꢣ
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ
2011-2015 Microchip Technology Inc.
DS20002270E-page 19
24AA1026/24LC1026/24FC1026
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002270E-page 20
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2015 Microchip Technology Inc.
DS20002270E-page 21
24AA1026/24LC1026/24FC1026
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002270E-page 22
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
APPENDIX A: REVISION HISTORY
Revision A (01/2011)
Original release of this document.
Revision B (5/2011)
Added Automotive Temperature.
Revision C (04/2012)
Revised document title (removed CMOS); Revised
Table 1-1, Param D9; Revised Section 5.1.
Revision D (07/2013)
Added TSSOP package.
Revision E (11/2015)
Removed TSSOP package.
2011-2015 Microchip Technology Inc.
DS20002270E-page 23
24AA1026/24LC1026/24FC1026
NOTES:
DS20002270E-page 24
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://www.microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2011-2015 Microchip Technology Inc.
DS20002270E-page 25
24AA1026/24LC1026/24FC1026
NOTES:
DS20002270E-page 26
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
X
/XX
[X]
PART NO.
Device
Examples:
a) 24AA1026-I/P: Industrial Temperature,
1.7V, PDIP package.
Temperature Package
Range
Tape and Reel
Option
b) 24AA1026-I/SN: Industrial Temperature,
1.7V, SOIC package.
2
Device:
24AA1026= 1024K Bit 1.7V I C CMOS Serial EEPROM
24AA1026T = 1024K Bit 1.7V I C CMOS Serial EEPROM
c) 24AA1026T-I/SN: Tape and Reel, Industrial
Temperature,1.7V, SOIC
2
(Tape and Reel)
package.
2
24LC1026 = 1024K Bit 2.5V I C CMOS Serial EEPROM
24LC1026T= 1024K Bit 2.5V I C CMOS Serial EEPROM
d) 24AA1026T-I/SM: Tape and Reel,
Industrial Temperature,
2
(Tape and Reel)
1.7V, SOIJ package.
2
24FC1026= 1024K Bit 1.8V I C CMOS Serial EEPROM
24FC1026T= 1024K Bit 1.8V I C CMOS Serial EEPROM
e) 24FC1026-I/SN: Industrial Temperature,
1.8V, SOIC package.
2
(Tape and Reel)
f)
24FC1026T-I/SN: Tape and Reel, Industrial
Temperature, 1.8V, SOIC
package.
Tape and
Reel Option:
Blank = Standard packaging (tube or tray)
(1)
T
= Tape and Reel
g) 24LC1026-I/P:
Industrial Temperature,
2.5V, PDIP package.
h) 24LC1026T-I/SM:Tape and Reel, Industrial
Temperature, 2.5V, SOIJ
Temperature
Range:
I
E
=
=
-40°C to +85°C
-40°C to +125°C
package.
i)
24LC1026-E/SM: Extended temperature,
2.5V, SOIJ package
Package:
P
SM
SN
=
=
=
Plastic DIP (300 mil Body), 8-lead
Plastic SOIJ (5.28 mm Body), 8-lead
Plastic SOIC (3.90 mm Body), 8-lead
Note1: Tape and Reel identifier only appears
in the catalog part number description.
This identifier is used for ordering pur-
poses and is not printed on the device
package. Check with your Microchip
Sales Office for package availability
with the Tape and Reel option.
2011-2015 Microchip Technology Inc.
DS20002270E-page 27
24AA1026/24LC1026/24FC1026
NOTES:
DS20002270E-page 28
2011-2015 Microchip Technology Inc.
24AA1026/24LC1026/24FC1026
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0012-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2011-2015 Microchip Technology Inc.
DS20002270E-page 29
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.micro-
chip.com/support
Web Address:
www.microchip.com
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
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Tower 6, The Gateway
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Tel: 86-756-3210040
Fax: 86-756-3210049
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Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
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Tel: 39-0331-742611
Fax: 39-0331-466781
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Tel: 774-760-0087
Fax: 774-760-0088
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Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
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Tel: 86-769-8702-9880
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Tel: 39-049-7625286
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Tel: 31-416-690399
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
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Tel: 852-2943-5100
Fax: 852-2401-3431
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Tel: 34-91-708-08-90
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Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Sweden - Stockholm
Tel: 46-8-5090-4654
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Novi, MI
UK - Wokingham
Tel: 44-118-921-5800
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Tel: 248-848-4000
Fax: 44-118-921-5820
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
San Jose, CA
Tel: 408-735-9110
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
07/14/15
DS20002270E-page 30
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